A design method for peripheral circuits in a test chip and a test chip thereof

Abstract

The present invention provides a method for designing peripheral circuits in a test chip, comprising: obtaining device array information of devices in the test chip, and information of a device to be tested selected from the devices; determining a peripheral circuit area for placing the peripheral circuit; designing the peripheral circuit based on the edge rows and / or edge columns of the device array; configuring corresponding peripheral circuit units for the devices to be tested located in the edge rows and / or edge columns in the peripheral circuit area, and connecting the devices to be tested to the corresponding peripheral circuit units via connecting wires to form a peripheral circuit. The beneficial effect of this technical solution is that this method combines the consideration of the device array and the peripheral circuit units for collaborative planning to optimize the placement design of the peripheral circuit, and can improve the device density of the test chip without affecting the function and performance of the peripheral circuit. A test chip is also provided.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and production, and in particular relates to a design method for a peripheral circuit in a test chip and the test chip thereof. Background Art

[0002] Traditional semiconductor manufacturing typically uses short-range test chips to test and obtain the defect rate and yield of the production process. Depending on their placement within the wafer, they can be divided into two categories: standalone test chips (MPWs) and test chips placed in the scribe line (Scribe line). Standalone test chips are larger in area and need to occupy the space of a chip, which is equivalent to the semiconductor manufacturer having to pay for the manufacturing cost of the mask for this area. The scribe line is the space reserved on the wafer when the chips are cut. Placing the test chip in the scribe line does not occupy the chip position, which means that the semiconductor manufacturer does not have to bear the expensive mask costs, saving a lot of costs.

[0003] The test chip mainly includes two parts: the device under test (DUT) and the peripheral circuit. Figure 1 As shown in , the devices under test are placed in an array, each device under test occupies a certain width, and each peripheral circuit unit also occupies a certain width. Figure 1 The enlarged view in the figure shows an ideal situation. The array is composed of identical DUTs. Each DUT occupies the same width. The width occupied by the peripheral circuit units is also the same as that of the DUT. Therefore, the peripheral circuit units can be placed in a one-to-one correspondence with the DUTs in the horizontal edge rows of the array. However, in reality, the width occupied by the peripheral circuit units and the width occupied by the DUT cannot be guaranteed to be exactly the same. Figure 2 As shown in , the ratio of the width occupied by the DUT to the width occupied by the peripheral circuit unit is 2.016:2, resulting in a poor one-to-one correspondence between the two sides. Furthermore, if the width occupied by the peripheral circuit unit is greater than that occupied by the DUT, simply placing them in sequence will cause the DUT to exceed the peripheral circuit area. Furthermore, the array can also be composed of different DUTs, resulting in different widths occupied by different DUTs, further complicating the situation.

[0004] Current test chip design methods fail to consider the collaborative design of the "DUT" and "peripheral circuits." Instead, each component manages its own area and then glues it together. This glued-together area also results in additional area overhead. For high-density test chips, this additional area overhead also impacts the density of the DUT. Therefore, it is necessary to provide a method that comprehensively considers the characteristics of both the "DUT" and "peripheral circuits" at the initial stages of test chip design, allowing for targeted planning and design of the peripheral circuits. This method, further reducing the area overhead of the glued-together area, can improve device density on the test chip. This approach has very practical application prospects. Summary of the Invention

[0005] The present invention provides a design method for peripheral circuits in a test chip, which can comprehensively consider devices and peripheral circuits for coordinated planning, optimize the placement design of peripheral circuits, and reduce the additional area generated by connecting device arrays and peripheral circuit units.

[0006] The present invention also provides a test chip, which can further improve the device density of the test chip.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for designing peripheral circuits in a test chip, comprising the following steps: obtaining device array information of devices in the test chip and information of a device to be tested selected from the devices; determining a peripheral circuit area on the test chip for placing peripheral circuits; designing peripheral circuits based on edge rows or / and edge columns of the device array, comprising: configuring corresponding peripheral circuit units for the devices to be tested located in the edge rows or / and edge columns in the peripheral circuit area, arranging the positions of the peripheral circuit units, connecting the devices to be tested with corresponding peripheral circuit units through connecting lines to form a peripheral circuit, which is used to control the connection or disconnection of the test path of the specified device to be tested in the device array through the peripheral circuit. The beneficial effect of this technical solution is that the design method combines the consideration of the device array and the peripheral circuit units for collaborative planning to optimize the placement design of the peripheral circuit, and can improve the device density of the test chip without affecting the function and performance of the peripheral circuit.

[0009] Preferably, the total number of connecting wires of the peripheral circuit is the shortest. The beneficial effect of this technical solution is that by rationally arranging the positions of the peripheral circuit units and simplifying the routing layout of the connecting wires, the number of metal layers used to connect the device under test and the peripheral circuit units can be reduced, which is a significant advantage.

[0010] The method for designing peripheral circuits in a test chip also includes selecting devices to be tested from the devices, which includes determining a number of devices to be tested from devices in edge rows and / or edge columns of the device array. If the device array has multiple rows and columns, the method also includes determining a number of devices to be tested from devices in remaining rows and / or remaining columns of the device array.

[0011] Each device under test in the edge row and / or edge column is respectively configured with a corresponding peripheral circuit unit.

[0012] The configuration method is specifically as follows: presetting the number of peripheral circuit units configured based on the device to be tested in the edge row to be M; or / and presetting the number of peripheral circuit units configured based on the device to be tested in the edge column to be N; recording the number of devices in the edge row or / and edge column as K, and determining a number of devices to be tested from the devices located in the edge row or / and edge column, including: if the number of devices in the edge row K≤M or / and the number of devices in the edge column K≤N, then determining all the devices in the edge row or / and edge column as devices to be tested; if the number of devices in the edge row K>M, then selecting M devices from the devices in the edge row as devices to be tested, or / and, if the number of devices in the edge column K>N, then selecting N devices from the devices in the edge column as devices to be tested.

[0013] The row direction of the edge row or the column direction of the edge column is defined as the X direction, and the peripheral circuit units meet the following three conditions when the position arrangement is completed: first, the projections of the peripheral circuit units and their corresponding devices under test in the X direction overlap; second, the projections of the peripheral circuit units in the same row or column in the X direction do not overlap; and third, the peripheral circuit units are located in the peripheral circuit area.

[0014] The position arrangement method of the peripheral circuit unit includes: step S1. Note that the row number of the peripheral circuit unit array is i, and the row number refers to the row number of the peripheral circuit unit array arranged based on the edge row configuration or the column number of the peripheral circuit unit array arranged based on the edge column configuration; based on the first condition, the peripheral circuit units are arranged in a single row, that is, i=1, and then it is determined whether the peripheral circuit units after the single row arrangement meet the second condition and the third condition; if so, the position arrangement of the peripheral circuit units is completed and the processing is ended; if the second condition or the third condition is not met, the processing is continued. Step S2: Increment the number of rows of the peripheral circuit unit array, i.e., let i=i+1, move any one of the two peripheral circuit units whose projections overlap in the X direction to a new row perpendicular to the X direction, and / or move the peripheral circuit units that exceed the peripheral circuit area to a new row on the basis of satisfying the first condition, and then determine whether the rearranged peripheral circuit units satisfy the second and third conditions; if so, complete the position arrangement of the peripheral circuit units and terminate the process; if not, return to step S2 and loop through the process.

[0015] Furthermore, step S1 and step S2 may also include, on the basis of satisfying the first condition, the second condition and the third condition, adjusting the positions of several peripheral circuit units in the same row in the X direction to optimize the position arrangement so that the total number of connection lines used to connect the device under test and the corresponding peripheral circuit units to form a peripheral circuit is the shortest.

[0016] In addition, when the second condition or the third condition is not met in step S1, step S1.1 may be added before proceeding to step S2. Based on the first condition, after adjusting the position arrangement of the peripheral circuit units in the same row in the X direction, it is determined whether the second condition and the third condition are met; if so, the position arrangement of the peripheral circuit units is completed and the processing ends; if the second condition or the third condition is not met, the processing continues with step S2.

[0017] The determination of a number of devices to be tested among the devices in the remaining rows or columns of the device array (except the edge rows or / and edge columns) described in the present application means: starting from the ends of the edge rows or / and edge columns, a number of devices to be tested are determined row by row or / and column by column.

[0018] The peripheral circuit area is arranged between the device array and the pad area, or / and, between the device array and the edge of the test chip.

[0019] The peripheral circuit unit is a switch circuit unit, and the connection or disconnection of a specified device under test is selected by the on-off state of the switch circuit unit.

[0020] The peripheral circuit further includes an addressing circuit, the output end of which is connected to the input end of the switch circuit unit and is used to send an address signal to the switch circuit unit to control the on and off of the switch circuit unit.

[0021] In addition, it should be noted that the above-mentioned device array can be composed of the same devices or several different types of devices; the several peripheral circuit units in the above-mentioned peripheral circuit can be the same peripheral circuit units or different peripheral circuit units.

[0022] To achieve one, some, or all of the above-mentioned objectives, or other objectives, another technical solution of the present invention further provides a test chip comprising a plurality of devices under test (DUTs) and a plurality of peripheral circuits, wherein the DUTs form at least one device array, and the peripheral circuits include a plurality of peripheral circuit units, which control the connection and / or disconnection of test paths for designated DUTs in the device array. The peripheral circuits are designed and implemented using the aforementioned method for designing peripheral circuits in a test chip. By employing the aforementioned method for designing peripheral circuits in a test chip, this technical solution can effectively increase the device density on the test chip and reduce the number of metal layers used for connections.

[0023] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0024] 1. The present invention's design method for peripheral circuits in a test chip combines device arrays and peripheral circuit units for collaborative planning, optimizing the placement of the peripheral circuits. This reduces the additional area required to connect the device under test (DUT) and the peripheral circuit units without compromising the functionality and performance of the peripheral circuits, further increasing the device density of the test chip. Furthermore, the rational arrangement of the peripheral circuit units using this design method simplifies the routing of connecting wires, thereby reducing the number of metal layers used to connect the DUT and the peripheral circuit units.

[0025] 2. The test chip of the present invention utilizes the above-mentioned design method to design the peripheral circuits on the test chip, which can effectively improve the density of devices on the test chip and reduce the number of metal layers for connection.

[0026] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 The figure shows the placement of the device under test and peripheral circuits on the test chip under ideal conditions, as well as a partial enlarged view of point A.

[0029] Figure 2 This is a schematic diagram of the placement of the device under test and peripheral circuits in actual conditions.

[0030] Figure 3 This is a layout diagram in which the peripheral circuit units are arranged in a single row in a one-dimensional device array and meet the first, second and third conditions.

[0031] Figure 4 This is a layout diagram in which the peripheral circuit units are arranged in a single row in a two-dimensional device array and meet the first, second and third conditions.

[0032] Figure 5 and Figure 6 In a one-dimensional device array, a single-row arrangement of peripheral circuit units does not satisfy the second condition and / or the third condition.

[0033] Figure 7 and Figure 8 In a two-dimensional device array, a single-row arrangement of peripheral circuit units does not satisfy the second condition and / or the third condition.

[0034] Figure 9 for Figure 7 The layout diagram of the peripheral circuit units after position optimization.

[0035] Figure 10 The diagram shows a layout of a one-dimensional device array with an additional row of peripheral circuit units.

[0036] Figure 11 The diagram shows a layout of a row of peripheral circuit units added to a two-dimensional device array.

[0037] Figure 12 for Figure 10 The layout diagram of the peripheral circuit units after position optimization.

[0038] Figure 13 and Figure 14 Results of determining several target devices for two types of devices. DETAILED DESCRIPTION

[0039] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0040] It should be noted that the array in the present invention only refers to the arrangement of devices in the form of rows and columns, and does not mean that the devices in the rows and columns are arranged in a standard equal height or equal width, nor does it mean that it is a matrix arrangement, because the sizes of the devices in the array may be inconsistent, resulting in a different number of devices arranged in each row or column.

[0041] The first embodiment of the present invention provides a method for designing a peripheral circuit in a test chip. Figure 3 The design method specifically includes the following steps: obtaining device array information of devices in a test chip and information of a device to be tested selected from the devices; determining a peripheral circuit area on the test chip for placing peripheral circuits, wherein the peripheral circuit area is arranged around the device to be tested; and designing peripheral circuits based on edge rows and / or edge columns of the device array, specifically including: configuring corresponding peripheral circuit units for the devices to be tested located in the edge rows and / or edge columns in the peripheral circuit area, arranging the positions of the peripheral circuit units, connecting the devices to be tested with the corresponding peripheral circuit units through connecting lines to form a peripheral circuit, and controlling the connection or disconnection of the test path of the specified device to be tested in the device array through the peripheral circuit, and minimizing the total number of connecting lines used to connect the peripheral circuit units to form the peripheral circuit.

[0042] In this embodiment, selecting devices under test in the device array specifically involves determining a number of devices under test from devices in edge rows of the device array. In other embodiments, selecting devices under test in the device array may also be accomplished by determining a number of devices under test from devices in edge columns of the device array. Furthermore, in some device arrays with multiple rows and columns, selecting devices under test in the device array specifically involves first determining a number of devices under test from devices in edge rows and / or edge columns of the device array, and then determining a number of devices under test from devices in remaining rows and / or remaining columns of the device array.

[0043] In this embodiment, a corresponding peripheral circuit unit is configured for each device under test in an edge row or / and edge column. In other embodiments, corresponding peripheral circuit units can also be configured for certain specific devices under test according to actual needs.

[0044] When configuring and arranging peripheral circuit units for a device under test, the following steps are specifically included: First, the number of peripheral circuit units configured based on the device under test in the edge row is preset as M, and the number of peripheral circuit units configured based on the device under test in the edge column is preset as N. These numbers cannot be changed throughout the design process, for example, M=64 and N=64 are preset. The advantage of this preset limit is that it can ensure that the placement and connection of the peripheral circuits can be successfully completed. Based on this, when determining a number of devices under test from the devices in the edge row or / and edge column, the number of devices in the edge row or / and edge column is recorded as K. If the number of devices in the edge row is K≤M, all devices in the edge row are determined as devices under test. Similarly, if the number of devices in the edge column is K≤N, all devices in the edge column are determined as devices under test. If the number of devices in the edge row is K>M, M devices under test are selected from the devices in the edge row. Similarly, if the number of devices in the edge column is K>N, N devices under test are selected from the devices in the edge column.

[0045] After determining the devices under test, peripheral circuit units are configured for the devices under test and the peripheral circuit units are arranged. During the arrangement, the row direction of the edge rows or the column direction of the edge columns are defined as the X direction. When the arrangement is completed, the peripheral circuit units must meet the following conditions: a first condition: the projections of the peripheral circuit unit and its corresponding device under test in the X direction overlap; a second condition: the projections of the peripheral circuit units in the same row or column in the X direction do not overlap; and a third condition: the peripheral circuit unit is located in the peripheral circuit area.

[0046] The method for arranging the positions of the peripheral circuit units in the peripheral circuit area specifically includes: step S1. Note that the number of rows of the peripheral circuit unit array is i, and the number of rows is defined as the number of rows of the peripheral circuit unit array arranged based on the edge row configuration or the number of columns of the peripheral circuit unit array arranged based on the edge column configuration; based on the first condition, the peripheral circuit units are arranged in a single row, that is, i=1, and then it is determined whether the peripheral circuit units after the above-mentioned attempt to arrange in a single row meet the second and third conditions. If they meet, the position arrangement of the peripheral circuit units is completed and the processing ends. For example, Figure 3 FIG shows an arrangement diagram in which the peripheral circuit units are arranged in a single row in the row direction when the device is a one-dimensional array and the second and third conditions are satisfied. Figure 4 The figure shows the arrangement diagram that satisfies the second and third conditions after the peripheral circuits are arranged in a single row in both row and column directions when the device is a two-dimensional array. In this case, Figure 3 and Figure 4 There is no overlap between the peripheral circuit units in the figure, and none of them exceeds the peripheral circuit area, so the peripheral circuit is placed.

[0047] If the second or third condition is not met, then continue with the subsequent processing. For example, Figure 5 and Figure 6 The figure shows the situation where the second and third conditions are not met in a one-dimensional device array. Figure 5 After the single-row arrangement in step S1, the peripheral circuit units overlap and exceed the peripheral circuit area, that is, the second condition and the third condition are not met at the same time. Figure 6 After single-row arrangement, the peripheral circuit units overlap, that is, the second condition is not met. In other cases, only the third condition may not be met. In all the above cases, the subsequent steps need to be continued. For example, Figure 7 and Figure 8 The figure shows the situation in which the second and third conditions are not met in a two-dimensional device array. Figure 7 After the rows and columns are arranged in a single row, there are overlaps between the peripheral circuit units in the column direction and some peripheral circuit units exceed the peripheral circuit area. At the same time, the second and third conditions are not met. There are overlaps between the peripheral circuit units in the row direction and the second condition is not met. Figure 8 After the rows and columns are arranged in a single row, the column direction does not meet both the second and third conditions, and the row direction only does not meet the third condition. In both cases, the subsequent steps need to be continued.

[0048] Subsequent processing steps can increase the number of rows in the peripheral circuit unit array, or optimize the positional arrangement by adjusting the relative positions of the peripheral circuit units in the same row, and then increase the number of rows after the optimization attempt fails. This embodiment selects the optimal embodiment for illustration, that is, in this embodiment, optimization is performed first, and then the number of rows is increased after the optimization attempt fails. In other embodiments, the user may also directly choose to increase the number of rows for considerations such as time efficiency, and the present invention does not specifically limit this.

[0049] In this embodiment, when the second condition or the third condition is not met, step S1.1 is first performed. Based on the first condition, the positions of the peripheral circuit units in the same row in the X direction are adjusted to optimize the position arrangement, and it is determined whether the optimized position arrangement meets the second condition and the third condition; if so, the position arrangement of the plurality of peripheral circuit units is completed and the process ends; if the second condition or the third condition is not met, the process continues with the subsequent step S2. For example, Figure 9 Shown Figure 7 The peripheral circuit units are arranged to meet the second and third conditions after optimization and adjustment in step S1.1. It should be noted that the optimized position arrangement in step S1.1 is to try all possible arrangements. If the second and third conditions are still not met, the subsequent step S2 will be processed. For example, Figure 5 and Figure 8 The peripheral circuit units in Figure 5 After trying all possible solutions, the peripheral circuit units in the peripheral circuit unit will inevitably exceed the peripheral circuit area when ensuring that there is no overlap between the peripheral circuit units, or will inevitably overlap when ensuring that there is no overlap between the peripheral circuit units. Figure 5 Then it is necessary to continue processing at step S2; for example, Figure 8 The column direction peripheral circuit unit in Figure 5 In the same situation, it is also necessary to continue processing at step S2.

[0050] Step S2 includes: increasing the number of rows of the peripheral circuit unit array, that is, setting i=i+1, moving any one of the two peripheral circuit units that overlap in the X direction to a new row perpendicular to the X direction, and / or moving the peripheral circuit units that exceed the peripheral circuit area to a new row based on satisfying the first condition, and then determining whether the rearranged peripheral circuit units meet the second and third conditions. If so, the position arrangement of the peripheral circuit units is completed and the process ends. For example, Figure 10 and Figure 11 The figure shows the arrangement of the peripheral circuits with an additional row of arrangement in the one-dimensional and two-dimensional device array states, wherein: Figure 11 yes Figure 8The arrangement diagram after processing in step S2: If the first condition or the second condition is not satisfied, the process goes back to step S2 and loops through.

[0051] To further optimize the arrangement of the peripheral circuit units, this embodiment further includes step S3. On the basis of satisfying the first, second, and third conditions, the positions of the peripheral circuit units in the same row in the X direction are adjusted to optimize the position arrangement so that the total number of connection lines used to connect the device under test and its corresponding peripheral circuit units to form a peripheral circuit is the shortest, and this arrangement position is used as the final arrangement position. Figure 12 Shown Figure 10 The peripheral circuit arrangement obtained after the optimization and adjustment in step S3. It should be noted that in actual applications, the user may not perform this step, and the present invention does not impose any specific limitation on this.

[0052] In addition, in this embodiment, determining the device under test among the devices inside the edge row or / and edge column means determining a number of devices under test row by row or / and column by column starting from the end of the edge row or / and edge column. Figure 13 and Figure 14 As shown, starting from the end of the edge row or edge column, the determination of the DUT in each row or column is completed step by step from the outside to the inside. If there are multiple DUTs to choose from, the one with the shorter connection line distance is selected. Of course, it can also be selected according to the requirements of external input; Figure 13 and Figure 14 In the diagram, the selected DUT is shaded, and unselected devices are displayed as blank boxes. Subsequent connections can also follow this order: starting from the end of an edge row or column, connect the DUT to its corresponding peripheral circuit unit row or column by row to form a peripheral circuit.

[0053] In this embodiment, the peripheral circuit region is disposed between the device array and the pad region, or / and between the device array and the edge of the test chip. The peripheral circuit unit is a switching circuit unit, and the on / off state of the switch in the switching circuit unit is used to select whether a specific device under test is connected or disconnected. In addition to the peripheral circuit units, the peripheral circuit also includes an addressing circuit. The output of the addressing circuit is connected to the input of the peripheral circuit unit, i.e., the switching circuit unit, for sending an address signal to the switching circuit unit to control the on / off state of the switch.

[0054] Another embodiment of the present invention provides a test chip, comprising a plurality of devices to be tested and a plurality of peripheral circuits. The plurality of devices to be tested form at least one device array, and the peripheral circuit comprises a plurality of peripheral circuit units, which control the connection or / and disconnection of the test path of the specified device to be tested in the device array through the peripheral circuit; wherein the peripheral circuit is designed and implemented by the design method of the peripheral circuit in the test chip in the above embodiment. According to comparative experiments, the device density of the test chip designed using the design method of the present invention can be further improved compared with the test chip designed using the prior art method, and the number of metal interconnection layers can be effectively reduced, with significant effects. The comparative data are shown in Table 1 below.

[0055] Table 1

[0056]

[0057]

[0058] The above description is only the preferred embodiment of this description, and it cannot be used to limit the scope of implementation of the present invention. That is, all simple equivalent changes and modifications made in accordance with the claims and description of the present invention are still within the scope of the patent of the present invention. In addition, any embodiment or claim of the present invention is not required to achieve all the purposes, advantages or features disclosed by the present invention. In addition, the abstract and the name of the invention are only used to assist in the retrieval of patent documents and are not used to limit the scope of rights of the present invention. In addition, the terms "first", "second", etc. mentioned in this description or claims are only used to name the name of the element or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements.

Claims

1. A method for designing peripheral circuits in a test chip, characterized in that: The steps include: Acquiring device array information of devices in the test chip and information of a device to be tested selected from the devices; determining a peripheral circuit area on the test chip for placing peripheral circuits; Designing peripheral circuits based on edge rows and / or edge columns of the device array includes: In the peripheral circuit area, corresponding peripheral circuit units are configured for the devices under test located in the edge rows and / or edge columns, and the peripheral circuit units are arranged in positions. The devices under test are connected to the corresponding peripheral circuit units via connecting wires to form a peripheral circuit, which is used to control the connection or disconnection of the test path of the specified device under test in the device array through the peripheral circuit; Each device under test in the edge row and / or edge column is respectively configured with a corresponding peripheral circuit unit.

2. The method for designing peripheral circuits in a test chip according to claim 1, wherein: The total number of connection lines of the peripheral circuit is the shortest.

3. The method for designing a peripheral circuit in a test chip according to claim 1 or 2, wherein: The method further includes selecting devices to be tested from the devices, which includes determining a number of devices to be tested from devices in edge rows and / or edge columns of the device array; when the device array has multiple rows and columns, the method also includes determining a number of devices to be tested from devices in the remaining rows and / or remaining columns of the device array.

4. The method for designing peripheral circuits in a test chip according to claim 1, wherein: The number of peripheral circuit units configured based on the device under test in the edge row is preset as M, or / and, the number of peripheral circuit units configured based on the device under test in the edge column is preset as N; the number of devices in the edge row or / and edge column is denoted as K, and determining a number of devices under test from the devices in the edge row or / and edge column includes: If the number of devices in the edge row K≤M or / and the number of devices in the edge column K≤N, all devices in the edge row and / or edge column are determined as devices to be tested; If the number of devices in the edge row K>M, then M devices are selected from the devices in the edge row as devices to be tested, or / and, if the number of devices in the edge column K>N, then N devices are selected from the devices in the edge column as devices to be tested.

5. The method for designing peripheral circuits in a test chip according to claim 1, wherein: The row direction of the edge row or the column direction of the edge column is defined as the X direction, and the peripheral circuit units meet the following three conditions when the position arrangement is completed: First condition: the projection of the peripheral circuit unit and its corresponding device under test in the X direction overlaps; Second condition: the projections of peripheral circuit units in the same row or column in the X direction do not overlap; Third condition: the peripheral circuit unit is located in the peripheral circuit area.

6. The method for designing peripheral circuits in a test chip according to claim 5, wherein: The method for arranging the positions of the peripheral circuit units includes: Step S1. The number of rows of the peripheral circuit unit array is recorded as i, where the number of rows refers to the number of rows of the peripheral circuit unit array arranged based on the edge row configuration or the number of columns of the peripheral circuit unit arrays arranged based on the edge column configuration; Based on the first condition, the peripheral circuit units are arranged in a single row, i.e., i=1, and then it is determined whether the peripheral circuit units arranged in a single row meet the second and third conditions; If the conditions are met, the arrangement of the positions of the peripheral circuit units is completed and the process ends; if the second condition or the third condition is not met, the process proceeds to step S2; Step S2. Increasing the number of rows of the peripheral circuit unit array by one row, i.e., setting i=i+1, moving any one of two peripheral circuit units whose projections overlap in the X direction to a new row perpendicular to the X direction, and / or moving peripheral circuit units that exceed the peripheral circuit area to a new row on the basis of satisfying the first condition, and then determining whether the rearranged peripheral circuit units satisfy the second and third conditions; If so, the arrangement of the positions of the peripheral circuit units is completed and the process ends; if the second condition or the third condition is not met, the process goes back to step S2 and loops through the process.

7. The method for designing peripheral circuits in a test chip according to claim 6, wherein: Step S1 and step S2 also include, on the basis of satisfying the first condition, the second condition and the third condition, optimizing the position arrangement by adjusting the positions of the peripheral circuit units in the same row in the X direction so that the total number of connection lines used to connect the device under test and the corresponding peripheral circuit units to form a peripheral circuit is the shortest.

8. The method for designing peripheral circuits in a test chip according to claim 6, wherein: If the second condition or the third condition is not satisfied in step S1, before proceeding to step S2, step S1.1 is added: based on the first condition, after adjusting the position arrangement of the peripheral circuit units in the same row in the X direction, it is determined whether the second condition and the third condition are satisfied; If so, the arrangement of the positions of the peripheral circuit units is completed and the process ends; if the second condition or the third condition is not met, the process continues at step S2.

9. The method for designing a peripheral circuit in a test chip according to claim 1 or 2, characterized in that: The peripheral circuit area is arranged between the device array and the pad area, or / and, between the device array and the edge of the test chip.

10. The method for designing peripheral circuits in a test chip according to claim 3, wherein: The peripheral circuit unit is a switch circuit unit, and the connection or disconnection of a specified device under test is selected by the on-off state of the switch circuit unit.

11. The method for designing peripheral circuits in a test chip according to claim 10, wherein: The peripheral circuit further includes an addressing circuit, the output end of which is connected to the input end of the switch circuit unit and is used to send an address signal to the switch circuit unit to control the on and off of the switch circuit unit.

12. A test chip, characterized in that: The invention comprises a plurality of devices under test and a plurality of peripheral circuits, wherein the plurality of devices under test form at least one device array, and the peripheral circuit comprises a plurality of peripheral circuit units, and the peripheral circuit is used to control the connection or / and disconnection of the test path of the specified devices under test in the device array; wherein the peripheral circuit is designed and implemented by the design method of the peripheral circuit in the test chip according to any one of claims 1 to 11.

Images