Target interface testing method and apparatus

Abstract

Embodiments of the present specification provide a target interface test method and device, wherein the target interface test method comprises: determining at least one initial order-preserving rule test item of a target interface according to a communication interface in a test device, determining a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement, determining an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter, sending a test instruction to the test device according to the parameter value of the initial test parameter, and receiving a test result of the target order-preserving rule test item of the target interface by the test device according to the test instruction. The initial order-preserving rule test item that can be tested is determined according to the communication interface of the test device, and the order-preserving rule of the target interface is tested by using a lower cost, so that the cost of the order-preserving rule test of the target interface is reduced, and the difficulty of the order-preserving rule test of the target interface is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to the technical field of hardware testing, and in particular, to a target interface testing method, a target interface testing device, a computing device, and a computer-readable storage medium. BACKGROUND

[0002] PCIe is the full name of Peripheral Component Interconnect Express, which is a high-speed serial communication standard. PCIe is an important high-speed channel for servers. In the server productization process, PCIe needs to be fully tested. Ordering is a sequencing rule in the PCIe transaction transmission process. Meeting this rule can avoid transaction transmission process exceptions such as deadlock and function error. Most PCIe features can be tested by purchasing EP devices with specific functions or through professional PCIe protocol analysis instruments. However, as an entirely transparent feature to users, there is currently no method to test this feature specifically. SUMMARY

[0003] Therefore, the embodiments of the present specification provide a target interface testing method. One or more embodiments of the present specification also relate to a target interface testing device, a computing device, a computer-readable storage medium, and a computer program to solve the technical defects in the prior art.

[0004] According to a first aspect of the embodiments of the present specification, a target interface testing method is provided, including:

[0005] determining at least one initial sequencing rule test item of the target interface according to a communication interface in a test device;

[0006] determining a target sequencing rule test item from the at least one initial sequencing rule test item according to a preset requirement;

[0007] determining an initial test parameter corresponding to the target sequencing rule test item and a parameter value of the initial test parameter;

[0008] sending a test instruction to the test device according to the parameter value of the initial test parameter;

[0009] receiving a test result of the target sequencing rule test item of the target interface by the test device according to the test instruction.

[0010] Optionally, the determining of the initial test parameter corresponding to the target sequencing rule test item and the parameter value of the initial test parameter includes:

[0011] determining a configuration signal of the test equipment corresponding to the target order-preserving rule test item, and setting a first signal value for the configuration signal.

[0012] Optionally, the determining the initial test parameter and the parameter value of the initial test parameter corresponding to the target order-preserving rule test item comprises:

[0013] determining a configuration signal of the test equipment corresponding to the target order-preserving rule test item, and a test timeout time;

[0014] setting a first signal value for the configuration signal, and determining a timeout time value of the test timeout time.

[0015] Optionally, the sending the test instruction to the test equipment according to the parameter value of the initial test parameter comprises:

[0016] sending a memory read instruction to the test equipment according to the first signal value and the timeout time value of the initial test parameter through a preset time interval, wherein the first signal value is used to limit the credit value recovery of the test equipment, and the credit value is used to determine whether the test equipment executes the test instruction;

[0017] in a case where it is determined that the credit value of the test equipment is exhausted and the current time is less than the timeout time value, sending a memory write instruction to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used to recover the credit value of the test equipment.

[0018] Optionally, the sending the test instruction to the test equipment according to the parameter value of the initial test parameter comprises:

[0019] sending a configuration write instruction to the test equipment according to the first signal value of the initial test parameter through a preset time interval, wherein the first signal value is used to limit the credit value recovery of the test equipment, and the credit value is used to determine whether the test equipment executes the test instruction;

[0020] in a case where it is determined that the credit value of the test equipment is exhausted, sending a memory write instruction to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used to recover the credit value of the test equipment.

[0021] Optionally, the sending the test instruction to the test equipment according to the parameter value of the initial test parameter comprises:

[0022] sending a memory read instruction request to the test equipment according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used to limit the test equipment to receive a read completion packet;

[0023] in case that the memory read instruction sent by the test device is received and the current time is less than the timeout time value, sending a read completion message to the test device and sending a memory write instruction, and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to receive the read completion message.

[0024] Optionally, the sending of the test instruction to the test device according to the parameter value of the initial test parameter comprises:

[0025] sending a memory write instruction to the test device according to a first signal value of the initial test parameter, wherein the first signal value is used to limit the test device to execute the test instruction;

[0026] in case that no return message of the test device for the memory write instruction is received, sending a memory read instruction request to the test device;

[0027] in case that the memory read instruction sent by the test device is received, sending a read completion message to the test device and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to execute the test instruction.

[0028] Optionally, the sending of the test instruction to the test device according to the parameter value of the initial test parameter comprises:

[0029] sending a memory read instruction to the test device according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used to limit the test device to execute the test instruction;

[0030] in case that no return message of the test device for the memory read instruction is received and the current time is less than the timeout time value, sending a memory read instruction request to the test device;

[0031] in case that the memory read instruction sent by the test device is received, sending a read completion message to the test device and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to execute the test instruction.

[0032] Optionally, the sending of the test instruction to the test device according to the parameter value of the initial test parameter comprises:

[0033] sending a configuration write instruction to the test device according to the first signal value of the initial test parameter, wherein the first signal value is used to limit the credit value of the test device to restore, and the credit value is used to determine whether the test device executes the test instruction.

[0034] in a case where it is determined that the credit value of the test device is exhausted, sending a memory read instruction request to the test device;

[0035] in a case where the memory read instruction sent by the test device is received, sending a read completion message to the test device, and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the credit value of the test device.

[0036] Optionally, the receiving the test result of the target order-preservation rule test item of the target interface by the test device according to the test instruction comprises:

[0037] in a case where the response information returned by the test device is received within the test timeout time, determining that the test result of the target order-preservation rule test item of the target interface is successful.

[0038] Optionally, the receiving the test result of the target order-preservation rule test item of the target interface by the test device according to the test instruction comprises:

[0039] in a case where the response information returned by the test device is received, determining that the test result of the target order-preservation rule test item of the target interface is successful.

[0040] Optionally, the receiving the test result of the target order-preservation rule test item of the target interface by the test device according to the test instruction comprises:

[0041] in a case where the response information returned by the test device is received within the test timeout time, and the value of the response information satisfies a preset response condition, determining that the test result of the target order-preservation rule test item of the target interface is successful.

[0042] Optionally, the communication interface comprises a first communication interface, a second communication interface, a third communication interface and a fourth communication interface;

[0043] the first communication interface is used for transmitting a memory read instruction or a memory write instruction of the host computer to the test device;

[0044] the second communication interface is used for transmitting a memory read completion message of the test device to the host computer;

[0045] the third communication interface is used for transmitting the memory read instruction or the memory write instruction of the test device to the host computer;

[0046] the fourth communication interface is used for transmitting the memory read completion message of the host computer to the test device.

[0047] According to a second aspect of the embodiments of the present specification, a target interface testing apparatus is provided, comprising:

[0048] An initial item determining module configured to determine at least one initial order-preserving rule test item of the target interface according to a communication interface in the testing device;

[0049] A target item determining module configured to determine a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement;

[0050] A parameter determining module configured to determine an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter;

[0051] A testing module configured to send a test instruction to the testing device according to the parameter value of the initial test parameter;

[0052] A receiving module configured to receive a test result of the target order-preserving rule test item of the target interface by the testing device according to the test instruction.

[0053] According to a third aspect of the embodiments of the present specification, a computing device is provided, comprising:

[0054] A memory and a processor;

[0055] The memory is configured to store computer executable instructions, and the processor is configured to execute the computer executable instructions, and the computer executable instructions, when executed by the processor, implement the steps of the target interface testing method.

[0056] According to a fourth aspect of the embodiments of the present specification, a computer readable storage medium is provided, which stores computer executable instructions, and the computer executable instructions, when executed by a processor, implement the steps of the target interface testing method.

[0057] According to a fifth aspect of the embodiments of the present specification, a computer program is provided, and when the computer program is executed in a computer, the computer program causes the computer to execute the steps of the target interface testing method.

[0058] The target interface test method provided in the specification comprises: determining at least one initial order-preserving rule test item of the target interface according to a communication interface in a test device, determining a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement, determining an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter, sending a test instruction to the test device according to the parameter value of the initial test parameter, and receiving a test result of the target order-preserving rule test item of the target interface in the test device according to the test instruction. The embodiment of the specification determines the initial order-preserving rule test item that can be tested by the communication interface of the test device, uses a lower cost to test the order-preserving rule of the target interface, reduces the cost of testing the order-preserving rule of the target interface, and reduces the difficulty of testing the order-preserving rule of the target interface. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1 is a scene schematic diagram of an application scenario of a target interface test method provided by an embodiment of the specification;

[0060] Figure 2 is a flowchart of a target interface test method provided by an embodiment of the specification;

[0061] Figure 3 is an architectural diagram of a target interface test method provided by an embodiment of the specification;

[0062] Figure 4 is an interface signal schematic diagram of a target interface test method provided by an embodiment of the specification;

[0063] Figure 5 is another flowchart of a target interface test method provided by an embodiment of the specification;

[0064] Figure 6 is a structural schematic diagram of a target interface test device provided by an embodiment of the specification;

[0065] Figure 7 is a structural block diagram of a computing device provided by an embodiment of the specification. DETAILED DESCRIPTION

[0066] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the specification. However, the specification can be implemented in many different ways from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the specification, so the specification is not limited by the specific implementation disclosed below.

[0067] The terminology used in this disclosure, one or more embodiments of the present specification, is for the purpose of describing particular embodiments only and is not intended to be limiting of one or more embodiments of the present specification. As used in this disclosure and the appended claims herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used in this disclosure, refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0068] It should be understood that although the terms first, second, etc. can be employed in this disclosure, one or more embodiments of the present specification, to describe various information, these information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information of the same type. For example, without departing from the scope of one or more embodiments of the present specification, first can also be referred to as second, and similarly, second can also be referred to as first. Depending on the context, the word "if" as used herein can be interpreted as meaning "when" or "in response to determining" or "in response to ascertaining".

[0069] Firstly, the noun terms related to one or more embodiments of the present specification are explained.

[0070] PCIe: The full name is Peripheral Component Interconnect Express, which is a high-speed serial communication standard.

[0071] Ordering: A sequencing rule in the process of PCIe transaction transmission. The sequencing rule is a rule for limiting the order of PCIe transaction transmission. The sequencing rule guarantees the ordered completion of transactions and avoids problems such as deadlock and conflict.

[0072] Credit: A flow control algorithm used by PCIe bus. The available buffer quantity of the receiving end is represented by credit value. When the credit value of the buffer is exhausted, the sending end will stop sending data.

[0073] CPU: Central processing unit (CPU) as the operation and control core of computer system, is the final execution unit of information processing and program running.

[0074] RAM: Random Access Memory (RAM), also known as main memory, is an internal memory that exchanges data directly with CPU. It is usually used as a temporary data storage medium for operating systems or other running programs.

[0075] In the specification, a target interface test method is provided, and the specification also relates to a target interface test device, a computing device, a computer readable storage medium and a computer program, which are described in detail one by one in the following embodiments.

[0076] In the following, a target interface test device, a computing device, a computer readable storage medium and a computer program according to an embodiment of the specification will be described in detail with reference to the accompanying drawings.

[0077] Figure 1 FIG. 1 is a scene diagram of an application scenario of a target interface test method according to an embodiment of the specification. The application scenario can include a host computer 102 and a test device 104.

[0078] The host computer 102 can be a device including at least a processor 1022 (CPU), a target interface 1026, a memory 1024 (RAM) and a bus, and an operating system. Here, the host computer 102 can be a personal computer (Personal Computer), a server (server), etc. computing device, and can also be a computing device applied in different fields. For example, the host computer 102 can be a personal computer including the target interface 1026, which can be connected to the test device 104 through the target interface 1026, and can send test instructions to the test device 104 through the operating system.

[0079] The test device 104 can be a circuit board supporting the function of communicating with the host computer 102. Here, the test device 104 can be an FPGA with the target interface 1026, and can also be a device with the target interface 1026 applied in different fields. For example, the test device 104 can be an FPGA supporting the target interface 1026.

[0080] The host computer 102 can be connected to the test device 104 through the target interface 1026 to receive or send information, etc. Specifically, the host computer 102 determines at least one initial order-preserving rule test item of the target interface 1026 according to the communication interface in the test device 104, determines the target order-preserving rule test item from the at least one initial order-preserving rule test item according to the preset requirement, determines the initial test parameter corresponding to the target order-preserving rule test item and the parameter value of the initial test parameter, sends the test instruction to the test device 104 according to the parameter value of the initial test parameter, and receives the test result of the target order-preserving rule test item of the target interface 1026 of the test device 104 according to the test instruction, so that the target interface 1026 test method of the embodiment of the specification can test the target interface 1026.

[0081] It should be noted that the specific types, quantities and combinations of the host computer 102, the target interface 1026 and the test device 104 can be adjusted according to actual requirements of application scenarios, and the embodiments of the specification do not limit this.

[0082] Figure 2 A flowchart of a target interface test method according to one embodiment of the specification is shown, which is applied to a host computer and specifically includes the following steps.

[0083] Step 202: Determine at least one initial ordering rule test item of the target interface according to the communication interface in the test device.

[0084] Wherein, the specific explanation of the host computer can be referred to the above-mentioned embodiments, which will not be repeated here; the test device can be understood as a device cooperating with the host computer to complete the test of the target interface; the communication interface can be understood as a channel for signal transmission, such as the interface on the test device; in actual application, the test device connects the host computer through the communication interface and communicates with the host computer through the communication interface; and the target interface can be understood as the interface to be tested on the host computer.

[0085] The ordering rule can be understood as the rule of the target interface in the transaction transmission process, which can avoid abnormality such as deadlock and function error in the transaction transmission process. Wherein, the deadlock refers to a blocking phenomenon caused by competition for resources or communication with each other in the execution process of two or more transactions, and without external force, two or more transactions will not be able to proceed.

[0086] Then the initial ordering rule test item can be understood as the test item determined according to the communication interface, which can be determined according to the function of the communication interface.

[0087] In actual application, the initial ordering rule test item of the target interface in the host computer determined is different according to the communication interface on the test device, that is, the executable instruction can be determined according to the function of the communication interface on the test device, and the initial ordering rule test item that can be performed can be determined based on the executable instruction. The specific implementation mode is as follows:

[0088] In one embodiment, the communication interface includes a first communication interface, a second communication interface, a third communication interface and a fourth communication interface;

[0089] The first communication interface is used to transmit the memory read instruction or the memory write instruction of the host computer to the test device;

[0090] The second communication interface is configured to transmit the memory read completion message from the test device to the host computer.

[0091] The third communication interface is configured to transmit the memory read instruction or the memory write instruction from the test device to the host computer.

[0092] The fourth communication interface is configured to transmit the memory read completion message from the host computer to the test device.

[0093] With the test device being an FPGA, the communication interfaces on the FPGA include a first communication interface, a second communication interface, a third communication interface and a fourth communication interface, the at least one initial order-preserving rule test item for determining the target interface according to the communication interfaces in the test device is described in detail.

[0094] Referring to Figure 3 , Figure 3 An architecture diagram of a target interface test method provided by one embodiment of the present specification is shown.

[0095] Figure 3 In the embodiment, the test device is an FPGA, the host computer is a server, and the target interface is a PCIe interface on the server.

[0096] The FPGA includes a PCIe core and four communication interfaces, which are cc, cq, rq and rc. The cq is configured to transmit the memory read instruction or the memory write instruction from the host computer to the FPGA, the cc is configured to transmit the memory read completion message from the FPGA to the host computer, the rq is configured to transmit the memory read instruction or the memory write instruction from the FPGA to the host computer, and the rc is configured to transmit the memory read completion message from the host computer to the FPGA.

[0097] Therefore, in the case that the communication interfaces of the FPGA are cc, cq, rq and rc, the selection of the at least one initial order-preserving rule test item for the target interface can refer to Table 1.

[0098] Table 1

[0099]

[0100] As shown in Table 1, the initial order-preserving rule test items that can be determined based on the cc, cq, rq and rc interfaces include the test items of memory write overriding memory read (row A, column 3), memory write overriding another memory write (row B, column 3), memory write overriding memory read completion (row A, column 5b), memory read completion overriding memory write (row D, column 2b), memory read completion overriding memory read request (row D, column 3), and memory read completion overriding another memory read completion (row D, column 5).

[0101] The target interface test method provided by the embodiment of the present specification can realize the test of the order preservation rule of the target interface by using only four communication interfaces of the FPGA, so that the test of the order preservation rule of the target interface becomes feasible, and the test cost is low and the test difficulty is reduced.

[0102] Step 204: determining a target order preservation rule test item from at least one initial order preservation rule test item according to a preset requirement.

[0103] The preset requirement can be set according to actual application, for example, the two initial order preservation rule test items of memory write surpassing memory read completion and memory read completion surpassing memory read request can be selected as the target order preservation rule test item according to the preset requirement.

[0104] The target order preservation rule test item can be understood as one, two or more initial order preservation rule test items selected from the initial order preservation rule test items according to the preset requirement, that is, the initial order preservation rule test item that needs to be tested subsequently.

[0105] In actual application, the initial order preservation rule test items do not necessarily need to be tested completely, and the test item that needs to be tested can be determined from the initial order preservation rule as the target order preservation rule test item for testing according to the preset requirement.

[0106] The target interface test method provided by the embodiment of the present specification can determine the target order preservation rule test item that needs to be tested from a plurality of initial order preservation rule test items according to a preset requirement, so as to realize the customizability of the test scheme, select different target order preservation rule test items for different test purposes, increase the diversity of the scheme, and improve the universality.

[0107] Step 206: determining the initial test parameter corresponding to the target order preservation rule test item and the parameter value of the initial test parameter.

[0108] The initial test parameter can be an initial parameter set for different target order preservation rule test items before testing.

[0109] In actual application, the test methods for different target order preservation rule test items are different, so in order to be able to perform the subsequent test steps, the initial test parameter and the corresponding parameter value need to be set for each target order preservation rule test item, so as to ensure that the current target order preservation rule test item can be performed smoothly.

[0110] Specifically, the initial test parameter and the corresponding parameter value that need to be set for each target order preservation rule test item are different according to the different target order preservation rule test items. The specific implementation manner is as follows:

[0111] The determining the initial test parameter corresponding to the target order-preserving rule test item and the parameter value of the initial test parameter comprises:

[0112] The configuration signal of the test equipment corresponding to the target order-preserving rule test item is determined, and a first signal value is set for the configuration signal.

[0113] The configuration signal can be understood as a signal for setting the test equipment, and the configuration signal can be pulled high or pulled low. Pulled low means setting the value of the configuration signal to 0, and pulled high means setting the value of the configuration signal to 1.

[0114] The first signal value can be 0. In the case where the first signal value is 0, setting the first signal value for the configuration signal is to set the configuration signal to a low level.

[0115] In actual application, some target order-preserving rule test items need to send a configuration signal to the test equipment and set a first signal value before performing subsequent test steps.

[0116] For example, in the case where the server determines that the memory write surpassing the memory read completion is the target order-preserving rule test item, the server looks up the configurations required before the test of the memory write surpassing the memory read completion from the database, and determines the configuration signal of the test equipment corresponding to the target order-preserving rule test item according to the required configurations, and sets a first signal value for the configuration signal.

[0117] The target interface test method provided by the embodiments of the present specification can customize the test of the target interface according to the initial test parameter and the parameter value of the initial test parameter of the target order-preserving rule test item, determine different test environments for different situations of the target interface, and improve the accuracy of the test result.

[0118] In another implementation example, in the case where the target order-preserving rule test item is different, not only the configuration signal of the target order-preserving rule test item needs to be set, but also a test timeout time needs to be set. The specific implementation manner is as follows:

[0119] The determining the initial test parameter corresponding to the target order-preserving rule test item and the parameter value of the initial test parameter comprises:

[0120] The configuration signal of the test equipment corresponding to the target order-preserving rule test item is determined, and a first signal value is set for the configuration signal.

[0121] The configuration signal of the test equipment corresponding to the target order-preserving rule test item is determined, and a first signal value is set for the configuration signal.

[0122] The configuration signal and the first signal value are specifically explained in the above embodiments, which will not be repeated here.

[0123] The test timeout time can be understood as a maximum waiting time counted from sending the test instruction, and a value greater than or equal to the timeout time triggers the occurrence of a timeout event (completion timeout).

[0124] In actual use, some order-preserving rule test items not only need to send a configuration signal to the test device and set a first signal value, but also need to set a timeout time value for determining the test timeout time.

[0125] For example, in the case of determining the memory write surpasses the memory read completion as the target order-preserving rule test item, first, the first signal value is set for the configuration signal, and further, the test timeout time needs to be set. The timeout time value can range from 4 seconds to 64 seconds. The timeout time value of the test timeout time can be understood as a fixed value set according to actual application experience, or different values can be set according to different target order-preserving rule test items. The embodiments of the present specification do not limit this.

[0126] The embodiments of the present specification determine the initial test parameters and the parameter values of the initial test parameters according to the target order-preserving rule test item, which can customize the test of the target interface. Different test environments are determined for different situations of the target interface, which improves the accuracy of the test results. Setting the test timeout time can reserve time to send other test instructions, which ensures the feasibility of the test.

[0127] Step 208: sending a test instruction to the test device according to the parameter value of the initial test parameter.

[0128] The test instruction can be an instruction sent by the host to the test device for testing. The form of the test instruction can be set according to the type of the test device, or it can be a self-defined instruction, such as devmem or setpci. The embodiments of the present specification do not limit this.

[0129] In actual application, the test of the target order-preserving rule test item can be understood as sending a test instruction to the test device based on the host, so that the host and the test device communicate, thereby completing the test of the target interface.

[0130] Following the above example, in the case of the target order-preserving rule test item being the memory write surpasses the memory read test item, the specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows:

[0131] The sending of the test instruction to the test device according to the parameter value of the initial test parameter includes:

[0132] According to the first signal value and the timeout time value of the initial test parameter, a memory read instruction is sent to the test device through a preset time interval, wherein the first signal value is used to limit the credit value recovery of the test device, and the credit value is used to determine whether the test device executes the memory read instruction;

[0133] In a case where it is determined that the credit value of the test device is exhausted and the current time is less than the timeout time value, a memory write instruction is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to recover the credit value of the test device.

[0134] The first signal value used to limit the credit value recovery of the test device can be understood as prohibiting the credit value recovery in a case where the configuration signal is the first signal value. The credit value used to determine whether the test device executes the memory read instruction can be understood as the credit value being used to determine whether the test device receives the test instruction.

[0135] For example, referring to Figure 4 , Figure 4The diagram illustrates the interface signals of a target interface testing method. The configuration signal can be the PCie_cq_np_req signal, and the first signal value can be 0 (low level). The PCie_cq_np_req signal is used to disable the credit update of memory read instructions or configuration read instructions and configuration write instructions. When the value of the PCie_cq_np_req signal is 0, the credit value will be exhausted according to the number of times the test instruction is executed, thereby causing the test instruction to be suspended. The PCie_cq_np_req signal is mapped to the PCIe bar space and can be read and written controlled by the host machine. For example, a target order-preserving rule test could be a test where memory writes outpace memory reads. The host machine sets the value of the PCIE_CQ_NP_ReQ signal to 0 via memory writes and sets a timeout of 4 seconds. The host machine sends memory read commands to the test device at one-second intervals. Each time the test device executes a memory read command sent by the host machine, a credit value is consumed. The initial value of the credit value can be 32, and the data size of the memory read command can be 8 bits to 64 bits. When the credit value is exhausted, the memory read command is suspended and no longer executed by the test device. Furthermore, if the host machine does not receive a read completion message from the test device, the host machine will no longer send memory read commands to the test device. The timing will start from the last memory read command sent by the host machine. If the timing time is less than the timeout value, the host machine will send a memory write command to the test device and set the value of the PCie_cq_np_req signal to the second signal value through memory write. The second signal value can be 1 (high level). When the value of the PCie_cq_np_req signal is set to 1, the credit value is returned, that is, the credit value is restored to 32, so that the suspended memory read command can continue to be executed.

[0136] The embodiments in this specification can test memory writes that exceed memory reads using only two test instructions between the host machine and the test device, which simplifies the test program and improves test efficiency.

[0137] Continuing with the previous example, when the target order-preserving rule test item is a test item where memory writes exceed another memory write, the specific implementation method for sending test commands to the test device based on the initial test parameter values ​​is as follows:

[0138] Sending test instructions to the test device based on the parameter values ​​of the initial test parameters includes:

[0139] Based on the first signal value of the initial test parameters, a first memory write instruction is sent to the test device, wherein the first signal value is used to restrict the test device from executing the first memory write instruction;

[0140] When the test device does not return a message for the first memory write instruction, a second memory write instruction is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device to execute the first memory write instruction.

[0141] For example, the host sets the value of the M_axis_cq_tready signal to 0 by configuration write, and specifically, the configuration write instruction can access the MSI MASK field of the ECAM space of the test device. The change of the MSI MASK field is reflected to the interface signal of the test device as the cfg_interrupt_msi_data signal, which is used to control the test logic to set the M_axis_cq_tready to 0, thereby preventing the first memory write operation from passing. That is, the memory write operation for controlling the generation of the MSIX interrupt cannot pass, the first memory write instruction is blocked, and the test device does not generate the MSIX interrupt. Then, a second memory write instruction is sent to the test device, and the address and data carried by the write instruction are both special values. In the test logic, the address and data fields of the m_axis_cq_tdata are parsed to obtain the expected special values, and then the M_axis_cq_tready is set to 1. Then, it is determined whether the MSIX is generated. If the MISX is generated, it is indicated that the second memory write successfully overrides the first memory write.

[0142] The embodiment of the present specification can test the test item of memory write overriding another memory write based on two test instructions between the host and the test device, so that the test program is simple, and the test efficiency is improved.

[0143] In the case where the target order preservation rule test item is the test item of memory write overriding memory read completion, the specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows according to the above example:

[0144] According to the first signal value and the timeout time value of the initial test parameter, a memory read instruction is sent to the test device, wherein the first signal value is used to limit the test device to receive a read completion message.

[0145] When the test device sends the memory read instruction, and the current time is less than the timeout time value, the read completion message and a memory write instruction are returned to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device to receive the read completion message.

[0146] Specifically, the configuration signal can be an M_axis_rc_tready signal, and the first signal value can be 0. For example, the target order-preservation rule test item can be a test item of memory write overriding memory read completion. The host sets the value of the M_axis_rc_tready signal to 0 through memory write, sets a timeout time value to 4 seconds, sends a memory read instruction request to the test device, and sends a memory read instruction to the host after receiving the memory read instruction request. Because the M_axis_rc_tready signal is set to 0, the read completion message sent by the host is locked after the memory read instruction is executed by the host, the test device cannot receive the read completion message returned by the host, the test device no longer sends a memory read instruction to the host, and the memory read instruction sent by the test device is timed. If the timing time is less than the timeout time value, the host sends a memory write instruction to the test device, sets the value of the M_axis_rc_tready signal to a second signal value through memory write, and the second signal value can be 1, so that the test device receives the read completion message.

[0147] The embodiment of the present specification can test the test item of memory write overriding memory read completion based on two test instructions between the host and the test device, so that the test procedure is simple, and the test efficiency is improved.

[0148] In the above example, in the case where the target order-preservation rule test item is a test item of memory read completion overriding memory write, the specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows:

[0149] The sending of the test instruction to the test device according to the parameter value of the initial test parameter includes:

[0150] According to the first signal value of the initial test parameter, a memory write instruction is sent to the test device, wherein the first signal value is used to limit the test device to execute the memory write instruction.

[0151] When a return message of the test device for the memory write instruction is not received, a memory read instruction request is sent to the test device.

[0152] In the case where the memory read instruction sent by the test device is received, a read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device to execute the memory write instruction.

[0153] Specifically, the configuration signal can be an M_axis_rc_tready signal, and the first signal value can be 0. For example, the target order preserving rule test item can be a test item of memory read completion overriding memory write. The host sets the value of the M_axis_rc_tready signal to 0 through memory write. The host sends a memory write instruction to the test device. The memory write instruction triggers the test device to generate an MSI-X interrupt. Because the value of the M_axis_rc_tready signal is 0, the memory write instruction is locked, and the memory write instruction is no longer executed by the test device, so the MSI-X interrupt does not occur. The test device sends a memory read instruction to a preset address of the host. After receiving the memory read instruction, the host sends a read completion packet with a preset payload to the test device. In the case that the test device receives the read completion packet with the preset payload, the host sets the value of the M_axis_rc_tready signal to a second signal value, which can be 1, so that the test device can execute the memory write instruction to generate an MSI-X interrupt.

[0154] The embodiment of the present specification can test the test item of memory read completion overriding memory write based on two test instructions between the host and the test device, so that the test procedure is simple, and the test efficiency is improved.

[0155] In the case that the target order preserving rule test item is a test item of memory read completion overriding memory read request, the specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows:

[0156] The sending of the test instruction to the test device according to the parameter value of the initial test parameter includes:

[0157] According to the first signal value of the initial test parameter and the timeout time value, a first memory read instruction is sent to the test device, where the first signal value is used to limit the test device to execute the first memory read instruction.

[0158] In the case that no return message of the test device for the first memory read instruction is received, and the current time is less than the timeout time value, a memory read instruction request is sent to the test device.

[0159] In the case that a second memory read instruction sent by the test device is received, a read completion packet is sent to the test device, and a second signal value is set for the configuration signal, where the second signal value is used to restore the test device to execute the first memory read instruction.

[0160] Specifically, the configuration signal can be an M_axis_cq_tready signal, and the first signal value can be 0. For example, the target order preserving rule test item can be a test item of memory read completion overriding memory read request, the host sets the value of the M_axis_cq_tready signal to 0 through memory write, sets a timeout time value to 4 seconds, sends a memory read instruction to the test device, the memory read instruction triggers the test device to generate an MSIX interrupt, because the value of the M_axis_cq_tready signal is 0, the memory read instruction is locked, the memory read instruction is no longer executed by the test device, and the host does not receive a read completion message returned by the test device, the memory read instruction is sent to the host from the host, in a case where the timing time is less than the timeout time value, the test device sends a read completion message with a preset load message to the test device after receiving the read completion message with the preset load message, the host sets the value of the M_axis_cq_tready signal to a second signal value, and the second signal value can be 1, so that the test device can execute the memory read instruction.

[0161] The embodiment of the present specification can test the test item of memory read completion overriding memory read request based on two test instructions between the host and the test device, so that the test procedure is simple, and the test efficiency is improved.

[0162] In the case where the target order preserving rule test item is a test item of memory read completion overriding another memory read completion, the specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows:

[0163] The sending of the test instruction to the test device according to the parameter value of the initial test parameter includes:

[0164] According to the first signal value and the timeout time value of the initial test parameter, a first memory read instruction request is sent to the test device, wherein the first signal value is used to limit the test device to receive a first read completion message.

[0165] In a case where the first memory read instruction sent by the test device is received, and the current time is less than the timeout time value, the first read completion message is returned to the test device, and a second memory read instruction request is sent.

[0166] In a case where the second memory read instruction sent by the test device is received, a second read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device to receive the first read completion message.

[0167] In actual situation, the test device sends two memory read commands to the host computer, both of which are for a specific memory address, and both of the specific addresses are written with specific values in advance, and the writing manner can be but is not limited to devmem. According to the first signal value and the timeout time value of the initial test parameter, the host computer returns a first read completion message to the test device, and the data and address carried in the first memory read completion message can trigger the test logic to generate an MSIX interrupt. In the case that the test device does not receive the first read completion message for the first memory read instruction, and the current time is less than the timeout time value, the test device sends a second memory read instruction to the specific memory address. The second read completion message returned by the host computer for the second memory read instruction can set the configuration signal to a second signal value, and the second signal value is used to allow the test device to accept the first read completion message for the first memory read instruction from the host computer. The test logic sets the configuration signal to the second signal value by analyzing the address and data fields of the second read completion message and obtaining the expected result.

[0168] Specifically, the configuration signal can be an M_axis_rc_tready signal, and the first signal value can be 0. For example, the target order preservation rule test item can be a test item of memory read completion overriding another memory read completion read request. The host computer can but is not limited to set the value of the M_axis_rc_tready signal to 0 by configuring the writing of the cfg_interrupt_msi_data, and set the timeout time value to 4 seconds. Then the test device sends a first memory read instruction to the host computer. The first memory read completion instruction triggers the test device to generate an MSIX interrupt. Because the value of the M_axis_rc_tready signal is 0, the first memory read completion instruction is locked, so the MSIX interrupt cannot be generated. The timing starts from the sending of the first memory read instruction by the test device. In the case that the timing time is less than the timeout time value, the test device sends a second memory read instruction to the host computer. The host computer sends a second read completion message with a preset load message to the test device. In the case that the test device receives the read completion message with the preset load message, the host computer sets the value of the M_axis_rc_tready signal to a second signal value, and the second signal value can be 1, so that the test device can receive the first read completion message, thereby successfully triggering the generation of the MSIX interrupt.

[0169] The embodiment of the present specification can test the test item of memory read completion overriding another memory read completion based on two test instructions between the host computer and the test device, so that the test program is simple, and the test efficiency is improved.

[0170] Step 210: receiving the test result of the target order preservation rule test item of the target interface by the test device according to the test instruction.

[0171] Specifically, after sending the test instruction to the test device according to the parameter value of the initial test parameter, the host computer can receive the test result of the target order preservation rule test item of the target interface by the test device according to the test instruction.

[0172] In the case of the target order preservation rule test item being memory write completion beyond memory read, memory read completion beyond memory read request, and memory read completion beyond another memory read completion, after sending the test instruction to the test device according to the parameter value of the initial test parameter, the host computer receives the test result of the target order preservation rule test item of the target interface by the test device according to the test instruction, and the specific implementation manner is as follows:

[0173] The receiving the test result of the target order preservation rule test item of the target interface by the test device according to the test instruction comprises:

[0174] In the case of receiving the response information returned by the test device within the test timeout time, it is determined that the test result of the target order preservation rule test item of the target interface is successful.

[0175] The response information can be a signal or data sent by the test device, and the response information can be actively acquired by the host computer or actively sent by the test device, which is not limited by the embodiments of the present application.

[0176] Specifically, the target order preservation rule test item can be a memory write completion beyond memory read test item. After the corresponding test step is performed, in the case that the timing time is less than 4 seconds, the test device receives the read completion packet returned by the host computer for the memory read instruction, and the host computer monitors the MSIX interrupt in the case that the timing time is less than 4 seconds, and determines that the memory write completion beyond memory read, so as to determine that the test result of the target order preservation rule test item is successful.

[0177] Further, the target order preservation rule test item can be a memory read completion beyond memory read request test item. After the corresponding test step is performed, in the case that the timing time is less than 4 seconds, the host computer receives the read completion packet returned by the test device for the memory read instruction, and determines that the memory read completion beyond memory read request, so as to determine that the test result of the target order preservation rule test item is successful. According to whether the response message is received within the test timeout time to determine the test result, the test flow is simple.

[0178] Further, the target order preserving rule test item can be a test item of memory read completion superseding another memory read completion. After the corresponding test step is performed, if the test device generates an MSIX interrupt in a case where the timing is less than 4 seconds, the host computer receives information that the test device generates the MSIX interrupt, determines that the memory read completion supersedes the other memory read completion, and thus determines that the test result of the target order preserving rule test item is successful. The test result is determined according to whether the response message is received, so that the test flow is simple.

[0179] In the above example, in a case where the target order preserving rule test item is a memory write superseding another memory write or a memory read completion superseding a memory write, after the test instruction is sent to the test device according to the parameter value of the initial test parameter, the host computer receives the test result of the target order preserving rule test item of the target interface by the test device according to the test instruction, and the specific implementation manner is as follows:

[0180] The receiving the test result of the target order preserving rule test item of the target interface by the test device according to the test instruction includes:

[0181] In a case where the response information returned by the test device is received, it is determined that the test result of the target order preserving rule test item of the target interface is successful.

[0182] Specifically, the target order preserving rule test item can be a test item of memory write superseding another memory write. After the corresponding test step is performed, if the test device generates an MSIX interrupt, the MSIMASK field of the ECAM space of the test device is also changed, the host computer receives the message that the MSIMASK field is changed, determines that the memory write supersedes the other memory write, and thus determines that the test result of the target order preserving rule test item is successful.

[0183] Further, the target order preserving rule test item can be a test item of memory read completion superseding a memory write. After the corresponding test step is performed, the host computer receives the information that the test device generates the MSIX interrupt, determines that the memory read completion supersedes the memory write, and thus determines that the test result of the target order preserving rule test item is successful.

[0184] In the above example, in a case where the target order preserving rule test item is a memory write superseding another memory write or a memory read completion superseding a memory write, after the test instruction is sent to the test device according to the parameter value of the initial test parameter, the host computer receives the test result of the target order preserving rule test item of the target interface by the test device according to the test instruction, and the specific implementation manner is as follows:

[0185] The receiving the test result of the target order preserving rule test item of the target interface by the test device according to the test instruction includes:

[0186] In a case that the response information returned by the test device is received within the test timeout time, and the value of the response information satisfies the preset response condition, it is determined that the test result of the target order-preservation rule test item of the target interface is successful.

[0187] Specifically, the target order-preservation rule test item can be a memory write surpassing memory read test item. After the corresponding test step is performed, in a case that the host computer receives a read completion packet returned by the test device for the last sent memory read instruction in a timing time less than 4 seconds, and the read completion packet is a preset read completion packet, it is determined that the memory write surpasses the memory read, so as to determine that the test result of the target order-preservation rule test item is successful. According to whether the response message is received and whether the response message is the preset response condition are determined to determine the test result, so that the accuracy of the test result is improved.

[0188] The above is described in combination with the accompanying Figure 5 With the application of the target interface test method provided in the specification to the server as an example, the target interface test method is further described. Among them, Figure 5 Another flowchart of a target interface test method provided by an embodiment of the specification is shown, specifically including the following steps.

[0189] Step 502: determining at least one initial order-preservation rule test item of the PCIe interface according to the communication interface in the FPGA.

[0190] Specifically, the FPGA includes a PCIe core, and the communication interface of the FPGA includes cc, cq, rq and rc. The initial order-preservation rule test item can be determined through the cc, cq, rq and rc interfaces, and the initial order-preservation rule test item includes the memory write surpassing memory read completion, the memory read completion surpassing memory read request, the memory write completion surpassing configuration write, the memory read completion surpassing memory write, the memory write surpassing configuration write and the memory write surpassing memory read test items.

[0191] Step 504: determining a target order-preservation rule test item from the at least one initial order-preservation rule test item according to a preset requirement.

[0192] Specifically, the preset requirement can be to perform two target order-preservation rule test items of the memory write surpassing memory read completion and the memory read completion surpassing memory read request.

[0193] Step 506: determining a configuration signal of the FPGA corresponding to the target order-preservation rule test item and a test timeout time, setting a first signal value for the configuration signal, and determining a timeout time value of the test timeout time.

[0194] Specifically, the target order preservation rule test item can be a memory write surpassing memory read completion test item. The server finds the configuration signal, the first signal value, and the timeout time value of the timeout time of the memory write surpassing memory read completion test item from the database. The database can be local or remote.

[0195] Step 508: send a test instruction to the FPGA according to the first signal value and the timeout time value of the initial test parameter.

[0196] Step 510: receive the test result of the target order preservation rule test item of the PCIe interface of the FPGA according to the test instruction within the test timeout time.

[0197] Specifically, the memory write surpassing memory read completion test item is performed: the server sets the value of the M_axis_rc_tready signal to 0 by memory write, and sets the timeout time value to 4 seconds. The server sends a memory read instruction request to the FPGA. After receiving the memory read instruction request, the FPGA sends a memory read instruction to the server. Because the M_axis_rc_tready signal is set to 0, after the memory read instruction is executed by the server, the read completion sent by the server is locked, and the FPGA cannot receive the read completion message returned by the server. The FPGA no longer sends a memory read instruction to the server. The timing starts from the memory read instruction sent by the FPGA. If the timing time is less than the timeout time value, the server sends a memory write instruction to the FPGA, and sets the value of the M_axis_rc_tready signal to a second signal value by memory write. The second signal value can be 1, so that the FPGA receives the read completion message. If the timing time is less than 4 seconds, the FPGA receives the read completion message returned by the server for the memory read instruction, and the server monitors the MSIX interrupt when the timing time is less than 4 seconds. It is determined that the memory write surpasses the memory read completion, so as to determine that the test result of the target order preservation rule test item is successful.

[0198] In a specific implementation, a test item of memory read completion overriding a memory read request is performed: the server sets the value of the M_axis_cq_tready signal to 0 by means of memory writing, sets a timeout value to 4 seconds, sends a memory read instruction to the FPGA, the memory read instruction triggers the FPGA to generate an MSIX interrupt, because the value of the M_axis_cq_tready signal is 0, the memory read instruction is locked, the memory read instruction is no longer executed by the FPGA, and the server cannot receive the read completion message returned by the FPGA, the FPGA sends the memory read instruction to the preset address of the server, the server receives the memory read instruction, and sends the read completion message with a preset load message to the FPGA, the FPGA receives the read completion message with the preset load message, the server sets the value of the M_axis_cq_tready signal to a second signal value, and the second signal value can be 1, so that the FPGA can execute the memory read instruction. In a case where the timing time is less than 4 seconds, the server receives the read completion message returned by the FPGA for the memory read instruction, and determines that the memory read completion overrides the memory write request, so as to determine that the test result of the target order preservation rule test item is successful.

[0199] It should be noted that the order of performing the test of each target order preservation rule test item is not limited, the test of the memory read completion overriding the memory read request can be performed first, or the test of the memory write overriding the memory read completion can be performed first, and the embodiment of the present application is not limited.

[0200] The embodiment of the present application can test the order preservation rule of the PCIe interface by using only four communication interfaces of the FPGA, so that the test of the order preservation rule of the PCIe interface becomes feasible, and the test cost is low and the test difficulty is reduced.

[0201] Corresponding to the method embodiment, the present application further provides a target interface test device embodiment, Figure 6 Fig. 1 shows a structure schematic diagram of a target interface test device provided by an embodiment of the present application. As shown in the figure, Figure 6 The device comprises:

[0202] An initial item determination module 602 is configured to determine at least one initial order preservation rule test item of a target interface according to a communication interface in a test device;

[0203] A target item determination module 604 is configured to determine a target order preservation rule test item from the at least one initial order preservation rule test item according to a preset requirement;

[0204] A parameter determination module 606 is configured to determine an initial test parameter corresponding to the target order preservation rule test item and a parameter value of the initial test parameter;

[0205] The test module 608 is configured to send a test instruction to the test device according to the parameter value of the initial test parameter.

[0206] The receiving module 610 is configured to receive a test result of a target order-preservation rule test item of the target interface by the test device according to the test instruction.

[0207] Optionally, the parameter determination module 606 is further configured to:

[0208] determine a configuration signal of the test device corresponding to the target order-preservation rule test item, and set a first signal value for the configuration signal.

[0209] Optionally, the parameter determination module 606 is further configured to:

[0210] determine a configuration signal of the test device corresponding to the target order-preservation rule test item and a test timeout time;

[0211] set a first signal value for the configuration signal, and determine a timeout time value of the test timeout time.

[0212] Optionally, the test module 608 is further configured to:

[0213] send a memory read instruction to the test device through a preset time interval according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used to limit the credit value recovery of the test device, and the credit value is used to determine whether the test device executes the memory read instruction;

[0214] send a memory write instruction to the test device and set a second signal value for the configuration signal in a case where it is determined that the credit value of the test device is exhausted and the current time is less than the timeout time value, wherein the second signal value is used to recover the credit value of the test device.

[0215] Optionally, the test module 608 is further configured to:

[0216] send a first memory write instruction to the test device according to the first signal value of the initial test parameter, wherein the first signal value is used to limit the test device to execute the first memory write instruction;

[0217] send a second memory write instruction to the test device and set a second signal value for the configuration signal when a return message of the test device for the first memory write instruction is not received, wherein the second signal value is used to recover the test device to execute the first memory write instruction.

[0218] Optionally, the test module 608 is further configured to:

[0219] sending a memory read instruction request to the test device according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used to limit the test device to receive a read complete message;

[0220] in a case that the test device sends the memory read instruction and the current time is less than the timeout time value, returning the read complete message and sending a memory write instruction to the test device, and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to receive the read complete message.

[0221] Optionally, the test module 608 is further configured to:

[0222] sending a memory write instruction to the test device according to the first signal value of the initial test parameter, wherein the first signal value is used to limit the test device to execute the memory write instruction;

[0223] sending a memory read instruction request to the test device in a case that no return message is received from the test device for the memory write instruction;

[0224] in a case that the test device sends the memory read instruction, sending a read complete message to the test device and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to execute the memory write instruction.

[0225] Optionally, the test module 608 is further configured to:

[0226] sending a first memory read instruction to the test device according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used to limit the test device to execute the first memory read instruction;

[0227] sending a memory read instruction request to the test device in a case that no return message is received from the test device for the first memory read instruction and the current time is less than the timeout time value;

[0228] in a case that the test device sends a second memory read instruction, sending a read complete message to the test device and setting a second signal value for the configuration signal, wherein the second signal value is used to restore the test device to execute the first memory read instruction.

[0229] Optionally, the test module 608 is further configured to:

[0230] According to the first signal value and the timeout time value of the initial test parameter, a first memory read instruction request is sent to the test device, wherein the first signal value is used to limit the test device to receive a first read completion message;

[0231] In a case where the test device sends a first memory read instruction and the current time is less than the timeout time value, the first read completion message is returned to the test device and a second memory read instruction request is sent to the test device;

[0232] In a case where the test device sends a second memory read instruction, a second read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device to receive the first read completion message.

[0233] Optionally, the receiving module 610 is further configured to:

[0234] In a case where the response information returned by the test device is received within the test timeout time, it is determined that the test result of the target order preservation rule test item of the target interface is successful.

[0235] Optionally, the receiving module 610 is further configured to:

[0236] In a case where the response information returned by the test device is received, it is determined that the test result of the target order preservation rule test item of the target interface is successful.

[0237] Optionally, the receiving module 610 is further configured to:

[0238] In a case where the response information returned by the test device is received within the test timeout time and the value of the response information meets a preset response condition, it is determined that the test result of the target order preservation rule test item of the target interface is successful.

[0239] The above is a schematic scheme of a target interface test device according to an embodiment of the present specification. It should be noted that the technical scheme of the target interface test device belongs to the same concept as the technical scheme of the target interface test method described above, and the details of the technical scheme of the target interface test device that are not described in detail can be referred to the description of the technical scheme of the target interface test method.

[0240] Figure 7 A structural block diagram of a computing device 700 according to an embodiment of the present specification is shown. The components of the computing device 700 include but are not limited to a memory 710 and a processor 720. The processor 720 is connected to the memory 710 through a bus 730, and a database 750 is used to save data.

[0241] The computing device 700 also includes an access device 740 that enables the computing device 700 to communicate via one or more networks 760. Examples of such networks include a public switched telephone network (PSTN), a local area network (LAN), a wide area network (WAN), a personal area network (PAN), or combinations of such networks, such as the Internet. The access device 740 can include one or more of any type of network interface (for example, a network interface card (NIC)), such as an IEEE 802.11 wireless local area network (WLAN) wireless interface, a global system for mobile communications (GSM) interface, a code division multiple access (CDMA) interface, a Bluetooth interface, a near field communication (NFC) interface, a universal serial bus (USB) interface, a Wi-Fi® interface, a Wi-MAX interface, an Ethernet interface, or the like.

[0242] In one embodiment of the present specification, the above-mentioned components of the computing device 700 and other components not shown in the above-mentioned components can be connected to each other, for example, through a bus. It should be understood that Figure 7 In one embodiment of the present specification, the above-mentioned components of the computing device 700 and other components not shown in the above-mentioned components can be connected to each other, for example, through a bus. It should be understood that Figure 7 The computing device structure diagram shown is merely for the purpose of example, and is not a limitation on the scope of the present specification. Other components can be added or replaced as needed by those skilled in the art.

[0243] The computing device 700 can be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (for example, a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook, and the like), a mobile phone (for example, a smartphone), a wearable computing device (for example, a smart watch, smart glasses, and the like), or other types of mobile devices, or a stationary computing device such as a desktop computer or a PC. The computing device 700 can also be a mobile or stationary server.

[0244] The processor 720 is configured to execute computer-executable instructions, which, when executed by the processor, implement the steps of the above-mentioned target interface testing method.

[0245] The above is a schematic scheme of a computing device according to an embodiment of the present specification. It should be noted that the technical scheme of the computing device belongs to the same concept as the technical scheme of the above-mentioned target interface testing method, and the details of the technical scheme of the computing device that are not described in detail can be referred to the description of the technical scheme of the above-mentioned target interface testing method.

[0246] An embodiment of the present specification also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the steps of the above-mentioned target interface testing method.

[0247] The above is a schematic solution of a computer readable storage medium according to an embodiment of the present specification. It should be noted that the technical solution of the storage medium and the technical solution of the target interface test method described above belong to the same concept, and the details of the technical solution of the storage medium that are not described in detail can be seen from the description of the technical solution of the target interface test method.

[0248] An embodiment of the present specification also provides a computer program, which causes a computer to execute the steps of the target interface test method described above when the computer program is executed in the computer.

[0249] The above is a schematic solution of a computer program according to an embodiment of the present specification. It should be noted that the technical solution of the computer program and the technical solution of the target interface test method described above belong to the same concept, and the details of the technical solution of the computer program that are not described in detail can be seen from the description of the technical solution of the target interface test method.

[0250] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than the order in which they are recited and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0251] The computer instructions include computer program code, which can be in the form of source code, object code, executable code, or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0252] It should be noted that, for the aforementioned method embodiments, the sequences of the described actions are not necessarily required to implement the present application, and certain actions can be performed in other sequences, or even at the same time, in accordance with the present application. Furthermore, certain actions can not be required to implement the present application. Additionally, the described embodiments are not necessarily the only possible implementation of the present application.

[0253] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0254] The above disclosed preferred embodiments of the present application are only used to help explain the present application. Alternative embodiments do not describe all the details and limit the present application to the specific embodiments described. Obviously, according to the content of the embodiments of the present application, many modifications and changes can be made. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present application, so that those skilled in the art can well understand and use the present application. The present application is limited by the claims and their full scope and equivalents.

Claims

1. A target interface testing method, applied to a host machine, comprising: Determine at least one initial order preservation rule test item for the target interface based on the communication interface in the test equipment, wherein the initial order preservation rule test item is a test scenario designed based on the order preservation rules of PCIe transaction transmission. Based on preset requirements, a target order preservation rule test item is determined from at least one initial order preservation rule test item; Determine the initial test parameters and parameter values ​​corresponding to the target order preservation rule test item, wherein the initial test parameters are configuration signals, or the initial test parameters are the configuration signal and the test timeout time; Test instructions are sent to the test device according to the parameter values ​​of the initial test parameters, wherein the sending and execution of the test instructions are based on the parameter values ​​of the initial test parameters, in order to test the order preservation rules of the target interface by limiting or restoring the credit value or execution state of the test device; Receive the test results of the target sequence preservation rule test items of the target interface by the test equipment according to the test instructions.

2. The method according to claim 1, wherein determining the initial test parameters corresponding to the target order-preserving rule test item and the parameter values ​​of the initial test parameters includes: Determine the configuration signal of the test device corresponding to the target order preservation rule test item, and set a first signal value for the configuration signal.

3. The method according to claim 1, wherein determining the initial test parameters corresponding to the target order-preserving rule test item and the parameter values ​​of the initial test parameters includes: Determine the configuration signal and test timeout of the test device corresponding to the target order preservation rule test item; Set a first signal value for the configuration signal, and determine the timeout value for the test timeout.

4. The method according to claim 3, wherein sending a test command to the test device based on the parameter value of the initial test parameters comprises: Based on the first signal value and the timeout value of the initial test parameters, a memory read instruction is sent to the test device at a preset time interval, wherein the first signal value is used to limit the recovery of the test device's credit value, and the credit value is used to determine whether the test device executes the memory read instruction; If it is determined that the credit value of the test device is exhausted and the current time is less than the timeout value, a memory write instruction is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the credit value of the test device.

5. The method according to claim 2, wherein sending a test command to the test device based on the parameter value of the initial test parameters comprises: Based on the first signal value of the initial test parameters, a first memory write instruction is sent to the test device, wherein the first signal value is used to restrict the test device from executing the first memory write instruction; If no return message is received from the test device for the first memory write instruction, a second memory write instruction is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to resume the test device from executing the first memory write instruction.

6. The method according to claim 3, wherein sending a test command to the test device based on the parameter value of the initial test parameters comprises: Based on the first signal value and the timeout value of the initial test parameters, a memory read instruction request is sent to the test device, wherein the first signal value is used to limit the test device from receiving read completion messages; Upon receiving the memory read instruction sent by the test device, and if the current time is less than the timeout value, the test device returns the read completion message and sends a memory write instruction to the test device, and sets a second signal value for the configuration signal, wherein the second signal value is used to restore the test device's ability to receive the read completion message.

7. The method according to claim 2, wherein sending a test command to the test device based on the parameter value of the initial test parameter comprises: Based on the first signal value of the initial test parameters, a memory write instruction is sent to the test device, wherein the first signal value is used to restrict the test device from executing the memory write instruction; If no return message is received from the test device for the memory write instruction, a memory read instruction request is sent to the test device; Upon receiving the memory read instruction from the test device, a read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device from executing the memory write instruction.

8. The method according to claim 3, wherein sending a test command to the test device based on the parameter value of the initial test parameter comprises: Based on the first signal value and the timeout value of the initial test parameters, a first memory read instruction is sent to the test device, wherein the first signal value is used to restrict the test device from executing the first memory read instruction; If no return message is received from the test device for the first memory read instruction, and the current time is less than the timeout value, a memory read instruction request is sent to the test device. Upon receiving the second memory read instruction from the test device, a read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device from executing the first memory read instruction.

9. The method according to claim 3, wherein sending a test command to the test device based on the parameter value of the initial test parameter comprises: Based on the first signal value and the timeout value of the initial test parameters, a first memory read instruction request is sent to the test device, wherein the first signal value is used to restrict the test device from receiving the first read completion message; Upon receiving the first memory read instruction sent by the test device, and if the current time is less than the timeout value, return the first read completion message to the test device and send a second memory read instruction request; Upon receiving a second memory read instruction from the test device, a second read completion message is sent to the test device, and a second signal value is set for the configuration signal, wherein the second signal value is used to restore the test device's ability to receive the first read completion message.

10. The method according to any one of claims 4, 6, 8, and 9, wherein receiving the test results of the test device on the target sequence preservation rule test item of the target interface according to the test instruction includes: If the test device returns a response within the test timeout period, the test result for the target order preservation rule test item of the target interface is determined to be successful.

11. The method according to any one of claims 5 and 7, wherein receiving the test results of the test device on the target order preservation rule test item of the target interface according to the test instruction includes: Upon receiving the response information returned by the testing device, the test result of the target order preservation rule test item for the target interface is determined to be successful.

12. A target interface testing apparatus, comprising: The initial project determination module is configured to determine at least one initial order preservation rule test item for the target interface based on the communication interface in the test device, wherein the initial order preservation rule test item is a test scenario designed based on the order preservation rules of PCIe transaction transmission. The target item determination module is configured to determine the target order preservation rule test item from the at least one initial order preservation rule test item according to preset requirements; The parameter determination module is configured to determine the initial test parameters corresponding to the target order preservation rule test item and the parameter values ​​of the initial test parameters, wherein the initial test parameters are configuration signals, or the initial test parameters are the configuration signals and the test timeout time; The testing module is configured to send test instructions to the testing device based on the parameter values ​​of the initial test parameters, wherein the sending and execution of the test instructions are based on the parameter values ​​of the initial test parameters in order to test the order preservation rules of the target interface by limiting or restoring the credit value or execution state of the testing device; The receiving module is configured to receive the test results of the test device on the target sequence preservation rule test item of the target interface according to the test instructions.

13. A computing device, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the target interface testing method according to any one of claims 1 to 11.

14. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the target interface testing method according to any one of claims 1 to 11.

15. A computer program product comprising computer instructions that, when executed by a processor, implement the steps of the target interface testing method according to any one of claims 1 to 11.

Images