Data processing method, device, and storage medium

Abstract

An embodiment of the present application provides a data processing method and device, and a storage medium, including: a neural network processor, a buffer memory, and a memory memory; wherein the buffer memory includes cache units, each cache unit includes a cache data block and a cache counter; the cache data block is used to cache storage data in the memory memory and / or output data generated by the neural network processor; the cache counter is used to cache the number of reads corresponding to the storage data and / or output data, and the number of reads is the same as the number of algorithm layers for reading the storage data and / or output data determined according to the network structure of the algorithm network.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence, and in particular to a data processing method and device, and a storage medium. Background Art

[0002] The architecture of AI processors often uses a structure that separates computing and storage. Specifically, AI processors employ a hierarchical storage structure, where a buffer is placed between the computing engine and the main memory. The buffer stores some data for temporary data exchange with the computing engine. If the data the computing engine is trying to read doesn't match the buffer, new data needs to be transferred from the main memory to the buffer, allowing the computing engine to read from the buffer.

[0003] Currently, a data mapping method between memory and buffer memory is designed for the CPU, taking into account the high flexibility and uncertain data access address during CPU execution. However, in the embedded neural network processing unit (NPU) architecture, if a data caching mechanism needs to be added, the design scheme of reusing the CPU's buffer memory leads to low data caching efficiency for the NPU. Summary of the Invention

[0004] The embodiments of the present application provide a data processing method and device, and a storage medium, which can improve the data caching efficiency for the NPU.

[0005] The technical solution of this application is achieved as follows:

[0006] In a first aspect, an embodiment of the present application provides a data processing device, comprising: a neural network processor, a buffer memory, and a memory memory; wherein the buffer memory includes cache units, each cache unit including a cache data block and a cache counter;

[0007] The cache data block is used to cache the storage data in the memory storage and / or the output data generated by the neural network processor;

[0008] The cache counter is used to cache the number of reads corresponding to the stored data and / or the output data, and the number of reads is the same as the number of algorithm layers for reading the stored data and / or the output data determined according to the network structure of the algorithm network.

[0009] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to the above-mentioned data processing device, and the method includes:

[0010] Obtaining a network structure of an algorithm network to be executed, and determining, based on the network structure, the number of algorithm layers to read stored data in a memory storage and / or output data of each algorithm layer in the algorithm network;

[0011] The number of algorithm layers is determined as the number of times the storage data is read and / or the number of times the output data is read; and the storage data and the number of times the storage data is read, and / or the output data and the number of times the output data is read are added to a buffer memory.

[0012] In a third aspect, an embodiment of the present application proposes a storage medium on which a computer program is stored. When the computer program is executed by a processor, the data processing method as described above is implemented.

[0013] The embodiment of the present application provides a data processing method, device, and storage medium, the device comprising: a neural network processor, a buffer memory, and a memory memory; wherein the buffer memory comprises a cache unit, each cache unit comprising a cache data block and a cache counter; the cache data block is used to cache the stored data in the memory memory and / or the output data generated by the neural network processor; the cache counter is used to cache the number of reads corresponding to the stored data and / or the output data, the number of reads being the same as the number of algorithm layers for reading the stored data and / or the output data determined according to the network structure of the algorithm network. By adopting the above-mentioned device implementation scheme, in view of the characteristics that the data flow of the neural network processor is fixed and can be pre-determined, the number of algorithm layers for reading data in the buffer memory is known in advance according to the network structure of the algorithm network, and a cache counter is set in the buffer memory to store the number of algorithm layers, which can ensure that the data to be processed is cached in the buffer memory, greatly reducing the number of times data is written from the memory memory to the buffer memory, thereby improving the data caching efficiency for the NPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0015] Figure 2 A schematic diagram of a structure in which calculation and storage are separated is provided for an exemplary data processing device provided in an embodiment of the present application;

[0016] Figure 3 A schematic diagram of the network structure of an exemplary NPU-executed algorithm network provided in an embodiment of the present application;

[0017] Figure 4 A schematic diagram of an exemplary storage mapping method between a memory storage and a buffer memory provided in an embodiment of the present application;

[0018] Figure 5 A flowchart of a data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0021] In the following description, reference is made to "some embodiments," which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that the terms "first, second, and third" in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that "first, second, and third" may be interchanged in a specific order or sequential order where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0022] The embodiment of the present application provides a data processing device 1, such as Figure 1 As shown, the device 1 includes: a neural network processor 10, a buffer memory 11 and a memory 12; wherein the buffer memory 11 includes a cache unit 110, each cache unit 110 includes a cache data block 1100 and a cache counter 1101;

[0023] The cache data block 1100 is used to cache the storage data in the memory storage 12 and / or the output data generated by the neural network processor 10;

[0024] The cache counter 1101 is used to cache the number of reads corresponding to the stored data and / or the output data, and the number of reads is the same as the number of algorithm layers for reading the stored data and / or the output data determined according to the network structure of the algorithm network.

[0025] The data processing device proposed in the embodiment of the present application is a data cache device designed for the NPU architecture.

[0026] In the embodiment of the present application, the neural network processor is an NPU, the buffer memory is a cache memory, and the memory memory can be a synchronous dynamic random-access memory (SDRAM), a double data rate synchronous dynamic random-access memory (DDR), and other memories.

[0027] In the embodiment of the present application, the data processing device adopts a structure in which calculation and storage are separated, such as Figure 2 As shown, the data processing device includes an NPU computing engine, a cache memory and a memory memory, wherein the NPU computing engine contains a large number of computing units, and the cache memory is a buffer memory close to the NPU computing engine, which stores a certain amount of data for the NPU computing engine to perform temporary data interaction. It has a fast reading and writing speed, but a small storage capacity. The memory memory is a memory far away from the NPU computing engine, which stores all data and has a large storage capacity, but a slow reading and writing speed, and each reading path is long, so the reading and writing efficiency is low.

[0028] It should be noted that, since NPU has a fixed data flow and can be pre-judged, before executing the algorithm network, the network structure of the algorithm network executed by NPU can be analyzed to determine the data dependency between the algorithm layers in the algorithm network, such as Figure 3 As shown in the figure, it is a schematic diagram of the network structure of the algorithm network executed by NPU. Each circle is an algorithm layer. For an algorithm layer, its workflow is to read the source data and perform operator processing, where the operator can be convolution, pooling, activation, full connection, etc. After the operator processing is completed, it enters the next algorithm layer for processing. For example, the output data of algorithm layer No. 0 will be read as input data by algorithm layer No. 1 and algorithm layer No. 2, the output data of algorithm layer No. 1 will be read as input data by algorithm layer No. 3 and algorithm layer No. 4, and the output data of algorithm layer No. 2 will be read as input data by algorithm layer No. 5, algorithm layer No. 6 and algorithm layer No. 7. Therefore, through the analysis of the network structure of the algorithm network, it can be known how many times the output data of each algorithm layer in the algorithm network is subsequently read, such as the number of times the output data of algorithm layer No. 0 is read is 2, the number of times the output data of algorithm layer No. 1 is read is 2, and the number of times the output data of algorithm layer No. 2 is read is 3.

[0029] Based on the above concept, in an embodiment of the present application, a cache counter is set for each cache data block in the cache memory between the NPU and the memory storage. A cache data block and a corresponding cache counter together constitute a cache unit, wherein the cache counter is filled with the number of times the data in the corresponding cache data block is read out.

[0030] It should be noted that the data stored in the cache memory can be storage data from the memory, or it can be output data generated after the neural network processor performs operator processing on the storage data. The specific selection can be made according to actual conditions, and the embodiments of this application do not make specific limitations.

[0031] Optionally, the buffer memory 11 is also used to reduce the number of reads in the cache counter corresponding to the cache data block by one each time a read operation on the stored data and / or the output data is detected; until the number of reads in the cache counter is set to zero, the stored data and / or the output data is deleted.

[0032] In an embodiment of the present application, the operator layer in the NPU reads storage data and / or output data from the buffer memory. Each time the storage data and / or output data is read from the buffer memory, the buffer memory determines the cache unit that caches the storage data and / or output data, and reduces the number of reads in the counter of the cache unit by one; until the number of reads in the cache counter is set to zero, indicating that the data in the cache unit will not be read out subsequently, the storage data and / or output data will be deleted from the buffer memory, and the corresponding cache unit of the buffer memory will be cleared for subsequent writing of data into the cache unit.

[0033] It should be noted that the number of reads also reflects the importance of the corresponding cache data block. The greater the number of reads, the more times the data stored in the cache data block will be read by the subsequent algorithm layer, which means that the data stored in the cache data block is more important. On the contrary, the smaller the number of reads, the less times the data stored in the cache data block will be read by the subsequent algorithm layer, which means that the data stored in the cache data block is less important.

[0034] Optionally, the neural network processor 10 is used to determine the number of times the output data is read based on the number of algorithm layers that read the output data; determine a first storage unit from the buffer memory and / or the memory memory based on the destination address of the output data in the memory and the storage mapping method between the memory and the buffer memory; and cache the number of times the output data is read and the output data, and / or the output data in the first storage unit.

[0035] In an embodiment of the present application, the neural network processor can determine the number of algorithm layers for reading output data based on the network structure of the algorithm network, and then determine the number of times the output data is read based on the number of algorithm layers.

[0036] In the embodiment of the present application, the storage mapping method between the memory and the buffer memory can be determined according to hardware parameters and cache efficiency, such as Figure 4 As shown, the storage data in each storage data block in the memory storage can be mapped to the four cache data blocks in the cache memory. For example, the cache data blocks include 16 cache data blocks 0-15. Each cache data block is preceded by a cache counter cnt, which together constitute 16 cache units. Storage data blocks No. 0, No. 8, ..., No. 2040 in the memory storage are mapped to cache data blocks No. 0-3 in the cache memory. And so on, storage data blocks No. 7, No. 15, and No. 2047 in the memory storage are mapped to cache data blocks No. 12-15 in the cache memory, which shows the storage mapping method between the memory storage and the buffer memory.

[0037] In an embodiment of the present application, the NPU receives an instruction that includes a source data address, a target data address, and a convolution operation command, where the target data address is the destination address of the output data in the memory storage in the present application. The NPU can determine the first storage unit from the buffer memory and / or the memory storage based on the destination address and the storage mapping relationship.

[0038] Specifically, the neural network processor 10 is further configured to determine, from the buffer memory, a first cache unit group corresponding to the output data based on a destination address of the output data in the memory and the storage mapping mode; if the first cache unit group includes a first free cache unit, determining the first free cache unit as the first cache unit;

[0039] The neural network processor 10 is further configured to, if the first cache unit group does not include the first free cache unit and a cache unit having a read count less than a read count of the output data is not found in the first cache unit group, determine the first storage unit from the memory according to the destination address;

[0040] The neural network processor 10 is further configured to, if the first cache unit group does not include the first idle first cache unit, and a cache unit having a read count less than the read count of the output data is found in the first cache unit group, determine the cache unit having a read count less than the read count of the output data as the first cache unit;

[0041] The buffer memory 11 is further configured to delete currently stored output data and the remaining reading times corresponding to the currently stored output data in the cache unit whose reading times are less than the reading times of the output data.

[0042] In an embodiment of the present application, the neural network processor writes the output data back to the cache memory or the memory. Specifically, the neural network processor first determines the first cache unit group from the cache memory according to the destination address and storage mapping method of the output data in the memory, and determines whether there is a first free cache unit in the first cache unit group; if there is a first free cache unit in the first cache unit group, the first free cache unit is determined as the first cache unit, and the output data and the number of times the output data is read are directly cached in the first free cache unit of the buffer memory.

[0043] In an embodiment of the present application, if there is no first free cache unit in the first cache unit group, the number of reads of the output data is compared with the number of reads stored in the first cache unit group in sequence. If there is a cache unit in the first cache unit group whose number of reads is less than the number of reads of the output data, it indicates that the importance of the output data is higher than the data cached in the cache unit whose number of reads is less than the number of reads of the output data. At this time, the cache unit whose number of reads is less than the number of reads of the output data is determined as the first cache unit, and the currently stored output data and the remaining number of reads corresponding to the currently stored output data in the cache unit whose number of reads of the output data is deleted, and then the output data and the number of reads of the output data are cached in the cache unit in the buffer memory whose number of reads is less than the number of reads of the output data.

[0044] In an embodiment of the present application, if there is no cache unit in the first cache unit group whose read count is less than the read count of the output data, it indicates that there is no data cached in the first cache unit group whose importance is lower than the output data. At this time, the first cache unit is determined directly from the memory storage based on the destination address, and the output data, and / or the output data and the read count of the output data are stored in the first cache unit in the memory storage.

[0045] Optionally, the neural network processor 10 is further configured to update the output data, and / or the output data and the number of times the output data is read, to the memory when the number of times the output data is read and the output data are cached in the buffer memory;

[0046] Alternatively, the neural network processor 10 is further configured to set a pending synchronization flag for the output data when the number of times the output data is read and the output data are cached in the buffer memory; and when the buffer memory deletes the output data and the number of times the output data is read, the output data and / or the output data and the number of times the output data is read are updated to the memory according to the pending synchronization flag.

[0047] It should be noted that the data in the cache memory is equivalent to a backup of the data in the internal memory. Therefore, when the neural network memory caches the output data and the number of times the output data is read in the buffer memory, the output data and / or the output data and the number of times the output data is read need to be synchronized to the internal memory to ensure data consistency between the cache memory and the internal memory. There are two ways to synchronize the data: one is to update the output data and / or the output data and the number of times the output data is read to the internal memory when the output data and the number of times the output data is cached in the buffer memory; the other is to set a pending synchronization flag for the output data. When the buffer memory deletes the output data and the number of times the output data is read, the output data and / or the output data and the number of times the output data is read are updated to the internal memory according to the pending synchronization flag.

[0048] It should be noted that the scenario in which the buffer memory deletes output data and the number of times the output data is read can be that the number of times the output data is read is reduced to zero; it can also be that when the NPU caches new output data in the buffer memory, it is determined that there is no idle cache unit in the cache unit group corresponding to the output data, and the number of times the output data is read is less than the number of times the new output data is read; it can also be that when the memory memory writes new storage data to the buffer memory, it is determined that there is no idle cache unit in the cache unit group corresponding to the output data, and the number of times the output data is read is the smallest number of reads in the corresponding cache unit group.

[0049] Optionally, the memory storage 12 is configured to determine, from the buffer memory, a second cache unit group corresponding to the stored data according to the storage address of the stored data and the storage mapping mode; if a second free storage unit exists in the second cache unit group, cache the stored data in the second free storage unit; if no second free storage unit exists in the second cache unit group, search the second cache unit with the minimum number of reads in the second cache unit group, and cache the stored data in the second cache unit;

[0050] The neural network processor 10 is further used to determine the number of times the stored data is read; if there is a second idle storage unit in the second cache unit group, the number of times the stored data is read is cached in the second idle storage unit; if there is no second idle storage unit in the second cache unit group, the number of times the stored data is read is cached in the second cache unit.

[0051] In an embodiment of the present application, when the memory storage caches the storage data to the cache memory, the neural network processor also determines the number of times the storage data is read. The memory storage first determines the second cache unit group corresponding to the storage data from the buffer memory based on the storage address and storage mapping relationship of the storage data, and determines whether there is a second free storage unit in the second cache unit group; if there is a second free storage unit in the second cache unit group, the storage data and the number of times the storage data is read are cached in the second free storage unit; if there is no second free storage unit in the second cache unit group, the second cache unit with the smallest number of reads is searched in the second cache unit group, and then the storage data and the number of times the storage data is read are cached in the second cache unit.

[0052] Optionally, if the memory storage 12 includes: a storage data block and a storage counter corresponding to the storage data block; the neural network processor 10 is further configured to obtain the number of times the storage data is read from the storage counter, where the number of reads in the storage counter is determined based on the number of algorithm layers for reading data in the storage data block and / or based on the number of reads transmitted by the neural network processor;

[0053] If the memory storage 12 only includes: the stored data block; then the neural network processor 10 is further used to determine the number of reads currently stored in the second cache unit from the buffer memory, determine the number of reads of the stored data based on the number of reads currently stored in the second cache unit, and / or determine the number of reads of the stored data based on the number of algorithm layers for reading the stored data.

[0054] In an optional embodiment, a storage counter may be set for each storage data block in the memory storage, and the number of times the storage data is read is stored in the corresponding storage counter; the neural network processor may directly obtain the number of times the storage data is read from the storage counter.

[0055] In another optional embodiment, only a storage data block may be set in the memory storage. In this case, the number of times the storage data is read is not stored in the memory storage; the neural network processor may determine the number of times the storage data is read based on the number of algorithm layers that read the storage data, or may determine the number of times the storage data is read based on the number of times the storage data is currently stored in the second cache unit, wherein the number of times the storage data is read is greater than the number of times the storage data is currently stored in the second cache unit, and the difference between the specific number of times the storage data is read and the number of times the storage data is currently stored in the second cache unit can be obtained based on the previous evaluation of the algorithm network.

[0056] It can be understood that, in view of the characteristics of the neural network processor's fixed and pre-determined data flow, the number of algorithm layers for reading data in the buffer memory is known in advance based on the network structure of the algorithm network, and a cache counter is set in the buffer memory to store the number of algorithm layers. This can ensure that the data to be processed is cached in the buffer memory, greatly reducing the number of times data is written from the memory to the buffer memory, thereby improving the data caching efficiency for the NPU.

[0057] Based on the above embodiments, the present application also proposes a data processing method, such as Figure 5 As shown, applied to the above data processing device, the method includes:

[0058] S101. Obtain a network structure of an algorithm network to be executed, and determine the number of algorithm layers to read stored data in a memory and / or output data of each algorithm layer in the algorithm network according to the network structure.

[0059] In the embodiment of the present application, since the NPU has a fixed data flow and can be pre-judged, before executing the algorithm network, the network structure of the algorithm network executed by the NPU can be analyzed to determine the data dependency between the algorithm layers in the algorithm network, such as Figure 2 As shown in the figure, it is a schematic diagram of the network structure of the algorithm network executed by NPU. Each circle is an algorithm layer. For an algorithm layer, its workflow is to read the source data and perform operator processing, where the operator can be convolution, pooling, activation, full connection, etc. After the operator processing is completed, it enters the next algorithm layer for processing. For example, the output data of algorithm layer No. 0 will be read as input data by algorithm layer No. 1 and algorithm layer No. 2, the output data of algorithm layer No. 1 will be read as input data by algorithm layer No. 3 and algorithm layer No. 4, and the output data of algorithm layer No. 2 will be read as input data by algorithm layer No. 5, algorithm layer No. 6 and algorithm layer No. 7. Therefore, through the analysis of the network structure of the algorithm network, it can be known how many times the output data of each algorithm layer in the algorithm network is subsequently read, such as the number of times the output data of algorithm layer No. 0 is read is 2, the number of times the output data of algorithm layer No. 1 is read is 2, and the number of times the output data of algorithm layer No. 2 is read is 3.

[0060] S102: Determine the number of algorithm layers as the number of times the stored data is read and / or the number of times the output data is read; and add the stored data and the number of times the stored data is read, and / or the output data and the number of times the output data is read to the buffer memory.

[0061] In an embodiment of the present application, the output data and the number of times the output data is read are added to the buffer memory, including: determining a first storage unit from the buffer memory based on the destination address of the output data in the memory and the storage mapping method between the memory and the buffer memory; and caching the number of times the output data is read and the output data in the first storage unit.

[0062] Specifically, according to the destination address of the output data in the memory storage and the storage mapping method between the memory storage and the buffer storage, the first storage unit is determined from the buffer storage, including: according to the destination address and the storage mapping method of the output data in the memory storage, the first cache unit group corresponding to the output data is determined from the buffer storage; if the first cache unit group includes a first free cache unit, the first free cache unit is determined as the first cache unit; if the first cache unit group does not include the first free first cache unit, and a cache unit with a reading number less than the reading number of the output data is found from the first cache unit group, the cache unit with the reading number of the output data is determined as the first cache unit.

[0063] Furthermore, if the first cache unit group does not include the first free cache unit and no cache unit having a read count less than the read count of the output data is found in the first cache unit group, the first storage unit is determined from the memory according to the destination address.

[0064] In an embodiment of the present application, the storage data and the number of times the storage data is read are added to the buffer memory, including: determining the number of times the storage data is read; determining the second cache unit group corresponding to the storage data from the buffer memory according to the storage address and storage mapping method of the storage data; if there is a second free storage unit in the second cache unit group, caching the storage data and the number of times the storage data is read in the second free storage unit; if there is no second free storage unit in the second cache unit group, searching the second cache unit with the smallest number of reads from the second cache unit group, and caching the number of times the storage data is read in the second cache unit.

[0065] In an embodiment of the present application, each time an algorithm layer detects a read operation on stored data and / or output data, the number of reads of the stored data and / or the number of reads of the output data in the buffer memory is reduced by one; until the number of reads of the stored data and / or the number of reads of the output data in the buffer memory is set to zero, the corresponding stored data and / or output data are deleted from the buffer memory.

[0066] It should be noted that after the output data and the number of times the output data is read are added to the buffer memory, a data synchronization process is also performed, specifically: the output data and / or the output data and the number of times the output data is read are updated to the memory memory; or, a pending synchronization flag is set for the output data, and when the output data and the number of times the output data is read are deleted in the buffer memory, the output data and / or the output data and the number of times the output data is read are updated to the memory memory according to the pending synchronization flag.

[0067] It can be understood that, in view of the characteristics of the neural network processor's fixed and pre-determined data flow, the number of algorithm layers for reading data in the buffer memory is known in advance based on the network structure of the algorithm network, and a cache counter is set in the buffer memory to store the number of algorithm layers. This can ensure that the data to be processed is cached in the buffer memory, greatly reducing the number of times data is written from the memory to the buffer memory, thereby improving the data caching efficiency for the NPU.

[0068] An embodiment of the present application provides a storage medium having a computer program stored thereon. The computer-readable storage medium stores one or more programs. The one or more programs can be executed by one or more neural network processors and applied to a data processing device. The computer program implements the data processing method as described above.

[0069] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0070] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling an image display device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0071] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A data processing device, characterized in that: The device includes: a neural network processor, a buffer memory and a memory memory; wherein the buffer memory includes cache units, each cache unit includes a cache data block and a cache counter; The cache data block is used to cache the storage data in the memory storage and / or the output data generated by the neural network processor; The cache counter is used to cache the number of reads corresponding to the stored data and / or the output data, where the number of reads is the same as the number of algorithm layers for reading the stored data and / or the output data determined according to the network structure of the algorithm network; The cache unit used to cache the stored data and the number of times the stored data is read is: a first idle storage unit in the first cache unit group of the buffer memory, or a cache unit with a number of reads less than the number of times the output data is read when the first idle cache unit does not exist in the first cache unit group and there is a cache unit with a number of reads less than the number of times the output data is read, or a cache unit in the memory when there is no idle cache unit in the first cache unit group and there is no cache unit with a number of reads less than the number of times the output data is read; The cache unit used to cache the output data and the number of times the output data is read is: the second idle storage unit in the second cache unit group of the buffer memory, or the second cache unit with the smallest number of times of reading in the second cache unit group when there is no second idle storage unit in the second cache unit group.

2. The device according to claim 1, characterized in that The buffer memory is further configured to decrement the number of reads in the cache counter corresponding to the cache data block by one each time a read operation on the stored data and / or the output data is detected; Until the number of read times in the cache counter is reset to zero, the stored data and / or the output data are deleted.

3. The device according to claim 1, characterized in that The neural network processor is used to determine the number of times the output data is read according to the number of algorithm layers that read the output data; determining a first storage unit from the buffer memory and / or the memory memory according to a destination address of the output data in the memory memory and a storage mapping mode between the memory memory and the buffer memory; The number of times the output data is read and the output data are cached in the first storage unit and / or the output data are cached in the first storage unit.

4. The device according to claim 3, characterized in that The neural network processor is further configured to determine, from the buffer memory, a first cache unit group corresponding to the output data based on a destination address of the output data in the memory and the storage mapping mode; If the first cache unit group includes a first free cache unit, determining the first free cache unit as the first cache unit; The neural network processor is further configured to determine the first storage unit from the memory according to the destination address if the first cache unit group does not include the first free cache unit and a cache unit whose read count is less than the read count of the output data is not found in the first cache unit group; The neural network processor is further configured to, if the first cache unit group does not include the first idle first cache unit, and a cache unit having a read count less than the read count of the output data is found in the first cache unit group, determine the cache unit having a read count less than the read count of the output data as the first cache unit; The buffer memory is further configured to delete the currently stored output data and the remaining read times corresponding to the currently stored output data in the cache unit whose read times are less than the read times of the output data.

5. The device according to claim 3, characterized in that The neural network processor is further configured to update the output data to the memory storage and / or update the output data and the output data reading times to the memory storage when the output data reading times and the output data are cached in the buffer memory; Alternatively, the neural network processor is further configured to set a pending synchronization flag for the output data when the number of times the output data is read and the output data are cached in the buffer memory; and when the buffer memory deletes the output data and the number of times the output data is read, the output data is updated to the memory memory and / or the output data and the number of times the output data is read are updated to the memory memory according to the pending synchronization flag.

6. The device according to claim 2, characterized in that The internal memory is configured to determine, from the buffer memory according to the storage address and storage mapping mode of the stored data, a second cache unit group corresponding to the stored data; if a second free storage unit exists in the second cache unit group, cache the stored data in the second free storage unit; if no second free storage unit exists in the second cache unit group, search the second cache unit with the minimum number of reads from the second cache unit group, and cache the stored data in the second cache unit; The neural network processor is further used to determine the number of times the stored data is read; If there is a second free storage unit in the second cache unit group, the number of reads of the stored data is cached in the second free storage unit; if there is no second free storage unit in the second cache unit group, the number of reads of the stored data is cached in the second cache unit.

7. The device according to claim 6, characterized in that If the memory storage includes a storage data block and a storage counter corresponding to the storage data block, the neural network processor is further configured to obtain a reading count of the storage data from the storage counter, where the reading count in the storage counter is determined based on the number of algorithm layers for reading data in the storage data block and / or the reading count in the storage counter is determined based on a reading count transmitted by the neural network processor; If the memory storage only includes the stored data block, the neural network processor is further used to determine the number of reads currently stored in the second cache unit from the buffer memory, and determine the number of reads of the stored data based on the number of reads currently stored in the second cache unit, and / or determine the number of reads of the stored data based on the number of algorithm layers for reading the stored data.

8. A data processing method, characterized in that: Applied to the data processing device according to any one of claims 1 to 7, the method comprises: Obtaining a network structure of an algorithm network to be executed, and determining, based on the network structure, the number of algorithm layers to read stored data in a memory storage and / or output data of each algorithm layer in the algorithm network; Determining the number of algorithm layers as the number of times the stored data is read and / or the number of times the output data is read; and adding the stored data and the number of times the stored data is read to a buffer memory and / or a memory memory and / or adding the output data and the number of times the output data is read to a buffer memory; The cache unit used to cache the stored data and the number of times the stored data is read is: a first idle storage unit in the first cache unit group of the buffer memory, or a cache unit with a number of reads less than the number of times the output data is read when the first idle cache unit does not exist in the first cache unit group and there is a cache unit with a number of reads less than the number of times the output data is read, or a cache unit in the memory when there is no idle cache unit in the first cache unit group and there is no cache unit with a number of reads less than the number of times the output data is read; The cache unit used to cache the output data and the number of times the output data is read is: the second idle storage unit in the second cache unit group of the buffer memory, or the second cache unit with the smallest number of times of reading in the second cache unit group when there is no second idle storage unit in the second cache unit group.

9. The method according to claim 8, characterized in that The method further comprises: Whenever a read operation of the stored data and / or the output data by an algorithm layer is detected, the number of reads of the stored data in the buffer memory is reduced by one and / or the number of reads of the output data in the buffer memory is reduced by one; Until the number of times the stored data in the buffer memory is read is set to zero and / or the number of times the output data in the buffer memory is read is set to zero, the corresponding stored data and / or the output data are deleted from the buffer memory.

10. The method according to claim 8, characterized in that The step of adding the output data and the number of times the output data is read into a buffer memory comprises: determining a first storage unit from the buffer memory according to a destination address of the output data in the memory and a storage mapping mode between the memory and the buffer memory; The number of times the output data is read and the output data are cached in the first storage unit.

11. The method according to claim 10, characterized in that The determining of the first storage unit from the buffer memory according to the destination address of the output data in the memory and the storage mapping mode between the memory and the buffer memory comprises: determining, from the buffer memory, a first cache unit group corresponding to the output data according to a destination address of the output data in the memory and the storage mapping mode; If the first cache unit group includes a first free cache unit, determining the first free cache unit as the first cache unit; If the first cache unit group does not include the first idle first cache unit, and a cache unit with a read count less than the read count of the output data is found from the first cache unit group, the cache unit with the read count of the output data is determined as the first cache unit.

12. The method according to claim 11, characterized in that The method further comprises: If the first cache unit group does not include the first free cache unit, and no cache unit with a read count less than the read count of the output data is found in the first cache unit group, the first storage unit is determined from the memory according to the destination address.

13. The method according to claim 8, characterized in that After adding the output data and the number of times the output data is read into the buffer memory, the method further includes: Updating the output data into the memory and / or updating the output data and the number of times the output data is read into the memory; Or, a pending synchronization flag is set for the output data, and when the buffer memory deletes the output data and the number of times the output data is read, the output data is updated to the memory storage and / or the output data and the number of times the output data is read are updated to the memory storage according to the pending synchronization flag.

14. The method according to claim 8, characterized in that The step of adding the stored data and the number of times the stored data is read into a buffer memory comprises: Determining the number of times the stored data is read; determining, from the buffer memory, a second cache unit group corresponding to the stored data according to a storage address of the stored data and the storage mapping mode; If there is a second free storage unit in the second cache unit group, cache the storage data and the number of times the storage data is read in the second free storage unit; If there is no second free storage unit in the second cache unit group, the second cache unit with the smallest read count is searched from the second cache unit group, and the read count of the stored data is cached in the second cache unit.

15. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a neural network processor, the method according to any one of claims 8 to 14 is implemented.

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