Display device having light emitting diode and driver circuit in a single package

Abstract

This disclosure relates to a display device having a single package containing a light-emitting diode (LED) and a driver circuit. An integrated circuit for the display device includes: a substrate; an LED layer that generates light in response to a driver current; a driver circuit layer on the substrate that drives the LED by controlling a driver current in response to a driver control signal; a conductive redistribution layer between the driver circuit layer and the LED layer that is used to: electrically connect the LED to the driver circuit to supply driver current; and mechanically fix the LED above the substrate such that the LED layer and the conductive redistribution layer are vertically stacked above the driver circuit layer; and an interconnect layer including traces supplying driver current from the driver circuit layer to the conductive redistribution layer.

Description

[0001] This application is a divisional application of the PCT invention patent application with application number 202010838023.5, application date August 19, 2020, and name “Display device with a single package having a light-emitting diode and a driver circuit”. Technical Field

[0002] The present disclosure relates generally to light emitting diodes (LEDs) and LED driver circuits for displays, and more particularly to display architectures with distributed driver circuits. Background Art

[0003] LEDs are used in many electronic display devices, such as televisions, computer monitors, laptops, tablet computers, smart phones, projection systems, and head-mounted devices. Modern displays can include far more than 10 million individual LEDs, which can be arranged in rows and columns in a display area. To drive each LED, current methods use driver circuits that require a large amount of external chip area, which affects the size of the display device. Summary of the invention

[0004] Embodiments relate to a display device including LEDs and driver circuits integrated into a single package. The display device includes a control circuit, an array of driver circuits distributed in a display area of ​​the device, and an array of LED zones. Each LED zone includes one or more LEDs that generate light in response to a corresponding driver current. Each driver circuit in the driver circuit array drives one or more LED zones in the LED zone by controlling a corresponding driver current through the LEDs in the LED zone in response to a driver control signal from the control circuit. The one or more LEDs in the LED zone and the driver circuit driving the one or more LEDs in the LED zone are integrated and vertically stacked on a substrate in an integrated package.

[0005] Embodiments also relate to an integrated LED and driver circuit for a display device. The integrated LED and driver circuit includes a substrate, one or more driver circuits in a driver circuit layer, and one or more LEDs in an LED layer. The LED generates light in response to a driver current. The driver circuit drives the LED by controlling the driver current in response to a driver control signal. A conductive redistribution layer between the driver circuit layer and the LED layer electrically connects the LED to the driver circuit for supplying the driver current. The LED layer and the conductive redistribution layer are vertically stacked on the driver circuit layer.

[0006] Embodiments also relate to a driver circuit for a display device utilizing drivers distributed in a display area. The driver circuit includes control logic for operating in at least an addressing mode and an operating mode. In the operating mode, the control logic obtains a driver control signal from a power line communication signal and controls a driver current based on the driver control signal. In the addressing mode, the control logic obtains an incoming addressing signal, stores an address of the driver circuit based on the incoming addressing signal, and generates an outgoing addressing signal based on the incoming addressing signal. During the addressing mode, a data input pin receives the incoming addressing signal. In the operating mode, a power line communication input pin receives a power line communication signal, the power line communication signal including a supply voltage that is modulated to encode the driver control signal. An output pin collects the driver current during the operating mode and outputs the outgoing addressing signal during the addressing mode. The driver circuit also includes a ground pin for providing a ground path.

[0007] Embodiments also relate to a display device that operates using power line communication technology. The display device includes an array of LED zones, each LED zone including one or more LEDs that generate light in response to a corresponding driver current. The display device also includes a driver circuit group for driving at least one LED zone in the LED zone respectively by controlling the corresponding driver current in response to a driver control signal. Each driver circuit includes a power line communication input pin for receiving a power line communication signal. The power line communication signal supplies power to the driver circuit and encodes one of the driver control signals into digital data, which is modulated onto a supply voltage. The display device also includes a power line communication line that provides the power line communication signal to the power line communication input pin of each driver circuit in the driver circuit group. The display device also includes a control circuit for generating a power line communication signal and providing the power line communication signal on the power communication line to power the driver circuit group and control the display device through the driver control signal.

[0008] Embodiments also relate to a driver circuit for a display device operating according to a power line communication technology. The driver circuit includes a power line communication input pin configured to receive a power line communication signal. The driver circuit also includes a power conditioning circuit for generating a supply voltage based on a DC component of the power line communication signal and a driver control signal based on a modulated component of the power line communication signal. The driver circuit also includes a control logic powered by the supply voltage for receiving the driver control signal and generating a current control signal for controlling a driver current passing through an LED zone via an output pin based on the driver control signal.

[0009] Embodiments also relate to a method for controlling a driver circuit of a display device using power line communication technology. A power line communication signal is received at a power line communication input pin. A power conditioning circuit generates a supply voltage based on a DC component of the power line communication signal and generates a driver control signal based on a modulated component of the power line communication signal. A control logic is powered by the supply voltage. The control logic receives the driver control signal and generates a current control signal for controlling a driver current through an LED zone of the display device based on the driver control signal.

[0010] Embodiments also relate to a display device that uses a chain addressing scheme to provide an address to a driver circuit coupled to a shared control data line. The display device includes a control circuit for generating an address communication signal during an addressing mode of the display device and a driver control signal during an operating mode of the display device. The display device also includes an array of LED zones, each LED zone including one or more LEDs that generate light in response to a corresponding driver current. A driver circuit group, each driver circuit drives a corresponding LED zone in an operating mode by controlling a corresponding driver current in response to a driver control signal. When operating in the addressing mode, each driver circuit in the group of driver circuits receives an incoming addressing signal via a data input pin, stores an address based on the incoming addressing signal, and generates an outgoing addressing signal to output via an output pin. A group of address communication lines is coupled between the output pins and the data input pins of adjacent driver circuits in the group of driver circuits.

[0011] Embodiments also relate to a driver circuit for driving an LED zone of a display device, wherein the display device provides an address to a driver circuit coupled to a shared control data line using a chain addressing scheme. The driver circuit includes a data input pin configured to receive an address communication signal during an addressing mode. The control logic is configured to store an address based on the address communication signal during the addressing mode and generate an outgoing address signal (e.g., by incrementing the address), and to generate a current control signal for controlling a driver current passing through the LED zone based on a driver control signal during an operating mode. The output pin provides the outgoing address signal as digital data to a subsequent driver circuit during the addressing mode of the driver circuit, and collects the driver current passing through the LED zone during the operating mode. The driver circuit also includes a ground pin configured to provide a path for the driver current to be grounded.

[0012] Embodiments also relate to a method for operating a driver circuit for driving an LED zone of a display device, the display device using a chain addressing scheme to provide an address to a driver circuit coupled to a shared control data line. The driver circuit activates an enable signal during an addressing mode to enable an address driver. The driver circuit receives an address communication signal providing address information as digital data at a data input pin during the addressing mode. The driver circuit stores an address to a storage medium based on the address of the address information, generates outgoing address information (e.g., by incrementing the stored address), and provides the outgoing address information to a subsequent driver circuit at an output pin. The driver circuit deactivates the enable signal during the operating mode to disable the address driver, and enables the driver circuit to drive the LED zone via the output pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The teachings of embodiments of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0014] Figure 1A is a circuit diagram of a display device according to one embodiment.

[0015] Figure 1B is a waveform diagram showing an example waveform of a power line communication signal according to one embodiment.

[0016] Figure 1C is a waveform diagram showing an operation mode of a display device according to one embodiment.

[0017] Figure 2 is an exemplary circuit diagram of a control circuit for a display device according to one embodiment.

[0018] Figure 3 is an exemplary circuit diagram of a driver circuit for a display device according to one embodiment.

[0019] Figure 4A is a cross-sectional view of a first embodiment of an LED and a driver circuit that can be used in a display device.

[0020] Figure 4B is a cross-sectional view of a second embodiment of an LED and a driver circuit that can be used in a display device.

[0021] Figure 4C is a cross-sectional view of a third embodiment of an LED and a driver circuit that can be used in a display device.

[0022] Figure 5 is a top view of a display device using an LED and a driver circuit according to one embodiment.

[0023] Figure 6A schematic diagram showing several layers of an LED and driver circuit for a display device according to one embodiment.

[0024] The features and advantages described in this specification are not all-inclusive, but in particular, many additional features and advantages will become apparent to those of ordinary skill in the art from the drawings, description and claims. In addition, it should be noted that the language used in this specification is primarily selected for readability and instructional purposes, and is not selected to delineate or limit the subject matter of the invention. DETAILED DESCRIPTION

[0025] The drawings and the following description relate to preferred embodiments of the present invention by way of illustration only. It should be noted that from the following discussion, it will be readily appreciated that alternative embodiments of the structures and methods disclosed herein are variable alternatives that can be employed without departing from the principles of the present disclosure.

[0026] Reference will now be made in detail to several embodiments of the present invention, examples of which are shown in the accompanying drawings. It should be noted that, where feasible, similar or similar reference numerals may be used in the accompanying drawings and may indicate similar or similar functions. The accompanying drawings depict embodiments of the present invention for illustrative purposes only. Those skilled in the art will readily appreciate from the following description that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles of the disclosure described herein.

[0027] Figure 1A 1 is a circuit diagram of a display device 100 for displaying an image or video according to one embodiment. In various embodiments, the display device 100 can be implemented in any suitable form factor, including display screens for computer display panels, televisions, mobile devices, billboards, etc. The display device 100 may include a liquid crystal display (LCD) device or an LED display device. In an LCD display device, an LED provides a white light backlight that passes through a liquid crystal color filter that controls the color of each pixel of the display. In an LED display device, the LED is directly controlled to emit colored light corresponding to each pixel of the display. The display device 100 may include a display area 105, a driver control line 115, and a control circuit 110. In various embodiments, the display device 100 may include additional, fewer, or different components.

[0028] The display area 105 includes a pixel array for displaying an image based on data received from the control circuit 110. In various embodiments, the display area 105 may include an LED zone 130, a set of distributed driver circuits 120, power supply lines including VLED lines (e.g., VLED_1, ... VLED_M) and ground (GND) lines, and various signaling lines (e.g., a set of address communication lines Int_Addr and power communication lines Pwr connecting adjacent driver circuits 120). In various embodiments, the display area 105 may include additional, fewer, or different components. The VLED line provides power to the LED zone 130 (e.g., by supplying power to the anodes of the LEDs in the LED zone 130). The GND line provides a path for the LED zone 130 and the driver circuit 120 to be grounded.

[0029] As will be described in further detail below, the display area 105 can be physically configured such that the LED zones 130 are stacked above the driver circuits 120. In other words, the array of LED zones 130 is arranged in a first xy plane, and the array of driver circuits 120 is arranged in a second xy plane that is parallel to the first xy plane. In one configuration, each LED zone 130 is stacked above the corresponding driver circuit 120 that drives the LED zone (i.e., in the z-direction). In addition, as FIG. 4A to FIG. 4C As further described in , the components of the display area 105 (e.g., the LED area 130 and the driver circuit 120) can be integrated on the same substrate and in the same package. This structure realizes a display device 100 in which the driver circuit 120 is distributed in the display area 105, and thus realizes a more compact display device 100 than a device in which the driver circuit 120 is outside the display area 105.

[0030] The LED zones 130 may be arranged in a two-dimensional array (e.g., arranged in rows and columns). Each of the LED zones 130 includes one or more LEDs, and the brightness of the light generated by each LED depends on its corresponding driver current 125. In an LCD display, the LED zone 130 may include one or more LEDs that provide backlight for the backlight zone, and the backlight zone may include a one-dimensional pixel array or a two-dimensional pixel array. In an LED display, the LED zone 130 may include one or more LEDs corresponding to a single pixel of the display device 100, or may include a one-dimensional LED array or a two-dimensional LED array corresponding to a pixel array (e.g., one or more columns or rows). For example, in one embodiment, the LED zone 130 may include one or more groups of red LEDs, green LEDs, and blue LEDs, which correspond to sub-pixels of the pixel, respectively. In another embodiment, the LED zone 130 may include one or more groups of red LED strings, green LED strings, and blue LED strings, which correspond to sub-pixel columns or a portion thereof or sub-pixel rows or a portion thereof. For example, the LED zone 130 may include a group of red sub-pixels, a group of green sub-pixels, or a group of blue sub-pixels.

[0031] The LED can be an organic light emitting diode (OLED), an inorganic light emitting diode (ILED), a mini-LED (e.g., ranging in size between 100 microns and 300 microns), a micro-LED (e.g., less than 100 microns in size), a white light emitting diode (WLED), an active matrix OLED (AMOLED), a transparent OLED (TOLED), or some other type of LED.

[0032] The driver circuit 120 drives the LED zones 130 by controlling the corresponding driver current 125 to the LED zones 130 in response to the driver control signal. In one embodiment, the driver circuits 120 are distributed in the display area 105 and arranged in a two-dimensional array (e.g., arranged in rows and columns) corresponding to the LED zones 130. In one embodiment, the driver circuit 120 controls the driver current 125 supplied by VLED via the output pin 126 to control the brightness of one LED zone 130 based on the driver control signal. For example, the brightness of the LED zone 130 generally increases as the driver current 125 increases.

[0033] In an embodiment, the driver circuits 120 can be arranged into groups that share a common set of driver control lines 115, VLED lines, and GND lines. For example, the driver circuits 120 within a group are coupled to a common power communication line Pwr, and each is indirectly controlled by a common address communication line Addr (described in further detail below). In an example embodiment, the driver circuits 120 in a group are daisy-chained together via a set of address communication lines that couple adjacent driver circuits 120 (e.g., from the output pin 126 of one driver circuit 120 to the data input pin 122 of the next driver circuit 120). Figure 1A In the illustrated embodiment of the display device, each row of the display device corresponds to a group of driver circuits 120 that share common driver control lines 115, VLED lines, and GND lines. In other embodiments, the group of driver circuits 120 may correspond to a portion of a row of the display area 105 or an entire column or a portion thereof of the display area 105. In another embodiment, the group of driver circuits 120 may correspond to a block of adjacent driver circuits 120 that may span multiple rows and columns.

[0034] The driver circuit 120 can operate in various modes, including at least an addressing mode, a configuration mode, and an operating mode. During the addressing mode, the control circuit 110 assigns a unique address to each driver circuit 120 in the group, which is used to broadcast additional commands and data in the configuration mode and the operating mode. During the configuration mode, the control circuit 110 configures the driver circuit 120 by one or more operating parameters (e.g., an overcurrent threshold, an overvoltage threshold, a clock division ratio, and / or a conversion rate control). During the operating mode, the control circuit 110 provides control data to the driver circuit 120, which controls the driver circuit 120 to control the corresponding driver current 125 to the LED zone 130, thereby controlling the brightness. In other embodiments, the mode in which the display device 100 operates may include additional, fewer, or different operating modes. For example, the operating mode may include an initialization mode and a shutdown mode.

[0035] The driver circuit 120 may include a four-pin configuration as shown in the illustrative example of FIG1. ​​In the four-pin configuration, the driver circuit 120 may include a data input pin (Di) 122, a power line communication input pin (PLCi) 124, an output pin (Out) 126, and a ground pin (Gnd) 128. In an embodiment, the output 126 may alternatively include a set of pins to control multiple channels of the LED zone 130. For example, the output 126 may include three pins to control a red channel, a green channel, and a blue channel of the LED zone 130.

[0036] The data input pin 122 is used in an addressing mode to receive an incoming addressing signal from the control circuit 110 via one of the common address communication lines (e.g., Addr1, Addr2, ... AddrN) (in the case of the first driver circuit 120 in each group) or via one of the address communication lines Int Addr coupled to adjacent driver circuits 120 (in the case of the remaining driver circuits 120 in each group not directly coupled to the control circuit 110). As will be described in further detail below, the incoming addressing signal may be a digital signal that controls the address of each respective driver circuit 120. The first driver circuit 120 in each group stores an address based on the incoming addressing signal and generates an outgoing addressing signal for output via the output pin 126. For example, the driver circuit 120 may receive an address, store the address, and increment the address by 1 or another fixed amount and send the incremented address as an outgoing addressing signal to the data input pin 122 of the next driver circuit 120 in the group. Alternatively, driver circuit 120 may receive an address of a previous driver circuit, increment the address, store the incremented address, and send the incremented address to the next driver circuit. In other implementations, driver circuit 120 may generate an address based on an incoming address signal according to a different function. Figure 1C The waveforms illustrating the addressing scheme are described in more detail in .

[0037] Output pin 126 serves a dual purpose depending on the mode of operation. In the addressing mode of display device 100, output pin 126 provides an outgoing addressing signal to the next driver circuit 120 in the group of driver circuits 120 as described above. In the operating mode of display device 100, output pin 126 is coupled to collect current from the corresponding LED zone 130 to control the supply of driver current 125. In one embodiment, driver circuit 120 includes more than one output pin 126. For example, in an LED display, LED zone 130 may include three or more LEDs or LED strings corresponding to three sub-pixels (e.g., red sub-pixel, green sub-pixel, and blue sub-pixel), and driver circuit 120 may include three output pins 126, one for each color channel.

[0038] The power line communication input pin 124 is configured to receive a power line communication signal from the control circuit 110 via a common power communication line (e.g., Pwr1, Pwr2, ... PwrM) of each group. The power line communication signal includes a supply voltage that can be modulated to encode a driver control signal or other control information as digital data. For example, the power line communication signal can encode operating parameter information or control data information for operating the driver circuit 120. Specifically, during the configuration mode, the power line communication signal provides one or more operating parameters as digital data (e.g., various over-current thresholds or over-voltage thresholds for preventing LED overload, different clock division ratios, and conversion rate control of the driver current 125). During the operation mode, the power line communication signal provides control data (e.g., brightness control information) for the LED zone 130. The brightness control information may include one or more address words for identifying the driver circuit 120 within the driver circuit 120 group, and one or more data words for controlling the brightness of the LED zone 130 by controlling the driver current 125 of the identified driver circuit 120. Figure 1B and Figure 1C Example waveforms associated with a power line communication signal are provided. In some embodiments, the power line communication signal supplies a DC voltage between 3 volts and 12 volts as a supply voltage. In one embodiment, the power line communication signal can provide a supply voltage greater than 4.5 volts, wherein the digital data signal has a digital data voltage of 0.5 peak-to-peak voltage signal with a maximum data rate of up to 2 megahertz (MHz).

[0039] The ground pin 128 is configured to provide a path to a ground line for the driver circuit 120 , and the LED zones 130 corresponding to the path can share the path.

[0040] Figure 1A The control circuit 110 shown in generates address communication signals and power line communication signals to control the display area 105 (as described in further detail above) via a common driver control line 115. In one example implementation, the number of common power communication lines (M) and the number of common address communication lines (N) are equal (e.g., M=N).

[0041] In another embodiment, a shared power line provides power to both the driver circuit 120 and the LED zone 130. Instead of using power line communication, a digital signal uses a clockless shift register to serially shift data into the driver circuit 120. The clockless shift register can be implemented in a variety of ways. In one embodiment, a bi-phase sign code encoding is used to extract the clock and shift the data into the driver circuit 120. The data can also be shifted all the way through each driver circuit 120 in the serial chain and then shifted out again for error detection. In this embodiment, data is written to all driver circuits 120 each time the brightness control signal changes. In this embodiment, the driver circuits 120 do not have to be individually addressable.

[0042] Figure 1B is a waveform diagram showing an example waveform of a power line communication signal according to an embodiment. The power line communication signal switches between a high data voltage V_high and a low data voltage V_low to encode digital data (e.g., operating parameters or brightness control information), which results in an approximate average voltage V_avg. In an example embodiment, the high data voltage V_high is 5.5 volts, the low data voltage V_low is 4.5 volts, and the average voltage V_avg is 5 volts. Digital data can be encoded using a bi-phase symbol code. In this encoding scheme, a logic value is represented by the presence or absence of a transition in each cycle. For example, a cycle including a transition can represent a logical high value, while a cycle without a transition can represent a logical low value. In addition, in this encoding, the signal also transitions between logic levels during each cycle. The encoding scheme advantageously ensures that the power line communication signal maintains an average voltage V_avg very close to the midpoint between the logic levels so as to provide a relatively stable DC supply voltage that can be extracted from the power line communication signal to power the driver circuit 120. Another advantage of this scheme is that it does not require a separate clock signal and can be implemented on a single lead.

[0043] Figure 1C 1 is a waveform diagram illustrating an operation mode of the display device 100 according to one embodiment. Three operation modes of the display device 100 (ie, addressing mode 150, configuration mode 160, and operation mode 170) and an off mode 180 are depicted. Figure 1C Shown are power line communication signals received at the power line communication input pin (PLCi) 124, address communication signals received at the data input pins 122 (e.g., Di_0, Di_1, ... Di_m), and address communication signals provided by the output pins 126 (e.g., Out_0, Out_1, ... Out_m-1) of the driver circuit 120 in the driver circuit 120 group during various operating modes.

[0044] During the addressing mode 150 of operation, at the beginning of the addressing mode 150, the power line communication signal received at the power line communication input pin 124 changes from low to high (i.e., the driver circuit 120 begins to receive the supply voltage). The address communication signal propagates through the data input pin 122 and the output pin 126 of the driver circuit 120 to assign the corresponding address to the driver circuit 120. For example, the control circuit 110 outputs a logic high signal on the common address communication line Addrn for group n and the first driver circuit 120 in the driver circuit 120 group n receives the high signal at its data input pin 122 (i.e., Di_0) as the incoming addressing signal. In response to detecting the high signal on Di_0, the driver circuit sets its address to the initial address value (e.g., 0000). The first driver circuit 120 stores the address, increments the address value (i.e., increases the address value by one), and provides the incremented address (e.g., 0001) as the outgoing addressing signal via the output pin 126 (i.e., Out_0) and the address communication line Int Addr. The next (subsequent) driver circuit 120 in group n receives the incremented address (i.e., 0001) as an incoming addressing signal at its data input pin 122 (i.e., Di_1). The driver circuit 120 similarly stores the address 0001, increments the address, and provides the incremented address (e.g., 0010) as an outgoing addressing signal to the next driver circuit 120 in group n via the output pin 126 (i.e., Out_1) and the address communication line Int Addr. The process of receiving and storing addresses, incrementing addresses, and sending the incremented address to the next driver circuit 120 continues until the addressing mode is complete (i.e., addresses have been assigned to all driver circuits 120 in the group of driver circuits 120). In some embodiments, the driver circuit 120 may alternatively modify the incoming address before storing the incoming address. For example, the driver circuit receives the address, increments the address, and stores and outputs the incremented address. In other alternative implementations, a different arbitrary addressing scheme may be used, where each driver circuit 120 may generate the next address according to some other function that is not necessarily incrementing. For example, driver circuit 120 may decrement the address, generate a random address, or apply some other arbitrary function to generate a new address.

[0045] During the configuration mode 160 , the power line communication signal received at the power line communication input pin 124 provides various operating parameters (Op params) as digital data on the power line communication input pin 124 .

[0046] During the operation mode 170, the power line communication signal provides control data (Con data) as digital data modulated onto the supply voltage. The Con data may be updated with each image frame or video frame. The operation mode 170 continues until the power line communication signal transitions from high to low (i.e., the driver circuit 120 no longer receives the supply voltage), at which time the driver circuit 120 shuts down.

[0047] Figure 2 1 is an example circuit diagram of a control circuit 110 according to one embodiment. The control circuit 110 generates an address communication signal Addr and a power line communication signal Pwr for controlling a display device (e.g., a display device 100), and provides these signals to a driver circuit 120 via a driver control line 115. The control circuit 110 may include a timing controller 210 and a bridge 220. In various embodiments, the control circuit 110 may include additional, fewer, or different components. For example, in some embodiments, a field programmable gate array (FPGA) and / or a PHY block may be used to implement the control circuit 110. The control circuit 110 is powered by an input voltage (VCC) and is connected to ground (GND). The control circuit 110 may control the display device using an active matrix (AM) driving method or a passive matrix (PM) driving method.

[0048] The timing controller 210 generates an image control signal 215 indicating a value for driving a pixel of the display device 100 and a timing for driving the pixel. For example, the timing controller 210 controls the timing of an image frame or a video frame, and controls the timing of driving each of the LED areas 130 within the image frame or the video frame. In addition, the timing controller 210 controls the brightness of each of the LED areas 130 during a given image frame or a video frame. The image control signal 215 is provided by the timing controller 210 to the bridge 220.

[0049] The bridge 220 converts the image control signal 215 into driver control signals of the address communication signal Addr and the power line communication signal Pwr. For example, the bridge 220 may generate the address communication signal Addr for the first driver circuit 120 in the driver circuit 120 group during the addressing mode according to the above control scheme.

[0050] Figure 3is an example circuit diagram of a driver circuit 120 according to one embodiment. The driver circuit 120 may include a voltage regulation circuit 310, an Rx_PHY 320, a low dropout regulator LDO_D 330, an oscillator OSC 340, a control logic 350, an address driver 360, a pulse width modulation (PWM) dimming circuit 370, a transistor 375, and a brightness control circuit 380. In various embodiments, the driver circuit 120 may include additional, fewer, or different components.

[0051] The voltage regulation circuit 310 demodulates the power line communication signal received at the power line communication input pin 124 into a supply voltage and digital data. The supply voltage represents the DC component of the power line communication signal, and the digital data represents the modulation component of the power line communication signal. In an example embodiment, the voltage regulation circuit 310 includes a first-order RC filter followed by an active follower. Digital data (e.g., a driver control signal) is provided to Rx_PHY 320. Rx_PHY 320 is a physical layer that provides a connection between the voltage regulation circuit 310 and the control logic 350. In an example embodiment, Rx_PHY 320 provides a connection with a maximum bandwidth of 2MHz with 36 levels of cascade. The supply voltage is provided to LDO_D 330. LDO_D 330 converts the supply voltage into a stable DC voltage (which can step down the voltage) for powering the oscillator OSC 340, the control logic 350 and other components (not shown). In an example embodiment, the stable DC voltage can be 1.8 volts. Oscillator OSC 340 provides a clock signal. In an example implementation, the maximum frequency of the clock signal is approximately 10.7 MHz.

[0052] The control logic 350 receives the driver control signal from the Rx_PHY 320, the DC voltage from the LDO_D 330, and the clock signal from the oscillator OSC 340. Depending on the operating mode of the display device, the control logic 350 may also receive digital data from the incoming addressing signal received at the data input pin 122. Depending on the operating mode, the control logic 350 may output an enable signal 352, an incremented data signal Inc_data 354, a PWM clock selection signal PWMCLK_sel 356, and a maximum current signal Max.Current 358. During the addressing mode, the control logic 350 activates the enable signal 352 to enable the address driver 360. The control logic 350 receives the incoming address signal via the data input pin 122, stores the address, and provides the incremented data signal Inc_data 354 representing the outgoing address to the address driver 360. When the enable signal 352 is activated during the addressing mode, the address driver 360 buffers the incremented data signal Inc_data 354 to the output pin 126. The control logic 350 can control the PWM dimming circuit 370 to turn off the transistor 375 during the addressing mode to effectively block the current path from the LED.

[0053] During the operational mode and configuration mode, the control logic deactivates the enable signal 352 and the output of the address driver 360 is tri-stated to effectively decouple it from the output pin 126. During the operational mode, the PWM clock select signal PWMCLK_sel 356 specifies the duty cycle for controlling the PWM dimming by the PWM dimming circuit 370. Based on the selected duty cycle, the PWM dimming circuit 370 controls the timing of the on and off states of the transistor 375. During the on state of the transistor 375, a current path is established from the output pin 126 (coupled to the LED zone 130) to the ground pin 128 through the transistor 375, and the brightness control circuit 380 sinks the driver current of the LEDs passing through the LED zone 130. During the off state of the transistor 375, the current path is interrupted to prevent current from flowing through the LED zone 130. When transistor 375 is in the on state, brightness control circuit 380 receives maximum current signal Max.Current 358 from control logic 350 and controls the current level flowing through the LED (from output pin 126 to ground pin 128). During the operation mode, control logic 350 controls the duty cycle of PWM dimming circuit 370 and maximum current Max.Current 358 of brightness control circuit 380 to set LED zone 130 to the desired brightness.

[0054] Figure 4A is a cross-sectional view of a first embodiment of a display device 400 including an integrated LED and driver circuit 405 .

[0055] exist Figure 4A In the example shown, the display device 400 includes a printed circuit board (PCB) 410, a PCB interconnect layer 420, and an integrated LED and driver circuit 405, which includes a substrate 430, a driver circuit layer 440, an interconnect layer 450, a conductive redistribution layer 460, and an LED layer 470. A bonding wire 455 may be included for connection between the PCB interconnect layer 420 and the integrated LED and driver circuit 405. The PCB 410 includes a support plate for mounting the integrated LED and driver circuit 405, the control circuit 110, and various other supporting electronic devices. The PCB 410 may include internal electrical traces and / or through holes that provide electrical connections between the electronic devices. The PCB interconnect layer 420 may be formed on the surface of the PCB 410. The PCB interconnect layer 420 includes pads for mounting various electronic devices and traces for achieving connections therebetween.

[0056] The integrated LED and driver circuit 405 includes a substrate 430 that can be mounted on a surface of the PCB interconnect layer 420. The substrate 430 can be, for example, a silicon (Si) substrate. In other embodiments, the substrate 430 can include various materials, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), sapphire, silicon carbide (SiC), etc.

[0057] The driver circuit layer 440 may be fabricated on the surface of the substrate 430 using a silicon transistor process (e.g., a BCD process). The driver circuit layer 440 may include one or more driver circuits 120 (e.g., a single driver circuit 120 or a group of driver circuits 120 arranged in an array). An interconnect layer 450 may be formed on the surface of the driver circuit layer 440. The interconnect layer 450 may include one or more metal or metal alloy materials, such as Al, Ag, Au, Pt, Ti, Cu, or any combination thereof. The interconnect layer 450 may include electrical traces to electrically connect the driver circuit 120 in the driver circuit layer 440 to wire bonds 455, which in turn are connected to the control circuit 110 on the PCB 410. In an embodiment, each wire bond 455 provides an electrical connection. For example, the integrated LED and driver circuit 405 may include five wire bonds, including: a first lead for providing a driver control signal from the control circuit 110 on the PCB 410 to one or more driver circuits 120 on the driver circuit layer 440; a second lead for providing an incoming address signal to the driver circuit layer 440; a third lead for providing an outgoing address signal from the driver circuit layer 440; a fourth lead for providing a supply voltage (e.g., VLED) to the LEDs in the LED region 130 on the LED layer 470; and a fifth lead for providing a path to the circuit ground (GND). In addition, the interconnect layer 450 may provide an electrical connection for supplying a driver current between the driver circuit layer 440 and the conductive redistribution layer 460.

[0058] In an embodiment, the interconnect layer 450 is not necessarily distinct from the driver circuit layer 440 , and these layers 440 , 450 may be formed in a single process, with the interconnect layer 450 representing the top surface of the driver layer 440 .

[0059] The conductive redistribution layer 460 may be formed on the surface of the interconnect layer 450. The conductive redistribution layer 460 may include a metal grid made of a conductive material such as Cu, Ag, Au, Al, etc. The LED layer 470 includes LEDs on the surface of the conductive redistribution layer 460. The LED layer 470 may include an LED array arranged into the LED region 130 as described above. The conductive redistribution layer 460 provides electrical connections between the LEDs in the LED layer 470 and one or more driver circuits in the driver circuit layer 440 for supplying driver current, and provides a mechanical connection to fix the LEDs on the substrate 430 so that the LED layer 470 and the conductive redistribution layer 460 are vertically stacked on the driver circuit layer 440.

[0060] Thus, in the illustrated circuit 405, one or more driver circuits 120 and an LED region 130 including LEDs are integrated into a single package including a substrate 430, wherein the LEDs in an LED layer 470 are stacked on the driver circuits 120 in a driver circuit layer 440. By stacking the LED layer 470 on the driver circuit layer 440 in this manner, the driver circuits 120 can be distributed in the display area 105 of the display device 100.

[0061] Figure 4B is a cross-sectional view of a second embodiment of a display device 480 including an integrated LED and driver circuit 485 according to one embodiment. The device 480 is substantially similar to Figure 4A The device 400 described above is a device 400, but the electrical connection between the driver circuit layer 440 and the PCB 410 is achieved by using through holes 432 and corresponding connecting solder balls 434 instead of leads 455. Here, the through holes 432 are electroplated vertical electrical connections that completely pass through the substrate layer 430. In one embodiment, the substrate layer 430 is a Si substrate, and the through chip through holes 432 are through silicon vias (TSVs). The through chip through holes 432 are etched into the substrate layer 430 during manufacturing and penetrate the substrate layer 430, and the through chip through holes 432 can be filled with metals, such as tungsten (W), copper (C) or other conductive materials. The solder balls 434 contain conductive materials that provide electrical and mechanical connections to the electrical traces on the PCB interconnect layer 420 and the plating of the through holes 432. In one embodiment, each through hole 432 provides an electrical connection for providing signals such as driver control signals from the control circuit 110 on the PCB 410 to the driver circuit 120 group on the driver circuit layer 440. The vias 432 may also provide connections for incoming and outgoing addressing signals, a supply voltage (e.g., VLED) to the LEDs in the LED zones 130 on the LED layer 470, and a path to circuit ground (GND). For example, five or more vias 432 may be utilized to provide these connections.

[0062] Figure 4C is a cross-sectional view of a third embodiment of a display device 490 including an integrated LED and driver circuit 495. The device 490 is substantially similar to Figure 4B4. The device 480 described in the foregoing, but includes a driver circuit layer 440 and an interconnect layer 450 on the opposite side of the substrate 430 from the conductive redistribution layer 460 and the LED layer 470. In this embodiment, the interconnect layer 450 and the driver circuit layer 440 are electrically connected to the PCB 410 via a lower conductive redistribution layer 465 and solder balls 434. The lower conductive redistribution layer 465 and the solder balls 434 provide mechanical and electrical connections (e.g., for driver control signals) between the driver circuit layer 440 and the PCB interconnect layer 420. The driver circuit layer 440 and the interconnect layer 450 are electrically connected to the LEDs of the conductive redistribution layer 460 and the LED layer 470 via one or more plated through holes 432 through the substrate 430. Figure 4C The one or more vias 432 seen in the figure may be used to provide driver current from the driver circuit in the driver circuit layer 440 to the LEDs in the LED layer 470 as well as to provide other signals as described above.

[0063] In alternative embodiments, the integrated driver and LED circuits 405 , 485 , 495 may be mounted to a different base, such as a glass base, instead of the PCB 410 .

[0064] Figure 5 is a top view of a display device using an integrated LED and driver circuit 500 according to one embodiment. The circuit 500 may correspond to FIG. 4A to FIG. 4C A top view of any integrated LED and driver circuit 405, 485, 495 depicted in FIG. Figure 5 In the passive matrix architecture, multiple LEDs 510 are arranged in rows and columns (e.g., C1, C2, C3, ..., Cn-1, Cn). For the passive matrix architecture, each row of LEDs 510 is connected to a demultiplexer that outputs multiple VLED signals (i.e., VLED_1, ..., VLED_M) through a conductive redistribution layer 520. The VLED signal provides power (i.e., a supply voltage) to the corresponding row of LEDs 510 via the conductive redistribution layer 520.

[0065] Figure 6 FIG. 6 is a schematic diagram showing several layers of a display device 600 with integrated LEDs and driver circuits according to one embodiment. The schematic diagram includes FIG. 4A to FIG. 4C The PCB 410, the driver circuit layer 440, the conductive redistribution layer 460 and the LED layer 470 described in the drawings. Figure 6 The schematic diagram shows FIG. 4A to FIG. 4CThe circuit connections of the circuits 405, 485, 495 of FIG. 4 are shown, but the physical layout is not reflected. As described above, in the physical layout, the LED layer 470 is located on top of the conductive redistribution layer 460 (i.e., vertically stacked on the conductive redistribution layer 460). The conductive redistribution layer 460 is located on top of the driver circuit layer 440 and the driver circuit layer 440 is located on top of the PCB 410.

[0066] PCB 410 includes connections to a power source (e.g., VLED) for powering the LEDs, control circuits for generating control signals, general I / O connections, and ground (GND) connections. Driver circuit layer 440 includes a plurality of driver circuits (e.g., DC1, DC2, ... DCn) and a demultiplexer DeMux. Conductive redistribution layer 460 provides electrical connections between the driver circuits and demultiplexer DeMux in driver circuit layer 440 and a plurality of LEDs in LED layer 470. LED layer 470 includes a plurality of LEDs arranged in rows and columns. In this example implementation, each LED column is electrically connected to a driver circuit in driver circuit layer 440 via conductive redistribution layer 460. The electrical connection established between each driver circuit and its corresponding LED column controls the supply of driver current from the driver circuit to the column. In this embodiment, each diode shown in the LED layer corresponds to an LED zone. Each LED row is electrically connected to an output (e.g., VLED_1, VLED_2, ... VLED_M) of demultiplexer DeMux in driver circuit layer 440 via conductive redistribution layer 460. The demultiplexer DeMux in the driver circuit layer 440 is connected to the power supply (VLED) and the control signal from the PCB 410. The control signal indicates to the demultiplexer DeMux which LED row or rows to enable and power them using the VLED line. Thus, when power (VLED) is supplied on the row associated with a particular LED in the LED layer 470 and the driver current is supplied to its associated column, the particular LED is enabled.

[0067] The technical solutions provided by the present invention include the following solutions.

[0068] Solution 1. A display device comprising:

[0069] A control circuit for generating a driver control signal for controlling the display device;

[0070] an array of LED zones, each LED zone comprising one or more LEDs that generate light in response to a corresponding driver current; and

[0071] a driver circuit array, the driver circuits being distributed in a display area of ​​the display device, each driver circuit in the driver circuit array being configured to drive one or more of the light emitting diode areas by controlling a corresponding driver current in response to the driver control signal,

[0072] The one or more light-emitting diodes in the light-emitting diode area and a driver circuit driving the one or more light-emitting diodes in the light-emitting diode area are integrated and vertically stacked above a substrate.

[0073] Solution 2. The display device according to Solution 1, wherein the one or more light emitting diodes are micro light emitting diodes having a size ranging between 100 micrometers μm and 300 micrometers μm.

[0074] Solution 3. The display device according to Solution 1, wherein the one or more light-emitting diodes are micro light-emitting diodes having a size less than 100 micrometers (μm).

[0075] Solution 4. The display device according to Solution 1, wherein the driver circuit of the driver circuit array comprises:

[0076] control logic to operate in at least an addressing mode and an operating mode, wherein in the operating mode the control logic obtains a driver control signal from a power line communication signal and controls a driver current based on the driver control signal, and wherein in the addressing mode the control logic obtains an incoming addressing signal, stores an address of the driver circuit based on the incoming addressing signal, and generates an outgoing addressing signal based on the incoming addressing signal;

[0077] a data input pin for receiving said incoming addressing signal during said addressing mode;

[0078] a power line communication input pin for receiving the power line communication signal in the operating mode, the power line communication signal comprising a supply voltage modulated to encode the driver control signal;

[0079] an output pin for sinking the driver current during the operating mode and outputting the outgoing addressing signal during the addressing mode; and

[0080] A ground pin is used to couple to a circuit ground.

[0081] Solution 5. The display device according to Solution 1, wherein the control circuit comprises:

[0082] a timing controller for providing an image control signal indicating a value for driving a pixel of the display device and a timing for driving the pixel; and

[0083] A bridge is used to convert the image control signal into a driver control signal for controlling the driver circuit array.

[0084] Solution 6. An integrated light emitting diode and driver circuit for a display device, comprising:

[0085] substrate;

[0086] a light emitting diode in the light emitting diode layer, the light emitting diode generating light in response to a driver current;

[0087] a driver circuit on the substrate in a driver circuit layer, the driver circuit for driving the light emitting diode by controlling the driver current in response to a driver control signal; and

[0088] A conductive redistribution layer is provided between the driver circuit layer and the light-emitting diode layer, the conductive redistribution layer being used for: electrically connecting the light-emitting diode to the driver circuit to supply the driver current; and mechanically fixing the light-emitting diode above the substrate so that the light-emitting diode layer and the conductive redistribution layer are vertically stacked above the driver circuit layer.

[0089] Embodiment 7. An integrated light-emitting diode and driver circuit according to Embodiment 6, wherein the light-emitting diode is a micro light-emitting diode having a size range between 100 micrometers μm and 300 micrometers μm.

[0090] Option 8. An integrated light-emitting diode and driver circuit according to Option 6, wherein the light-emitting diode is a micro light-emitting diode having a size less than 100 micrometers μm.

[0091] Option 9. An integrated light-emitting diode and driver circuit according to Option 6, wherein the light-emitting diode layer includes a plurality of light-emitting diodes arranged in a two-dimensional array, and the conductive redistribution layer electrically connects each row of light-emitting diodes to a power source.

[0092] Solution 10. The integrated light emitting diode and driver circuit according to Solution 9, further comprising:

[0093] A demultiplexer is configured to receive a supply voltage from the power supply and output the supply voltage to selected lines of the conductive redistribution layer, the selected lines connecting one or more selected rows of the light emitting diodes.

[0094] Embodiment 11. The integrated light emitting diode and driver circuit of Embodiment 6, wherein the driver circuit layer is stacked between the substrate and the conductive redistribution layer.

[0095] Embodiment 12. The integrated light emitting diode and driver circuit according to embodiment 11 further comprises:

[0096] An interconnect layer includes traces that supply driver current from the driver circuit layer to the conductive redistribution layer.

[0097] Embodiment 13. The integrated light emitting diode and driver circuit according to embodiment 12 further comprises:

[0098] A set of bonding wires are coupled between the interconnect layer and the printed circuit board.

[0099] Option 14. An integrated light-emitting diode and driver circuit according to Option 13, wherein the interconnect layer is connected to the printed circuit board via at least five leads, the five leads comprising: a first lead, which provides a driver control signal from a control circuit on the printed circuit board to the driver circuit; a second lead, which provides an address communication input signal to the driver circuit; a third lead, which provides an address communication output signal from the driver circuit; a fourth lead, which provides a supply voltage to the light-emitting diode; and a fifth lead, which provides a path to circuit ground.

[0100] Embodiment 15. The integrated light emitting diode and driver circuit according to embodiment 12 further comprises:

[0101] A set of vias passes through the substrate, connecting the interconnect layer to a printed circuit board.

[0102] Option 16. An integrated light-emitting diode and driver circuit according to Option 15, wherein the group of through holes includes: a first through hole for providing a driver control signal from a control circuit on the printed circuit board to the driver circuit; a second through hole for providing an address communication input signal to the driver circuit; a third through hole for providing an address communication output signal from the driver circuit; a fourth through hole for providing a supply voltage to the light-emitting diode; and a fifth through hole for providing a path to the circuit ground.

[0103] Option 17. An integrated light-emitting diode and driver circuit according to Option 6, wherein the driver circuit layer is on the side of the substrate opposite to the conductive redistribution layer and the light-emitting diode layer, and wherein the driver circuit layer is coupled to the conductive redistribution layer through one or more through holes in the substrate.

[0104] Embodiment 18. The integrated light emitting diode and driver circuit according to embodiment 17 further comprises:

[0105] an interconnect layer stacked vertically between the driver circuit layer and the substrate, the interconnect layer for providing traces for supplying the driver current to the conductive redistribution layer; and

[0106] A lower conductive redistribution layer is used to electrically and mechanically couple the driver circuit layer to a printed circuit board.

[0107] 19. A driver circuit for a display device, comprising:

[0108] control logic to operate in at least an addressing mode and an operating mode, wherein in the operating mode the control logic obtains a driver control signal from a power line communication signal and controls a driver current based on the driver control signal, and wherein in the addressing mode the control logic obtains an incoming addressing signal, stores an address of the driver circuit based on the incoming addressing signal, and generates an outgoing addressing signal based on the incoming addressing signal;

[0109] a data input pin for receiving said incoming addressing signal during said addressing mode;

[0110] a power line communication input pin for receiving the power line communication signal in the operating mode, the power line communication signal comprising a supply voltage modulated to encode the driver control signal;

[0111] an output pin for sinking the driver current during the operating mode and outputting the outgoing addressing signal during the addressing mode; and

[0112] Ground pin, which is used to provide a ground path.

[0113] Embodiment 20. The driver circuit according to embodiment 19 further comprises:

[0114] an address driver for receiving an enable signal from the control logic to enable the address driver during the addressing mode and disabling the address driver during the operating mode, and providing an outgoing addressing signal from the control logic to the output pin when the address driver is enabled during the addressing mode.

[0115] Embodiment 21. The driver circuit according to embodiment 19 further includes:

[0116] a pulse width modulation dimming circuit for receiving a brightness signal from the control logic and generating a pulse width modulation signal based on the brightness signal;

[0117] a pulse width modulation transistor coupled to the output pin, the output pin being used to sink a driver current from a light emitting diode when the pulse width modulation signal turns on the pulse width modulation transistor; and

[0118] The brightness control circuit is configured to receive a current control signal from the control logic and control a current passing through the pulse width modulation transistor when the pulse width modulation signal turns on the pulse width modulation transistor.

[0119] Embodiment 22. The driver circuit according to embodiment 19 further includes:

[0120] a voltage regulation circuit for receiving the power line communications signal from a power line communications pin and demodulating the power line communications signal to generate the driver control signal and a DC voltage to the control logic; and

[0121] A low dropout voltage regulator is used to generate a supply voltage to the control logic based on the DC voltage.

[0122] When reading this disclosure, those skilled in the art will recognize that additional alternative embodiments can be implemented by the principles disclosed herein. Therefore, although specific embodiments and applications have been shown and described, it is to be understood that the disclosed embodiments are not limited to the specific structures and components disclosed herein. Various modifications, changes and variations that are obvious to those skilled in the art may be made to the arrangement, operation and details of the methods and devices disclosed herein without departing from the spirit and scope described herein.

Claims

1. An integrated circuit for a display device, comprising: substrate; Any one of a silicon substrate, a gallium arsenide substrate, an indium phosphide substrate, a gallium nitride substrate, an aluminum nitride substrate, a sapphire substrate, and a silicon carbide substrate; a light emitting diode in the light emitting diode layer, the light emitting diode generating light in response to a driver current; a driver circuit on the substrate in a driver circuit layer, the driver circuit for driving the light emitting diode by controlling the driver current in response to a driver control signal; a conductive redistribution layer between the driver circuit layer and the light emitting diode layer, the conductive redistribution layer being used to: electrically connect the light emitting diode to the driver circuit to supply the driver current; and mechanically fix the light emitting diode above the substrate so that the light emitting diode layer and the conductive redistribution layer are vertically stacked above the driver circuit layer, wherein the driver circuit layer is stacked between the substrate and the conductive redistribution layer; as well as An interconnect layer includes traces that supply driver current from the driver circuit layer to the conductive redistribution layer. 2 . The integrated circuit according to claim 1 , wherein the light emitting diode is a micro light emitting diode having a size range between 100 micrometers μm and 300 micrometers μm.

3. The integrated circuit according to claim 1, wherein: The light emitting diode is a micro light emitting diode with a size less than 100 micrometers μm.

4. The integrated circuit according to claim 1, wherein: The light emitting diode layer includes a plurality of light emitting diodes arranged in a two-dimensional array, and the conductive redistribution layer electrically connects each row of light emitting diodes to a power source.

5. The integrated circuit of claim 4 , further comprising: A demultiplexer is configured to receive a supply voltage from the power supply and output the supply voltage to selected lines of the conductive redistribution layer, the selected lines connecting one or more selected rows of the light emitting diodes.

6. The integrated circuit of claim 1 , further comprising: A set of bonding wires are coupled between the interconnect layer and the printed circuit board.

7. The integrated circuit according to claim 6, wherein: The interconnect layer is connected to the printed circuit board by at least five leads, the five leads including: a first lead that provides a driver control signal from a control circuit on the printed circuit board to the driver circuit; a second lead that provides an address communication input signal to the driver circuit; a third lead that provides an address communication output signal from the driver circuit; a fourth lead that provides a supply voltage to the light emitting diode; and a fifth lead that provides a path to circuit ground.

8. The integrated circuit of claim 1 , further comprising: A set of vias passes through the substrate, connecting the interconnect layer to a printed circuit board.

9. The integrated circuit of claim 8, wherein: The set of through holes includes: a first through hole for providing a driver control signal from a control circuit on the printed circuit board to the driver circuit; a second through hole for providing an address communication input signal to the driver circuit; a third through hole for providing an address communication output signal from the driver circuit; a fourth through hole for providing a supply voltage to the light emitting diode; and a fifth through hole for providing a path to circuit ground.

10. The integrated circuit of claim 1, wherein the driver circuit layer is on an opposite side of the substrate from the conductive redistribution layer and the light emitting diode layer, and wherein: The driver circuit layer is coupled to the conductive redistribution layer through one or more through vias of the substrate.

11. The integrated circuit of claim 10, further comprising: an interconnect layer stacked vertically between the driver circuit layer and the substrate, the interconnect layer for providing traces for supplying the driver current to the conductive redistribution layer; as well as A lower conductive redistribution layer is used to electrically and mechanically couple the driver circuit layer to a printed circuit board.

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