A memory and a method of using the same

Abstract

The present application discloses a memory and a method for using the memory. The memory retains the input and output ports of the first sense amplifier and the write drive circuit integrated on one side of the memory cell, and further adds at least one second sense amplifier and at least one read drive circuit on the other side of the memory cell; wherein, each bit line in each memory cell in the memory cell array is connected one-to-one to a second sense amplifier, and the other end of the second sense amplifier is connected to the read drive circuit. Since each bit line in each memory cell in the memory cell array is connected to a second sense amplifier, the data in the bit where the bit line is located can be read through each second sense amplifier without interfering with each other. In this way, a large amount of data can be read in parallel (as many data as there are bits can be read simultaneously), which is particularly suitable for application scenarios with high-bandwidth read and low-bandwidth write.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a memory and a method of using the memory. Background Art

[0002] In applications with low-bandwidth writes and high-bandwidth reads, using conventional read-write memories can make the read port a bottleneck, making it difficult to meet the demands of dense read operations. Therefore, this problem is often addressed by increasing the memory's data output bandwidth, for example, by using an 8TB Static Random-Access Memory (SRAM) consisting of a register file with a single write and two reads; or by increasing the read frequency, for example, by using a high-speed single-port SRAM.

[0003] However, using 8TSRAM will increase the area and must avoid the problem of writing on one side and reading from the other side at the same time, which will reduce the bandwidth. Although using high-speed single-port SRAM can keep the area unchanged, it cannot read and write simultaneously, which not only limits the bandwidth but also greatly increases power consumption due to the increased read frequency. Summary of the Invention

[0004] In response to the above technical problems, the applicant creatively provides a memory and a method for using the memory.

[0005] According to a first aspect of an embodiment of the present application, a memory is provided, characterized in that the memory includes: a memory cell array; an address decoder located on one side of the memory cell array, and an input / output port integrated with a first sensitive amplifier and a write driver circuit; at least one second sensitive amplifier and at least one read driver circuit located on the other side of the memory cell array; wherein each bit line in each memory cell in the memory cell array is one-to-one connected to a second sensitive amplifier, and the other end of the second sensitive amplifier is connected to the read driver circuit.

[0006] Optionally, the second sense amplifier is connected to the read driver circuit in a one-to-one manner.

[0007] Optionally, the second sense amplifier comprises a latch-type sense amplifier.

[0008] Optionally, the memory is further provided with an isolation device between the bit line and the second sense amplifier, wherein the isolation device has a switch that can be used to connect or disconnect the second sense amplifier and the bit line.

[0009] Optionally, the memory cell array includes a two-dimensional matrix structure.

[0010] According to the second aspect of an embodiment of the present application, a method for using a memory is also provided, which is applied to any of the memories mentioned above, and the method includes: receiving at least one address input; determining at least one read drive circuit to be turned on based on the at least one address input; and sending an on signal to at least one read drive circuit to perform at least one read operation in parallel.

[0011] Optionally, the method further includes: establishing a one-to-one mapping between addresses and read driver circuits.

[0012] Optionally, the memory is provided with an isolation device between the bit line and the first sense amplifier. Accordingly, after sending an enable signal to at least one read drive circuit to perform at least one read operation in parallel, the method further includes: enabling the isolation device to disconnect the connection between the bit line and the first sense amplifier.

[0013] Optionally, after turning on the isolation device, the method further includes, in response to a write operation request for the bit line, performing the following operations: turning on a write driver circuit corresponding to the bit line; and sending a turn-on signal to the write driver circuit to perform a write operation.

[0014] An embodiment of the present application provides a memory that, while retaining an input / output port integrated with a first sense amplifier and a write driver circuit on one side of a memory cell, further includes at least one second sense amplifier and at least one read driver circuit on the other side of the memory cell. Each bit line in each memory cell in a memory cell array is connected one-to-one to a second sense amplifier, and the other end of the second sense amplifier is connected to the read driver circuit.

[0015] Because each bit line in each memory cell in the memory cell array is connected to a second sense amplifier, the data in the bit line's corresponding position can be read by each second sense amplifier without interfering with each other. This allows for parallel reading of large amounts of data (as many bits as possible can be read simultaneously), making it particularly suitable for high-bandwidth readout applications. Furthermore, because the second sense amplifier and the driver circuit are located on the same side of the memory cell, the wiring between the second sense amplifier and the driver circuit can be significantly shortened, reducing the delay caused by the wiring length, thereby accelerating data reading.

[0016] It should be understood that the implementation of the embodiments of the present application does not need to achieve all of the above beneficial effects, but a specific technical solution can achieve a specific technical effect, and other implementation methods of the embodiments of the present application can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an illustrative and non-limiting manner, in which:

[0018] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0019] Figure 1 A schematic cross-sectional view of a commonly used memory structure is shown;

[0020] Figure 2 1 shows a schematic cross-sectional view of the structure of an embodiment of the memory of the present application in the Y direction;

[0021] Figure 3 A schematic diagram of a two-dimensional structure of another embodiment of the memory of the present application is shown;

[0022] Figure 4 FIG2 shows a schematic cross-sectional view of the structure of another embodiment of the memory of the present application in the Y direction;

[0023] Figure 5 A flow chart showing the memory usage method of the present application is shown. DETAILED DESCRIPTION

[0024] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0025] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0027] Figure 1 This figure shows a commonly used arrangement of a memory embodiment of the present application in the Y direction. YDEC is the word line address decoder in the Y direction of the memory embodiment of the present application; IOBLK is the input / output port; BiteLine is the bit line of the memory cell of the memory embodiment of the present application; Array is the memory cell array of the memory embodiment of the present application; Driver is the read driver circuit; SAMP is the sense amplifier used for read operations; and WRITEDRV is the write driver circuit.

[0028] exist Figure 1 In the memory embodiment of the present application shown, the storage capacity of each memory cell (the array corresponding to each word line address decoder YDEC) is 64 bits, corresponding to 64 bit lines (for example, Bt Line0, Bt Line1, ..., Bt Line 63) and an input and output port (IOBLK), the most common of which is 1 read and 1 write port. Each input and output port will be integrated with a sense amplifier and a write driver circuit (SAMP&WRITEDRV) to perform read / write operations on each memory cell in the memory cell array. Each input and output port will be connected to a read driver circuit (Driver0, Driver1, ..., Driver63) corresponding to a bit line one by one, and the data stored in the bit (Bit cell) controlled by the corresponding bit line can be read through the read driver circuit.

[0029] Since the input and output ports of each storage unit are connected to 64 drive circuits, Figure 1 Taking the memory embodiment of the present application as an example, 8 storage units require 8*64 connections.

[0030] Furthermore, because the write driver circuit and input / output ports are on one side of the memory cell array, while the read driver circuit is on the other side, a long wire is required to connect the input / output ports on one side of the memory cell array to the read driver circuit on the other side. Long wires increase the latency in reading data, slowing down the speed of reading data. This problem is particularly prominent in low-bandwidth write and high-bandwidth read applications, significantly impacting memory performance.

[0031] In order to solve the above technical problems, the present invention provides a Figure 2 The memory embodiment of the present application is shown. Figure 2 The memory embodiment of the present application provided in the embodiment of the present application includes: a memory cell array 201; an address decoder 202 located on one side of the memory cell array, and an input / output port 203 integrated with a first sensitive amplifier and a write driver circuit; at least one second sensitive amplifier 204 and at least one read driver circuit 205 located on the other side of the memory cell array; wherein each bit line (for example, Bitline 0 (000)) in each memory cell in the memory cell array (for example, the memory cell corresponding to YDEC0) is one-to-one connected to a second sensitive amplifier 204, and the other end of the second sensitive amplifier 204 is connected to the read driver circuit 205.

[0032] Because each bit line in each memory cell in the memory cell array is connected to a second sense amplifier 204, the data in the bit line can be read by each second sense amplifier 204 without interfering with each other. This allows for parallel reading of large amounts of data (as many bits as there are can be read simultaneously), making it particularly suitable for high-bandwidth readout applications. Furthermore, because the second sense amplifier 204 and the driver circuit 205 are located on the same side of the memory cell, the wiring between the second sense amplifier 204 and the driver circuit 205 can be significantly shortened, reducing delays caused by wiring length and, consequently, enabling faster data reading.

[0033] also, Figure 2 The memory embodiment of the present application shown retains the input / output port 203 integrated with the first sense amplifier and the write driver circuit located on one side of the memory cell, and can still continue to write data to each bit line of every memory cell in the memory cell array.

[0034] Need to explain Figure 2 The memory embodiment of the present application shown is only a basic embodiment of the memory of the present application, and implementers can further refine, expand and optimize it on this basis.

[0035] For example, in Figure 2 In the illustrated memory embodiment of the present application, the second sense amplifier 204 corresponding to each bit line is connected to a read driver circuit (e.g., driver0, driver1, ..., driver7) corresponding to each bit line. This requires a switch or a shift register within each driver circuit to manage the connection relationship with each second sense amplifier 204 and the storage of each memory cell. This implementation is not conducive to reducing circuit length and complexity.

[0036] To this end, in Figure 3In another embodiment of the memory of the present application, in addition to having Figure 1 In addition to the memory cell array 301, address decoder 302, input / output port 303 integrating a first sense amplifier and a write driver circuit, second sense amplifier 304, and read driver circuit 305 similar to the memory embodiment of the present application shown, the connection between the second sense amplifier 304 and the read driver circuit 305 is improved, the driver circuit is subdivided, so that the connection between the second sense amplifier 304 and the read driver circuit 305 becomes a one-to-one connection, and a one-to-one mapping is established between the driver circuit 305 and the address corresponding to the bit line, which can reduce the increase of additional winding space due to storage position mismatch.

[0037] In this way, when reading data from a bit, a one-to-one mapping is established between the driver circuit 305 and the address corresponding to the bit line. The driver circuit to be activated can be directly determined based on the address, eliminating the need for switches or shift registers within the driver circuit. This further shortens the wiring between the second sense amplifier 304 and the read driver circuit 305 and significantly simplifies the complexity of the driver circuit. This further improves the speed of reading each bit of data in parallel through each bit line while reducing energy consumption.

[0038] Figure 3 The memory cell array in the embodiment of the present application shown in FIG. 1 adopts a two-dimensional matrix structure, such as Figure 3 As shown, N word lines 308 (WLs) and a bit line address decoder 307 (XDEC) are arranged in the X direction.

[0039] In this way, the entire chip area can be further reduced and the connection length between the storage unit and the input and output ports can be shortened, thereby highlighting the beneficial effects of the static random access memory of the present application.

[0040] In another embodiment of the memory device of the present application, a low-power sense amplifier is used as the second sense amplifier. Since the second sense amplifier is only used for reading data and does not involve writing data, the low-power sense amplifier can meet the basic requirements of reading data. Furthermore, the low-power sense amplifier requires a very small area. Using a low-power sense amplifier as the second sense amplifier does not increase the area of ​​the memory device of the present application, thereby better meeting the requirements of miniaturization.

[0041] In another embodiment of the memory device of the present application, a latch-type sense amplifier is used as the second sense amplifier. Latch-type sense amplifiers not only have low power consumption but also provide high-speed access and offer superior overall performance compared to other types of SAs when subjected to severe potential offsets. Therefore, using a latch-type sense amplifier as the second sense amplifier can further improve the speed and accuracy of data reading.

[0042] Figure 4 Another embodiment of the memory of the present application is shown. Figure 4 In this embodiment, in addition to the memory cell array 401, the address decoder 402, the input / output port 403 integrated with the first sense amplifier and the write driver circuit, and the second sense amplifier 404, an isolation device 406 is provided between the bit line of each memory cell in the memory cell array 401 and the second sense amplifier 404. The isolation device has a switch that can be used to connect or disconnect the second sense amplifier and the bit line.

[0043] Isolation device 406 can be implemented using a P-type transistor. The switch in isolation device 406 is closed to maintain the connection between second sense amplifier 405 and the bit line. After the latch-type second sense amplifier 404 reads the data stored in the bit line through the bit line, the read data can be cached in the second sense amplifier. At this point, the switch in isolation device 406 can be opened to disconnect the second sense amplifier 405 from the bit line, freeing the bit line without having to wait for the read operation to complete. This allows the bit line to be used more frequently by the input / output port 403 on the other side of the memory cell, which integrates the first sense amplifier and write driver circuit, for write operations. This further shortens the switching time between read and write operations, significantly improving the parallel processing capability between read and write operations.

[0044] In order to latch the read data, in this embodiment, the second sense amplifier 405 is a latch amplifier. Otherwise, when the connection between the second sense amplifier 405 and the bit line is disconnected, the data may be lost.

[0045] According to a second aspect of the embodiment of the present application, a method for using a memory is also provided, such as Figure 5 As shown, the method is applied to any of the memories described above, and the method includes: operation S510, receiving at least one address input; operation S520, determining at least one read driver circuit to be turned on based on the at least one address input; operation S530, sending an on signal to the at least one read driver circuit to perform at least one read operation in parallel.

[0046] In operation S510, the address corresponds to a bit of a memory cell in a memory cell array, and generally includes a row address and a column address, wherein the row address corresponds to a word line of the memory cell (the address obtained by a bit line address decoder), and the column address corresponds to a bit line of the memory cell (the address obtained by a word line address decoder), and the intersection of the word line and the bit line is the selected bit to be read.

[0047] In operation S520 , a driver circuit connected to the bit line may be determined as at least one read driver circuit to be activated based on a connection relationship with the read driver circuit.

[0048] In operation S530 , an enable signal is sent to at least one read driver circuit, and data of a corresponding bit is read in conjunction with a word line.

[0049] Since each bit line in each memory cell in the memory cell array is connected to a second sense amplifier, the data in the bit line can be read by each second sense amplifier without interfering with each other. In this way, a large amount of data can be read in parallel.

[0050] Optionally, the method further includes: establishing a one-to-one mapping between the address and the read driver circuit, thereby significantly reducing the calculation time for determining the read driver circuit based on the address.

[0051] Optionally, the memory is provided with an isolation device between the bit line and the first sense amplifier. Accordingly, after sending an enable signal to at least one read drive circuit to perform at least one read operation in parallel, the method further includes: enabling the isolation device to disconnect the connection between the bit line and the first sense amplifier.

[0052] Disconnecting the bit line from the first sense amplifier does not affect the data that has been read, and allows the bit line to be released so that it can be used for a write operation on an input / output port integrated with the first sense amplifier and the write driver circuit on the other side of the memory cell.

[0053] Optionally, after turning on the isolation device, the method further includes: in response to a write operation request for the bit line, performing the following operations: turning on a write driver circuit corresponding to the bit line; and sending a turn-on signal to the write driver circuit to perform a write operation.

[0054] In the embodiment of the present application, there is no need to wait for the read operation to be completed. As long as the isolation device is turned on and the connection between the bit line and the first sensitive amplifier is disconnected, the same bit can be written, thereby further shortening the switching time between the read and write operations and greatly improving the parallel processing capability between read and write.

[0055] It should be noted that the above embodiments of the present application are all illustrative descriptions and are not limitations on the implementation methods and application scenarios of the embodiments of the present application. Implementers can adopt any applicable implementation methods according to specific implementation needs and implementation conditions, or combine the above-mentioned implementation methods to apply to any applicable application scenarios.

[0056] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0057] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another device, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0058] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The memory includes: A memory cell array including a plurality of memory cells, each memory cell having a storage capacity of 8 bits or 64 bits, corresponding to 8 or 64 bit lines, respectively; An address decoder located on one side of the memory cell array, and an input / output port integrated with a first sense amplifier and a write driver circuit, wherein the input / output port integrated with the first sense amplifier and the write driver circuit is used for writing data; at least one second sense amplifier and at least one read driver circuit located on the other side of the memory cell array, wherein the second sense amplifier is used to read data; Each bit line in each memory cell in the memory cell array is connected one-to-one to a second sensitive amplifier, and the other end of the second sensitive amplifier is connected to the read drive circuit; wherein the connection between the second sensitive amplifier and the read drive circuit is a one-to-one connection. 2 . The memory of claim 1 , wherein the second sense amplifier comprises a low power sense amplifier. 3 . The memory according to claim 2 , wherein the second sense amplifier comprises a latch-type sense amplifier.

4. The memory according to claim 3, further comprising: An isolation device includes a switch for connecting or disconnecting the second sense amplifier and the bit line. The memory according to claim 1 , wherein the memory cell array comprises a two-dimensional matrix structure.

6. A method for using a memory, characterized in that: The method is applied to the memory according to any one of claims 1 to 5, and the method includes: receiving at least one address input; determining at least one read driver circuit to be enabled according to the at least one address input; Sending an enable signal to the at least one read driver circuit to perform at least one read operation in parallel; A one-to-one mapping is established between the addresses and the read driver circuits.

7. The method according to claim 6, characterized in that The memory is provided with an isolation device between the bit line and the first sense amplifier. Accordingly, after sending a start signal to the at least one read driver circuit to perform at least one read operation in parallel, the method further includes: The isolation device is turned on to disconnect the bit line from the first sense amplifier.

8. The method according to claim 7, further comprising, after turning on the isolation device, performing the following operations in response to a write operation request being made to the bit line: Turning on the write drive circuit corresponding to the bit line; An on signal is sent to the write driving circuit to perform a write operation.

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