A method for manufacturing a thin film transistor, a thin film transistor, and a display device

Abstract

The present invention provides a method for manufacturing a thin film transistor, a thin film transistor, and a display device, which solve the problem of the increase in the effective tail during the channel fabrication process of thin film transistor devices. The method for manufacturing the thin film transistor includes: providing a substrate; forming a gate electrode, a gate insulating layer, an active layer, and a metal layer stacked in sequence on the substrate; patterning the active layer and the metal layer to respectively form an active island and source-drain electrodes located above the active island; wherein, the active island includes an epitaxial portion located on its outer periphery, and the orthographic projection of the epitaxial portion on the substrate does not cover the orthographic projections of the gate electrode and the source-drain electrodes on the substrate; patterning the active island to remove the epitaxial portion, thereby forming a thin film transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a method for manufacturing a thin film transistor, a thin film transistor, and a display device. Background Art

[0002] Currently, liquid crystal display (LCD) is widely used in various sizes of liquid crystal display fields due to its advantages such as low power consumption, thin volume, wide viewing angle, and high definition. Generally, after wet etching the source / drain of a thin film transistor (TFT) device, the ohmic contact layer and part of the dielectric layer are continuously etched to complete the channel fabrication of the thin film transistor device. Due to the isotropic nature of the wet etching process, during the etching process, the ohmic contact layer exposed to the etching solution will be completely removed, resulting in an increase in the effective tail, deterioration of the characteristics of the TFT device, such as an increase in the light leakage current, a decrease in the product reliability margin, and an increase in the pixel charging rate difference between the presence and absence of light, causing waterfall defects. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method for manufacturing a thin film transistor, a thin film transistor, and a display device, which solve the problem of an increase in the effective tail during the channel fabrication of a thin film transistor device.

[0004] A method for manufacturing a thin film transistor provided by an embodiment of the present invention includes: providing a substrate;

[0005] Forming a gate electrode, a gate insulating layer, an active layer, and a metal layer stacked in sequence on the substrate;

[0006] Performing patterning on the active layer and the metal layer to respectively form an active island and source / drain electrodes located above the active island; wherein, the active island includes an epitaxial portion on its outer periphery, and the orthographic projection of the epitaxial portion on the substrate does not cover the orthographic projections of the gate electrode and the source / drain electrodes on the substrate;

[0007] Performing patterning on the active island to remove the epitaxial portion, thereby forming a thin film transistor.

[0008] In one embodiment, the step of performing patterning on the active island to remove the epitaxial portion, thereby forming a thin film transistor includes:

[0009] Forming a first protective layer covering the active island, the source / drain electrodes, and the gate insulating layer;

[0010] Pattern the first protective layer to form a first etching window penetrating the first protective layer; wherein, the first etching window exposes at least the epitaxial portion.

[0011] Using the patterned first protective layer as a mask, etch the active island through the first etching window to remove the epitaxial portion, thereby forming a thin film transistor.

[0012] Remove the patterned first protective layer.

[0013] In one embodiment, the etching window also exposes the sidewall of the source-drain electrode close to the epitaxial portion.

[0014] In one embodiment, the steps of patterning the active layer and the metal layer to respectively form an active island and a source-drain electrode located above the active island include:

[0015] Pattern the active layer and the metal layer to respectively form an active island, a source-drain electrode located above the active island, and a data signal line.

[0016] Wherein, the orthographic projection of the epitaxial portion on the substrate does not cover the orthographic projection of the data signal line on the substrate.

[0017] In one embodiment, the etching window also exposes the sidewall of the data signal line close to the epitaxial portion.

[0018] In one embodiment, the steps of using the patterned first protective layer as a mask and etching the active island through the first etching window to remove the epitaxial portion to form a thin film transistor include:

[0019] Using the patterned first protective layer as a mask, etch the active island through the first etching window by wet etching or dry etching to remove the epitaxial portion, thereby forming a thin film transistor.

[0020] In one embodiment, the steps of patterning the active layer and the metal layer to respectively form an active island and a source-drain electrode located above the active island include:

[0021] Form a second protective layer covering the metal layer.

[0022] Pattern the second protective layer to form a second etching window penetrating the second protective layer.

[0023] Using the patterned second protective layer as a mask, through the second etching window, etch the active layer and the metal layer to respectively form active islands and source-drain electrodes located above the active islands;

[0024] Remove the patterned second protective layer.

[0025] In one embodiment, the step of using the patterned second protective layer as a mask, through the second etching window, etching the active layer and the metal layer to respectively form active islands and source-drain electrodes located above the active islands includes:

[0026] Using the patterned second protective layer as a mask, through the second etching window, etch the active layer and the metal layer by wet etching to respectively form active islands and source-drain electrodes located above the active islands.

[0027] In one embodiment, an ohmic contact layer is provided on a side of the metal layer close to the active layer.

[0028] A thin film transistor is prepared by using the preparation method of the thin film transistor described above.

[0029] A display device includes the thin film transistor described above.

[0030] The preparation method of the thin film transistor provided by the embodiments of the present invention has the following advantages compared with the prior art:

[0031] 1. The effective tail is reduced, the difference in pixel charging rate with and without light illumination is weakened, the Waterfall defect is solved, and the product quality is improved;

[0032] 2. The effective tail is reduced, the parasitic capacitances between the signal line and the pixel electrode, between the signal line and the common electrode, and between the lines in the Fanout area are solved, the line pitch in the Fanout area can be minimized, and the narrow border requirement can be met;

[0033] 3. The effective tail is reduced, the light leakage current of the TFT device can be reduced, and the reliability defects related to product characteristics, such as vertical / horizontal crosstalk, unconfirmed Mura defect, etc., can be improved;

[0034] 4. The active layer of the TFT channel semiconductor layer is wet-etched, which can improve the etching uniformity. Description of the Drawings

[0035] Figure 1 The figure shows a flowchart of a preparation method of a thin film transistor provided by an embodiment of the present invention.

[0036] Figure 2The figure shows a flowchart of a preparation method for forming an active island and source-drain electrodes above the active island provided by an embodiment of the present invention.

[0037] Figure 3 The figure shows a schematic diagram of a preparation method for forming an active island and source-drain electrodes above the active island provided by an embodiment of the present invention.

[0038] Figure 4 The figure shows a flowchart of a preparation method for forming a thin-film transistor provided by an embodiment of the present invention.

[0039] Figure 5 The figure shows a schematic diagram of a preparation method for forming a thin-film transistor provided by an embodiment of the present invention.

[0040] Figure 6 The figure shows a schematic diagram of a preparation method for forming a thin-film transistor provided by another embodiment of the present invention. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the protection scope of the present invention.

[0042] This embodiment provides a preparation method for a thin-film transistor, as Figure 1 shown. The preparation method for the thin-film transistor includes:

[0043] Step 01: Provide a substrate 1.

[0044] Step 02: Form a gate electrode 2, a gate insulating layer 3, an active layer 4, and a metal layer 6 stacked in sequence on the substrate 1.

[0045] Step 03: Perform patterning on the active layer 4 and the metal layer 6 to respectively form an active island and source-drain electrodes above the active island; wherein, the active island includes an epitaxial portion at its outer periphery, and the orthographic projection of the epitaxial portion on the substrate 1 does not cover the orthographic projections of the gate electrode 2 and the source-drain electrodes on the substrate 1. Optionally, as Figure 2 and Figure 3 shown, the implementation manners include:

[0046] Step 031: Form a second protective layer 8 covering the metal layer 6;

[0047] Step 032: Perform patterning on the second protective layer 8 to form a second etching window penetrating the second protective layer 8;

[0048] Step 033: Using the patterned second protective layer 8 as a mask, etch the active layer 4 and the metal layer 6 through the second etching window to respectively form active islands and source-drain electrodes located above the active islands.

[0049] Optionally, the active layer 4 and the metal layer 6 are etched by a wet etching method to respectively form active islands and source-drain electrodes located above the active islands. Fluoride ions with a concentration of 0.1% - 0.3% are added to the etching solution. In existing TFT devices, usually the metal is first removed by wet etching, and then the ohmic contact layer and part of the dielectric layer are removed by dry etching to complete the channel fabrication of the TFT device, resulting in low production efficiency and increased operating costs. To reduce the operating costs, improve the production efficiency, and enhance the competitiveness of the production line, the present invention realizes the wet etching process of the metal layer 6 and the non-metal layer by adding fluoride ions to the etching solution, that is, after wet etching the source / drain electrodes, continue to etch the ohmic contact layer and part of the dielectric layer, thereby completing the channel fabrication of the TFT device.

[0050] Step 034: Remove the patterned second protective layer 8.

[0051] In one embodiment, the steps of patterning the active layer 4 and the metal layer 6 to respectively form active islands and source-drain electrodes located above the active islands include: patterning the active layer 4 and the metal layer 6 to respectively form active islands, source-drain electrodes located above the active islands, and data signal lines; wherein, the orthographic projection of the epitaxial portion on the substrate 1 does not cover the orthographic projection of the data signal lines on the substrate 1.

[0052] Step 04: Pattern the active islands to remove the epitaxial portion, thereby forming a thin film transistor. Optionally, as Figure 4 、 Figure 5 and Figure 6 shown, the implementation manners include:

[0053] Step 041: Form a first protective layer 7 covering the active islands, the source-drain electrodes, and the gate insulating layer 3.

[0054] Step 042: Pattern the first protective layer 7 to form a first etching window penetrating through the first protective layer 7; wherein, the first etching window exposes at least the epitaxial portion, refer to Figure 5 shown.

[0055] Optionally, the first etching window also exposes the sidewalls of the source-drain electrodes close to the epitaxial portion, refer to Figure 6 shown.

[0056] Optionally, the first etching window also exposes the sidewall of the data signal line close to the epitaxial portion.

[0057] Step 043: Using the patterned first protective layer 7 as a mask, through the first etching window, etch the active island to remove the epitaxial portion, thereby forming a thin film transistor. Optionally, the active island is etched by wet etching or dry etching to remove the epitaxial portion.

[0058] Step 044: Remove the patterned first protective layer 7.

[0059] By adopting a full-exposure technology, the present invention removes the active layer 4 at the edges of the data signal line and the source / drain electrode through one etching, thereby reducing the effective tail and improving the etching uniformity.

[0060] When a 4Mask display product is paired with PWM (Pulse Width Modulation) modulated backlight, bright and dark stripes appear on the whole machine, resembling "water ripples", namely Waterfall defect. Its occurrence mechanism is that there is an effective tail under the data signal line of the 4Mask product. When illuminated, electrons in the semiconductor layer are excited, having approximate conductor characteristics, and the resulting effect is equivalent to the widening of the source / drain electrode traces, and the Data RC Delay changes. At the same time, when illuminated, the parasitic capacitance between the data signal line and the pixel electrode increases, and the voltage of the pixel electrode decreases, resulting in insufficient pixel charging. For FFS or ADS displays, it shows a constant black mode, so macroscopically it appears as a dark band. Since the present invention reduces the effective tail, the Waterfall defect is thus solved.

[0061] Reducing the effective tail can solve the parasitic capacitance between the signal line and the pixel electrode, between the signal line and the common electrode, and between the lines in the Fanout area, and minimize the line pitch in the Fanout area, thereby meeting the narrow bezel requirement.

[0062] Reducing the effective tail can reduce the light leakage current of the TFT device and improve the reliability defects related to product characteristics, such as vertical / horizontal crosstalk, unconfirmed Mura defects, etc.

[0063] In an embodiment of the present invention, an ohmic contact layer is provided on the side of the metal layer 6 close to the active layer 4.

[0064] This embodiment provides a thin film transistor, which is prepared by using the preparation method of the above thin film transistor.

[0065] This embodiment provides a display device, which includes the thin-film transistor described in the above embodiment. Among them, the display device can be a computer, a mobile phone, a tablet computer, etc.

[0066] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0067] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings, direct couplings, or communication connections shown or discussed with each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] The basic principles of the present application have been described above in combination with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. In addition, the specific details disclosed above are only for the purposes of illustration and easy understanding, and are not limitations. The above details do not limit the present application to necessarily adopt the above specific details for implementation.

[0069] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner.

[0070] It should also be noted that in the devices, equipment and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations shall be regarded as equivalent solutions of the present application.

[0071] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0072] In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back, top, bottom...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products or devices.

[0073] In addition, the mention of "embodiment" in this document means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0074] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, and all of them should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a thin film transistor, characterized in that, comprising: providing a substrate; forming a gate electrode, a gate insulating layer, an active layer, and a metal layer stacked in sequence on the substrate; patterning the active layer and the metal layer to respectively form an active island and source-drain electrodes located above the active island; wherein, the active island includes an epitaxial portion located on its outer periphery, and the orthographic projection of the epitaxial portion on the substrate does not cover the orthographic projections of the gate electrode and the source-drain electrodes on the substrate; patterning the active island to remove the epitaxial portion, thereby forming a thin film transistor; The step of patterning the active island to remove the epitaxial portion, thereby forming a thin film transistor includes: forming a first protective layer covering the active island, the source-drain electrodes, and the gate insulating layer; patterning the first protective layer to form a first etching window penetrating the first protective layer; wherein, the first etching window exposes at least the epitaxial portion; using the patterned first protective layer as a mask, through the first etching window, etching the active island to remove the epitaxial portion, thereby forming a thin film transistor; removing the patterned first protective layer.

2. The method for manufacturing a thin film transistor according to claim 1, characterized in that, the first etching window also exposes the side wall of the source-drain electrode close to the epitaxial portion.

3. The method for manufacturing a thin film transistor according to claim 1, characterized in that, the step of patterning the active layer and the metal layer to respectively form an active island and source-drain electrodes located above the active island includes: patterning the active layer and the metal layer to respectively form an active island, source-drain electrodes, and data signal lines located above the active island; wherein, the orthographic projection of the epitaxial portion on the substrate does not cover the orthographic projection of the data signal line on the substrate.

4. The method for manufacturing a thin film transistor according to claim 3, characterized in that, the first etching window also exposes the side wall of the data signal line close to the epitaxial portion.

5. The method for manufacturing a thin film transistor according to claim 1, characterized in that, the step of using the patterned first protective layer as a mask, through the first etching window, etching the active island to remove the epitaxial portion, thereby forming a thin film transistor includes: using the patterned first protective layer as a mask, through the first etching window, etching the active island by wet etching or dry etching methods to remove the epitaxial portion, thereby forming a thin film transistor.

6. The method for manufacturing a thin film transistor according to claim 1, characterized in that, the step of patterning the active layer and the metal layer to respectively form an active island and source-drain electrodes located above the active island includes: forming a second protective layer covering the metal layer; patterning the second protective layer to form a second etching window penetrating the second protective layer; Using the patterned second protective layer as a mask, through the second etching window, etch the active layer and the metal layer to respectively form active islands and source-drain electrodes located above the active islands; Remove the patterned second protective layer.

7. The method for manufacturing a thin film transistor according to claim 6, wherein, The step of using the patterned second protective layer as a mask, through the second etching window, to etch the active layer and the metal layer to respectively form active islands and source-drain electrodes located above the active islands includes: Using the patterned second protective layer as a mask, through the second etching window, etch the active layer and the metal layer by wet etching to respectively form active islands and source-drain electrodes located above the active islands.

8. The method for manufacturing a thin film transistor according to claim 1, wherein, An ohmic contact layer is provided on a side of the metal layer close to the active layer.

9. A thin film transistor, wherein, It is manufactured by using the method for manufacturing a thin film transistor according to any one of claims 1 to 8 above.

10. A display device, wherein, It includes the thin film transistor according to claim 9 above.

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