Three-dimensional memory and methods of manufacturing the same

Abstract

The present disclosure relates to a three-dimensional memory, a manufacturing method thereof, and a storage device. The method comprises: forming a first stack block; forming a first step structure on the first stack block; forming a second stack block on one side of the first stack block along a stacking direction of the first stack block; forming a second step structure on the second stack block, wherein at least one of the first step structure and the second step structure comprises at least one pair of homologous steps, and each pair of homologous steps is arranged in a vertical plane of the stacking direction; and forming a plurality of conductive channels on the one side of the first step structure, wherein the conductive channels are electrically connected to corresponding steps in the first step structure or the second step structure, and each pair of homologous steps is electrically connected to each other through the conductive channels.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and more particularly, to a three-dimensional memory and a manufacturing method thereof. BACKGROUND

[0002] It is desired to increase the storage capacity of memory devices. However, when increasing the storage capacity or storage density of memory devices, new problems may be encountered, such as process complexity, high manufacturing difficulty, cost increase, etc.

[0003] With the increase of the number of stacked layers of three-dimensional memory, in order to control the size of the three-dimensional memory while improving the storage density, the thickness of each layer can be thinned. However, when the thickness of the gate layer for conduction is thinned, the resistance of the gate layer will become larger, which will in turn generate a larger resistance-capacitance delay (RC delay). In addition, when the thickness of the gate layer is controlled to a certain thickness, the height of the entire stacked structure becomes very high with the increase of the number of layers. It will be more difficult to perform deep etching or filling and other processing technologies on such a high stacked structure. SUMMARY

[0004] Embodiments of the present application provide a method for manufacturing a three-dimensional memory, the method comprising: forming a first stacked block; forming a first step structure on the first stacked block; forming a second stacked block on one side of the first stacked block along a stacking direction of the first stacked block; forming a second step structure on the second stacked block, wherein at least one of the first step structure and the second step structure comprises at least one pair of homologous steps, and a pair of the homologous steps are arranged in a vertical plane of the stacking direction; and forming a plurality of conductive channels on the one side of the first step structure, wherein the conductive channels are electrically connected to corresponding steps of the first step structure or the second step structure, and each pair of the homologous steps are electrically connected to each other through the conductive channels.

[0005] In some embodiments, the method further comprises: forming an interconnection layer electrically connected to the conductive channels on a side of the plurality of conductive channels away from the first step structure, wherein at least one of the first step structure and the second step structure comprises at least one pair of steps electrically connected through a metal interconnection in the interconnection layer.

[0006] In some embodiments, the second step structure is located on both sides of the first step structure along a direction opposite to a pair of the homologous steps.

[0007] In some embodiments, the method further comprises: forming a first insulating filler on the side of the first step structure before the step of forming the second stack structure; forming a second insulating filler on the side of the second step structure facing away from the first step structure; and wherein the conductive channel connected to the first step structure passes through the first insulating filler and the second insulating filler, and the conductive channel connected to the second step structure passes through the second insulating filler.

[0008] In some embodiments, the method further comprises: forming a third stack structure and a fifth stack structure on opposite sides of the first stack structure, respectively; forming a seventh stack structure between the third stack structure and the fifth stack structure; forming a fourth stack structure and a sixth stack structure on opposite sides of the second stack structure, respectively; and forming an eighth stack structure between the fourth stack structure and the sixth stack structure.

[0009] In some embodiments, the first step structure comprises at least one pair of the same steps, one of the pair of the same steps is connected to the third stack structure, and the other is connected to the fifth stack structure, and a first twin step structure is formed in the seventh stack structure which is at least partially the same as the first step structure; or the second step structure comprises at least one pair of the same steps, one of the pair of the same steps is connected to the fourth stack structure, and the other is connected to the sixth stack structure, and a second twin step structure is formed in the eighth stack structure which is at least partially the same as the second step structure.

[0010] In some embodiments, at least one of the first step structure and the second step structure comprises a plurality of steps at different depths.

[0011] In some embodiments, the method further comprises: the step of forming the plurality of steps at different depths comprises: determining the depth to be etched for each of the steps, wherein the depth to be etched is an integer multiple of the height of one of the steps; and synchronously etching at least two of the steps, wherein the depth of each of the synchronous etchings is an integer multiple of the height of one of the steps.

[0012] In another aspect, the present disclosure provides a three-dimensional memory, comprising: a first stack block comprising a first stepped structure; a second stack block comprising a second stepped structure disposed at one side of the first stepped structure along a stacking direction of the first stepped structure, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of homologous steps, and each pair of the homologous steps is spaced apart in a plane perpendicular to the stacking direction; and a plurality of conductive channels located at the one side of the first stepped structure, wherein the conductive channels are electrically connected to corresponding steps of the first stepped structure or the second stepped structure, and each pair of the homologous steps are electrically connected to each other through the conductive channels.

[0013] In some embodiments, the three-dimensional memory further comprises: an interconnection layer disposed at a side of the plurality of conductive channels facing away from the first stepped structure and electrically connected to the conductive channels, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of first steps electrically connected through a metal interconnection in the interconnection layer.

[0014] In some embodiments, the second stepped structure is located at both sides of the first stepped structure in the plane perpendicular to the stacking direction.

[0015] In some embodiments, the three-dimensional memory further comprises a first insulating filler structure located at the first side of the first stepped structure, and a second insulating filler structure located at a side of the second stepped structure facing away from the first stepped structure; wherein the conductive channels connected to the first stepped structure pass through the first insulating filler structure and the second insulating filler structure, and the conductive channels connected to the second stepped structure pass through the second insulating filler structure.

[0016] In some embodiments, the three-dimensional memory further comprises: a third stack block, a fifth stack block and a seventh stack block disposed in parallel with the first stack block, wherein the third stack block and the fifth stack block are oppositely disposed at both sides of the first stack block, and the seventh stack block is located between and connected to the third stack block and the fifth stack block; and a fourth stack block, a sixth stack block and an eighth stack block disposed in parallel with the second stack block, wherein the fourth stack block and the sixth stack block are oppositely disposed at both sides of the second stack block, and the eighth stack block is located between and connected to the fourth stack block and the sixth stack block.

[0017] In some embodiments, the first step structure comprises at least one pair of the same steps, one of the pair of the same steps is connected with the third stack block, and the other is connected with the fifth stack block, the seventh stack block comprises a first twin step structure which is at least partially same as the first step structure; or the second step structure comprises at least one pair of the same steps, one of the pair of the same steps is connected with the fourth stack block, and the other is connected with the sixth stack block, the eighth stack block comprises a second twin step structure which is at least partially same as the second step structure.

[0018] In some embodiments, at least one of the first step structure and the second step structure comprises a plurality of steps at different depths.

[0019] The application also provides, in another aspect, a storage device comprising: the three-dimensional memory as described above; and a controller electrically connected with the three-dimensional memory and configured to control the three-dimensional memory.

[0020] The manufacturing method of the three-dimensional memory provided by the embodiments of the application reduces the overall process difficulty by dividing the etching into two times and stacking. Specifically, the difficulty of processes such as photoetching, etching and filling in the step area is reduced.

[0021] The manufacturing method provided by the application can flexibly adjust the setting of the step structure, reduce the overall manufacturing cost and maintain good use performance of the manufactured three-dimensional memory. BRIEF DESCRIPTION OF DRAWINGS

[0022] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings:

[0023] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the application;

[0024] Figures 2 to 17 is a process diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the application;

[0025] Figure 18 is a three-dimensional memory according to an exemplary embodiment of the application;

[0026] Figure 19 is a three-dimensional memory according to an exemplary embodiment of the application;

[0027] Figure 20 is a process diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the application;

[0028] Figure 21is a three-dimensional memory according to an exemplary embodiment of the present application;

[0029] Figure 22 is a three-dimensional memory according to an exemplary embodiment of the present application;

[0030] Figure 23 is a structure diagram of a storage device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0031] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be noted that these detailed descriptions are merely exemplary of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, like reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It is noted that, in this specification, the expressions first, second, third, etc. are merely used to distinguish one feature from another feature, and do not indicate any limitation on the features. Thus, the first step structure discussed below can also be referred to as the second step structure, without departing from the teachings of the present application. The converse is also true.

[0033] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are merely exemplary and are not strictly drawn to scale. For example, the thickness of the first stack block and the thickness of the second stack block are not in proportion as in actual production. As used in this document, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measuring or calculating values that would be recognized by those of ordinary skill in the art.

[0034] It is also to be understood that the terms "comprise", "comprising", "have", "having", "contain" and / or "containing", when used in this specification, indicate the presence of stated features, elements and / or components but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof. Furthermore, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the term "exemplary" is intended to mean an example or an illustration.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0036] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. In addition, the specific steps included in the methods described in the present application are not necessarily limited to the order described unless expressly limited or contradictory in context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0037] Figure 1 is a flowchart of a method of manufacturing a three-dimensional memory according to an embodiment of the present application. Referring to Figure 1 , the method 1000 provided by the embodiment of the present application includes the following steps.

[0038] Step S101, a first stack block is formed. Illustratively, the method includes forming a first stack structure extending in a vertical plane of a stacking direction of the first stack block. The first stack block can be regarded as a part of the first stack structure. The first stack structure is divided in the vertical plane of the stacking direction into a first storage region and a second storage region, and a step region between the first storage region and the second storage region, the first storage region and the second storage region can be arranged in a first direction parallel to the vertical plane. The step region can include a first step region and a second step region, the projections of the first step region and the second step region along the stacking direction include non-overlapping parts.

[0039] Step S102, a first step structure is formed in the first stack block. Specifically, the first step structure corresponds to the first step region.

[0040] Step S103, a second stack block is formed on one side of the first stack block along the stacking direction of the first stack block. In general, the second stack block can be formed on the first stack block in the processing direction.

[0041] Step S104, a second step structure is formed in the second stack block. Specifically, the second step structure corresponds to the second step region. At least one of the first step structure and the second step structure includes at least one pair of co-located steps, and the pair of co-located steps are arranged in the vertical plane of the stacking direction.

[0042] Step S105, a plurality of conductive channels are formed on one side of the first stepped structure. The conductive channels are electrically connected with corresponding steps in the first stepped structure or the second stepped structure. Specifically, at least one pair of homologous steps are electrically connected by the conductive channels. Exemplarily, in the first stepped structure or the second stepped structure, one of the aforementioned pair of steps is connected with only the first storage region, and the other is connected with only the second storage region.

[0043] Exemplarily, after step S102 and before step S103, the method further comprises a step of forming a first insulating filler on the first stepped structure to fill the first stack block. After step S104, the method further comprises a step of forming a second insulating filler on the second stepped structure.

[0044] The method provided by the embodiments of the present application forms the first stack block and the second stack block in steps, so that the height of each of the first stack block and the second stack block is not too high. When the first stack block / second stack block is processed to form the first stepped structure / second stepped structure, the processing technology is not too difficult. The use performance of the manufactured three-dimensional memory is better.

[0045] Exemplarily, the method 1000 further comprises forming a plurality of lower channel hole structures penetrating the first stack block and a plurality of upper channel holes penetrating the second stack block in the first storage region and the second storage region. The upper channel holes and the lower channel hole structures are in one-to-one correspondence, thereby forming channel structures. The channel structures can comprise, from outside to inside, a blocking layer, a charge storage layer, a tunneling layer, a channel layer and an insulating core filler layer.

[0046] In an exemplary embodiment, the first stack block and the second stack block respectively comprise alternatingly stacked sacrificial layers and insulating layers. The method 1000 further comprises a step of replacing the sacrificial layers with gate layers.

[0047] Exemplarily, the method 1000 further comprises forming a plurality of conductive channels in the first stepped region and the second stepped region. The conductive channels are electrically connected with corresponding steps in the first stepped structure or the second stepped structure.

[0048] Exemplarily, the method 1000 further comprises forming an interconnection layer on the second stack block, which is electrically connected with the conductive channels.

[0049] Exemplarily, the method 1000 further comprises disposing a peripheral circuit on the interconnection layer. Exemplarily, the peripheral circuit wafer can be electrically connected on the interconnection layer by bonding or the like. Specifically, the peripheral circuit wafer can be, for example, a CMOS wafer, which comprises, for example, field effect transistors, capacitors, inductors and / or PN junction diodes, etc., for realizing different functions of the three-dimensional memory, such as buffering, amplification, decoding, etc.

[0050] Reference Figures 2 to 14A method of manufacturing a three-dimensional memory is provided in the exemplary embodiments of the present application.

[0051] Specifically, a first stack structure 2 is formed.

[0052] Referring to Figure 2 and Figure 3 Exemplarily, the first stack structure 2 can be formed on the substrate 1. In the processing space, the first stack structure 2 can be divided into a first storage region GB1, a second storage region GB2, a first step region SSA, a second step region SSB1-SSB2 and a bridge region GW in the XY plane according to the design size, and the above-mentioned regions are three-dimensional regions extending in the Z direction.

[0053] The first storage region GB1 and the second storage region GB2 are oppositely arranged in the X direction, and the bridge region GW is located between and connected with the first storage region GB1 and the second storage region GB2. Figure 3 The first step region SSA and the second step region SSB1-SSB2 are collectively regarded as a step region located between the first storage region GB1 and the second storage region GB2. At least one of the first step region SSA and the second step region SSB1-SSB2 is connected with the bridge region GW.

[0054] In the present embodiment, the second step region can include a first sub-region SSB1 and a second sub-region SSB2 arranged on both sides of the first step region SSA in the first direction. In other embodiments, the first step region and the second step region can be arranged side by side.

[0055] Referring to Figure 2 The substrate 1 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), a group III-V compound semiconductor material, a group II-VI compound semiconductor material or other semiconductor materials known in the art.

[0056] The first stack structure 2 is formed on the substrate 1 and includes first sacrificial layers 201 and first insulating layers 202 alternately stacked. The first stack structure 2 can be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, etc. The material of the first sacrificial layers 201 can include silicon nitride, silicon oxynitride, polysilicon, polysilicon germanium, TEOS, polysilicon germanium, silicon oxide and any combination of the foregoing, and the material of the first insulating layers 202 can include silicon oxide, silicon oxynitride, silicon nitride, TEOS or silicon oxide doped with any one of fluorine, carbon, nitrogen and hydrogen, or a high dielectric constant dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide or lanthanum oxide. The specific selection of the materials can make the first sacrificial layers 201 and the first insulating layers 202 have etching selectivity in some etching modes.

[0057] According to the area division in the XY plane, the first stack structure 2 can include a first stack block located at the staircase region SS, a third stack block located at the first storage region GB1, a fifth stack block located at the second storage region GB2, and a seventh stack block located at the bridge region GW. Specifically, the first stack block located at the staircase region SS includes a first sub-stack block located at the first staircase region SSA, a first sub-stack block located at the first sub-region SSB1, and a first sub-stack block located at the second sub-region SSB2, wherein the first sub-region SSB1 and the second sub-region SSB2 belong to the second staircase region. Understandably, the step of forming the first stack structure 2 includes the step of forming each stack block, and each sub-stack block can be considered to be formed synchronously.

[0058] Referring to Figure 4 and Figure 5 , a first step structure 20 is formed at the first storage block of the first stack structure 2 located at the staircase region SS. Specifically, for the first sub-stack block located at the first staircase region SSA, the first step structure 20 can be formed by “trim-etching”, and each step of the first step structure 20 is located at a different height in the illustrated Z direction, i.e., the stacking direction of the first stack structure 2 (see Figure 16 ). Each step can correspond to a layer pair including a first sacrificial layer 201 and a second insulating layer 202. When performing the “trim-etching” process, a mask layer including a slit can be first formed on the first stack structure 2, and then the trimming of the mask layer and the etching of the first stack structure 2 are alternately performed. Each time the trim-etching cycle is performed, one layer pair is etched downward and the etching width is increased. After multiple cycles, a staircase morphology can be obtained. Exemplarily, the obtained staircase can also be etched to different height positions to obtain the first step structure 20 Figure 16 ). The aforementioned etching process can include any one or a combination of dry etching process and wet etching process. The stack blocks located at regions outside the first staircase region SSA are temporarily not subjected to the “trim-etching” process, and the stack blocks of other regions do not form step structures.

[0059] Then a plurality of lower channel hole structures 30 are formed at the third stack block of the first storage region GB1 and the fifth stack block of the second storage region GB2. Referring to Figure 6 , the lower channel hole structure 30 penetrates the first stack structure 2 along the stacking direction and can extend into the substrate 1.

[0060] Specifically, the step of forming the lower channel hole structure 30 includes forming a lower channel hole segment, and filling a material to be sacrificed in the lower channel hole segment to form the lower channel hole structure 30. The material to be sacrificed can be deposited on the surface of the structure by a deposition process, and fills the lower channel hole segment and can have a portion on the first stack structure 2, so that the top of the lower channel hole structure 30 can also be polished to be flush with the first stack structure 2 by a chemical mechanical polishing process. The material of the lower channel hole structure 30 can include polysilicon, silicon nitride, silicon oxide, silicon oxynitride, etc. The material of the lower channel hole structure 30 needs to be selected to have etching selectivity of the lower channel hole structure 30 with respect to the first sacrificial layer 201 and the first insulating layer 202 in some etching modes.

[0061] Further, the first insulating fill 22 is formed on the first step structure 20. The material of the first insulating fill 22 can include silicon oxide. Specifically, the material of the first insulating fill 22 can include tetraethyl orthosilicate (TEOS). Exemplarily, the first insulating fill 22 can be formed by a chemical vapor deposition process with TEOS as a precursor, for example, by introducing TEOS and H2O reaction gases, and then starting radio frequency to make TEOS and H2O active to form the first insulating fill 22 on the first step structure 20. Exemplarily, the first insulating fill 22 can be formed by a spin coating process. Referring to Figure 7 The first insulating fill 22 fills the top surface of the first stack structure 2. Specifically, the first sub memory block located in the first step area SSA can be filled. Exemplarily, mechanical chemical polishing (CMP) can be performed after the first insulating fill 22 is filled on the first step structure 20 to obtain a flat top surface.

[0062] Then, the second stack structure 4 can be formed on the first stack structure 2. The process of forming the second stack structure 4 can be the same as the process of forming the first stack structure 2. The first stack structure 2 and the second stack structure 4 can be used to constitute a composite stack structure 5.

[0063] Referring to Figure 8 The second stack structure 4 is arranged on the first stack structure 2, and can cover the first insulating fill 22 and the lower channel hole structure 30. The second stack structure 4 can include second sacrificial layers 401 and second insulating layers 402 stacked alternately. The thickness of each of the first stack structure 2 and the second stack structure 4 can be allocated according to the etching difficulty of the step structure.

[0064] According to the region division, the second stack structure 4 can include a second stack block located at the staircase region SS, a fourth stack block located at the first storage region GB1, a sixth stack block located at the second storage region GB2, and an eighth stack block located at the bridge region GW. Specifically, the second stack block located at the staircase region SS includes a second sub-stack block located at the first staircase region SSA, a second sub-stack block located at the first sub-region SSB1, and a second sub-stack block located at the second sub-region SSB2.

[0065] Exemplarily, referring to Figure 9 The channel structure 3 can be formed first. Specifically, this step includes: forming an upper channel hole segment of the second stack structure 4; removing the lower channel hole structure 30 so as to integrate the upper channel hole segment and the lower channel hole segment to form a channel hole; and then forming the channel structure 3 in the channel hole.

[0066] The upper channel hole segment of the second stack block located at the first storage region GB1 and the upper channel hole segment of the second stack block located at the second storage region GB2 can be formed by etching. A mask can be used to ensure the overlay accuracy of the upper channel hole segment and the lower channel hole structure 30, and the bottom end of the upper channel hole segment exposes the lower channel hole structure 30. As described above, the material of the lower channel hole structure 30 is a material to be sacrificed, for example, which has etching selectivity with the material of the first stack block and the material of the second stack block, and then the lower channel hole structure 30 can be removed by etching. After the upper channel hole segment and the lower channel hole segment are integrated to form a channel hole, the channel structure 3 can be formed in the channel hole. Referring to Figure 9 , the channel structure 3 can penetrate through the composite stack structure 5 and can extend into the substrate 1.

[0067] Referring to Figure 10 , the channel structure 3 can include, from outside to inside, a blocking layer 31, a charge storage (trapping) layer 32, a tunneling layer 33, a channel layer 34, and an insulating core filling layer 35. Further, the channel structure 3 can also include a drain at the top and a source at the bottom.

[0068] Referring to Figure 12 , Figure 16 The second stack block of the staircase region SS and the eighth stack block located at the bridge region GW can form a second step structure 40 and a third step structure 41 by a “trim-etch” process, wherein the height of each step of the third step structure 41 can be consistent with the height of each step in the second step structure 40. Referring to Figure 10 The second sub-stack block located at the first staircase region SSA is etched off completely, so that the first step structure 20 is exposed from the second stack structure 4 along the stacking direction. Exemplarily, referring to Figure 16For the eighth stacked block located in the bridging region GW, the portion of the stacked structure parallel to the first step region SSA in the Y direction is etched away, and the portion of the stacked structure parallel to the second step region SSB1 / SSB2 in the Y direction can be formed into a third step structure 41 with the same shape as the second step structure 40. Figure 16 ).

[0069] Specifically, the second step structure 40 is located in the second step region SSB1 / SSB2. The second step structure 40 may include two parts located in the first sub-region SSB1 and the second sub-region SSB2, respectively. The second step structure 40 includes at least one pair of steps located at the same height.

[0070] The second insulating filler 42 can then be formed. Exemplarily, the second insulating filler 42 can be formed by chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a precursor; in other embodiments, it can also be formed by spin coating. The second insulating filler 42 can cover the first step structure 20, the bridging structure 21, the second step structure 40, and the third step structure 41, and fill the top surface of the second stacked structure 4. The second insulating filler 42 can form a composite insulating filler structure 6 with the first insulating filler 22.

[0071] The gate can then be replaced. Specifically, the sacrificial layer 201 / 401 of the composite stack structure 5 can be removed, for example, through a gate line gap (not shown), to obtain a sacrificial gap; then a conductive material such as tungsten is deposited into the sacrificial gap to form the gate layer 203 / 403.

[0072] like Figure 12 As shown, the composite stacked structure 5 after the gate replacement process includes alternately stacked gate layers 203 / 403 and insulating layers 202 / 402. Specifically, the first stacked structure 2 includes alternately stacked first gate layer 203 and first insulating layer 202, while the second stacked structure 4 includes alternately stacked second gate layer 403 and second insulating layer 402.

[0073] According to an embodiment of this application, the method further includes forming a plurality of conductive channels 71-73 in the first stepped region SSA and the second stepped region SSB. The conductive channels 71-73 are electrically connected to the corresponding steps in the first stepped structure 20 or the second stepped structure 40.

[0074] refer to Figure 13Conductive channels 71-73 penetrate the composite insulating fill structure 6. Specifically, the first conductive channel penetrates the second insulating fill layer 42 and the first insulating fill layer 22 and is electrically connected to the first stepped structure 20. The second conductive channel 72 and the third conductive channel 73 respectively penetrate the second insulating fill layer 42 and are electrically connected to one of a pair of co-located steps 403-1 / 403-2. In other embodiments, the second conductive channel 72 or the third conductive channel 73 may be electrically connected to one of the twin steps 404-1 / 404-2.

[0075] An interconnect layer 8 electrically connected to the conductive channels 71-73 can then be formed on the second stacked structure 4. In this embodiment, the second step structure 40 includes at least one pair of first co-position steps 403-1 and second co-position steps 403-2 electrically connected through metal interconnects 81 in the interconnect layer 8.

[0076] refer to Figure 14 , Figure 14 yes Figure 13 The cross-sectional view at point AA shows the structure of a first gate layer 203. The portions of the first gate layer 203 located in the two memory regions GB1 / GB2 are connected as one unit via its portion located in the bridging region GW, and are also electrically connected to its first step 203-1 located in the first stepped region SSA. The first step 203-1 is used for electrical connection to the first conductive channel 71 to be formed. Multiple channel structures 3 pass through the first gate layer 203 and are controlled by the first gate layer 203 in the circuit system.

[0077] refer to Figure 15 , Figure 15 yes Figure 13 The cross-sectional view at point BB shows the structure of a second gate layer 403. This second gate layer 403 is divided into two blocks that are not directly electrically connected; instead, a second insulating filler separates the two blocks. Specifically, the second gate layer 403 includes a first co-position step 403-1 located in the first sub-region SSB1 (belonging to the second step region), a second co-position step 403-2 located in the second sub-region SSB2, and a first twin step 404-1 and a second twin step 404-2 located in the bridging region GW. The first twin step 404-1 is parallel to the first co-position step 403-1, and the second twin step 404-2 is parallel to the second co-position step 403-2.

[0078] The part of the second gate layer 403 located in the first storage region GB1 is integrated with the first co-level step 403-1, and the part of the second gate layer 403 located in the second storage region GB2 is integrated with the second co-level step 403-2. Exemplarily, the first co-level step 403-1 can be used to be electrically connected with the second conductive channel 72 to be formed, and the second co-level step can be used to be electrically connected with the third conductive channel 73 to be formed.

[0079] Reference is made to Figure 16 In an exemplary embodiment, the first co-level step 403-1 and the second co-level step 403-2 are located at the same height. In another embodiment, a pair of co-level steps located at different heights are electrically connected by a metal interconnection, and each pair of co-level steps is at the same electric potential in use due to the electrical connection.

[0080] In the circuit system, the first conductive channel 71 and the first gate layer 203 can be used as a word line of the channel structure 3. The metal interconnection 81 and the second gate layer 403 can be used as another word line of the channel structure 3.

[0081] The method can further include: disposing a peripheral circuit 9 on the interconnection layer 8. Reference is made to Figure 17 The peripheral circuit 9 includes a string driver (CMOS string driver) 91 for controlling the word line.

[0082] The method for manufacturing the three-dimensional memory provided by the embodiment does not form a composite stack structure in one process, but forms at least two stack structures stacked together in steps, which can reduce the processing difficulty of the composite step structure and is suitable for manufacturing a three-dimensional memory with more layers and higher thickness.

[0083] Reference is made to Figure 17 In an exemplary embodiment of the present application, a three-dimensional memory is provided. The three-dimensional memory includes a substrate (not shown), a composite stack structure 5, an interconnection layer 8, and a plurality of conductive channels 71-73.

[0084] The composite stack structure 5 is disposed on the substrate. The composite stack structure 5 includes a first storage structure 52, a composite step structure 51, and a second storage structure 53 disposed in sequence from left to right. When the number of layers of the composite stack structure 5 is large and the thickness is high, a process of manufacturing in steps can be used to form the composite stack structure 5. Specifically, different process routes can form the same composite step structure 51.

[0085] The composite step structure 5 includes a plurality of steps, including at least a pair of co-level steps 403-1 / 403-2. Since the first storage structure 52 and the second storage structure 53 are spaced apart, the first co-level step 403-1 can be electrically connected with the first storage structure 52, and the second co-level step 403-2 can be electrically connected with the second storage structure 53.

[0086] Exemplarily, the three-dimensional memory includes a plurality of channel structures (not shown). The channel structures penetrate through the composite stack structure 5 and can extend into the substrate. When the channel structures are also formed by a distributed manufacturing process, the segmentation of the channel structures can be utilized to define the first stack structure 2 and the second stack structure 4 included in the composite stack structure 5 and arranged in sequence in the direction away from the substrate.

[0087] Exemplarily, the three-dimensional memory further includes a composite insulating filling structure (not shown) located on the composite step structure 5. The composite insulating filling structure fills the top surface of the composite stack structure 5.

[0088] The conductive channels 71-73 penetrate through the composite insulating filling structure and further electrically connect with the corresponding steps in the composite step structure 51. Specifically, the first conductive channel 71 can electrically connect with the first step 203-1, the second conductive channel 72 can electrically connect with the first homologous step 403-1, and the third conductive channel 73 can electrically connect with the second homologous step 403-2.

[0089] The interconnection layer 8 is arranged on the composite stack structure 5, and the interconnection layer 8 includes a plurality of interconnection structures, such as copper interconnections, tungsten interconnections, with a preset pattern. These interconnection structures are electrically connected to the respective corresponding conductive channels 71-73. Exemplarily, some interconnection structures are electrically connected to the channel structures. When designing the interconnection layer 8, the pattern of the interconnection structures can be adjusted to form some spare pattern spaces. In the embodiments of the present application, the interconnection layer 8 includes a metal interconnection 81 arranged in such a spare pattern space, which is electrically connected to the second conductive channel 72 and the third conductive channel 73, i.e., a pair of homologous steps 403-1 / 403-2, thereby electrically connecting the two parts of one gate layer that are spaced apart.

[0090] In addition, the first stack structure 2 includes a bridge structure 21. The bridge structure 21 is used to electrically connect the first storage structure 52 and the second storage structure 53. In turn, the first step 203-1 electrically connects one gate layer at this height into one body through the bridge structure 21. Exemplarily, each string driver (CMOS string driver) 91 included in the peripheral circuit 9 controls one gate layer.

[0091] Exemplarily, the interconnection layer 8 is also electrically connected to a plurality of channel structures (not shown).

[0092] In the three-dimensional memory provided by the embodiments of the present application, by utilizing the spare space of the interconnection layer to arrange the metal interconnection, a pair of homologous steps are electrically connected, thereby reducing the design, manufacturing difficulty and manufacturing cost of the composite step structure.

[0093] Reference Figure 18A three-dimensional memory is provided in the exemplary embodiments of this application. The three-dimensional memory includes a substrate (not shown) and a composite stack structure 5. In addition, the three-dimensional memory can also include a composite insulative fill structure, an interconnect layer and a plurality of conductive channels (not shown).

[0094] The composite stack structure 5 is disposed on the substrate, and includes a first memory structure 52, a composite step structure 51 and a second memory structure 53 disposed in sequence from left to right.

[0095] The composite stack structure 5 can be formed by a step-by-step fabrication process. Specifically, different process routes can form the same composite step structure 51. Exemplarily, the composite stack structure 5 includes a first stack structure 2 and a second stack structure 4 disposed in sequence in a direction away from the substrate.

[0096] In fabricating the three-dimensional memory, the step of fabricating the composite stack structure 5 can include: forming the first stack structure 2; forming a first step structure 20 at the first memory block of the first staircase region SSA and a twin step structure 21 at the seventh memory block of the bridge region GW. Exemplarily, after forming the first step structure 20 and the twin step structure 21, a first insulative fill (not shown) can be formed to level the first stack structure 2.

[0097] The step of fabricating the composite stack structure 5 can also include: forming the second stack structure 4; and forming a second step structure 40 at the second stack block of the second staircase region SSB1-SSB2, and the eighth stack block of the bridge region GW can be protected by a mask for later use as a bridge structure 40. The etching process and the filling process of this method are easier to implement.

[0098] Reference is made to Figure 18 The composite step structure 51 includes at least one pair of twin steps electrically connected to the first memory structure 52 and the second memory structure 53, respectively, and the pair of twin steps can be located in the first step structure 20.

[0099] The conductive channels in the three-dimensional memory are electrically connected to the corresponding steps in the composite step structure 51. The interconnect layer of the three-dimensional memory is disposed on the composite stack structure 5 and is electrically connected to the conductive channels. Each pair of twin steps in the first step structure 20 is electrically connected by a metal interconnect in the interconnect layer. The steps in the second step structure 40 are electrically connected to the first memory structure 52 and the second memory structure 53 by the bridge structure 41.

[0100] Reference is made to Figure 19 A three-dimensional memory is provided in the exemplary embodiments of this application. The three-dimensional memory includes a substrate (not shown) and a composite stack structure 5. In addition, the three-dimensional memory can also include a composite insulative fill structure, an interconnect layer and a plurality of conductive channels (not shown).

[0101] The composite stack structure 5 is disposed on a substrate, and includes a first memory structure, a composite step structure, and a second memory structure disposed in sequence from left to right.

[0102] The composite stack structure 5 can be formed by a step-by-step manufacturing process. Specifically, different process routes can form the same composite step structure. Exemplarily, the composite stack structure 5 includes the first stack structure 2 and the second stack structure 4 disposed in sequence in a direction away from the substrate.

[0103] In manufacturing the three-dimensional memory, the step of manufacturing the composite stack structure 5 can include: forming the first stack structure 2; forming the first step structure 20 in the first staircase region SSA and forming the bridge structure 21 in the bridge region, wherein the part of the first stack structure 2 not used for forming the bridge structure 21 is formed into a first twin step structure (not shown) at least partially identical to the first step structure 20; forming the second stack structure 4; forming the second step structure 40 in the second staircase regions SSB1-SSB2 and forming a second twin step structure (not shown) in the bridge region.

[0104] In the method of forming the three-dimensional memory of the present embodiment, the step of forming the first step structure 2 can include: forming a plurality of staircases 210 / 220 at different depths.

[0105] Specifically, the depth to be etched of each staircase 210 / 220 is determined. The depth to be etched is an integer multiple of the height of a staircase. As shown, the depths to be etched of the staircases of the first step structure 20 from left to right are 0, 1, 2, 5, 6, 8, 7 (220), 4, 3, and 0 (210) times the height of a staircase, respectively. Figure 18

[0106] Referring to Figure 20 The pairs of staircases 210 / 220 can be formed in the first stack structure 2 using a mask first. Then, different staircases are etched to different depths. For example, at least two staircases are etched synchronously, wherein the depth of each synchronous etching is an integer multiple of the height of a staircase. Exemplarily, the thickness of the bridge structure 21 is the same as the height of the eight inner staircases. In other embodiments, the thickness of the bridge structure can be the same as the first step structure.

[0107] Referring to Figure 19 The composite step structure includes at least one pair of homologous steps electrically connected to the first memory structure and the second memory structure, respectively, which can be located in the first step structure 20. Specifically, the homologous steps belong to the first staircase 210 and the staircase opposite to the first staircase 210. In addition, the second step structure 40 also includes homologous steps.

[0108] ​The conductive channel in the three-dimensional memory is electrically connected with a corresponding step in the composite step structure. An interconnection layer of the three-dimensional memory is disposed on the composite stack structure 5 and is electrically connected with the conductive channel. Each pair of homologous steps in the first step structure 20 or the second step structure 40 is electrically connected by a metal interconnection in the interconnection layer. Steps other than the homologous steps in the first step structure 20 (for example, the steps of the second step 220) are electrically connected with the first storage structure and the second storage structure by the bridge structure 21.

[0109] At least according to the third embodiment and the fourth embodiment, in a direction perpendicular to the drawing plane, at least one of the first step structure and the second step structure which is juxtaposed with the bridge structure includes a plurality of steps at different depths.

[0110] Reference Figure 21 In the exemplary embodiments of the present application, a three-dimensional memory is provided. The three-dimensional memory includes a substrate (not shown) and a composite stack structure 5. In addition, the three-dimensional memory can also include a composite insulating filling structure, an interconnection layer and a plurality of conductive channels (not shown).

[0111] The composite stack structure 5 is disposed on the substrate, and the composite stack structure 5 includes a first storage structure, a composite step structure and a second storage structure disposed in sequence from left to right.

[0112] The composite stack structure 5 can be formed by a step-by-step manufacturing process. Specifically, different process routes can form the same composite step structure. Exemplarily, the composite stack structure 5 includes a first stack structure 2 and a second stack structure 4 disposed in sequence in a direction away from the substrate.

[0113] In manufacturing the three-dimensional memory, the step of manufacturing the composite stack structure 5 can include: forming the first stack structure 2; forming the first step structure 20 in the first step region SSA and forming the first bridge structure 21 in the bridge region; forming the second stack structure 4; forming the second step structure 40 in the second step regions SSB1-SSB2, wherein the second step structure 40 includes a lower step 410 facing the first storage structure; and forming a twin step structure (not shown) and the second bridge structure 41 in the bridge region.

[0114] The composite step structure 51 includes at least one pair of homologous steps electrically connected with the first storage structure and the second storage structure, respectively. The pair of homologous steps can be located in the second step structure 40.

[0115] The conductive channels in the three-dimensional memory are electrically connected with corresponding steps in the composite step structure. The interconnection layer of the three-dimensional memory is disposed on the composite stack structure 5 and is electrically connected with the conductive channels. Each pair of homologous steps in the second step structure 40 is electrically connected by a metal interconnection in the interconnection layer. The steps of the first step structure 20 and the steps other than the homologous steps in the second step structure (for example, the steps of the ladder 410) are electrically connected with the first storage structure and the second storage structure by the composite bridge structure (which includes the first bridge structure 21 and the second bridge structure 41).

[0116] Reference Figure 22 In the exemplary embodiments of the present application, a three-dimensional memory is provided. The three-dimensional memory includes a substrate (not shown) and a composite stack structure 5. In addition, the three-dimensional memory can also include a composite insulating filling structure, an interconnection layer and a plurality of conductive channels (not shown).

[0117] The composite stack structure 5 is disposed on the substrate, and the composite stack structure 5 includes a first storage structure 52, a composite step structure 51 and a second storage structure 53 disposed in sequence from left to right.

[0118] The composite stack structure 5 can be formed by a step-by-step manufacturing process. Specifically, different process routes can form the same composite step structure 51. Exemplarily, the composite stack structure 5 includes a first stack structure 2 and a second stack structure 4 disposed in sequence in the direction away from the substrate.

[0119] In the manufacture of the three-dimensional memory, the step of manufacturing the composite stack structure 5 can include: forming the first stack structure 2; forming the first step structure 20 in the first ladder region SSA and the first twin step structure 21 in the bridge region; forming the second stack structure 4; forming the second step structure 40 in the second ladder region SSB1-SSB2, wherein the second step structure 40 includes a plurality of ladders 410 located at different depths; forming the second twin step structure 42 and the bridge structure 41 in the bridge region.

[0120] The composite step structure 51 includes at least one pair of homologous steps electrically connected with the first storage structure and the second storage structure, respectively. The pair of homologous steps can be located in the first step structure 20 and the second step structure 40.

[0121] The conductive via in the three-dimensional memory is electrically connected with the corresponding step in the composite step structure 51. The interconnection layer of the three-dimensional memory is disposed on the composite stack structure 5 and is electrically connected with the conductive via. Each pair of homologous steps in the first step structure 20 and the second step structure 40 is electrically connected by a metal interconnection in the interconnection layer. The steps other than the homologous steps in the composite step structure 51 (for example, the steps of the staircase 410) are electrically connected with the first storage structure 52 and the second storage structure 53 by the bridge structure 41.

[0122] As shown in Figure 23 The present disclosure also provides a storage device 6, which includes at least one three-dimensional memory 61, a controller 62, and a connector 63. The connector 63 is used to couple the storage system 6 with an external device.

[0123] The three-dimensional memory 61 provided by the present disclosure can be the three-dimensional memory described above. The three-dimensional memory 61 can include a composite stack structure serving as a storage structure and a peripheral circuit. The peripheral circuit is electrically connected with the composite stack structure to facilitate the functions of the composite stack structure in the circuit, and the peripheral circuit can for example include a page buffer / sense amplifier, a column decoder / bit line (BL) driver, a row decoder / word line (WL) driver, a voltage generator, a control logic unit, a register, an interface, and a data bus.

[0124] Exemplarily, the controller 62 and the at least one three-dimensional memory 61 can be integrated into a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage card (UFS), etc. Exemplarily, the controller 62 and the at least one three-dimensional memory 61 can be integrated into a solid state drive (SSD).

[0125] The three-dimensional memory or the storage device provided by the present disclosure has a better form of the composite stack structure, a higher manufacturing yield, and can stably and long-term provide a better storage capacity.

[0126] The above description is merely preferred embodiments of the present application and a description of the technical principles of the application. It should be understood by those skilled in the art that the protection scope of the present application is not limited to the technical solutions formed by the specific combinations of the technical features described above, and also covers other technical solutions formed by any combinations of the technical features described above or equivalent features without departing from the technical concept. For example, the technical solutions formed by replacing the above-described features with technical features having similar functions in the present application (but not limited to) with each other.

Claims

1. A method of fabricating a three-dimensional memory, comprising: The method comprises: forming a first stack block; forming a first stepped structure on the first stack block; forming a second stack block on one side of the first stack block along a stacking direction of the first stack block; forming a second stepped structure on the second stack block, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of homologous steps, and the pair of homologous steps are arranged in a vertical plane of the stacking direction; forming a plurality of conductive channels on the one side of the first stepped structure, wherein the conductive channels are electrically connected with corresponding steps in the first stepped structure or the second stepped structure, and each pair of homologous steps are electrically connected with each other through the conductive channels; wherein part of the homologous steps in the first stepped structure are connected through a bridge structure, and part of the homologous steps in the second stepped structure are connected through a bridge structure.

2. The method of claim 1, wherein, The method further comprises: forming an interconnection layer electrically connected with the conductive channels on the side of the plurality of conductive channels away from the first stepped structure, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of steps electrically connected through a metal interconnection in the interconnection layer.

3. The method of claim 1, wherein, The second stepped structure is located on both sides of the first stepped structure along the direction opposite to the pair of homologous steps.

4. The method of claim 1, wherein, The method further comprises: forming a first insulating filler on the one side of the first stepped structure before the step of forming the second stack structure; forming a second insulating filler on the side of the second stepped structure away from the first stepped structure; and wherein the conductive channels connected to the first stepped structure pass through the first insulating filler and the second insulating filler, and the conductive channels connected to the second stepped structure pass through the second insulating filler.

5. The method of claim 1, wherein, The method further comprises: forming a third stack block and a fifth stack block on opposite sides of the first stack block, respectively; forming a seventh stack block between the third stack block and the fifth stack block; forming a fourth stack block and a sixth stack block on opposite sides of the second stack block, respectively; and 6. The method of claim 5, wherein, forming an eighth stack block between the fourth stack block and the sixth stack block. The first stepped structure comprises at least one pair of homologous steps, one of the pair of homologous steps is connected to the third stack block, and the other is connected to the fifth stack block, and a first twin stepped structure at least partially same as the first stepped structure is formed in the seventh stack block; or 7. The method of claim 5, wherein, The second stepped structure comprises at least one pair of homologous steps, one of the pair of homologous steps is connected to the fourth stack block, and the other is connected to the sixth stack block, and a second twin stepped structure at least partially same as the second stepped structure is formed in the eighth stack block.

8. The method of claim 7, wherein, At least one of the first stepped structure and the second stepped structure comprises a plurality of steps at different depths. The method further comprises: The step of forming the plurality of steps at different depths comprises: determining the depth to be etched of each of the steps, wherein the depth to be etched is an integer multiple of the height of one of the steps; and Synchronously etching at least two of the steps, wherein a depth of each of the synchronously etching is an integer multiple of a height of one of the steps.

9. A three-dimensional memory, comprising: Comprise: a first stack block comprising a first stepped structure; a second stack block comprising a second stepped structure, disposed at one side of the first stepped structure along a stacking direction of the first stepped structure, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of homologous steps, and a pair of the homologous steps are disposed at intervals in a vertical plane of the stacking direction; and a plurality of conductive channels disposed at the one side of the first stepped structure, wherein the conductive channels are electrically connected with corresponding steps of the first stepped structure or the second stepped structure, and each pair of the homologous steps are electrically connected with each other through the conductive channels, and part of the homologous steps in the first stepped structure are connected through a bridging structure, and part of the homologous steps in the second stepped structure are connected through a bridging structure.

10. The three-dimensional memory of claim 9, further comprising: an interconnection layer disposed at a side of the plurality of conductive channels away from the first stepped structure and electrically connected with the conductive channels, wherein at least one of the first stepped structure and the second stepped structure comprises at least one pair of first steps electrically connected through a metal interconnection in the interconnection layer.

11. The three-dimensional memory of Claim 9 wherein, The second stepped structure is disposed at two sides of the first stepped structure in the vertical plane of the stacking direction.

12. The three-dimensional memory of Claim 9 wherein, Further comprising a first insulating filler disposed at the one side of the first stepped structure, and a second insulating filler disposed at a side of the second stepped structure away from the first stepped structure; wherein the conductive channels connected to the first stepped structure pass through the first insulating filler and the second insulating filler, and the conductive channels connected to the second stepped structure pass through the second insulating filler.

13. The three-dimensional memory of Claim 9 wherein, Further comprising: a third stack block, a fifth stack block and a seventh stack block disposed in parallel with the first stack block, wherein the third stack block and the fifth stack block are oppositely disposed at two sides of the first stack block, and the seventh stack block is disposed between and connected the third stack block and the fifth stack block; and a fourth stack block, a sixth stack block and an eighth stack block disposed in parallel with the second stack block, wherein the fourth stack block and the sixth stack block are oppositely disposed at two sides of the second stack block, and the eighth stack block is disposed between and connected the fourth stack block and the sixth stack block.

14. The three-dimensional memory of Claim 13 wherein, The first stepped structure comprises at least one pair of the homologous steps, one of a pair of the homologous steps is connected with the third stack block, and the other is connected with the fifth stack block, and the seventh stack block comprises a first twin stepped structure at least partially same as the first stepped structure; or the first stepped structure comprises at least one pair of the homologous steps, one of a pair of the homologous steps is connected with the third stack block, and the other is connected with the fifth stack block, and the seventh stack block comprises a second twin stepped structure at least partially same as the second stepped structure. The second step structure includes at least one pair of the same steps, one of the pair of the same steps is connected with the fourth stack block, and the other is connected with the sixth stack block. The eighth stack block includes a second twin step structure which is at least partially identical to the second step structure.

15. The three-dimensional memory of Claim 13 wherein, At least one of the first step structure and the second step structure includes a plurality of steps at different depths.

16. A memory device, comprising: Comprise: The three-dimensional memory according to any one of claims 9-15; And A controller, electrically connected with the three-dimensional memory, and configured to control the three-dimensional memory.

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