Wide bandgap semiconductor device comprising gate fingers between bonding pads

Abstract

A wide bandgap semiconductor device includes gate fingers between bonding pads. A semiconductor device includes a semiconductor body made of a wide bandgap semiconductor material. A plurality of first bonding regions are connected to a first load terminal of the semiconductor device. First gate fingers are arranged between the first bonding regions. The first gate fingers extend in a first lateral direction and branch from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. A sum of the first length and the second length is equal to or greater than a lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.

Description

Technical Field

[0001] This invention relates to a wide-bandgap semiconductor device comprising gate fingers between bonding pads. Background Technology

[0002] Wide bandgap semiconductor devices are based on semiconductor materials with a bandgap of at least 2 eV or at least 3 eV, allowing for lower on-state resistance and higher current density compared to conventional silicon-based semiconductor devices. When switching high current densities at high frequencies in wide bandgap semiconductor devices (such as, for example, field-effect transistors (FETs) or insulated-gate bipolar transistors (IGBTs)), a uniform current distribution across the active region of the transistor cell array is desirable to avoid excessive stress, which can be caused by non-uniform current distribution and may degrade the reliability of the semiconductor device.

[0003] The goal is to improve the uniformity of load current distribution across the active region of a wide-bandgap semiconductor device. Summary of the Invention

[0004] This disclosure relates to a semiconductor device comprising a semiconductor body made of a wide-bandgap semiconductor material. A plurality of first junction regions are electrically connected to first load terminals of the semiconductor device. First gate fingers are disposed between the first junction regions. The first gate fingers extend in a first lateral direction and branch from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. The sum of the first length and the second length is equal to or greater than the lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.

[0005] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0006] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with this description, serve to explain the principles of the invention. Other embodiments and intended advantages of the invention will be readily appreciated as they become better understood with reference to the following detailed description.

[0007] Figure 1A , 1B Figures 2 and 2 are schematic plan views used to illustrate a wide-bandgap semiconductor device containing gate fingers between bonding pads.

[0008] Figure 3 It is along the strip-shaped trench gate structure shown in the figure. Figure 2 An example of a schematic cross-sectional view of line AA.

[0009] Figure 4 The diagram shows the electrical connection between the gate line and the gate junction region along... Figure 2 An example of a schematic cross-sectional view of line BB.

[0010] Figure 5 The diagram shows the edge termination structure electrically connected to the source line along... Figure 2 An example of a schematic cross-sectional view of the line CC.

[0011] Figure 6 This is an example of a schematic plan view used to illustrate a joining wiring pattern.

[0012] Figure 7 This is an example of a schematic plan view used to illustrate a semiconductor module including a wide-bandgap semiconductor device. Detailed Implementation

[0013] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate specific embodiments in which the present disclosure may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. For example, features illustrated or described for one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another embodiment. Such modifications and variations are intended to be included in this disclosure. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0014] The terms “having,” “containing,” “including,” “comprising,” etc., are open-ended and indicate the presence of the described structure, element, or feature, but do not exclude the presence of additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0015] The term "electrical connection" describes a permanent low-ohmic connection between electrically connected elements, such as a direct contact between elements or a low-ohmic connection via a metal and / or highly doped semiconductor. The term "electrical coupling" includes one or more intervening elements adapted for signal transmission that may exist between electrically coupled elements, such as elements temporarily providing a low-ohmic connection in a first state and a high-ohmic electrically decoupled element in a second state.

[0016] As used in this specification, the term "horizontal" is intended to describe an orientation that is substantially parallel to a first or main surface of the semiconductor substrate or body. This could be, for example, the surface of a wafer or die.

[0017] As used herein, the term "vertical" is intended to describe an orientation that is substantially perpendicular to the first surface, i.e., parallel to the normal direction of the first surface of the semiconductor substrate or body.

[0018] In this specification, the second surface of a semiconductor substrate or semiconductor body is considered to be formed by the lower or rear surface of the semiconductor substrate, while the first surface is considered to be formed by the upper, front, or main surface of the semiconductor substrate. Therefore, the terms "above" and "below" as used in this specification describe the relative position of a structural feature with respect to another structural feature.

[0019] In this specification, p-doping is referred to as the first conductivity type, and n-doping is referred to as the second conductivity type. Alternatively, semiconductor devices can be formed with the opposite doping relationship, such that the first conductivity type can be n-doped and the second conductivity type can be p-doped.

[0020] Figure 1A and 1B This is a schematic plan view illustrating a wide-bandgap semiconductor device 1000 containing gate fingers between bonding pads.

[0021] Semiconductor device 1000 includes a semiconductor body made of a wide-bandgap semiconductor material. A plurality of first junction regions 102 are electrically connected to a first load terminal of the semiconductor device, such as the source terminal of a FET or the emitter terminal of an IGBT. In some embodiments, the first junction regions 102 form part of a contact metallization of the first load terminal and may be defined, for example, by openings in a passivation layer. First gate fingers 104 are disposed between the first junction regions 102. The first gate fingers 104 extend in a first lateral direction x1 and branch from at least one of a first gate line portion 106 and a second gate line portion 108. Second gate fingers 110 extend in the first lateral direction x1. A first length l1 of any of the first gate fingers 104 along the first lateral direction x1 is greater than a second length l2 of any of the second gate fingers 110 along the first lateral direction x1. The sum of the first length l1 and the second length l2 is equal to or greater than the lateral distance d between the first gate line portion 106 and the second gate line portion 108 along the first lateral direction x1. The first and second gate line portions may be part of a gate line or a so-called gate runner, and for example, the gate line or the gate runner may be electrically coupled to a gate junction region.

[0022] like Figure 1A and 1B As illustrated, each of the first gate fingers 104 can extend parallel to the longitudinal direction of the first bonding region 102, which is the direction in which the first bonding region 102 extends to its maximum extent in any lateral direction. Figure 1A and 1B In the embodiment illustrated, the longitudinal direction coincides with the first lateral direction x1. In some embodiments, the length of the first bonding region 102 along the longitudinal direction can range between 0.2 mm and 10 mm. In one or more embodiments, the first gate finger 104 can extend from the first gate line portion 106 or from the second gate line portion 108 along the longitudinal direction of the first bonding region 102 through the gap between two adjacent first bonding regions 102 up to or beyond the lateral end E of the first bonding region 102.

[0023] exist Figure 1A and 1B In the embodiment illustrated, the first gate fingers 104 and the first junction region 102 are arranged alternately along a second lateral direction x2. The second lateral direction x2 may be perpendicular to the first lateral direction x1. Figure 1A In the embodiment illustrated in the figure, the first gate finger 104 branches off from the first gate line portion 106. Figure 1BIn the embodiment illustrated in the figure, the first gate finger 104 branches from the first gate line portion 106 and from the second gate line portion 108.

[0024] In some embodiments, the lateral distance between two adjacent first gate fingers 104, for example, is as shown in Figure 1A The lateral distance d1 shown in the figure can be constant within the first gate finger 104.

[0025] Similar to the first gate finger 104, the second gate finger 110 may also branch from the first gate line portion 106 and / or the second gate line portion 108. In some embodiments, the lateral distance between two adjacent second gate fingers 110, for example as in Figure 1A The lateral distance d2 illustrated in the figure can be equal among one or all of the second gate fingers 110. In one or more embodiments, a first distance d1 can correspond to a second distance d2. This can be advantageous in terms of similar or equal gate signal transit time for the gate signal to propagate from the first junction region 102 of the wide bandgap semiconductor device 1000 to the gate electrode. Since the signal delay caused by the resistance of the gate fingers and gate lines between the gate pad and the gate electrode is generally negligible compared to the resistance of the gate electrode at the location with the maximum distance to the gate fingers at the gate finger and gate electrode, setting d1 to be equal to or similar to d2 allows the maximum distance between the gate fingers and any location along the gate electrode to be set to half of d1 when the gate electrode extends along the second direction x2, regardless of whether the gate electrode is driven by the first gate finger 104 or the second gate finger 110.

[0026] In some embodiments, in addition to the first and second gate fingers 104, 110, additional gate fingers may branch from the first or second gate line portions 106, 108, for example, to electrically connect the gate electrode in the following portions of the transistor cell region, said portions being located at or near corner regions and not being part of a regular array of gate finger contacts.

[0027] In one or more embodiments, the first bonding region 102 includes a first bonding region segment 112 of continuous metallized regions, the first bonding region segment 112 being merged by a first interconnect segment 114 of continuous metallized regions. The continuous metallized regions can be formed, for example, by photolithographically patterning one or more metallization layers that can be formed in one or more metallization levels. In some embodiments, each of the first gate fingers 104 is offset relative to each of the second gate fingers 110 along a second lateral direction x2, thereby providing a direction contact between the first bonding region segment 112 and the first interconnect segment 114.

[0028] exist Figure 1A In the embodiment illustrated, length l1 is constant within the first gate finger 104. Similarly, length l2 is... Figure 1A The second gate finger 110 shown in the figure is constant. In one or more other embodiments, the lengths of some or all of the first gate fingers 104 may be different from each other, and the lengths of some or all of the first gate fingers 104 may also be different from each other, as long as the first length l1 of any of the first gate fingers 104 is greater than the second length l2 of any of the second gate fingers 110.

[0029] In one or more embodiments, the first length l1 is between 0.2 mm and 10 mm, and the first lateral distance d1 between the first gate fingers is between 0.1 mm and 1.5 mm.

[0030] In one or more embodiments, a first length l1 is greater than a first lateral distance d1 between two adjacent first gate fingers 104, and a second length l2 is less than a second lateral distance d2 between second gate fingers 110. In some embodiments, for example in Figure 1A In the embodiment illustrated, the second length l2 is less than 60% of the second lateral distance d2 between the second gate fingers 110. This allows the first interconnect segment 114 to provide a low-ohmic electrical connection from the first junction region segment 112 of the wide bandgap semiconductor device 1000 to a first load region, which is, for example, located below the first interconnect segment 114 and electrically connected to the source region of the first interconnect segment 114 via a contact plug.

[0031] In one or more embodiments, the semiconductor device 1000 includes a gate structure that can extend in the shape of parallel strips. The gate structure can extend along a second lateral direction x2 perpendicular to a first lateral direction x1. The gate structure can also extend along a different lateral direction than the second lateral direction x2. In one or more embodiments, the gate structure is a trench gate structure including gate electrodes in a trench, the gate electrodes being electrically insulated from a surrounding portion of the wide-bandgap semiconductor body by a gate dielectric. In some other embodiments, the gate structure is a planar gate structure including planar gate electrodes disposed on the surface of the semiconductor body and electrically insulated from a surrounding portion of the wide-bandgap semiconductor body by a gate dielectric. In one or more embodiments, the gate electrode material of the gate structure is one or a combination of doped polysilicon and metal silicides.

[0032] Semiconductor device 1000 is based on a semiconductor body made of a wide-bandgap semiconductor material having a bandgap of 2.0 eV or higher. As an example, the wide-bandgap semiconductor material can have a hexagonal lattice and can be silicon carbide (SiC) or gallium nitride (GaN). For example, the semiconductor material is 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to another embodiment, the semiconductor material is 4H polytype silicon carbide (4H-SiC). Wide-bandgap semiconductor materials other than SiC and GaN can be alternatively used to realize semiconductor devices requiring operation at high current densities.

[0033] In one or more embodiments, each of the first and second gate fingers 104, 110, the first and second gate line portions 106, 108, the first junction region segment 112, and the first interconnect segment 114 is a plurality of portions of the same patterned metallization structure.

[0034] In some embodiments, for example in Figure 1A , 1B In the illustrated embodiment, the semiconductor device 1000 further includes a source line 116, wherein a first gate line portion 106 is disposed between the source line 116 and the transistor cell region 118, and a second gate line portion 108 is disposed between the source line 116 and the transistor cell region 118. Similar to the first and second gate line portions 106, 108, the first junction region segment 112, and the first interconnect segment 114, the source line 116 may also be part of the same patterned metallization structure. For example, the source line 116 may be advantageous in relation to an edge-terminating structure in a region of the semiconductor body that is outside the transistor cell region 118 and completely or partially surrounds the transistor cell region 118.

[0035] refer to Figure 2In a schematic plan view, source line 116 and first junction region 102 are electrically connected by a second interconnect 120 extending through the gap between opposite ends E1, E2 of gate line 122. First gate line portion 106 and second gate line portion 108 are components of gate line 122, which at least partially surrounds the transistor cell region. Gate line 122 is electrically coupled to a second junction region 124 containing a second junction region segment 125. For example, the second junction region 124 may be a gate junction region.

[0036] In one or more embodiments, for example in Figure 2 In the embodiment illustrated, a gate resistor 126 is electrically coupled between the gate line 122 and the second bonding region 124. In some embodiments, the resistance of the gate resistor 126 ranges from 2Ω to 30Ω. For example, the resistance of the gate resistor 126 can allow for setting a gate signal delay. The gate line 122 and the gate resistor 126 can be electrically connected via a measurement region 128. The measurement region 128 may have a similar structure to the first and second bonding regions 102, 124, and may differ in size from the first and second bonding regions 102, 124. As an example, the size of the measurement region 128 may be too small for wire bonding, but large enough for contact pin contacts of the component under test.

[0037] In addition to the first and second gate fingers 104, 110, the semiconductor device 1000 further includes a third gate finger 130 for electrically connecting the gate electrode of the transistor cell in a corner region of the active transistor cell region. For example, these corner regions are outside the regular contact pattern formed by the first and second gate fingers 104, 110 due to the arrangement of the second junction region 124.

[0038] Figure 3 The diagram shows the extension direction of the gate structure. Figure 2 An exemplary cross-sectional view of line AA. This exemplary cross-sectional view illustrates a trench gate structure comprising a gate electrode 132 and a gate dielectric 134 in a trench extending along a second lateral direction x2. + The doped shielding structure 136 is adjacent to the gate dielectric 134 at the bottom side of the trench structure. The shielding structure 136 allows the semiconductor device 1000 to achieve the desired reliability under blocking conditions by limiting the electric field strength in the gate dielectric 134, for example, at the trench corners. The semiconductor device 1000 may contain n - A vertical FET with a doped drift region of 138. - The doped drift region 138 can be electrically coupled to the second load terminal L2 at the second side of the semiconductor body.

[0039] The gate electrode 132 of the gate structure is electrically connected to the first gate finger 104 at the intersection of the gate structure and the first gate finger 104. For example, an insulating structure 140 provides electrical insulation between the first gate finger 104 and the first junction region segment 112, and between the first junction region segment 112 and the semiconductor body. The insulating structure 140 may comprise one or more insulating materials, such as oxides and / or nitrides. A passivation structure 142 is disposed on the insulating structure 140 and the first junction region segment 112. The passivation structure 142 may comprise one or more passivation materials, such as imides, nitrides, and oxides. An opening in the passivation structure 142 exposes the first junction region segment 112 for providing chip contact, for example, via wire bonding, and defines the first junction region 102.

[0040] exist Figure 4 The diagram shows along Figure 2 An exemplary cross-sectional view of line BB at the second junction region 124. Gate resistor 126 may be formed of a doped semiconductor material, such as doped polysilicon. The p-doped body structure 137 is electrically connected to source line 116 and the first interconnect segment 114. The p-doped body structure 137 may be contained within... Figure 3 p in the diagram + Doped shielding structure 136. In Figure 5 The diagram shows along Figure 2 An exemplary cross-sectional view of line CC at the edge of the semiconductor body. The semiconductor device 1000 further includes an edge termination structure 143 within the semiconductor body. The edge termination structure 143 at least partially surrounds the transistor cell region, for example, with... Figure 2 The gate line is similar to that shown in the diagram and is electrically connected to the source line 116 via a p-doped body structure 137.

[0041] In one or more embodiments, for example in Figure 5 In the embodiment illustrated, the edge-termination structure 143 is a junction-termination extension (JTE) structure. The JTE structure includes a plurality of p-doped semiconductor regions 146 spaced laterally from each other. The plurality of p-doped semiconductor regions 146 are arranged on p... - In the doped semiconductor well region 144 and by the p - The semiconductor well region 144 is surrounded by p-doped semiconductor regions. The maximum doping concentration of the p-doped semiconductor region 146 is greater than that of the p-doped region. - Maximum doping concentration of the doped semiconductor well region 144.

[0042] In one or more embodiments, for example in Figures 1A to 5In the illustrated embodiment, the semiconductor device 1000 is a power semiconductor field-effect transistor (power FET) or a power insulated-gate bipolar transistor (power IGBT) configured to conduct currents ranging from 1A to 60A for each of the first junction regions 102. In some embodiments, for example, the semiconductor device is configured to conduct currents ranging from 2A / mm². 2 Up to 20 A / mm 2 The current density is used for operation. Therefore, by summing the multiple first junction regions 102, the maximum rated current can be determined and specified in the datasheet of the semiconductor device 1000. In one or more embodiments, for example in Figures 1A to 5 In the embodiment illustrated in the figure, the semiconductor device 1000 is a vertical semiconductor transistor including a first load terminal and a control terminal on a first side of the semiconductor body and a second load terminal on a second side of the semiconductor body.

[0043] exist Figure 6 In the schematic plan view, the semiconductor device 1000 may further include first bonding wires 150, wherein one end of each of the first bonding wires 150 is attached to a corresponding one of the first bonding regions 102. The first bonding wires 150 extend along a third lateral direction x3, which is aligned with the first lateral direction x1 by an angular deviation of up to + / -20°. The details described above regarding the first bonding region 102 apply accordingly. Figure 6 In the exemplary view, the first lateral direction x1 coincides with the third lateral direction x3. However, the extension direction of the first bonding wire 150 may fall within... Figure 6 The angle range is + / -20° as illustrated by the dashed line. For example, the first bonding wire 150 may also be attached to the first load conductive rail 152 of the lead frame.

[0044] The second bonding wire 154 is attached to the second bonding region 124 and also to the gate contact region 156 of the lead frame. The third bonding wire 158 is attached to one of the first bonding regions 102 and also to the auxiliary contact region 159.

[0045] In one or more embodiments, the semiconductor module includes a semiconductor device 1000 described with reference to any of the embodiments described above. For example, the semiconductor module may include a plurality of semiconductor devices 1000 connected in parallel. The semiconductor module may include additional semiconductor devices different from the semiconductor device 1000.

[0046] In one or more embodiments, the semiconductor module is a power semiconductor module configured to conduct currents ranging from 50A to 2000A.

[0047] Figure 7The schematic plan view illustrates a portion of a semiconductor module 2000 comprising at least three of the semiconductor devices 1000 connected in parallel. First bonding leads 150 of the three semiconductor devices 1000 are attached to a first load rail 152. Second bonding leads 154 of the three semiconductor devices 1000 are attached to a gate rail 1560. Second load terminal contacts of semiconductor devices 100 may be attached to a second load rail 160 via a second side of the semiconductor body, for example, via the rear side of the semiconductor body. The first load rail 152 may be electrically connected to an external first load connector LC1 of the semiconductor module 2000. The second load rail 160 may be electrically connected to an external second load connector LC2 of the semiconductor module 2000. The gate rail 1560 may be electrically connected to an external gate load connector CC1 of the semiconductor module 2000.

[0048] The above embodiments allow for improved uniformity of load current distribution across the active region of a wide-bandgap semiconductor device.

[0049] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor body made of wide-bandgap semiconductor material; A plurality of first bonding regions connected to a first load terminal of the semiconductor device; A first gate finger disposed between the first junction regions, wherein the first gate finger extends in a first lateral direction and branches off from at least one of a first gate line portion and a second gate line portion; A second gate finger extending in the first lateral direction; and wherein The first gate finger has a first length along the first lateral direction that is greater than the second gate finger along the first lateral direction, and the sum of the first length and the second length is equal to or greater than the lateral distance along the first lateral direction between the first gate line portion and the second gate line portion. The second length is less than the second lateral distance between the second gate fingers.

2. A semiconductor device, comprising: Semiconductor body made of wide-bandgap semiconductor material; A plurality of first bonding regions connected to a first load terminal of the semiconductor device; A first gate finger disposed between the first junction regions, wherein the first gate finger extends in a first lateral direction and branches off from at least one of a first gate line portion and a second gate line portion; A second gate finger extending in the first lateral direction; and wherein The first gate finger has a first length along the first lateral direction that is greater than the second gate finger along the first lateral direction, and the sum of the first length and the second length is equal to or greater than the lateral distance along the first lateral direction between the first gate line portion and the second gate line portion. The first gate finger and the second gate finger are arranged alternately in the second lateral direction, wherein the second length is less than the second lateral distance between the second gate fingers.

3. The semiconductor device according to any one of claims 1-2, wherein the second gate finger is disposed between the first gate finger.

4. The semiconductor device according to any one of claims 1-2, wherein the first gate finger and the first junction region are arranged alternately along a second lateral direction.

5. The semiconductor device according to any one of claims 1-2, further comprising a gate structure extending along a second lateral direction.

6. The semiconductor device according to any one of claims 1-2, wherein the first lateral distance between the first gate fingers corresponds to the second lateral distance between the second gate fingers.

7. The semiconductor device according to any one of claims 1-2, wherein the first length along the first lateral direction is greater than the first lateral distance between the first gate fingers along the second lateral direction.

8. The semiconductor device according to any one of claims 1-2, wherein the first length is between 0.2 mm and 10 mm, and the first lateral distance between the first gate fingers is between 0.1 mm and 1.5 mm.

9. The semiconductor device according to any one of claims 1-2, wherein the second length is less than 60% of the second lateral distance between the second gate fingers.

10. The semiconductor device according to any one of claims 1-2, wherein the first junction region comprises junction region segments of continuous metallization regions, the junction region segments being merged by first interconnect segments of the continuous metallization regions.

11. The semiconductor device of claim 10, wherein each of the first and second gate fingers, the first and second gate line portions, and the junction region segment comprises a corresponding portion of the same patterned metallization structure.

12. The semiconductor device according to any one of claims 1-2, wherein the wide bandgap semiconductor material is SiC.

13. The semiconductor device of claim 5, wherein the gate electrode of the gate structure is electrically connected to the first and second gate fingers at the intersection of the gate structure and the first or second gate finger.

14. The semiconductor device according to any one of claims 1-2, further comprising first bonding wires, wherein one end of each of the first bonding wires is attached to a corresponding one in the first bonding region, the first bonding wires extending along a third lateral direction aligned with the first lateral direction by an angular deviation of up to + / -20°.

15. The semiconductor device of claim 5, wherein the first gate line portion and the second gate line portion are portions of a continuous gate line that at least partially surrounds a transistor cell region comprising the gate structure, the continuous gate line being electrically coupled to a second junction region.

16. The semiconductor device of claim 5, wherein the gate electrode material of the gate structure is one or a combination of doped polycrystalline silicon and metal silicide.

17. The semiconductor device according to any one of claims 1-2, wherein the semiconductor device is a power semiconductor field-effect transistor configured to conduct current in the range of 1A to 60A for each of the first junction regions.

18. The semiconductor device according to any one of claims 1-2, wherein the semiconductor device is a vertical semiconductor transistor comprising a first load terminal and a control terminal on a first side of the semiconductor body and a second load terminal on a second side of the semiconductor body.

19. The semiconductor device according to any one of claims 1-2, wherein each of the first gate fingers extends parallel to a longitudinal direction of the first junction region, the longitudinal direction being the direction in which the first junction region extends to its maximum extent in any lateral direction.

20. The semiconductor device according to any one of claims 1-2, wherein the first junction region is disposed between the first gate line portion (106) and the second gate line portion (108) along the first lateral direction (x1).

21. The semiconductor device according to any one of claims 1-2, wherein the first lateral direction extends perpendicular to the second lateral direction.

22. The semiconductor device according to any one of claims 1-2, wherein the longitudinal direction of the first bonding region extends parallel to the first transverse direction.

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