Injection-locked frequency division circuit and control method

Abstract

This application discloses an injection-locked frequency divider circuit and its control method, relating to the field of circuit technology. The injection voltage is adjustable, which can expand the operating range of the frequency divider. The injection-locked frequency divider circuit includes: an orthogonal frequency divider, which generates an orthogonal differential signal based on an input differential clock signal; and a voltage injection module, which adjusts the injection voltage output to the orthogonal frequency divider according to a voltage adjustment command, wherein the voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to an injection-locked frequency divider circuit and its control method. Background Technology

[0002] The mixer in an orthogonal frequency converter transceiver requires a set of orthogonal differential signals. These orthogonal differential signals are used for frequency conversion. Typically, a divider is used to generate orthogonal differential signals based on the stable frequency signal generated by the RF phase-locked loop.

[0003] However, the existing injection-locked divider has a relatively narrow operating frequency range. Once the input signal frequency is higher or lower than the locked operating range, the divider will lose lock and the output frequency will no longer be 1 / 2 of the input frequency. Summary of the Invention

[0004] This application provides an injection-locked frequency divider circuit and control method, wherein the injection voltage is adjustable, which can expand the operating range of the frequency divider.

[0005] A first aspect of this application provides an injection-locked frequency divider circuit, comprising:

[0006] An orthogonal frequency divider, wherein the orthogonal frequency divider is used to generate an orthogonal differential signal based on the input differential clock signal;

[0007] A voltage injection module is provided, which is used to adjust the injection voltage output to the quadrature divider according to a voltage adjustment command, wherein the voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal.

[0008] In some embodiments, the voltage injection module includes:

[0009] Output unit, the output unit being used to output the injected voltage to the orthogonal frequency divider;

[0010] An adjustment unit is configured to adjust the current flowing through the output unit according to the voltage adjustment command, so as to adjust the injected voltage.

[0011] In some embodiments, the output unit includes a first MOSFET and a large resistor. The drain of the first MOSFET is electrically connected to the adjustment unit, the source of the first MOSFET is grounded, one end of the large resistor is electrically connected to the gate of the first MOSFET, and the voltage at the other end of the large resistor is the injection voltage.

[0012] In some embodiments, the regulating unit includes at least one fixed-on subunit and at least one current regulating subunit, the current regulating subunit being used to turn on or off according to the voltage regulating command.

[0013] In some embodiments, the current regulating subunit includes at least one regulating branch.

[0014] In some embodiments, the current regulating subunit includes at least two regulating branches, and all regulating branches within the same current regulating subunit are connected in parallel.

[0015] In some embodiments, the regulating branch includes a second MOSFET and a switch, wherein the second MOSFET is connected in series with the switch;

[0016] The switch is used to close or open according to the voltage regulation command to control the conduction or disconnection of the regulation branch.

[0017] In some embodiments, the injection-locked divider circuit further includes:

[0018] A current mirror module, which is electrically connected to the voltage injection module.

[0019] A second aspect of this application provides a control method for an injection-locked frequency divider circuit, comprising:

[0020] The voltage regulation command is determined based on the amplitude and frequency of the input differential clock signal;

[0021] Adjust the injection voltage according to the voltage adjustment command;

[0022] Based on the adjusted injection voltage, an orthogonal differential signal is generated.

[0023] In some implementations, before determining the voltage regulation command based on the amplitude and frequency of the input differential clock signal, the method further includes:

[0024] Plot the self-resonance sensitivity curve of the orthogonal frequency divider corresponding to each injected voltage output by the voltage injection module;

[0025] The step of determining the voltage adjustment command based on the amplitude and frequency of the input differential clock signal includes:

[0026] In the self-resonance sensitivity curve of the orthogonal divider, find the self-resonance frequency that is closest to the frequency of the differential clock signal at the amplitude of the input differential clock signal, and determine the injection voltage corresponding to the found self-resonance frequency as the target injection voltage;

[0027] The voltage regulation command is generated based on the target injection voltage.

[0028] The injection-locked divider circuit and control method provided in this application embodiment allow the voltage injection module to adjust the injection voltage output to the quadrature divider according to a voltage adjustment command. The voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal. This can be understood as the injection voltage input to the quadrature divider by the voltage injection module being adaptively adjusted based on the differential clock signal input to the quadrature divider. This ensures that the input differential clock signal always falls within the operating range of the quadrature divider, guaranteeing its normal operation and obtaining the corresponding quadrature differential output clock signal. Attached Figure Description

[0029] Figure 1 A schematic block diagram of an injection-locked frequency divider circuit provided in an embodiment of this application;

[0030] Figure 2 A schematic structural diagram of another injection-locked frequency divider circuit provided in an embodiment of this application;

[0031] Figure 3 A timing diagram of an orthogonal frequency divider provided in an embodiment of this application;

[0032] Figure 4 A self-resonance sensitivity curve of an orthogonal frequency divider is provided in an embodiment of this application;

[0033] Figure 5 A schematic flowchart illustrating a control method for an injection-locked frequency divider circuit provided in an embodiment of this application;

[0034] Figure 6 The self-resonance sensitivity curve of an orthogonal frequency divider corresponding to each injection voltage output by a voltage injection module is provided in an embodiment of this application. Detailed Implementation

[0035] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0036] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0037] The mixer in a quadrature frequency converter transceiver requires a set of quadrature differential signals for frequency conversion. These quadrature differential signals are typically generated by a frequency divider based on the stable frequency signal produced by the RF phase-locked loop. However, existing injection-locked frequency dividers have a relatively narrow operating frequency range. Once the input signal frequency is higher or lower than the locked operating range, the divider will lose lock, and the output frequency will no longer be half of the input frequency.

[0038] This application provides an injection-locked frequency divider circuit and control method, wherein the injection voltage is adjustable, which can expand the operating range of the frequency divider.

[0039] A first aspect of this application provides an injection-locked frequency divider circuit. Figure 1 This is a schematic block diagram of an injection-locked frequency divider circuit provided in an embodiment of this application. For example... Figure 1 As shown, the injection-locked divider circuit provided in this application includes: an orthogonal divider 100, which generates an orthogonal differential signal based on an input differential clock signal; and a voltage injection module 200, which adjusts the injection voltage Vinj output to the orthogonal divider 100 according to a voltage adjustment command, wherein the voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal.

[0040] For example, such as Figure 1As shown, the quadrature divider 100 is used to input a positive-phase clock signal LO+ and a negative-phase clock signal LO-. The positive-phase clock signal LO+ and the negative-phase clock signal LO- are differential clock signals with a phase difference of 180°. Under the action of the injected voltage Vinj, it can output a first positive-phase clock signal I+, a first negative-phase clock signal I-, a second positive-phase clock signal Q+, and a second negative-phase clock signal Q-. The first positive-phase clock signal I+ and the first negative-phase clock signal I- can be 180° out of phase, the second positive-phase clock signal Q+ and the second negative-phase clock signal Q- can be 180° out of phase, and the first positive-phase clock signal I+ and the second positive-phase clock signal Q+ can be 90° out of phase. Therefore, the first positive-phase clock signal I+, the first negative-phase clock signal I-, the second positive-phase clock signal Q+, and the second negative-phase clock signal Q- are quadrature differential signals. Existing injection-locked dividers have non-adjustable injection voltage. Therefore, once the input signal frequency is higher or lower than the locked operating range, the divider will lose lock, and the output frequency will no longer be half of the input frequency. The injection-locked divider circuit provided in this application embodiment allows the voltage injection module 200 to adjust the injection voltage Vinj output to the quadrature divider 100 according to a voltage adjustment command. The voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal. This can be understood as the injection voltage output by the voltage injection module 200 to the quadrature divider 100 being adaptively adjusted based on the differential clock signal input to the quadrature divider 100. This ensures that the input differential clock signal always falls within the operating range of the quadrature divider 100, guaranteeing its normal operation and obtaining the corresponding quadrature differential clock signal.

[0041] The injection-locked divider circuit provided in this application embodiment allows the voltage injection module 200 to adjust the injection voltage Vinj output to the quadrature divider 100 according to a voltage adjustment command. The voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal. This can be understood as the injection voltage output by the voltage injection module 200 to the quadrature divider 100 being adaptively adjusted based on the differential clock signal input to the quadrature divider 100. This ensures that the input differential clock signal always falls within the operating range of the quadrature divider 100, guaranteeing its normal operation and the generation of the corresponding quadrature differential signal.

[0042] In some embodiments, the voltage injection module 200 includes: an output unit for outputting an injection voltage to an orthogonal frequency divider; and an adjustment unit for adjusting the current flowing through the output unit according to a voltage adjustment command, so as to adjust the injection voltage.

[0043] For example, the output unit includes a first MOSFET and a large resistor. The drain of the first MOSFET is electrically connected to the adjustment unit, and the source of the first MOSFET is grounded. One end of the large resistor is electrically connected to the gate of the first MOSFET, and the voltage at the other end of the large resistor is the injection voltage. The adjustment unit may include an adjustable resistor. By adjusting the resistance value, the bias current supplied to the first MOSFET is adjusted, thereby changing the bias voltage of the first MOSFET and thus changing the gate voltage of the first MOSFET. If the resistance value of the large resistor is relatively large, it will not carry current, but only voltage.

[0044] The injection-locked divider circuit provided in this application embodiment includes an adjustment unit that adjusts the current flowing through the output unit according to a voltage adjustment command to adjust the injection voltage. The adjustment unit adjusts the injection voltage by regulating the current, making the injection voltage output by the voltage injection module 200 adjustable, thereby widening the operating range of the quadrature divider 100.

[0045] In some embodiments, the adjustment unit includes at least one fixed-on subunit and at least one current-regulating subunit. The current-regulating subunit is used to turn on or off according to a voltage adjustment command. The fixed-on subunit provides the basic current input to the voltage injection module 200, and the switching on and off of the current-regulating subunit can regulate the current flowing through the output unit, thereby regulating the injected voltage. The number of current-regulating subunits determines the adjustment level and range of the injected voltage of the voltage injection module 200.

[0046] In some implementations, the current regulating subunit includes at least one regulating branch. Where the current regulating subunit may include at least two regulating branches, all regulating branches within the same current regulating subunit are connected in parallel.

[0047] For example, Figure 2 A schematic structural diagram of another injection-locked divider circuit provided in an embodiment of this application. (See diagram below.) Figure 2As shown, the regulating branch includes a second MOSFET and a switch, with the second MOSFET connected in series with the switch. The switch is used to close or open according to a voltage regulation command to control the conduction or disconnection of the regulating branch. The fixed-on subunit may include a fourth PMOS transistor M4, with its source connected to the power supply voltage VDD and its drain connected to the output unit. The output unit includes a twelfth NMOS transistor M12 and a large resistor R1. The regulating branch may include a PMOS transistor and a switch, with the switch connected to the drain of the PMOS transistor. The current regulation subunit may include three subunits. One subunit may include one regulation branch, corresponding to the fifth PMOS transistor M5 and the first switch SW1. Another subunit may include two parallel regulation branches, corresponding to the second MOS transistors M6-7 (i.e., the sixth PMOS transistor M6 and the seventh PMOS transistor M7) and switches SW2-3 (i.e., the second switch SW2 and the third switch SW3). A third subunit may include four parallel regulation branches, corresponding to the second MOS transistors M8-11 (i.e., the eighth PMOS transistor M8, the ninth PMOS transistor M9, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11) and switches SW4-7 (i.e., the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7).

[0048] For example, in order to expand the adjustable range of the injection voltage of the voltage injection module 200, the channel width-to-length ratio of the fifth PMOS transistor M5, the sixth PMOS transistor M6, the seventh PMOS transistor M7, the eighth PMOS transistor M8, the ninth PMOS transistor M9, the tenth PMOS transistor M10 and the eleventh PMOS transistor M11 can be set to different values ​​so that the current values ​​flowing through different adjustment branches are different. This application embodiment does not make specific limitations.

[0049] Continue to refer to Figure 2 The quadrature frequency divider 100 includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 and the second capacitor C2 are used to retain the AC signal, and the injected voltage Vinj is used to provide the DC signal. The quadrature frequency divider 100 includes two latches. A latch consisting of the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth NMOS transistor M15, the sixteenth NMOS transistor M16, the seventeenth NMOS transistor M17, and the eighteenth NMOS transistor M18 is used to generate a set of quadrature differential signals; a latch consisting of the nineteenth PMOS transistor M19, the twentieth PMOS transistor M20, the twenty-first NMOS transistor M21, the twenty-second NMOS transistor M22, the twenty-third NMOS transistor M23, and the twenty-fourth NMOS transistor M24 can also generate a set of quadrature differential signals.

[0050] Continue to refer to Figure 2 The injection-locked divider circuit provided in this embodiment further includes a current mirror module 300, which is electrically connected to the voltage injection module 200. The current mirror module 300 includes a first NMOS transistor M1, a second NMOS transistor M2, and a third PMOS transistor M3. The input current Ib of the current mirror module 300 comes from a current reference circuit to provide a stable reference current. M1, M2, and M3 change the direction of the bias current output to provide a suitable direction of reference current output for the next-stage voltage injection module 200.

[0051] For example, continue to refer to Figure 2 The current regulation subunit has three components, and the voltage injection module 200 provides a 3-bit adjustable voltage injection circuit. The fourth PMOS transistor M4 is normally open. The voltage regulation command can control the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7. The voltage regulation command corresponds to a 3-bit binary code. The gate of the twelfth NMOS transistor M12 can generate an injection voltage Vinj, which is provided as an output injection voltage Vinj through a large resistor R1. The injection voltage Vinj can be input into the quadrature divider 100. The quadrature divider 100 adopts a latch structure with I-path and Q-path mutually coupled. Figure 3 This is a timing diagram of an orthogonal frequency divider provided in an embodiment of this application. Figure 3 As shown, the working principle of the quadrature divider 100 is as follows: It is assumed that all output logic remains unchanged until the edges of all input signals LO+ and LO- arrive. When LO+ is high, output signals I+ and I- are low; when LO- is high, output signals Q+ and Q- are low. At the rising edge of LO+, assuming I+ is initially high, M21 pulls Q+ low, while Q- cannot be high, otherwise, enabling M15 would cause I+ to be high, violating the initial assumption. Therefore, only one output signal is high at any given time. At the falling edge of LO-, Q- is pulled high, and I+ also becomes low. Based on the above analysis, the order in which the four output signals become high is I+, Q-, I-, Q+, and the duty cycle of the four output signals is 25%.

[0052] For example, Figure 4 The self-resonance sensitivity curve of an orthogonal frequency divider provided in an embodiment of this application is shown. Figure 4As shown, the horizontal axis represents the operating frequency of the quadrature divider (in GHz), and the vertical axis represents the amplitude (in V). f_max is the highest operating frequency of the quadrature divider. Near the self-resonant frequency f_osc, the quadrature divider requires only a very small amplitude to achieve frequency division, thus reducing the requirement for input amplitude. Figure 4 Only frequencies and amplitudes within the indicated operating range are sufficient for the quadrature divider to function properly. Generally, the operating frequency range of a second harmonic-injected locked quadrature divider is relatively limited, typically around 10% of the center frequency. If the input signal frequency is higher or lower than the locked range, the divider's output frequency will no longer be half the input frequency, and the divider will lose lock. This application's embodiment introduces a 3-bit adjustable injection voltage Vinj as the second harmonic injection signal, enabling the quadrature divider to achieve lock-in adjustment over a wider frequency range, thereby expanding the operating frequency range of the injection-locked quadrature divider.

[0053] A second aspect of this application provides a control method for an injection-locked frequency divider circuit. Figure 5 This is a schematic flowchart illustrating a control method for an injection-locked frequency divider circuit provided in an embodiment of this application.

[0054] like Figure 5 As shown in the embodiment of this application, the control method for the injection-locked frequency divider circuit includes:

[0055] S100: Determine the voltage adjustment command based on the amplitude and frequency of the input differential clock signal. The voltage adjustment command can be generated and issued by the injection-locked divider circuit through an external serially connected memory or controller; this embodiment does not impose specific limitations.

[0056] S200: Adjusts the injection voltage according to the voltage adjustment command. The voltage injection module can be adjusted according to the voltage adjustment command to generate the corresponding adjusted injection voltage.

[0057] S300: Generates an orthogonal differential signal based on the adjusted injection voltage. An orthogonal frequency divider can generate an orthogonal differential signal based on the adjusted injection voltage.

[0058] The injection-locked divider control method provided in this application allows the voltage injection module to adjust the injection voltage output to the quadrature divider according to a voltage adjustment command. The voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal. This can be understood as the injection voltage output by the voltage injection module to the quadrature divider being adaptively adjusted based on the differential clock signal input to the quadrature divider. This ensures that the input differential clock signal always falls within the operating range of the quadrature divider, guaranteeing its normal operation and obtaining the corresponding quadrature differential clock signal.

[0059] In some implementations, before step S100, the following steps are also included:

[0060] Plot the self-resonance sensitivity curve of the quadrature frequency divider corresponding to each injected voltage output by the voltage injection module; Figure 6 This application provides an embodiment of a voltage injection module that displays the self-resonance sensitivity curve of an orthogonal frequency divider corresponding to each injected voltage. For example... Figure 6 As shown, based on the adjustment range corresponding to the voltage injection module, each adjustment level can correspond to a self-resonance sensitivity curve of an orthogonal frequency divider. Figure 6 The voltage injection module shown has 5 adjustment levels, corresponding to 5 self-resonant sensitivity curves and 5 self-resonant frequencies, namely f1, fc1, fc2, fc3, and fc4.

[0061] Step S100 may include:

[0062] In the self-resonant sensitivity curve of the quadrature divider, find the self-resonant frequency that is closest to the frequency of the differential clock signal corresponding to the amplitude of the input differential clock signal. Determine the injection voltage corresponding to the found self-resonant frequency as the target injection voltage. First, based on the amplitude A0 of the input differential clock signal, confirm that the operating frequency range of the quadrature divider is f1-f2. Then, determine the self-resonant frequency that is closest to the frequency of the input differential clock signal. For example, if the self-resonant frequency closest to the frequency of the input differential clock signal is fc3, then adjust the injection voltage to the injection voltage corresponding to the self-resonant sensitivity curve with the self-resonant frequency fc3.

[0063] Based on the target injection voltage, a voltage regulation command is generated. For example, the self-resonant frequency is fc3, and the corresponding voltage injection module regulation scheme is that SW1 and SW2-3 are closed, SW4-7 is open, that is, the regulation branch where M5 is located and the regulation branch where M6-7 is located are connected, and the regulation branch where M8-M11 is located is disconnected.

[0064] The injection-locked divider control method provided in this application adjusts the injection voltage based on the amplitude and frequency of the input differential clock signal. This increases the operating range of the quadrature divider. The adjusted injection voltage makes the input differential clock signal of the quadrature divider closer to its self-resonant frequency, further reducing the phase noise of the injection-locked divider and improving the quality of the output quadrature differential signal. Additionally, it reduces the amplitude requirement of the input differential clock signal, enabling the quadrature divider to achieve locking adjustment.

[0065] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0066] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. An injection-locked frequency divider circuit, characterized in that, include: An orthogonal frequency divider, wherein the orthogonal frequency divider is used to generate an orthogonal differential signal based on the input differential clock signal; A voltage injection module is provided, which is used to adjust the injection voltage output to the quadrature frequency divider according to a voltage adjustment command, wherein the voltage adjustment command is determined based on the amplitude and frequency of the differential clock signal. The voltage injection module includes: Output unit, the output unit being used to output the injected voltage to the orthogonal frequency divider; An adjustment unit is configured to adjust the current flowing through the output unit according to the voltage adjustment command, so as to adjust the injected voltage; The adjustment unit includes at least one fixed conduction subunit and at least one current adjustment subunit. The current adjustment subunit is used to turn on or off according to the voltage adjustment command. The number of the current adjustment subunits is used to determine the adjustment level and adjustment range of the injection voltage of the voltage injection module.

2. The injection-locked frequency divider circuit according to claim 1, characterized in that, The output unit includes a first MOS transistor and a large resistor. The drain of the first MOS transistor is electrically connected to the adjustment unit, the source of the first MOS transistor is grounded, one end of the large resistor is electrically connected to the gate of the first MOS transistor, and the voltage at the other end of the large resistor is the injection voltage.

3. The injection-locked frequency divider circuit according to claim 1, characterized in that, The current regulation subunit includes at least one regulation branch.

4. The injection-locked frequency divider circuit according to claim 3, characterized in that, The current regulation subunit includes at least two regulation branches, and all regulation branches within the same current regulation subunit are connected in parallel.

5. The injection-locked frequency divider circuit according to claim 3, characterized in that, The regulating branch includes a second MOSFET and a switch, wherein the second MOSFET is connected in series with the switch; The switch is used to close or open according to the voltage regulation command to control the conduction or disconnection of the regulation branch.

6. The injection-locked frequency divider circuit according to claim 1, characterized in that, Also includes: A current mirror module, which is electrically connected to the voltage injection module.

7. A control method for an injection-locked frequency divider circuit, characterized in that, include: The voltage regulation command is determined based on the amplitude and frequency of the input differential clock signal; Adjust the injection voltage according to the voltage adjustment command; Based on the adjusted injection voltage, an orthogonal differential signal is generated.

8. The control method for the injection-locked frequency divider circuit according to claim 7, characterized in that, Before determining the voltage adjustment command based on the amplitude and frequency of the input differential clock signal, the method further includes: Plot the self-resonance sensitivity curve of the orthogonal frequency divider corresponding to each injected voltage output by the voltage injection module; The step of determining the voltage adjustment command based on the amplitude and frequency of the input differential clock signal includes: In the self-resonance sensitivity curve of the orthogonal divider, find the self-resonance frequency that is closest to the frequency of the differential clock signal at the amplitude of the input differential clock signal, and determine the injection voltage corresponding to the found self-resonance frequency as the target injection voltage; The voltage regulation command is generated based on the target injection voltage.

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