A digital locking system and a digital locking method

Abstract

The invention belongs to the technical field of nuclear magnetic resonance spectrometers and discloses a digital locking method. The method calculates the locking error frequency in the frequency domain, realizes accurate calculation of the locking error frequency when the locking signal is a single frequency or multi-frequency component, adopts a PID algorithm and a variable low-pass filter parameter to calculate the locking error data, and divides the error data into two parts, namely, coarse adjustment data and fine adjustment data, so that the locking frequency can be automatically corrected when it deviates from the target frequency by any distance, the locking feedback direction can be automatically switched, and can adapt to magnetic fields of various change rates, so as to realize fast and fully automatic locking.

Description

Technical Field

[0001] The present invention belongs to the technical field of nuclear magnetic resonance spectrometers, and more specifically, relates to a digital locking system and a digital locking method. Background Art

[0002] The nuclear magnetic resonance spectrometer emits a high-power pulse signal to the sample under test placed in a strong magnetic field to excite and receive the nuclear magnetic resonance signal of the sample under test. The frequency f of the nuclear magnetic resonance signal is proportional to the intensity of the magnetic field B0:

[0003]

[0004] Where γ is the gyromagnetic ratio of the nucleus and is the intrinsic coefficient of the nucleus.

[0005] The nuclear magnetic resonance spectrometer uses the frequency f to characterize the strength of the magnetic field B0.

[0006] When the NMR spectrometer detects the NMR signal of the sample, it is objectively required that the magnetic field strength B0 remain stable to ensure the consistency of the NMR signal obtained each time. However, the magnetic field provided by the magnet is actually affected by various factors such as ambient temperature, external moving objects, and magnetic attenuation, and is always in a state of slow drift. Modern NMR spectrometers use a lock field system to detect the current magnetic field strength (corresponding to the NMR signal frequency f Lock , referred to as the lock signal frequency f Lock ) and correct the error between it and the target magnetic field strength B0 (corresponding to the nuclear magnetic resonance signal frequency f0, referred to as the target frequency f0), so that the magnetic field strength B0 is at a constant value, that is, the lock field. At the same time, the lock field system needs to set the lock field switch (Lock On) to turn on or off the lock field process, and set the magnetic field hold switch (B0 Hold) to turn on or off the lock error update.

[0007] The main existing locking method is to control the transmission channel to output the excitation pulse and simulate the orthogonal receiving system to receive the locking signal frequency f Lock The down-conversion is two mutually orthogonal paths, and the frequencies are both locked error frequencies Δf = f Lock -f0 analog signal (lock real part signal and lock imaginary part signal), the lock imaginary part signal is sent to the analog PID circuit built by the operational amplifier for analog operation, the result of the operation is converted into current, and after the manual direction switch is switched, the Z0 shim coil is driven to form a magnetic field opposite to the magnetic field intensity error, thereby achieving the purpose of magnetic field intensity error correction. At the same time, the analog switch circuit is used in the PID circuit to realize the functions of the lock field switch (Lock On) and the magnetic field holding switch (B0 Hold).

[0008] However, the existing locking methods have some drawbacks that cannot be ignored:

[0009] 1. Use the imaginary part of the time domain lock signal to represent the lock error. When the lock signal frequency f Lock When the lock imaginary signal is not equal to the target frequency f0, the analog PID circuit cannot calculate the error feedback result and can only Lock Used when the frequency is equal to the target frequency f0;

[0010] 2. Use the imaginary part of the time domain lock signal to represent the lock error. When the lock signal frequency f Lock When there are multiple frequency components, multiple frequencies cannot be distinguished through time domain signals. The analog PID circuit calculates the signals of multiple frequency components at the same time, which is inaccurate or even impossible to calculate the error feedback result. It can only calculate the error feedback result at the lock signal frequency f. Lock Used for single frequency components;

[0011] 3. The feedback loop of the locking system is separated from the Z0 channel. When the locking signal frequency f Lock When the target frequency f0 is far away, the lock error has exceeded the adjustment capability of the lock field system. At this time, it is necessary to readjust the Z0 channel current to correct the offset magnetic field in large steps. However, the lock field system cannot control the Z0 channel and cannot automatically adjust the lock error that exceeds the range.

[0012] 4. The analog switch circuit is used in the feedback loop to realize the functions of the lock switch (Lock On) and the magnetic field holding switch (B0Hold). When the analog switch circuit is switched, an instantaneous impact voltage will be generated, causing the magnetic field to be disturbed, resulting in interference signals in the nuclear magnetic resonance signal being collected;

[0013] 5. Use a manual switch to switch the direction of the current formed by the lock error feedback. When the direction of the magnetic field formed by the lock error feedback is the same as the direction of the magnetic field drift, it is necessary to cut off the power and remove the circuit board and then manually switch the switch to switch the direction of the lock error feedback current. The operation is inconvenient and cannot achieve automated operation;

[0014] 6. The lock error feedback circuit is built by an analog PID circuit. The PID parameters are fixed and cannot be changed arbitrarily according to needs. The lock field adjustment capability is limited and cannot adapt to the lock field of magnetic fields with various change rates. Summary of the invention

[0015] In view of the above defects or improvement needs of the prior art, the present invention provides a digital locking system and a digital locking method, the purpose of which is to solve the above technical problems existing in the existing locking methods.

[0016] To achieve the above-mentioned purpose, according to one aspect of the present invention, a digital lock field system is provided, including a lock transceiver circuit, a lock preamplifier, a nuclear magnetic probe, and a Z0 shimming coil. The lock transceiver circuit is electrically connected to an external client, a lock transceiver circuit, a lock preamplifier, a nuclear magnetic probe, and a Z0 shimming coil through a communication interface. The nuclear magnetic probe and the Z0 shimming coil are arranged at the center of the main magnetic field. The lock transceiver circuit includes an FPGA controller, a lock transmitting channel, a lock receiving channel, and a Z0 current output module; the FPGA controller is electrically connected to the lock transmitting channel, the lock receiving channel, and the Z0 current output module; the Z0 current output module includes a first digital-to-analog converter, a second digital-to-analog converter, a first resistor, a second resistor, a third resistor, a fourth resistor, and a voltage-to-current conversion circuit; one end of the first digital-to-analog converter and one end of the second digital-to-analog converter are electrically connected to the FPGA controller, and the voltage-to-current conversion circuit is electrically connected to the Z0 shimming coil. One end of the first digital-to-analog converter is electrically connected to the FPGA controller, and one end of the second digital-to-analog converter is electrically connected to the FPGA controller. The other end of the first digital-to-analog converter is electrically connected to one end of the first resistor; the other end of the second digital-to-analog converter is electrically connected to one end of the second resistor; the other end of the first resistor, the other end of the second resistor, the input end of the voltage-to-current conversion circuit, and one end of the third resistor are electrically connected; the output end of the voltage-to-current conversion circuit is electrically connected to the other end of the third resistor and one end of the fourth resistor through the Z0 shim coil, and the other end of the fourth resistor is grounded.

[0017] According to another aspect of the present invention, a digital locking method is provided, which is applied in the above digital locking method, and the digital locking method comprises the following steps:

[0018] (1) Receive the digital lock system working parameters input by the user from the client, including the Z0 basic value D Z0 , lock center frequency f0, and set the operating frequencies of the lock transmitting channel and the lock receiving channel to the lock center frequency f0;

[0019] (2) Control the lock transmitting channel to output a transmitting pulse with a frequency of f0, thereby generating a lock signal, and control the lock receiving channel to receive the lock signal through the lock preamplifier, where the frequency of the lock signal is f Lock ;

[0020] (3) Control the ADC lock signal f of the lock receiving channel Lock Perform analog-to-digital conversion and convert the lock signal f Lock Performing digital orthogonal down-conversion processing, thereby obtaining real-part locking data and imaginary-part locking data respectively;

[0021] (4) performing sampling processing on the real part data and the imaginary part data obtained in step (3) to obtain sampled real part data and imaginary part data, respectively, and filtering the sampled real part data and the imaginary part data using a low-pass filtering algorithm to obtain filtered real part data and imaginary part data, respectively;

[0022] (5) performing fast Fourier transform on the filtered real part data and the imaginary part data to obtain a real part spectrum and an imaginary part spectrum, respectively, and adjusting the phase of the real part spectrum to 0°;

[0023] (6) Obtain the lock error frequency Δf corresponding to the locked part spectrum after the phase adjustment in step (5), and determine whether the lock error frequency Δf is less than the threshold value. If so, set the lock system to the locked state and enter step (7). Otherwise, set the lock system to the unlocked state and enter step (7);

[0025] (7) The locking error frequency Δf corresponding to the locking part spectrum is calculated using the PID algorithm and the calculation result is filtered using a low-pass filter to obtain the error data D Err , and the forward and reverse parameters and error data D Err Perform multiplication to obtain new error data D′ Err ;

[0026] (8) Determine the calculation result D′ obtained in step (7) Err Is it within the maximum lock error channel value range [-Max Err , Max Err ], if yes, go to step (9), otherwise, for Z0 basic value D Z0 and the new error data D′ Err Update to get the updated Z0 base value D′ Z0 and error data D″ Err , then go to step (10):

[0027] (9) Set the voltage control values ​​of the first digital-to-analog converter and the second digital-to-analog converter to Z0 base value D respectively. Z0 and the error data D′ obtained in step (7) Err , then go to step (11);

[0028] (10) The voltage control values ​​of the first digital-to-analog converter and the second digital-to-analog converter are respectively set to the Z0 base value D obtained in step (8) Z0 and error data D′ Err Or the updated Z0 base value D′ Z0 and error data D″ Err ;

[0029] (11) Repeat the above steps (2) to (10) until a lock termination command is received from the client, and the process ends.

[0030] Preferably, in step (2), the transmission pulse passes through the sequentially connected lock preamplifier and nuclear magnetic probe to excite the atomic nuclei used for locking in the main magnetic field, thereby generating a locking signal f Lock , the lock signal f Lock The frequency is proportional to the strength of the main magnetic field B0:

[0031]

[0032] where γ represents the gyromagnetic ratio of the nucleus used for locking the field.

[0033] Preferably, in step (3), the input data rate of the orthogonal down-conversion process is

[0034] ≤25Msps, the phases of the real part data and the imaginary part data are orthogonal to each other, and the frequencies of both are the lock error frequency Δf:

[0035] Δf=f Lock -f0

[0036] Preferably, in step (8), the Z0 base value D Z0 and the new error data D′ Err The update is specifically performed using the following formula:

[0037]

[0038] D" Err =D' Err %Max Err

[0039] Where k represents the ratio between the second resistor and the first resistor, k>100, the maximum lock error channel value Max Err The value is 2 15 .

[0040] Preferably, after step (9), the voltage V output by the first digital-to-analog converter is Z0 The output current I is converted from voltage to current by the voltage-current conversion circuit Z0 , current I Z0 Flows through the Z0 shim coil and forms a magnetic field B Z0 , current I Z0 With voltage V Z0 The relationship is:

[0041]

[0042] The second DAC output voltage VErr The output current I is converted from voltage to current by the voltage-current conversion circuit Err , current I Err Flows through the Z0 shim coil and forms a magnetic field B Err , current I Err With voltage V Err The relationship is:

[0043]

[0044] Where R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, R3 represents the resistance value of the third resistor, R s represents the resistance value of the fourth resistor;

[0045] Magnetic field B Err , magnetic field B Z0 It is superimposed on the main magnetic field to correct the drift of the main magnetic field.

[0046] Preferably, the method further comprises the following steps after step (5) and before step (6):

[0047] (5') Receive the lock signal Lock On from the client and determine whether the lock signal is valid. If it is valid, proceed to step (6). Otherwise, set the lock error frequency Δf corresponding to the lock part spectrum after phase adjustment in step (5) to zero, and repeat the above steps (2) to (5') until the lock field end command is received from the client. The process ends.

[0048] Preferably, the method further comprises the following steps after step (5) and before step (6):

[0049] (5") Receive the lock signal Lock On from the client and determine whether it is valid. If the lock signal is valid, receive the main magnetic field hold signal B0 Hold and determine whether the main magnetic field hold signal is valid. If the main magnetic field hold signal is valid, repeat the above steps (2) to (5"), otherwise proceed to step (6).

[0050] Preferably, in step (11), when a cycle process reaches step (7), it is necessary to determine whether the lock error frequency Δf obtained in the current cycle is greater than the lock error frequency Δf obtained in the previous cycle process. If so, when the next cycle reaches step (7), the forward and reverse parameters are inverted, otherwise continue to execute step (8).

[0051] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0052] (1) The present invention adopts steps (3) to (6), which transforms the time domain locking signal into a spectrum through fast Fourier transform FFT. The frequency of the locking signal can be directly obtained in the spectrum, and the difference between it and the target frequency (i.e., the locking error frequency) can be calculated. Therefore, it can solve the problem that the prior art locking system can only be used at the locking signal frequency f. Lock Technical issues when using the frequency equal to the target frequency f0;

[0053] (2) Since the present invention adopts steps (3) to (6), it can distinguish signals with multiple frequency components in the spectrum and obtain the frequency value of the specified frequency peak to calculate the difference between it and the target frequency (i.e., the lock error frequency). Therefore, it can solve the problem that the prior art lock system can only lock the signal frequency f. Lock Technical issues for use in the case of a single frequency component;

[0054] (3) The present invention adopts steps (8) to (10), which allocates the calculated lock error value as the Z0 base value D′ Z0 and error data D″ Err , and are used to control the first DAC and the second DAC of the Z0 channel respectively to achieve coarse and fine adjustment of the lock error, thereby solving the technical problem that the prior art lock field system cannot control the Z0 channel and cannot automatically adjust the lock error that exceeds the range;

[0055] (4) The present invention adopts step (5') to step (5"), and realizes the functions of the lock field switch (Lock On) and the magnetic field holding switch (B0 Hold) by conditional judgment in the process of lock error calculation. The change of the lock field data will not act on the shim coil and will not have any effect on the magnetic field. Therefore, it can solve the technical problem that when the analog switch circuit of the lock field system of the prior art is switched, an instantaneous impulse voltage is generated, causing the magnetic field to be disturbed, and causing interference signals to appear in the nuclear magnetic resonance signal being collected;

[0056] (5) The present invention adopts step (7) and step (11), which uses a digital method of multiplying the forward and reverse parameters by the lock error to control the direction of the lock error, and automatically adjusts the values ​​of the forward and reverse parameters according to the trend of the lock error change. The values ​​of the forward and reverse parameters can be directly switched in the digital domain, thereby solving the technical problem that the lock field system of the prior art needs to be powered off and the circuit board removed and then manually switched to switch the direction of the lock error feedback current, which is inconvenient to operate and cannot realize automated operation;

[0057] (6) Since the present invention adopts step (7), the effect of the lock error feedback is adjusted by the PID parameters in the PID operation. The PID value can be modified according to the change of external conditions or the lock field system automatically modifies the PID parameters to adapt to magnetic fields with various change rates. Therefore, it can solve the technical problems of the lock field system in the prior art that the PID parameters are fixed and cannot be changed arbitrarily according to needs, the lock field adjustment ability is limited, and the lock field cannot adapt to magnetic fields with various change rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a structural block diagram of the digital lock field system of the present invention;

[0059] Figure 2 It is a structural block diagram of the Z0 current output module in the digital lock field system of the present invention;

[0060] Figure 3 It is a flow chart of the digital locking method of the present invention;

[0061] Figure 4 It is a schematic diagram of the calculation of the locking error of the digital locking method of the present invention under a single frequency spectrum peak;

[0062] Figure 5 Schematic diagram of lock error calculation of the digital lock field method of the present invention under multi-frequency spectrum peaks. In all the drawings, the same reference numerals are used to represent the same elements or structures, wherein:

[0063] 1-external client, 2-lock transceiver circuit, 3-lock preamplifier, 4-nuclear magnetic field probe, 5-Z0 uniform field coil, 6-magnetic field, 21-FPGA controller, 22-lock transmission channel, 23-lock receiving channel, 24-Z0 current output module, 241-first DAC, 242-second DAC, 243-first resistor R1, 244-second resistor R2, 245-third resistor R3, 246-fourth resistor Rs, 247-voltage-current conversion circuit. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0065] The basic idea of ​​the present invention is to propose a digital locking method, to perform orthogonal down-conversion processing on the locking signal in the digital domain, and to convert the locking signal in the time domain into spectrum data, to realize accurate calculation of the locking error frequency in the frequency domain when the locking signal is a single frequency component or multiple frequency components, to calculate the locking error data using a PID algorithm and variable low-pass filter parameters, and to divide the error data into two parts, Z0 basic data and error feedback data, so that the locking frequency can be automatically corrected when it deviates far from the target frequency, the locking feedback direction can be automatically switched, and it can adapt to magnetic fields of various change rates to achieve fast and fully automatic locking.

[0066] like Figure 1 As shown, the digital lock field system includes a lock transceiver circuit 2, a lock preamplifier 3, a nuclear magnetic probe 4, and a Z0 shim coil 5. The lock transceiver circuit 2 is electrically connected to the external client 1, the lock transceiver circuit 2, the lock preamplifier 3, the nuclear magnetic probe 4, and the Z0 shim coil 5 through a communication interface, and the nuclear magnetic probe 4 and the Z0 shim coil 5 are arranged at the center of the main magnetic field 6.

[0067] In the present invention, the Z0 shim coil 5 is a shim coil that generates a magnetic field in the same direction as the main magnetic field.

[0068] The lock transceiver circuit 2 includes an FPGA controller 21, a lock transmitting channel 22, a lock receiving channel 23, and a Z0 current output module 24. The FPGA controller 21 is electrically connected to the lock transmitting channel 22, the lock receiving channel 23, and the Z0 current output module 24 respectively.

[0069] The FPGA controller 21 completes all circuit and functional module operations of the lock transceiver circuit 2 and is the control core of the lock system.

[0070] The specific circuit structure of the lock transmitting channel 22 and the lock receiving channel 23 has been disclosed in detail in the invention “A digital broadband lock field system and working method” submitted by the applicant on June 26, 2019, and will not be repeated here.

[0071] An analog-digital converter (ADC) at the end of the lock receiving channel 23 is electrically connected to the FPGA controller 21 .

[0072] like Figure 3 As shown, the Z0 current output module 24 includes a first digital-analog converter (DAC) 241 , a second DAC 242 , a first resistor 243 , a second resistor 244 , a third resistor 245 , a fourth resistor 246 , and a voltage-current (V / I) conversion circuit 247 .

[0073] The output voltage range of the first DAC 241 and the second DAC 242 is [-10V, +10V].

[0074] The resistance value of the first resistor 243 is 20KΩ, the resistance value of the second resistor 244 is 2.56MΩ, the resistance value of the third resistor 245 is 1KΩ, and the resistance value of the fourth resistor 246 is 10Ω.

[0075] One end of the first DAC 241 and one end of the second DAC 242 are electrically connected to the FPGA controller 21 , respectively, and the voltage-current conversion circuit 247 is electrically connected to the Z0 shim coil 5 .

[0076] One end of the first DAC 241 is electrically connected to the FPGA controller 21 , and one end of the second DAC 242 is electrically connected to the FPGA controller 21 .

[0077] The other end of the first DAC 241 is electrically connected to one end of the first resistor 243, the other end of the second DAC 242 is electrically connected to one end of the second resistor 244, the other end of the first resistor 243, the other end of the second resistor 244, the input end of the voltage-current conversion circuit 247 are electrically connected to one end of the third resistor 245, the output end of the voltage-current conversion circuit 247 is electrically connected to the other end of the third resistor 245 and one end of the fourth resistor 246 through the Z0 shim coil 5, and the other end of the fourth resistor 246 is grounded.

[0078] like Figure 4 As shown, the present invention provides a digital locking method, which is applied in the above-mentioned FPGA module 21, and the method comprises the following steps:

[0079] (1) Receive the digital lock system working parameters input by the user from the client, including the Z0 basic value D Z0 , lock center frequency f0, and set the operating frequencies of the lock transmitting channel 22 and the lock receiving channel 23 to the lock center frequency f0;

[0080] (2) Control the lock transmitting channel 22 to output a transmitting pulse with a frequency of f0, thereby generating a lock signal, and control the lock receiving channel 23 to receive the lock signal via the lock preamplifier 3, wherein the frequency of the lock signal is f Lock ;

[0081] Specifically, the transmission pulse passes through the sequentially connected lock preamplifier 3 and the nuclear magnetic resonance probe 4, and excites the atomic nuclei used for locking in the main magnetic field 6, thereby generating a nuclear magnetic resonance signal (i.e., the locking signal f Lock ), the lock signal f Lock The frequency is proportional to the strength B0 of the current main magnetic field 6:

[0082]

[0083] Where γ is the gyromagnetic ratio of the nucleus used for locking the field, and is the intrinsic coefficient of the nucleus.

[0084] Lock signal f Lock The frequency reflects the strength B0 of the main magnetic field 6.

[0085] (3) Control the ADC lock signal f of the lock receiving channel 23 Lock Perform analog-to-digital conversion and convert the lock signal f Lock Digital orthogonal down-conversion processing is performed to obtain real-part data and imaginary-part data, respectively. The phases of the real-part data and the imaginary-part data are orthogonal to each other, and the frequencies of both are the lock error frequency Δf:

[0086] Δf=f Lock -f0

[0087] The lock error frequency Δf reflects the frequency difference between the current main magnetic field strength B0 and the target magnetic field strength; the input data rate of the orthogonal down-conversion processing process is ≤25Msps.

[0088] (4) performing sampling processing on the real part data and the imaginary part data obtained in step (3) to obtain sampled real part data and imaginary part data, respectively, and filtering the sampled real part data and the imaginary part data using a low-pass filtering algorithm to obtain filtered real part data and imaginary part data, respectively;

[0089] Specifically, the data rate of the real part data and the imaginary part data obtained after sampling processing is

[0090] ≤10Ksps; the effective bandwidth of the low-pass filtering process is ≤10KHz.

[0091] The advantages of the above steps (3) and (4) are that the real part data and the imaginary part data are obtained by using the method of digital orthogonal down-conversion and digital low-pass filter, and the data rate and effective bandwidth of the real part data and the imaginary part data can be flexibly adjusted according to needs. When the lock error frequency Δf is close to 0, the data rate and the effective bandwidth can be reduced. When the lock error frequency Δf is large, the data rate and the effective bandwidth can be increased to increase the lock error detection range of the lock field system.

[0092] (5) performing fast Fourier transform (FFT) on the filtered real part data and the imaginary part data to obtain a real part spectrum and an imaginary part spectrum, respectively, and adjusting the phase of the real part spectrum to 0°;

[0093] Specifically, the process of adjusting the spectrum phase has been disclosed in detail in the invention “An automatic phase correction method” filed on November 24, 2011, and will not be repeated here.

[0094] (6) Obtain the lock error frequency Δf corresponding to the locked part spectrum after the phase adjustment in step (5), and determine whether the lock error frequency Δf is less than the threshold value. If so, set the lock system to the locked state and enter step (7). Otherwise, set the lock system to the unlocked state and enter step (7);

[0096] Specifically, the threshold value range is [-0.1 Hz, 0.1 Hz], preferably -0.1 Hz or 0.1 Hz;

[0097] The lock error frequency Δf is calculated according to the number of spectrum peaks of the real part of the lock spectrum:

[0098] like Figure 4 As shown in FIG. 1 , when the locked real part spectrum is a single spectrum peak, the calculation process of the locking error frequency Δf is specifically as follows:

[0099] A. Set the frequency at the center of the spectrum to 0;

[0100] B. Find the maximum spectrum peak in the spectrum diagram and obtain the frequency corresponding to the spectrum peak, which is recorded as the lock error frequency Δf.

[0101] like Figure 5 As shown in FIG. 1 , when the locked part spectrum is a multi-spectral peak, the calculation process of the locking error frequency Δf is specifically as follows:

[0102] A. Set the frequency at the center of the spectrum to 0;

[0103] B. The user specifies a spectrum peak in the spectrum diagram as the lock signal peak;

[0104] C. If the user does not specify the lock signal peak, the spectrum peak with the largest peak value in the spectrum graph is automatically found as the lock signal peak;

[0105] D. Obtain the frequency corresponding to the lock signal peak selected in steps b) and c), and record it as the lock error frequency Δf.

[0106] The advantages of the above steps (5) and (6) are that the lock error signal in the time domain is transformed into a spectrum by fast Fourier transform FFT, the frequency of the single frequency component lock signal can be directly obtained in the spectrum, and the signals of multiple frequency components can be distinguished in the spectrum to obtain the frequency value of any specified spectrum peak, and the lock error frequency Δf is calculated using a single spectrum peak or a specified spectrum peak. The calculation of the lock error frequency in the frequency domain is no longer limited by the offset distance between the lock signal frequency and the target frequency, nor is it limited by the number of frequency components of the lock signal.

[0107] (7) The locking error frequency Δf corresponding to the locking part spectrum is calculated using the PID algorithm and the calculation result is filtered using a low-pass filter to obtain the error data D Err , and the forward and reverse parameters and error data D Err Perform multiplication to obtain new error data D′ Err ;

[0108] Specifically, the forward and reverse parameters are +1 or -1. If the forward and reverse parameters are -1, the new error data D′ Err Yes-D Err When the drift rate of the main magnetic field 6 changes, the parameters of the PID and the passband frequency of the low-pass filter are adjusted to adjust the amplitude and rate of the feedback to achieve a rapid response to the change of the main magnetic field 6.

[0109] The advantage of step (7) is that the digital PID method is used to calculate the lock error data, and the PID parameters can be adjusted in real time according to the change of the lock error frequency Δf, and the adjustment range is not limited, so that the lock field system can adapt to the lock field of the magnet under various changes. The digital forward and reverse parameter adjustment replaces the manual switching of the analog switch, which is flexible and saves the device cost.

[0110] (8) Determine the calculation result D′ obtained in step (7) Err Is it within the maximum lock error channel value range [-Max Err , Max Err ], if yes, go to step (9), otherwise, for Z0 basic value D Z0 and the new error data D′ Err Update to get the updated Z0 base value D′ Z0 and error data D″ Err , then go to step (10):

[0111]

[0112] D" Err =D' Err %Max Err

[0113] Where k represents the ratio between the second resistor 244 and the first resistor 243, k>100, the maximum lock error channel value Max Err The value is 2 15 .

[0114] The Z0 basic value D′0 consists of two parts: Z0 basic value D Z0 And lock error data D' Err Exceeding the maximum value Max ErrThe Z0 base value D′0 can be used to adjust the center frequency position of the main magnetic field 6, and is also used for automatically coarsely adjusting the center frequency position of the main magnetic field 6 by the locking method when the locking error is large.

[0115] (9) The input values ​​(i.e., voltage control values) of the first DAC 241 and the second DAC 242 are respectively set to the Z0 base value D Z0 and the lock error data D' obtained in step (7) Err , then go to step (11):

[0116] (10) The input values ​​(i.e., voltage control values) of the first DAC 241 and the second DAC 242 are respectively set to the Z0 base value D′ updated in step (8) Z0 and error data D″ Err .

[0117] After step (9) and step (10), the output voltages of the first DAC 241 and the second DAC 242 are converted into currents in the Z0 current output module 24, and a correction magnetic field having a drift direction opposite to that of the main magnetic field 6 and a drift magnitude equal to that of the main magnetic field 6 is formed in the Z0 shim coil 5.

[0118] Specifically, the voltage V output by the first DAC 241 is Z0 The output current I is passed through the voltage-current conversion circuit 247 Z0 , current I Z0 Flows through Z0 shim coil 5 and forms B Z0 Magnetic field, current I Z0 With voltage V Z0 The relationship is:

[0119]

[0120] The voltage V output by the second DAC 242 Err The output current I is passed through the voltage-current conversion circuit 247 Err , current I Err Flows through Z0 shim coil 5 and forms B Err Magnetic field, current I Err With voltage V Err The relationship is:

[0121]

[0122] B Err Magnetic field, B Z0 The magnetic field is superimposed on the main magnetic field 6 to correct the drift of the main magnetic field 6 and keep the main magnetic field 6 stable.

[0123] Specifically, the first resistor R1 and the second resistor R2 have the following relationship:

[0124] R2=k·R1,k>100

[0125] The B formed by the first resistor R1 Z0 The maximum range of the magnetic field is B formed by the second resistor R2 Err The magnetic field is k times, and the B formed by the second resistor R2 Err The adjustment accuracy is B formed by the first resistor R1 Z0 k times the adjustment accuracy of the magnetic field, B Z0 The magnetic field is used to roughly adjust the drift of the main magnetic field 6, B Err The magnetic field is used to fine-tune the drift of the main magnetic field 6 .

[0126] The advantage of the above steps (8), (9) and (10) is that the lock error data is further subdivided into two parts: Z0 base value D′ Z0 and error data D″ Err , and act on the first DAC 241 for coarse adjustment and the second DAC 242 for fine adjustment respectively, the adjustment range of the lock error is extended to the sum of the maximum coarse adjustment range and the maximum fine adjustment range, so that the lock field system meets the use requirements when the lock signal frequency deviates far from the target frequency.

[0127] (11) Repeat the above steps (2) to (10) until a lock termination command is received from the client, and the process ends.

[0128] After one cycle is completed, it is necessary to determine whether the lock error frequency Δf obtained in the current cycle is greater than the lock error frequency Δf obtained in the previous cycle. If so, when the next cycle is executed to step (7), the forward and reverse parameters are inverted.

[0129] The advantage of step (11) is that the locking process of stimulating the locking signal, receiving the locking signal, calculating the locking error, and correcting the locking error forms a continuously iterative cycle, which can continuously correct the locking error during the operation of the nuclear magnetic resonance spectrometer, so that the magnetic field remains stable during the locking process. During the cycle, the change trend of the locking error frequency Δf is continuously monitored and used to automatically adjust the forward and reverse parameters, thereby realizing the parameter automation of the locking system.

[0130] As a further preferred embodiment, the locking method of the present invention further comprises the following steps after step (5) and before step (6):

[0131] (5') Receive a lock (Lock On) signal from the client and determine whether the lock signal is valid. If it is valid, proceed to step (6). Otherwise, set the lock error frequency Δf corresponding to the lock part spectrum after phase adjustment in step (5) to zero, and repeat the above steps (2) to (5') until a lock field end command is received from the client, and the process ends.

[0132] As a further preferred embodiment, the locking method of the present invention further comprises the following steps after step (5) and before step (6):

[0133] (5") receiving a lock (Lock On) signal from the client and determining whether it is valid. If the lock signal is valid, receiving a main magnetic field hold (B0 Hold) signal and determining whether the main magnetic field hold signal is valid. If the main magnetic field hold signal is valid, repeating the above steps (2) to (5"), otherwise proceeding to step (6);

[0134] If the lock (Lock On) signal is invalid, the lock error frequency Δf corresponding to the locked part spectrum after phase adjustment in step (5) is set to zero, and the above steps (2) to (5) are repeated until a lock field end command is received from the client, and the process ends.

[0135] When the main magnetic field hold (B0 Hold) signal is valid, the lock error frequency Δf, the voltage output by the first DAC 241 and the voltage output by the second DAC 242 will remain unchanged before the main magnetic field hold (B0 Hold) signal is valid to avoid the influence of intentionally applied magnetic field fluctuations.

[0136] The advantages of the above steps (5') and (5") are that the value of the lock feedback is switched in the digital domain, and the switching of the lock (LockOn) and main magnetic field hold (B0 Hold) signals will not have any impact on the main magnetic field, thus avoiding the damage to the validity of the nuclear magnetic test data caused by the fluctuation of the main magnetic field.

[0137] In summary, the digital locking method of the present invention can realize accurate calculation of the locking error signal when it is single frequency and multi-frequency. In the case of multi-frequency, a certain spectrum peak can be automatically selected or specified as the locking target frequency. When the locking frequency deviates far from the center frequency, it can be automatically corrected. The feedback direction can be automatically controlled. The locking error feedback method based on PID and variable low-pass filter parameters enables the system to adapt to magnetic fields of various change rates and realize fast and fully automatic locking.

[0138] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital lock field method is applied in a digital lock field system, wherein the digital lock field system comprises a lock transceiver circuit, a lock preamplifier, a nuclear magnetic probe, and a Z0 shim coil, wherein the lock transceiver circuit is electrically connected to an external client, a lock preamplifier, a nuclear magnetic probe, and a Z0 shim coil through a communication interface, respectively, wherein the nuclear magnetic probe and the Z0 shim coil are arranged at the center of the main magnetic field, and the lock transceiver circuit comprises an FPGA controller, a lock transmitting channel, a lock receiving channel, and a Z0 current output module; the FPGA controller is electrically connected to the lock transmitting channel, the lock receiving channel, and the Z0 current output module respectively; the Z0 current output module comprises a first digital-to-analog converter, a second digital-to-analog converter, a first resistor, a second resistor, a third resistor, a fourth resistor, a voltage-current conversion circuit; one end of the first digital-to-analog converter and one end of the second digital-to-analog converter are electrically connected to the FPGA controller respectively, and the voltage-to-current conversion circuit is electrically connected to the Z0 shim coil; one end of the first digital-to-analog converter is electrically connected to the FPGA controller, and one end of the second digital-to-analog converter is electrically connected to the FPGA controller; the other end of the first digital-to-analog converter is electrically connected to one end of the first resistor; the other end of the second digital-to-analog converter is electrically connected to one end of the second resistor; the other end of the first resistor, the other end of the second resistor, and the input end of the voltage-to-current conversion circuit are electrically connected to one end of the third resistor; the output end of the voltage-to-current conversion circuit is electrically connected to the other end of the third resistor and one end of the fourth resistor through the Z0 shim coil, and the other end of the fourth resistor is grounded, characterized in that The digital locking method comprises the following steps: (1) Receive the digital lock system working parameters input by the user from the client, including the Z0 basic value D Z0 , lock center frequency f0, and set the operating frequencies of the lock transmitting channel and the lock receiving channel to the lock center frequency f0; (2) Control the lock transmitting channel to output a transmitting pulse with a frequency of f0, thereby generating a lock signal, and control the lock receiving channel to receive the lock signal through the lock preamplifier, where the frequency of the lock signal is f Lock ; (3) Control the ADC lock signal f of the lock receiving channel Lock Perform analog-to-digital conversion and convert the lock signal f Lock Performing digital orthogonal down-conversion processing, thereby obtaining real-part locking data and imaginary-part locking data respectively; (4) performing sampling processing on the real part data and the imaginary part data obtained in step (3) to obtain sampled real part data and imaginary part data, respectively, and filtering the sampled real part data and the imaginary part data using a low-pass filtering algorithm to obtain filtered real part data and imaginary part data, respectively; (5) performing fast Fourier transform on the filtered real part data and the imaginary part data to obtain a real part spectrum and an imaginary part spectrum, respectively, and adjusting the phase of the real part spectrum to 0°; (6) obtaining the lock error frequency Δf corresponding to the lock real part spectrum after the phase adjustment in step (5), and determining whether the lock error frequency Δf is less than a threshold value; if so, setting the lock field system to a locked state and proceeding to step (7); otherwise, setting the lock field system to an unlocked state and proceeding to step (7); (7) The locking error frequency Δf corresponding to the locking part spectrum is calculated using the PID algorithm and the calculation result is filtered using a low-pass filter to obtain the error data D Err , and the forward and reverse parameters and error data D Err Perform multiplication to obtain new error data D′ Err ; (8) Determine the calculation result D′ obtained in step (7) Err Is it within the maximum lock error channel value range [-Max Err , Max Err ], if yes, go to step (9), otherwise, for Z0 basic value D Z0 and the new error data D′ Err Update to get the updated Z0 base value D′ Z0 and error data D″ Err , then go to step (10); (9) Set the voltage control values ​​of the first digital-to-analog converter and the second digital-to-analog converter to Z0 base value D respectively. Z0 And the calculation result D′ obtained in step (7) Err , then go to step (11); (10) The voltage control values ​​of the first digital-to-analog converter and the second digital-to-analog converter are respectively set to the Z0 base value D′ updated in step (8) Z0 and error data D″ Err ; (11) Repeat the above steps (2) to (10) until a lock termination command is received from the client, and the process ends.

2. The digital locking method according to claim 1, characterized in that: In step (2), the transmission pulse passes through the sequentially connected lock preamplifier and nuclear magnetic probe, and excites the atomic nuclei used for locking in the main magnetic field, thereby generating a locking signal f Lock , the lock signal f Lock The frequency is proportional to the strength of the main magnetic field B0: where γ represents the gyromagnetic ratio of the nucleus used for locking the field.

3. The digital locking method according to claim 1, characterized in that: In step (3), the input data rate of the orthogonal down-conversion process is ≤25Msps, the phases of the real part data and the imaginary part data are orthogonal to each other, and the frequencies of both are the lock error frequency Δf: Δf=f Lock -f0。 4. The digital locking method according to claim 1, characterized in that: In step (8), the base value D of Z0 Z0 and the new error data D′ Err The update is specifically performed using the following formula: D" Err =D' Err %Max Err Where k represents the ratio between the second resistor and the first resistor, k>100, the maximum lock error channel value Max Err The value is 2 15 .

5. The digital locking method according to claim 1, characterized in that: The method further comprises the following steps after step (5) and before step (6): (5') Receive the lock signal Lock On from the client and determine whether the lock signal is valid. If it is valid, proceed to step (6). Otherwise, set the lock error frequency Δf corresponding to the lock part spectrum after phase adjustment in step (5) to zero, and repeat the above steps (2) to (5') until the lock field end command is received from the client. The process ends.

6. The digital locking method according to claim 5, characterized in that: The method further comprises the following steps after step (5) and before step (6): (5") Receive the lock signal Lock On from the client and determine whether it is valid. If the lock signal is valid, receive the main magnetic field hold signal B0 Hold and determine whether the main magnetic field hold signal is valid. If the main magnetic field hold signal is valid, repeat the above steps (2) to (5"), otherwise proceed to step (6).

7. The digital locking method according to claim 1, characterized in that: In step (11), when a cycle process reaches step (7), it is necessary to determine whether the lock error frequency Δf obtained in the current cycle is greater than the lock error frequency Δf obtained in the previous cycle process. If so, when the next cycle reaches step (7), the forward and reverse parameters are inverted, otherwise continue to execute step (8).

Images