A buried barrier metal foil

Abstract

The present invention relates to the field of printed circuit board technology, and discloses a buried metal foil comprising a dielectric layer, a first barrier layer, and a buried metal foil body. The buried metal foil body comprises a resistor layer and a conductive layer. The first barrier layer is disposed between the dielectric layer and the resistor layer, and the conductive layer is plated on a side of the resistor layer away from the first barrier layer. The resistance tolerance per unit area at any point on the resistor layer is within a range of -10% to 10%. The buried metal foil is formed without the need to press-fit copper foil to the resistor layer, thereby avoiding the problem of varying resistance per unit area of the resistor layer in various directions due to pressing copper foil with uneven surface roughness to the resistor layer, and reducing the variation in resistance per unit area of the resistor layer in various directions. The first barrier layer isolates the dielectric layer from the resistor layer, preventing direct contact between the dielectric layer and the resistor layer, and preventing the dielectric layer from entering the resistor layer, thereby preventing the dielectric layer from affecting the performance of the resistor layer in circuit transmission.

Description

Technical Field

[0001] The invention relates to the technical field of printed circuit boards, in particular to a buried barrier metal foil. Background Art

[0002] With the development trend of miniaturization of electronic products, higher requirements are placed on the packaging density and volume of electronic products. Embedding passive components such as resistors in printed circuit boards is an effective means to reduce the size of electronic products.

[0003] Currently, existing printed circuit boards with embedded resistors typically consist of a resistor layer and a copper foil layer. The copper foil layer is typically made from pre-made copper foil and laminated to the resistor layer. Embedded resistors typically require a support. If the support is coated with glue, the glue directly contacts the resistor layer, potentially creating pinholes in the resistor layer. Even if the pinholes are small enough, the glue can seep into them, affecting the performance of the resistor layer. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a buried metal foil that can protect a resistor layer and improve the circuit performance of the resistor layer.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a buried barrier metal foil, comprising a dielectric layer, a first barrier layer and a buried barrier metal foil body, wherein the buried barrier metal foil body comprises a resistor layer and a conductive layer, the first barrier layer is arranged between the dielectric layer and the resistor layer, the conductive layer is plated on a side of the resistor layer away from the first barrier layer, and the resistance tolerance within a preset unit area at any point on the resistor layer is within the range of -10% to 10%.

[0006] As a preferred solution, the buried metal foil further includes a plurality of conductive protrusions;

[0007] The plurality of conductive protrusions are distributed at intervals on a side of the resistor layer away from the first barrier layer, and the plurality of conductive protrusions are covered by the conductive layer.

[0008] As a preferred solution, the plurality of conductive protrusions are first metal particles and / or particle clusters composed of a plurality of second metal particles.

[0009] As a preferred solution, the buried barrier metal foil further includes a carrier layer, and the carrier layer is provided on a side of the dielectric layer away from the first barrier layer.

[0010] As a preferred embodiment, the first barrier layer includes a high temperature resistant layer and a metal bonding layer stacked together;

[0011] The metal bonding layer is arranged between the high temperature resistant layer and the resistance layer.

[0012] As a preferred solution, the high temperature resistant layer is an organic high temperature resistant layer; or,

[0013] The high temperature resistant layer includes any one or more of tungsten, chromium, zirconium, titanium, nickel, molybdenum, cobalt and graphite.

[0014] As a preferred solution, the high temperature resistant layer is a single-layer alloy structure, a multi-layer structure consisting of a single metal layer, or a multi-layer structure consisting of an alloy layer and a single metal layer.

[0015] As a preferred solution, the metal bonding layer includes any one or more of copper, zinc, nickel, iron and manganese.

[0016] As a preferred solution, the thickness of the conductive layer is 2 microns to 20 microns.

[0017] As a preferred solution, the conductive layer includes any one or more of aluminum, silver, copper, and gold.

[0018] As a preferred solution, the conductivity of the conductive layer is 2-1000 times that of the resistance layer.

[0019] As a preferred solution, the resistance layer includes any one metal of nickel, chromium, platinum, palladium, and titanium, or an alloy of at least two of nickel, chromium, platinum, palladium, titanium, and silicon.

[0020] As a preferred solution, the buried metal foil further includes a second barrier layer, and the second barrier layer is provided between the resistance layer and the conductive layer.

[0021] Compared to the prior art, the buried metal foil provided in the embodiments of the present invention includes a dielectric layer, a first barrier layer, and a buried metal foil body. The buried metal foil body includes a resistor layer and a conductive layer. The first barrier layer is disposed between the dielectric layer and the resistor layer, and the conductive layer is plated on the side of the resistor layer away from the first barrier layer. The resistance tolerance per unit area at any point on the resistor layer is within a range of -10% to 10%. By disposing the first barrier layer between the dielectric layer and the resistor layer, the dielectric layer and the resistor layer are effectively isolated, avoiding direct contact between the dielectric layer and the resistor layer, preventing the dielectric layer from entering the resistor layer, and thus preventing the dielectric layer from affecting the resistor layer's circuit transmission performance. Moreover, by plating the conductive layer on the side of the resistor layer away from the first barrier layer, it is no longer necessary to press a finished copper foil onto the resistor layer to form a buried metal foil. This effectively avoids the problem in the prior art of directly pressing a copper foil with uneven surface roughness onto the resistor layer, which results in uneven surface roughness of the resistor layer and consequently different resistance values per unit area in all directions of the resistor layer. This reduces the difference in resistance values per unit area in all directions of the resistor layer, and facilitates the design of high-precision buried resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a schematic structural diagram of the buried barrier metal foil provided in Example 1 of the present invention;

[0023] Figure 2 1 is a schematic structural diagram of a buried barrier metal foil with a carrier layer provided in Example 1 of the present invention;

[0024] Figure 3 1 is a schematic structural diagram of a buried barrier metal foil including conductive protrusions provided in a first embodiment of the present invention;

[0025] Figure 4 Schematic diagram of the structure of the buried barrier metal foil provided in the second embodiment of the present invention;

[0026] Figure 5 Schematic diagram of the structure of the buried barrier metal foil provided in the third embodiment of the present invention;

[0027] Figure 6 It is a schematic flow chart of the method for preparing the buried barrier metal foil provided in the fourth embodiment of the present invention.

[0028] Among them, 1. carrier layer; 2. first barrier layer; 21. high temperature resistant layer; 22. metal bonding layer; 3. buried metal foil body; 31. resistor layer; 32. conductive layer; 4. dielectric layer; 5. second barrier layer; 6. conductive protrusion. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] Example 1

[0031] See also Figure 1 , is a schematic structural diagram of the buried barrier metal foil provided in Example 1 of the present invention.

[0032] In an embodiment of the present invention, the buried barrier metal foil includes a dielectric layer 4, a first barrier layer 2 and a buried barrier metal foil body 3. The buried barrier metal foil body 3 includes a resistor layer 31 and a conductive layer 32. The first barrier layer 2 is arranged between the dielectric layer 4 and the resistor layer 31. The conductive layer 32 is plated on the side of the resistor layer 31 away from the first barrier layer 2. The resistance tolerance within a preset unit area at any point on the resistor layer 31 is within the range of -10% to 10%.

[0033] During the implementation of the present invention, the inventors discovered that pinholes may form in the resistor layer during the manufacturing process. Without a barrier layer, the dielectric layer can easily enter the pinholes, thereby affecting the circuit performance of the resistor layer. However, in the present embodiment, by placing the first barrier layer 2 between the dielectric layer 4 and the resistor layer 31, the dielectric layer 4 and the resistor layer 31 are effectively isolated, preventing direct contact between the dielectric layer 4 and the resistor layer 31, thereby preventing the dielectric layer 4 from entering the resistor layer 31 and thus preventing the dielectric layer 4 from affecting the circuit transmission performance of the resistor layer 31. Furthermore, in the present embodiment, by coating the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2, it is no longer necessary to form a buried resistor metal foil by laminating a finished copper foil with the resistor layer. This effectively avoids the problem of uneven surface roughness of the resistor layer caused by directly laminating a copper foil with uneven surface roughness with the resistor layer in the prior art, which results in different resistance values per unit area in different directions of the resistor layer. This reduces the resistance value per unit area of the resistor layer 31 in different directions, thereby facilitating the design of high-precision buried resistors.

[0034] See also Figure 2 As shown, in an optional embodiment, the buried barrier metal foil further includes a carrier layer 1 , and the carrier layer 1 is provided on a side of the dielectric layer 4 away from the first barrier layer 2 .

[0035] During the implementation of the present invention, the inventors discovered that when preparing a printed circuit board, the buried metal foil needs to be pressed onto the printed circuit board body. However, since pressing must be performed under high temperature conditions, if the carrier layer and the resistor layer are in direct contact, the carrier layer and the resistor layer are prone to mutual diffusion under high temperature conditions, resulting in adhesion between the carrier layer and the resistor layer, making it difficult to peel them off. This, in turn, causes a large number of pinholes to appear in the resistor layer when the carrier layer is peeled off from the resistor layer, further exacerbating the directionality of the resistance value of the resistor layer. The present invention effectively avoids the problem of adhesion caused by mutual diffusion between the carrier layer 1 and the resistor layer 31 at high temperatures by arranging the first barrier layer 2 between the carrier layer 1 and the resistor layer 31. This makes it easier to peel the carrier layer 1 from the resistor layer 31, further reducing the difference in resistance per unit area of the resistor layer 31 in all directions, and further facilitating the design of high-precision buried resistors.

[0036] In an embodiment of the present invention, the resistance tolerance within a preset unit area at any location on the resistor layer 31 is within a range of -10% to 10%. The preset unit area can be, for example, 1cm*1cm, or other unit areas can be selected based on actual requirements. The resistance tolerance is calculated by obtaining the resistance values (R1, R2, R3, ..., Rn) of the preset unit areas at multiple different locations, calculating the average value Rv of the multiple resistance values, Rv = (R1 + R2 + R3 + ... + Rn) / n, then calculating the difference between each resistance value and the average value, dividing the difference by the average value, and then converting the percentage to obtain the resistance tolerance, that is, D1 = {(R1-Rv) / Rv}%, D2 = {(R2-Rv) / Rv}%, ..., D1 and D2 respectively represent the resistance tolerance corresponding to the resistance values at different locations, and both D1 and D2 fall within the range of -10% to +10%. The resistance tolerance range indicates that the resistance within a preset unit area at any location falls within the resistance tolerance range. Preferably, the resistance tolerance within a preset unit area at any location on the resistor layer 31 is within a range of -7% to +7%, and more preferably, within a range of -5% to +5%, to facilitate the design of high-precision buried resistors.

[0037] In an embodiment of the present invention, the carrier layer 1 is preferably, but not limited to, made of materials such as polyimide (PI) or polyethylene terephthalate (PET). In addition, the thickness of the carrier layer 1 of this embodiment can be set according to actual use requirements, and no further details are given here. Specifically, the dielectric layer 4 is a peeling layer or a stripping agent, and the thickness of the dielectric layer 4 is 10 angstroms to 100 angstroms. Of course, the thickness of the dielectric layer 4 can also be set to other values according to actual use requirements, and no further details are given here. By arranging the dielectric layer 4 between the carrier layer 1 and the resistor layer 31, the carrier layer 1 and the resistor layer 31 have good peeling strength, that is, the carrier layer 1 is not easy to fall off, and when the buried metal foil is used later, the carrier layer 1 can also be well peeled off from the resistor layer 31.

[0038] See also Figure 3As shown, in an optional embodiment, the buried metal foil further includes a plurality of conductive protrusions 6; the plurality of conductive protrusions 6 are spaced apart on the side of the resistor layer 31 away from the first barrier layer 2, and the plurality of conductive protrusions 6 are covered by the conductive layer 32. By plating the conductive layer 32 on the side of the resistor layer 31 where the conductive protrusions 6 are provided, thereby covering the resistor layer 31 and the conductive protrusions 6, the problem of uneven resistance values per unit area of the resistor layer in the prior art, which is caused by direct contact between copper foil with uneven surface roughness and the resistor layer, is avoided. This reduces the difference in resistance values per unit area of the resistor layer in various directions, thereby facilitating the design of high-precision buried resistors.

[0039] It should be noted that in this embodiment of the present invention, conductive protrusions 6 are disposed between the resistor layer 31 and the conductive layer 32, preventing direct contact between the conductive layer 32 and the resistor layer 31 while also increasing the adhesion between the conductive layer 32 and the resistor layer 31. The conductive protrusions 6 are spaced apart to prevent adhesion between the conductive protrusions 6, which would otherwise occur if the resistivity of the conductive protrusions 6 were lower than that of the resistor layer. This would cause current to flow through the conductive ends formed by the conductive layer 32 and into the path formed by the adhesion between the conductive protrusions 6, rendering the resistor layer 31 ineffective and affecting its function. In this embodiment, since the multiple conductive protrusions 6 are spaced apart on one surface of the resistor layer 31, i.e., the conductive protrusions 6 do not adhere to each other, the multiple conductive protrusions 6 do not conduct electricity to each other and form resistance. Furthermore, during implementation, due to factors such as process errors, several adjacent conductive protrusions 6 may adhere to each other, but the impact is minimal. Therefore, the present invention facilitates the formation of spaced conductive protrusions 6 on the resistor layer 31, eliminating the need for stringent process requirements and reducing production costs.

[0040] Specifically, each of the conductive protrusions 6 is a first metal particle or a particle cluster composed of a plurality of second metal particles; or a portion of the conductive protrusions 6 are first metal particles, and another portion of the conductive protrusions 6 are particle clusters composed of a plurality of second metal particles. The materials of the first metal particles and the second metal particles can be the same or different. The first metal particles are individual particles, the first metal particles are spaced apart, and the particle clusters composed of a plurality of second metal particles are also spaced apart. As a preferred embodiment, the first metal particles and the particle clusters are alternately distributed, and one or more particle clusters are spaced apart between a plurality of spaced apart first metal particles, or one or more second metal particles are spaced apart between a plurality of spaced apart particle clusters. When the conductive protrusions 6 are particle clusters composed of a plurality of second metal particles, the surface roughness is increased relative to that of a single first metal particle, thereby facilitating an increase in the adhesion of the conductive layer 32, so that the conductive layer 32 can be reliably connected to the resistive layer 31.

[0041] As an optional embodiment, the first metal particles and the conductive layer 32 may be made of different materials. The first metal particles and the conductive layer 32 have different resistivities. When the resistivity of the first metal particles is lower than that of the conductive layer 32, the first metal particles have less impact on the resistive circuit after the buried metal foil forms the resistive circuit. Accordingly, the second metal particles may also be made of a different material than the conductive layer 32. The first and second metal particles may be made of the same or different materials.

[0042] Specifically, the height H of the conductive protrusion 6 in this embodiment is 0.5 microns to 20 microns. In specific applications, if the height of the conductive protrusion 6 is too small, it will not be able to increase the adhesion between the conductive layer 32 and the resistor layer 31. If the height of the conductive protrusion 6 is too large, it may cause pinholes in the conductive layer 32, thereby affecting the performance of the conductive layer 32. This embodiment ensures that the conductive protrusion 6 has a good effect of increasing the adhesion between the conductive layer 32 and the resistor layer 31 by setting the height of the conductive protrusion 6 to 0.5 microns to 20 microns. Of course, the height of the conductive protrusion 6 can also be set to other values according to actual use requirements, which will not be further explained here.

[0043] It should be noted that the conductive protrusions 6 can be randomly distributed on the resistor layer 31. However, in order to further ensure the connection stability between the conductive layer 32 and the resistor layer 31, the multiple conductive protrusions 6 in this embodiment are evenly distributed on the resistor layer 31. By evenly distributing the multiple conductive protrusions 6 on the resistor layer 31, the peel strength at each connection between the conductive layer 32 and the resistor layer 31 is relatively close, further ensuring the connection stability between the conductive layer 32 and the resistor layer 31. In a specific implementation, the multiple conductive protrusions 6 can be evenly or randomly distributed on the resistor layer 31 through conventional processes such as electroplating, ensuring that the conductive protrusions 6 do not adhere to each other. Furthermore, the height of the conductive protrusions 6 is set to be consistent, further improving the direct adhesion between the conductive layer 32 and the resistor layer 31 and making the buried metal foil smoother. When the conductive protrusions 6 are evenly distributed and the height is set to be consistent, the combined effect is more effective.

[0044] In an embodiment of the present invention, in order to facilitate the coating of the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2, preferably, the conductive layer 32 of this embodiment is formed on the side of the resistor layer 31 away from the first barrier layer 2 by adopting any one or more processes of chemical plating, physical vapor deposition, chemical vapor deposition, evaporation plating, sputtering plating, electroplating and mixed plating.

[0045] It should be noted that this is only a specific implementation method of coating the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2. The embodiment of the present invention does not limit the specific method of coating the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2. Those skilled in the art can also use other methods to coat the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2 according to the specific circumstances of actual applications.

[0046] In an embodiment of the present invention, the buried metal foil disclosed in this embodiment is used to make a resistor circuit, wherein the conductive layer 32 is processed to form a conductive end, and the resistor layer 31 is processed to form a resistor. When used, the buried metal foil can be first pressed onto the circuit board, and then the buried metal foil is formed into a resistor circuit through processing, or the buried metal foil is first formed into a resistor circuit, and then the resistor circuit is pressed onto the circuit board, and the conductive end is connected to the electrical device or circuit on the circuit board, and the conductive end is connected to the resistor, so that a conductive circuit is formed. Therefore, the conductivity of the conductive layer 32 is greater than the conductivity of the resistor layer 31. Exemplarily, the conductivity of the conductive layer 32 is 2-1000 times the conductivity of the resistor layer 31. Of course, the conductivity of the conductive layer 32 and the conductivity of the resistor layer 31 can be set according to actual use requirements, and no further details are given here.

[0047] In this embodiment of the present invention, the conductive layer 32 includes any one or more of aluminum, silver, copper, and gold. When the conductive layer 32 is made of copper, the buried metal foil is a buried copper foil product. Of course, the conductive layer 32 can also be made of other materials with good conductivity, which will not be further described here.

[0048] Furthermore, the thickness of the conductive layer 32 in this embodiment is 2 to 20 microns. Setting the thickness of the conductive layer 32 to 2 to 20 microns satisfies the requirements for fine circuit fabrication on printed circuit boards. Of course, the thickness of the conductive layer 32 can be set to other values based on actual use requirements, and further details are omitted here.

[0049] In an embodiment of the present invention, the resistor layer 31 includes any one of nickel, chromium, platinum, palladium, and titanium, or an alloy comprising at least two of nickel, chromium, platinum, palladium, titanium, silicon, and phosphorus. For example, the resistor layer 31 may include an alloy such as a nickel-phosphorus alloy, or a metal such as nickel, or a combination of different metals such as nickel and chromium, or a combination of a nickel-phosphorus alloy and nickel, or a combination of nickel and silicon. Of course, the resistor layer 31 may also be made of other materials, which will not be described in detail here.

[0050] In addition, the thickness of the resistance layer 31 of this embodiment can be set according to actual use requirements, and no further details are given here.

[0051] Accordingly, embodiments of the present invention further provide a printed circuit board (PCB) comprising the aforementioned buried metal foil body 3. For example, when fabricating a resistor circuit, the conductive layer 32 and the resistor layer 31 of the buried metal foil are etched according to a predetermined resistor circuit pattern to obtain the desired resistor circuit. For example, when designing a buried resistor in a specific area of the PCB, the conductive layer 32 in the predetermined area can be etched to expose the resistor layer 31 in that predetermined area.

[0052] Example 2

[0053] See also Figure 4 , is a schematic structural diagram of the buried barrier metal foil provided in the second embodiment of the present invention.

[0054] like Figure 4As shown, in this embodiment of the present invention, in order to ensure that the carrier layer 1 and the resistor layer 31 can avoid mutual diffusion at high temperatures and thus cause adhesion problems, and at the same time, the first barrier layer 2 can remain on the resistor layer 31 when the carrier layer 1 is peeled off from the resistor layer 31, thereby preventing the resistor layer 31 from oxidizing, preferably, the first barrier layer 2 of this embodiment includes a stacked high-temperature resistant layer 21 and a metal bonding layer 22, wherein the metal bonding layer 22 is disposed between the high-temperature resistant layer 21 and the resistor layer 31. By disposing the metal bonding layer 22 between the high-temperature resistant layer 21 and the resistor layer 31, the first barrier layer 2 can be firmly connected to the resistor layer 31, thereby preventing the first barrier layer 2 from peeling off from the carrier layer 1. When the carrier layer 1 is peeled off from the resistor layer 31, the first barrier layer 2 can remain on the resistor layer 31, thereby preventing the resistor layer 31 from oxidizing and protecting the resistor layer 31.

[0055] Specifically, the high-temperature resistant layer 21 of this embodiment is an organic high-temperature resistant layer; or, the high-temperature resistant layer 21 is made of any one or more materials selected from tungsten, chromium, zirconium, titanium, nickel, molybdenum, cobalt and graphite. Preferably, the high-temperature resistant layer 21 is a single-layer alloy structure, or a multi-layer structure composed of a single metal layer, or a multi-layer structure composed of an alloy layer and a single metal layer. Specifically, the single-layer alloy structure is a single-layer structure made of an alloy material, for example, a single-layer structure made of a tungsten-chromium alloy; the multi-layer structure composed of a single metal layer is a multi-layer structure composed of multiple single-layer structures, each single-layer structure is made of a metal, for example, a multi-layer structure composed of a tungsten metal layer and a chromium metal layer; the multi-layer structure composed of an alloy layer and a single metal layer is a multi-layer structure composed of multiple single-layer structures, each single-layer structure is made of a metal or alloy material, for example, a multi-layer structure composed of a zirconium metal layer and a tungsten-chromium alloy layer.

[0056] In addition, the thickness of the high temperature resistant layer 21 of this embodiment can be set according to actual use requirements, and no further details are given here.

[0057] In this embodiment of the present invention, the metal bonding layer 22 includes a metal A capable of bonding to the resistor layer 31 and / or a metal B capable of bonding to the high-temperature resistant layer 21, thereby preventing delamination between the resistor layer 31 and the first barrier layer 2. For example, metal A is copper or zinc, and metal B is nickel, iron, or manganese. It is understood that the metal bonding layer 22 may include any one or more of copper, zinc, nickel, iron, and manganese; alternatively, the metal bonding layer 22 may be made of one of copper or zinc and one of nickel, iron, or manganese. The structure of the metal bonding layer 22 may include but is not limited to the following situations: (1) the metal bonding layer 22 is a single metal layer composed of metal A, wherein the metal A is copper or zinc; (2) the metal bonding layer 22 is a single metal layer composed of metal B, wherein the metal B is nickel or iron or manganese; (3) the metal bonding layer 22 is a single-layer alloy structure composed of metal A and metal B, such as a single-layer alloy structure made of copper-nickel alloy; (4) the metal bonding layer 22 includes a multi-layer structure consisting of an alloy layer and a single metal layer; wherein the alloy layer of the metal bonding layer 22 is made of metal A and metal B, and the single metal layer of the metal bonding layer 22 is made of metal A or metal B; for example, an alloy layer made of copper-nickel alloy and a single metal layer made of manganese; (5) the metal bonding layer 22 is a multi-layer structure consisting of a single-layer structure of metal A and a single-layer structure of metal B, for example, a multi-layer structure consisting of a copper metal layer and a nickel metal layer. When the metal bonding layer 22 is a multi-layer structure consisting of a single-layer structure of metal A and a single-layer structure of metal B, the single-layer structure of metal A is arranged between the resistance layer 31 and the single-layer structure of metal B. Since the bonding force between metal A and the resistance layer 31 is relatively strong, and the bonding force between metal B and the high-temperature resistant layer 21 is relatively strong, the single-layer structure of metal A is arranged between the resistance layer 31 and the single-layer structure of metal B, so that the first barrier layer 2 is not easily separated from the resistance layer 31.

[0058] In addition, the thickness of the first barrier layer 2 of this embodiment is greater than or equal to Preferably, the thickness of the first barrier layer 2 is preferably Of course, the thickness of the first barrier layer 2 can be set to other values according to actual use requirements, and no further details will be given here.

[0059] In the embodiment of the present invention, other structures and working principles of the buried metal foil of this embodiment are the same as those of the first embodiment, and are not further described here.

[0060] Example 3

[0061] See also Figure 5 , is a schematic structural diagram of the buried barrier metal foil provided in the third embodiment of the present invention.

[0062] The buried barrier metal foil of this embodiment differs from that of the first embodiment in that the buried barrier metal foil of this embodiment further includes a second barrier layer 5, which is disposed between the resistor layer 31 and the conductive layer 32. In this embodiment, the conductive layer 32 is plated on the surface of the resistor layer 31 away from the first barrier layer 2, that is, the conductive layer 32 is plated on the surface of the resistor layer 31 away from the first barrier layer 2 through the second barrier layer 5.

[0063] In this embodiment of the present invention, a second barrier layer 5 is disposed between the resistor layer 31 and the conductive layer 32 to protect the resistor layer 31. After the buried metal foil is etched to form the resistor circuit, the conductive layer 32 forms the conductive end. The second barrier layer 5 between the resistor layer 31 and the conductive layer 32 protects the resistor layer 31, preventing the resistor layer 31 from being directly exposed. The material and thickness of the second barrier layer 5 can be the same as or different from those of the first barrier layer 2. The specific configuration can be determined based on actual usage requirements and is not further described here.

[0064] The other structures and working principles of the buried metal foil in this embodiment are the same as those in the first embodiment, and are not described in detail here.

[0065] Example 4

[0066] See also Figure 4 , is a schematic flow chart of the method for preparing the buried barrier metal foil provided in Example 4 of the present invention.

[0067] The method for preparing the buried barrier metal foil provided in the embodiment of the present invention is applicable to preparing the buried barrier metal foil described in the first embodiment. The method for preparing the buried barrier metal foil comprises the following steps S11-S14:

[0068] S11. Forming a dielectric layer; in a specific implementation, the dielectric layer can be formed on the carrier layer.

[0069] S12, forming a first barrier layer on the dielectric layer;

[0070] S13, forming a resistance layer on a side of the first barrier layer away from the dielectric layer;

[0071] S14, depositing a conductive layer on a side of the resistor layer away from the first barrier layer.

[0072] Specifically, in step S12, forming a resistance layer on a side of the first barrier layer away from the dielectric layer specifically includes:

[0073] A resistance layer is formed on a side of the first barrier layer away from the dielectric layer by using conventional processes such as coating or electroplating.

[0074] In step S13, the step of depositing a conductive layer on a side of the resistor layer away from the first barrier layer specifically includes:

[0075] The conductive layer is formed on the side of the resistor layer away from the first barrier layer by using any one or more processes selected from chemical plating, physical vapor deposition, chemical vapor deposition, evaporation plating, sputtering plating, electroplating and mixed plating.

[0076] Of course, this is only a specific implementation method of coating the conductive layer on the side of the resistor layer away from the first barrier layer. The embodiment of the present invention does not limit the specific method of coating the conductive layer on the side of the resistor layer away from the first barrier layer. Those skilled in the art can also use other methods to coat the conductive layer on the side of the resistor layer away from the first barrier layer according to the specific circumstances of actual applications.

[0077] Furthermore, it should be noted that the method for preparing the buried barrier metal foil provided in this embodiment is merely an example of preparing the buried barrier metal foil described in the first embodiment. The buried barrier metal foil described in the first embodiment may also be prepared using other methods. Furthermore, the methods for preparing the buried barrier metal foil described in the second and third embodiments may be specifically referred to in the method for preparing the buried barrier metal foil provided in this embodiment, and further details will not be given here.

[0078] In summary, an embodiment of the present invention provides a buried barrier metal foil, comprising a carrier layer 1, a dielectric layer 4, a first barrier layer 2, and a buried barrier metal foil body 3. The buried barrier metal foil body 3 comprises a resistor layer 31 and a conductive layer 32. The dielectric layer 4 is disposed between the carrier layer 1 and the first barrier layer 2. The resistor layer 31 is disposed on the side of the first barrier layer 2 away from the dielectric layer 4. The conductive layer 32 is plated on the side of the resistor layer 31 away from the first barrier layer 2. The resistance tolerance within a preset unit area at any point on the resistor layer 31 is within a range of -10% to 10%. By disposing the first barrier layer 2 between the dielectric layer 4 and the resistor layer 31, the dielectric layer 4 and the resistor layer 31 can be effectively isolated, avoiding direct contact between the dielectric layer 4 and the resistor layer 31, preventing the dielectric layer 4 from entering the resistor layer 31, and thus preventing the dielectric layer 4 from affecting the circuit transmission performance of the resistor layer 31. Moreover, by plating the conductive layer 32 on the side of the resistor layer 31 away from the first barrier layer 2, there is no need to press a finished copper foil with the resistor layer to form a buried metal foil. This effectively avoids the problem in the prior art that the surface roughness of the resistor layer is uneven due to the direct pressing of the copper foil with uneven surface roughness with the resistor layer, which in turn causes different resistance values per unit area in all directions of the resistor layer. This reduces the difference in resistance values per unit area in all directions of the resistor layer 31, making it easier to design high-precision buried resistors.

[0079] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. A buried barrier metal foil, characterized in that: The buried metal foil body comprises a dielectric layer, a first barrier layer, and a resistive layer. The buried metal foil body comprises a resistive layer and a conductive layer. The first barrier layer is disposed between the dielectric layer and the resistive layer. The conductive layer is plated on a side of the resistive layer away from the first barrier layer. The resistance tolerance within a preset unit area at any location on the resistive layer is within a range of -10% to 10%. The buried metal foil further includes a plurality of conductive protrusions; the height of the conductive protrusions is 0.5 microns to 20 microns; The plurality of conductive protrusions are spaced apart and distributed on a side of the resistor layer away from the first barrier layer, and the plurality of conductive protrusions are covered by the conductive layer; The plurality of conductive protrusions are first metal particles and / or particle clusters composed of a plurality of second metal particles; the first metal particles are made of a different material from that of the conductive layer, and the second metal particles are made of a different material from that of the conductive layer.

2. The buried metal foil according to claim 1, wherein The buried metal foil further includes a carrier layer, and the carrier layer is arranged on a side of the dielectric layer away from the first barrier layer.

3. The buried metal foil according to claim 1, wherein: The first barrier layer includes a high temperature resistant layer and a metal bonding layer stacked together; The metal bonding layer is arranged between the high temperature resistant layer and the resistance layer.

4. The buried metal foil according to claim 3, wherein: The high temperature resistant layer is an organic high temperature resistant layer; or The high temperature resistant layer includes any one or more of tungsten, chromium, zirconium, titanium, nickel, molybdenum, cobalt and graphite.

5. The buried metal foil according to claim 3, wherein: The high temperature resistant layer is a single-layer alloy structure, a multi-layer structure consisting of a single metal layer, or a multi-layer structure consisting of an alloy layer and a single metal layer.

6. The buried metal foil according to claim 3, wherein: The metal bonding layer includes any one or more of copper, zinc, nickel, iron and manganese.

7. The buried barrier metal foil according to any one of claims 1 to 6, characterized in that: The thickness of the conductive layer is 2 micrometers to 20 micrometers.

8. The buried barrier metal foil according to any one of claims 1 to 6, wherein: The conductive layer includes any one or more of aluminum, silver, copper, and gold.

9. The buried barrier metal foil according to any one of claims 1 to 6, wherein: The conductivity of the conductive layer is 2-1000 times that of the resistive layer.

10. The buried barrier metal foil according to any one of claims 1 to 6, wherein: The resistance layer includes any one metal of nickel, chromium, platinum, palladium, and titanium, or an alloy of at least two of nickel, chromium, platinum, palladium, titanium, and silicon.

11. The buried barrier metal foil according to any one of claims 1 to 6, characterized in that: The buried metal foil further includes a second barrier layer disposed between the resistance layer and the conductive layer.

Images