Task scheduling circuit, method, electronic device and computer readable storage medium
By optimizing task allocation across cores through task scheduling circuitry, the problem of low scheduling efficiency in existing technologies is solved, achieving efficient task scheduling and core resource utilization, and improving the performance and flexibility of multi-core systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STREAM COMPUTING INC
- Filing Date
- 2020-11-19
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, task scheduling for processing cores is inflexible and complex to control, resulting in low scheduling efficiency. In particular, in multi-tasking scenarios, each core needs to reuse the scheduler, which reduces efficiency.
A task scheduling circuit is provided, including a core resource storage circuit, a task package scheduling circuit, and a control circuit. By storing the status information and computing power level of the processing cores, the circuit efficiently allocates tasks to idle processing cores based on the coordination information and computing power requirements between task packages, and updates the core status information to optimize scheduling.
It improves the scheduling efficiency of the processing cores, fully utilizes the effective computing power of each core, enhances the flexibility and parallel performance of the multi-processor core system, and reduces power consumption and on-chip network load.
Smart Images
Figure CN114518942B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of processors, and more particularly to a task scheduling circuit, method, electronic device, and computer-readable storage medium. Background Technology
[0002] With the development of science and technology, human society is rapidly entering the intelligent era. A key characteristic of the intelligent era is the increasing variety and volume of data people acquire, coupled with ever-growing demands for faster data processing. Chips are the cornerstone of task scheduling, fundamentally determining our data processing capabilities. From an application perspective, chips mainly follow two paths: one is the general-purpose chip path, such as CPUs (Central Processing Units), which offer great flexibility but have relatively low effective computing power when processing algorithms in specific domains; the other is the dedicated chip path, such as TPUs (Tensor Processing Units), which can exert high effective computing power in certain specific domains, but their processing capabilities are relatively poor or even incapable of handling more general and flexible domains. Because the data in the intelligent era is diverse in type and enormous in quantity, chips are required to possess both extremely high flexibility to handle different and rapidly evolving algorithms in various domains, and extremely strong processing capabilities to quickly process massive and rapidly increasing amounts of data.
[0003] In neural network computing, multi-core or many-core chips are frequently used. In this multi-core (many-core) architecture, each core has a certain degree of independent processing capability and a relatively large internal memory space to store its own program, data, and weights.
[0004] Ensuring that numerous cores can efficiently utilize their computing power is crucial to the overall performance of a chip. The computing power of each core depends on various factors, such as task scheduling and allocation, chip architecture, core structure, and core circuitry. Among these, task scheduling and allocation is a critical factor. If tasks are scheduled and allocated reasonably, the effective computing power of each core can be fully utilized; otherwise, the effective computing power of each core will be reduced.
[0005] The following schemes are generally used in existing technologies to handle the scheduling of kernel tasks:
[0006] like Figure 1The diagram illustrates a task scheduling scheme using a scheduler. In this scheme, the scheduler receives instructions from the instruction source and then transmits these instructions to each processing core according to a certain strategy, such as sequence. Each processing core executes the same instructions on different data. Each processing core can have a relatively simple structure, such as SIMD (Single Instruction Multiple Data), which shares control circuitry and registers, or a more complex structure with some autonomy, such as SIMT (Single Instruction Multiple Threads), which has independent control circuitry and registers. However, this scheme is generally used for instruction-level scheduling, which can only schedule one or a few instructions at a time. When large tasks need to be completed, frequent scheduling is required, reducing scheduling efficiency. Furthermore, this scheme is generally suitable for single-task scenarios; when executing multiple tasks, each core needs to reuse the scheduler, which also reduces scheduling efficiency. Summary of the Invention
[0007] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.
[0008] To address the technical problems of inflexible task scheduling and complex control in existing technologies for processing kernels, this disclosure proposes the following technical solution:
[0009] In a first aspect, embodiments of this disclosure provide a task scheduling circuit, including:
[0010] Nuclear resource storage circuitry, task packet scheduling circuitry, and control circuitry; among which,
[0011] The core resource storage circuit is used to store the status information and computing power level of each processing core;
[0012] The task package scheduling circuit is used to acquire a first task package to be executed, the task package including at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package; determine all other task packages that need to be executed in coordination with the first task package based on the coordination information between the task packages; confirm all idle processing cores to participate in the computation from the core resource storage circuit based on the coordination information and computing power requirements of all task packages, the computing power level of the idle processing cores corresponding one-to-one with the computing power requirement of the task package; and send all the task packages to the corresponding idle processing cores respectively.
[0013] A control circuit is used to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit according to the status information.
[0014] Furthermore, the core resource storage circuit is used to store the status information and computing power level of each processing core, including:
[0015] The core resource storage circuit is used to store a core resource table, which includes a processing core identifier, a processing core status bit corresponding to the processing core identifier, and a computing power level of the processing core corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.
[0016] Furthermore, the requirement to coordinate execution means that the execution times of the multiple task packages need to satisfy a preset relationship.
[0017] Furthermore, the task package scheduling circuit, based on the coordination information between the task packages, the computing power requirements of all the task packages, and the computing power level, identifies idle processing cores from the core resource storage circuit, including:
[0018] When the coordination information between the task packages indicates that the task package does not need to cooperate with other task packages, an idle processing core with a computing power level corresponding to the computing power requirement is identified from the core resource storage circuit according to the computing power requirement of the task package.
[0019] When the coordination information between the task packages indicates that the task package needs to cooperate with other task packages, multiple idle processing cores with computing power levels corresponding to the computing power requirements of the multiple task packages that need to cooperate are identified from the core resource storage circuit.
[0020] Furthermore, the process of identifying multiple idle processing cores from the core resource storage circuit based on the computing power requirements of multiple task packages as needed includes:
[0021] Calculate the proportional relationship between the computing power requirements of the multiple task packages;
[0022] Find multiple idle processing cores in the nuclear resource storage circuit whose computing power level matches the stated ratio.
[0023] Furthermore, the task packet scheduling circuit is also used for:
[0024] Modify the status information of the idle processing core in the nuclear resource storage circuit to a busy state.
[0025] Furthermore, the control circuit is configured to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit according to the status information, including:
[0026] The control circuit is used to receive information from the idle processing core that the task package has been completed; and to modify the state information of the idle processing core in the core resource storage circuit to an idle state based on the information that the task package has been completed.
[0027] Furthermore, the task scheduling circuit also includes:
[0028] A task instruction caching circuit includes a task instruction caching queue corresponding to each processing core, and each member in the task package caching queue is used to cache the task instructions in the task package corresponding to the processing core.
[0029] Secondly, embodiments of this disclosure provide a task scheduling method for use in a system including at least two processing cores, the method comprising:
[0030] Obtain the first task package to be executed, wherein the task package includes at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package;
[0031] Based on the coordination information between the task packages, determine all other task packages that need to be executed in coordination with the first task package;
[0032] Based on the coordination information of all the task packages and the computing power requirements of all the task packages, all idle processing cores to be participated in the calculation are identified from the core resource storage circuit. The computing power level of each idle processing core corresponds one-to-one with the computing power requirements of the task package.
[0033] Send all the task packets to the corresponding idle processing cores;
[0034] The status information of the idle processing core is received, and the status information of the idle processing core in the core resource storage circuit is updated according to the status information.
[0035] Furthermore, the status information of the processing core is stored in a core resource table, wherein the core resource table includes a processing core identifier, a processing core status bit corresponding to the processing core identifier, and a computing power level of the processing core corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.
[0036] Furthermore, the requirement to coordinate execution means that the execution times of the multiple task packages need to satisfy a preset relationship.
[0037] Furthermore, the step of determining the available processing cores based on the coordination information between the task packages, the computing power requirements of all the task packages, and the computing power level includes:
[0038] When the coordination information between the task packages indicates that the task package does not need to cooperate with other task packages, an idle processing core with a computing power level corresponding to the computing power requirement is identified from the core resource storage circuit according to the computing power requirement of the task package.
[0039] When the coordination information between the task packages indicates that the task package needs to cooperate with other task packages, multiple idle processing cores with computing power levels corresponding to the computing power requirements of the multiple task packages that need to cooperate are identified from the core resource storage circuit.
[0040] Furthermore, the process of identifying multiple idle processing cores from the core resource storage circuit based on the computing power requirements of multiple task packages as needed includes:
[0041] Calculate the proportional relationship between the computing power requirements of the multiple task packages;
[0042] Find multiple idle processing cores in the nuclear resource storage circuit whose computing power level matches the stated ratio.
[0043] Furthermore, the method also includes: modifying the status information of the idle processing core to a busy state.
[0044] Furthermore, receiving the status information of the idle processing core and updating the status information of the idle processing core in the core resource storage circuit according to the status information includes:
[0045] Receive information from the idle processing core indicating that the task package has been completed; modify the status information of the idle processing core to an idle state based on the information indicating that the task package has been completed.
[0046] Furthermore, sending all the task packages to the corresponding idle processing cores includes: sending the task instructions in all the task packages to the task instruction cache queue corresponding to the idle processing core corresponding to the task package.
[0047] Thirdly, embodiments of this disclosure provide a chip, including at least one task scheduling circuit as described in any one of the first aspects.
[0048] Fourthly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the task scheduling methods described in the second aspect above.
[0049] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the task scheduling methods described in the second aspect above.
[0050] In a sixth aspect, embodiments of this disclosure provide a computer program product, characterized in that it includes computer instructions, wherein when the computer instructions are executed by a computing device, the computing device can execute any of the task scheduling methods described in the second aspect above.
[0051] In a seventh aspect, embodiments of this disclosure provide a computing device, characterized in that it includes any of the chips described in the fourth aspect.
[0052] This disclosure provides a task scheduling circuit, method, electronic device, and computer-readable storage medium. The task scheduling circuit includes a core resource storage circuit, a task package scheduling circuit, and a control circuit. The core resource storage circuit stores the status information and computing power level of each processing core. The task package scheduling circuit acquires a first task package to be executed, the task package including at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package. Based on the coordination information between task packages, it determines all other task packages that need to cooperate with the first task package for execution. Based on the coordination information and computing power requirements of all task packages, it identifies all idle processing cores to participate in the computation from the core resource storage circuit, where the computing power level of each idle processing core corresponds one-to-one with the computing power requirement of each task package. The control circuit receives the status information of the idle processing cores and updates the status information of the idle processing cores in the core resource storage circuit according to the status information. This task scheduling circuit schedules task packages using the status information of the processing cores and the coordination information between task packages, solving the problem of low scheduling efficiency in the prior art.
[0053] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0054] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0055] Figure 1 This is a schematic diagram of existing technology;
[0056] Figure 2 This is a schematic diagram of the structure of the task scheduling circuit provided in an embodiment of the present disclosure;
[0057] Figure 3 A flowchart illustrating the task scheduling method provided in this embodiment of the disclosure;
[0058] Figure 4 A schematic diagram of an example of a task scheduling circuit provided in an embodiment of this disclosure;
[0059] Figure 5 A timing diagram of an example of a task scheduling circuit provided in an embodiment of this disclosure. Detailed Implementation
[0060] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.
[0061] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.
[0062] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0063] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.
[0064] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0065] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.
[0066] Figure 2 This is a schematic diagram of the structure of a task scheduling circuit provided in an embodiment of this disclosure. The task scheduling circuit is used in a system including at least two processing cores, such as... Figure 2 As shown, the task scheduling circuit 200 includes:
[0067] Nuclear resource storage circuit 201, task packet scheduling circuit 202, and control circuit 203;
[0068] The core resource storage circuit 201 is used to store the status information and computing power level of each processing core.
[0069] The task package scheduling circuit 202 is used to acquire a first task package to be executed, the task package including at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package; determine all other task packages that need to be executed in coordination with the first task package based on the coordination information between the task packages; confirm all idle processing cores to participate in the calculation from the core resource storage circuit based on the coordination information and computing power requirements of all task packages, the computing power level of the idle processing cores corresponding one-to-one with the computing power requirement of the task package; and send all the task packages to the corresponding idle processing cores respectively.
[0070] The control circuit 203 is used to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit according to the status information.
[0071] Through the aforementioned task scheduling circuit, tasks can be assigned to different types of processing cores based on computing power levels, ensuring that each task finds a suitable processing core for execution. This allows for the fastest possible task completion based on computing power requirements while maximizing chip performance. Furthermore, the task scheduling circuit schedules task packets to processing cores based on their status information. Each task packet contains at least one instruction for the same task. This eliminates the need for processing cores to consider data dependencies between tasks when executing instructions within a packet, improving the parallel performance of multi-processor systems and reducing the complexity of designing solutions to dependencies. Processor cores can continuously execute at least one instruction from a task packet for the same task, avoiding frequent communication between the processing core and the task scheduling circuit, thus improving processing core efficiency, reducing on-chip network load, and lowering power consumption. The independence of each task packet allows the multi-processor system to execute completely unrelated tasks simultaneously, significantly enhancing system flexibility.
[0072] Optionally, the core resource storage circuit 201 is used to store the status information and computing power level of each processing core, including: the core resource storage circuit 201 is used to store a core resource table, the core resource table including a processing core identifier, a processing core status bit corresponding to the processing core identifier, and a computing power level of the processing core corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.
[0073] like Figure 2 As shown, the core resource table RT includes a processing core identifier Ci, a processing core status bit Si corresponding to the processing core identifier Ci, and a computing power level Pi corresponding to the processing core identifier Ci. For example, the processing core identifier Ci is the number of the processing core in the system including at least two processing cores; the value of the processing core status bit S is 0 or 1, where 0 indicates that the processing core is in an idle state and can execute tasks; 1 indicates that the processing core is in a busy state and is executing tasks; the computing power level Pi of the processing core represents the computing power of the processing core. Pi can be the actual computing power of the processing core, such as a value in GOPS (Giga Operations Per Second), or Pi can be a number after standardizing the computing power, such as Pi∈[1,10] and Pi is an integer.
[0074] Further, optionally, the requirement for coordinated execution indicates that the execution times of each task package need to satisfy a preset relationship. Optionally, the preset relationship includes the simultaneous completion of all task packages. The multiple task packages can be multiple task packages of the same task or multiple task packages of different tasks. When generating the task package, the coordination information is added to the task package according to the relationship between the task packages or tasks. The coordination information indicates which task package the task package needs to be executed simultaneously with. The process of determining all other task packages that need to be executed in coordination with the first task package based on the coordination information between the task packages includes: starting from the current task package, obtaining the task number and task package number of the target task package that needs to be executed simultaneously with the current task package, then obtaining the task number and task package number of the target task package that needs to be executed simultaneously with the target task package, and so on, until all task packages that need to be executed simultaneously are obtained.
[0075] Optionally, the task scheduling circuit 200 further includes a task packet caching circuit 204, which is used to cache task packets received from the task source. The task packet includes one or more instructions for the same task. The task can be a complete task, such as a complete neural network like ResNet50 or BERT; or, the task can be a subtask of a complete task, such as a complete operation like convolution in ResNet50; the task or subtask includes one or more task instructions. The task source issues tasks to the task scheduling circuit 200 in the form of task packets. The same task can be divided into multiple task packets and sent sequentially to the task scheduling circuit to form a task packet stream. Each task packet includes a task number, a task packet number, coordination information, computing power requirements, and at least one task instruction. Table 1 below shows the data format of the task packet:
[0076] T_ID T_R P_ID CP_ID P_body
[0077] (Table 1)
[0078] Wherein, T_ID represents the task number, each task has a unique task number, and task packages belonging to the same task have the same task number; T_R represents the computing power requirement of the task package, the larger the number, the higher the computing power requirement, where the computing power requirement represents the computing power of the processing cores required to execute the task package, and the method of representing the computing power requirement in this disclosure is the same as the computing power level; P_ID represents the task package number, which represents the task package number of the task package in the task with the T_ID number; CP_ID represents the coordination information between task packages, which is composed of the task number and the task package number; P_body represents the task package content, that is, the task instructions of the task or subtask.
[0079] Optionally, the task package scheduling circuit 202 is used to read the task package from the task package cache circuit 204. After reading the task package, the computing power requirement T_R of the task package and the cooperation information CP_ID between task packages are read from the task package. If the CP_ID indicates that the task package does not need to cooperate with other task packages, an idle processing core with a computing power level corresponding to the computing power requirement is identified from the core resource storage circuit according to the computing power requirement of the task package. If the CP_ID indicates that the task package needs to cooperate with other task packages, multiple idle processing cores with computing power levels corresponding to the computing power requirements of the multiple task packages that need to cooperate are identified from the core resource storage circuit.
[0080] Optionally, CP_ID = 0 indicates that the task package does not need to cooperate with other task packages. In this case, based on the task's computing power requirement T_R, an idle processing core with a computing power level that meets the task's computing power requirement is determined from the core resource table RT in the core resource storage circuit 201. For example, the core resource table RT is as follows:
[0081] Ci Pi Si 1 1 0 2 2 0 3 3 0 4 4 1
[0082] The core resource table RT indicates that the system includes four processing cores, namely C1, C2, C3 and C4, with computing power levels of 1, 2, 3 and 4 respectively, and their states being idle, idle, idle and busy respectively.
[0083] Optionally, when CP_ID ≠ 0, it indicates that the task package needs to cooperate with other task packages. In this case, the value of CP_ID represents the task number and task package number of the task package that needs to cooperate with the current task package. For example, CP_ID = T_ID_P_ID. If CP_ID = 2_1, it means that the task package that needs to cooperate with the current task package is the first task package of task number 2. At this time, the task package scheduling circuit 202 continues to read the task package with task number 2 and task package number 1 from the task package cache circuit 204. Then, it continues to determine whether the task package needs to cooperate with other task packages. If so, it continues to obtain subsequent task packages until the CP_ID of the obtained task packages is 0, thus obtaining all task packages that need to cooperate with each other. Afterward, multiple idle processing cores are identified from the core resource storage circuit according to the computing power requirements of the multiple task packages that need to cooperate. Optionally, the computing power requirements of the multiple task packages that need to cooperate are determined from the core resource storage circuit by identifying multiple idle processing cores, including: calculating the ratio between the computing power requirements of the multiple task packages; and searching the core resource storage circuit for multiple idle processing cores whose computing power levels match the ratio. For example, if there are three task packages that need to cooperate, with computing power requirements of 1, 2, and 3 respectively, then the ratio between their computing power requirements is 1:2:3. Therefore, three idle processing cores need to be found simultaneously, and the ratio of the computing power levels of these three idle processing cores must be 1:2:3. After finding three idle processing cores whose computing power levels match the ratio, the three task packages are sent to the corresponding processing cores with the appropriate computing power levels. As shown in the example above, P1:P2:P3 = 1:2:3, and C1, C2, and C3 are all idle processing cores; therefore, the three task packages are sent to C1, C2, and C3 for execution. Understandably, in the process of determining multiple idle processing cores with computing power levels corresponding to the computing power requirements of multiple task packages, the computing power level corresponding to the computing power requirements includes cases where the computing power level and computing power requirements are not equal. For example, the system may include idle processing cores with computing power levels that meet the aforementioned proportional relationship, but the computing power level of the idle processing cores is higher or lower than the corresponding computing power requirements. In this case, to prevent long waiting times, the multiple idle processing cores can be used as idle processing cores to execute the multiple task packages. In this way, the task packages can be executed more promptly, and multiple task packages can still be completed simultaneously.
[0084] Optionally, when there are multiple idle processing cores that meet the criteria, one or more idle processing cores can be determined according to a pre-set scheduling strategy. For example, one idle processing core or multiple idle processing cores can be determined according to the order of the processing core identifiers.
[0085] Alternatively, a random scheduling strategy can be used, whereby all idle processing cores are first identified, and then the task packet is randomly sent to one of the processing cores that meets the criteria. It is understood that the above scheduling strategies are merely examples and do not constitute a limitation of this disclosure.
[0086] Optionally, the task package scheduling circuit 202 is further configured to: modify the status information of the idle processing core in the core resource storage circuit to a busy state. After sending a task package to the idle processing core, the task package scheduling circuit 202 is configured to modify the status information of the idle processing core in the core resource table RT. Specifically, the task package scheduling circuit 202 modifies the status of the idle processing core in the core resource table RT to a busy state. As in the example above, if processing core C1 is determined to be an idle processing core, the value of the status corresponding to processing core C1 can be modified to 1 before or after the task package is sent to processing core C1 to indicate that processing core C1 is executing a task. When multiple task packages cooperate, the task package scheduling circuit 202 modifies the status information of multiple idle processing cores whose computing power levels match the ratio to a busy state.
[0087] Optionally, the control circuit 203 is configured to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit 201 according to the status information, including: the control circuit 203 receiving information from the idle processing core indicating that a task package has been completed; and modifying the status information of the idle processing core in the core resource storage circuit 201 to an idle state according to the information indicating that the task package has been completed. After the idle processing core completes the task package, it sends information indicating that the task package has been completed. After receiving the information indicating that the task package has been completed, the task package scheduling circuit 202 modifies the status information of the idle processing core in the core resource table RT in the core resource storage circuit to an idle state.
[0088] Optionally, the task scheduling circuit 200 further includes a task instruction cache circuit 205, which includes a task instruction cache queue corresponding one-to-one with each processing core. Each member of the task package cache queue is used to cache task instructions in the task package corresponding to the processing core. Figure 2 As shown, the task instruction caching circuit 205 includes a task instruction caching queue IQi, where IQi corresponds to Ci. When the task package scheduling circuit 202 determines an idle processing core Ci, it sends the task instructions in the read task package to the task instruction caching queue IQi corresponding to Ci. Then, Ci retrieves the task instructions from the task instruction caching queue and executes them to complete the corresponding task or subtask.
[0089] Figure 3This is a flowchart illustrating a task scheduling method provided in an embodiment of the present disclosure. The task scheduling method is used in a system including at least two processing cores, and includes:
[0090] Step S301: Obtain the first task package to be executed. The task package includes at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package.
[0091] Step S302: Determine all other task packages that need to be executed in cooperation with the first task package based on the cooperation information between the task packages;
[0092] Step S303: Based on the coordination information of all the task packages and the computing power requirements of all the task packages, identify all idle processing cores to participate in the calculation from the core resource storage circuit. The computing power level of each idle processing core corresponds one-to-one with the computing power requirements of the task package.
[0093] Step S304: Send all the task packets to the corresponding idle processing cores respectively;
[0094] Step S305: Receive the status information of the idle processing core, and update the status information of the idle processing core in the core resource storage circuit according to the status information.
[0095] Furthermore, the status information of the processing core is stored in a core resource table, wherein the core resource table includes a processing core identifier, a processing core status bit corresponding to the processing core identifier, and a computing power level of the processing core corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.
[0096] Furthermore, the requirement to coordinate execution means that the execution times of multiple task packages need to meet a preset relationship.
[0097] Furthermore, the step of determining the available processing cores based on the coordination information between the task packages, the computing power requirements of all the task packages, and the computing power level includes:
[0098] When the coordination information between the task packages indicates that the task package does not need to cooperate with other task packages, an idle processing core with a computing power level corresponding to the computing power requirement is identified from the core resource storage circuit according to the computing power requirement of the task package.
[0099] When the coordination information between the task packages indicates that the task package needs to cooperate with other task packages, multiple idle processing cores with computing power levels corresponding to the computing power requirements of the multiple task packages that need to cooperate are identified from the core resource storage circuit.
[0100] Furthermore, the process of identifying multiple idle processing cores from the core resource storage circuit based on the computing power requirements of multiple task packages as needed includes:
[0101] Calculate the proportional relationship between the computing power requirements of the multiple task packages;
[0102] Find multiple idle processing cores in the nuclear resource storage circuit whose computing power level matches the stated ratio.
[0103] Furthermore, the method also includes: modifying the status information of the idle processing core to a busy state.
[0104] Furthermore, receiving the status information of the idle processing core and updating the status information of the idle processing core in the core resource storage circuit according to the status information includes:
[0105] Receive information from the idle processing core indicating that the task package has been completed; modify the status information of the idle processing core to an idle state based on the information indicating that the task package has been completed.
[0106] Furthermore, sending all the task packages to the corresponding idle processing cores includes: sending the task instructions in all the task packages to the task instruction cache queue corresponding to the idle processing core corresponding to the task package.
[0107] It is understood that the task scheduling method is executed by the task scheduling circuit, and the specific implementation of each step can be found in the description of the task scheduling circuit, which will not be repeated here.
[0108] Figure 4 This is an example of a task scheduling circuit described in an embodiment of this disclosure. Figure 4 As shown in this example, the task scheduling circuit is used in a system comprising two processing cores, C1 and C2. C1 has a computing power level of 1, and C2 has a computing power level of 2. The task scheduling circuit includes a task packet cache circuit TB, a task packet scheduling circuit TS, a control circuit Ctrl, a core resource table RT, and a task instruction cache queue IQ1 corresponding to processing core C1 and a task instruction cache queue IQ2 corresponding to processing core C2. The processing core identifiers, computing power levels, and status information of processing cores C1 and C2 are stored in the core resource table RT.
[0109] In this example, the task source includes four tasks T1, T2, T3, and T4, with IDs 1, 2, 3, and 4 respectively. T1 and T3 require 1 unit of computing power, while T2 and T4 require 2 units. Each task includes a task package, and each task package contains at least one task instruction from the task's program. The specific contents of the task package include:
[0110] T_ID T_R P_ID CP_ID P_body 1 1 1 2_1 Program 1 2 2 1 0 Program2 3 1 1 4_1 Program3 4 2 1 0 Program4
[0111] In this context, Program1, Program2, Program3, and Program4 represent at least one task instruction from T1, T2, T3, and T4, respectively.
[0112] Based on the CP_ID in the task packages, it can be determined that task package 1_1 needs to be executed simultaneously with task package 2_1, and task package 3_1 needs to be executed simultaneously with task package 4_1. Since the computing power requirements of these task packages differ, it is necessary to determine the available processing cores by combining the information and computing power requirements. The timing diagram for C1 and C2 executing the four tasks is shown below. Figure 5 As shown.
[0113] Combination Figure 4 and Figure 5 The process by which the task scheduling circuit schedules the four tasks is as follows:
[0114] The task source sends the task packets of the four tasks to the task packet cache circuit TB of the task scheduling circuit in sequence.
[0115] TS reads task packets from the TB in sequence.
[0116] The first task packet is the task packet with T_ID 1. Since the value of CP_ID is 2_1, TS continues to read the task packet with T_ID 2 from TB. The TR ratio of the two task packets is 1:2. Therefore, TS searches for two idle processing cores C1 and C2 with a computing power level ratio of 1:2 from RT. In RT, the states of C1 and C2 are S1=0 and S2=0, and P1:P2=1:2. Therefore, C1 and C2 satisfy the coordination information and computing power requirements of T1 and T2. At this time, the task instructions in the task packet of T1 are sent to the task instruction cache queue IQ1 corresponding to C1, and the task instructions in the task packet of T2 are sent to the task instruction cache queue IQ2 corresponding to C2. C1 executes the task instructions after obtaining them from IQ1, and C2 executes them after obtaining them from IQ2. Before or after sending the task instructions to C1 and C2, TS sets S1 and S2 in RT to 1.
[0117] TS continues to read the task packet of T3 from the TB. Since the CP_ID of the task packet of T3 is 4_1, TS continues to read the task packet of the task with T_ID 4 from the TB. The ratio of TR of the two task packets is 1:2. Therefore, TS searches for two idle processing cores with a computing power level ratio of 1:2 from the RT. However, there are no idle processing cores in the RT at this time, so TS enters the waiting state.
[0118] Afterwards, when C1 and C2 finish executing the task packages T1 and T2 simultaneously and send the completion information to Ctrl, Ctrl sets S1 in RT to 0 and S2 to 0 based on the identifier of the processing core and the completion information.
[0119] When the TS detects an idle processing core, it queries the idle processing cores whose computing power level matches the TR ratio of 1:2 for the two task packets mentioned above. It finds that idle processing cores C1 and C2 satisfy the coordination information and computing power requirements of T3 and T4. At this time, the task instructions in the T3 task packet are sent to the task instruction cache queue IQ1 corresponding to C1, and the task instructions in the T4 task packet are sent to the task instruction cache queue IQ2 corresponding to C2. C1 executes the task instructions after obtaining them from IQ1, and C2 executes them after obtaining them from IQ2. Before or after sending the task instructions to C1 and C2, the TS sets S1 and S2 in RT to 1.
[0120] After that, since there are no other task packages in TB, TS no longer reads task packages from TB and enters an idle state.
[0121] Afterwards, processing cores C1 and C2 simultaneously complete the execution of task packets T3 and T4, and send the completion information to Ctrl. Ctrl sets S1 in RT to 0 and S2 to 0 based on the identifier of the processing core and the completion information.
[0122] At this point, all four tasks have been completed. The system is now awaiting new task packages to execute.
[0123] The example above shows a scheme with two processing cores of different computing power levels. In actual implementation, more processing cores with different computing power levels and more task packages can be included to achieve more flexible and complex task scheduling, which will not be elaborated here.
[0124] This disclosure also provides a chip including at least one task scheduling circuit as described in any of the above embodiments.
[0125] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the task scheduling methods described in the embodiments.
[0126] This disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the task scheduling methods described in the foregoing embodiments.
[0127] This disclosure also provides a computer program product, characterized in that it includes computer instructions, which, when executed by a computing device, can execute any of the task scheduling methods described in the foregoing embodiments.
[0128] This disclosure also provides a computing device, characterized in that it includes any of the chips described in the embodiments.
[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0130] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.
[0131] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.
[0132] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
Claims
1. A task scheduling circuit for use in a system comprising at least two processing cores, characterized in that, include: Nuclear resource storage circuitry, task packet scheduling circuitry, and control circuitry; among which, The core resource storage circuit is used to store the status information and computing power level of each processing core; The task package scheduling circuit is used to acquire a first task package to be executed, the task package including at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package; determine all other task packages that need to be executed in coordination with the first task package based on the coordination information between the task packages; confirm all idle processing cores to participate in the computation from the core resource storage circuit based on the coordination information and computing power requirements of all task packages, the computing power level of the idle processing cores corresponding one-to-one with the computing power requirements of the task packages; and send all the task packages to the corresponding idle processing cores, the idle processing cores being used to continuously execute at least one task instruction in the corresponding task package. A control circuit is used to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit according to the status information.
2. The task scheduling circuit as described in claim 1, characterized in that, The core resource storage circuit is used to store the status information and computing power level of each processing core, including: The core resource storage circuit is used to store a core resource table, which includes a processing core identifier, a processing core status bit corresponding to the processing core identifier, and a computing power level of the processing core corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.
3. The task scheduling circuit as described in any one of claims 1-2, characterized in that: The requirement to coordinate with the first task package means that the execution times of the multiple task packages need to meet a preset relationship.
4. The task scheduling circuit as described in any one of claims 1-2, characterized in that, The task package scheduling circuit identifies idle processing cores from the core resource storage circuit based on the coordination information between the task packages, the computing power requirements of all the task packages, and the computing power level, including: When the coordination information between the task packages indicates that the task package does not need to cooperate with other task packages, an idle processing core with a computing power level corresponding to the computing power requirement is identified from the core resource storage circuit according to the computing power requirement of the task package. When the coordination information between the task packages indicates that the task package needs to cooperate with other task packages, multiple idle processing cores with empty computing power levels corresponding to the computing power requirements of the multiple task packages that need to cooperate are identified from the core resource storage circuit.
5. The task scheduling circuit as described in claim 4, characterized in that, The computing power requirements of multiple task packages to be coordinated as needed are determined from the core resource storage circuit to identify multiple idle processing cores, including: Calculate the proportional relationship between the computing power requirements of the multiple task packages; Find multiple idle processing cores in the nuclear resource storage circuit whose computing power level matches the stated ratio.
6. The task scheduling circuit as described in any one of claims 1-2, characterized in that, The task packet scheduling circuit is also used for: Modify the status information of the idle processing core in the nuclear resource storage circuit to a busy state.
7. The task scheduling circuit as described in any one of claims 1-2, characterized in that, The control circuit is configured to receive the status information of the idle processing core and update the status information of the idle processing core in the core resource storage circuit according to the status information, including: The control circuit is used to receive information from the idle processing core that the task package has been completed; and to modify the state information of the idle processing core in the core resource storage circuit to an idle state based on the information that the task package has been completed.
8. The task scheduling circuit as described in any one of claims 1-2, characterized in that, The task scheduling circuit further includes: A task instruction caching circuit includes a task instruction caching queue corresponding to each processing core, and each member in the task package caching queue is used to cache the task instructions in the task package corresponding to the processing core.
9. A task scheduling method, used in the task scheduling circuit according to any one of claims 1-8, characterized in that, include: Obtain the first task package to be executed, wherein the task package includes at least one task instruction for the same task, coordination information between task packages, and the computing power requirement of the task package; Based on the coordination information between the task packages, determine all other task packages that need to be executed in coordination with the first task package; Based on the coordination information of all the task packages and the computing power requirements of all the task packages, all idle processing cores to participate in the calculation are identified from the core resource storage circuit. The computing power level of each idle processing core corresponds one-to-one with the computing power requirements of the task package. Each idle processing core is used to continuously execute at least one task instruction in the corresponding task package. Send all the task packets to the corresponding idle processing cores; The status information of the idle processing core is received, and the status information of the idle processing core in the core resource storage circuit is updated according to the status information.
10. A chip, characterized in that, It includes at least one task scheduling circuit as described in any one of claims 1-8.