An optional bit number high speed serializer and a high speed interface

Abstract

This application discloses a high-speed serializer with selectable bit width and a high-speed interface, belonging to the field of high-speed interface technology. The high-speed serializer includes: multiple shift registers and a tree-structured serializer for converting the data output from the multiple shift registers into serial data; the selection signals corresponding to the two-to-one selection modules in each shift register are independent; wherein each signal input terminal of the tree-structured serializer is connected to the signal output terminals of the multiple shift registers. When supporting parallel-to-serial conversion output with different bit widths, only the selection signals of the two-to-one selection modules of the shift registers need to be selected for output, eliminating the need for multiple sets of serializers, thus significantly reducing the hardware overhead required by the serializer. Furthermore, when implementing parallel-to-serial conversion with the same bit width, the number of D flip-flops in the phase-shift register can be reduced, thereby greatly reducing the power consumption required by the serializer.

Description

Technical Field

[0001] This invention relates to the field of high-speed interface technology, and in particular to a high-speed serializer with selectable bit width and a high-speed interface. Background Technology

[0002] A serializer is a device that converts parallel data into serial data. It is widely used in chip interconnects, memory, and the internet. In practical applications, if it's necessary to support serial conversion output of parallel data with different bit widths, one approach is to use multiple independent serializers; however, this method incurs significant hardware overhead. Another approach is to use a shift register. However, this method requires the shift register's bit width to match the maximum number of bits in the parallel data. For example, if the shift register needs to support serial conversion output of 10-bit, 16-bit, and 20-bit parallel data, a 20-bit shift register is required. Furthermore, this method requires the D flip-flops in the shift register to operate at the highest clock frequency, resulting in high power consumption. Currently, there is no effective solution to this technical problem.

[0003] Therefore, it is evident that providing a serializer with low hardware overhead and low power consumption, capable of parallel-to-serial conversion of different bit widths, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a high-speed serializer with selectable bit width and a high-speed interface to solve the technical problems of high hardware overhead and high power consumption when performing serial conversion and output of parallel data with different bit widths in the prior art. The specific solution is as follows:

[0005] To address the aforementioned technical problems, this invention provides a high-speed serializer with selectable bit width, comprising: multiple shift registers and a tree-structured serializer for converting the data output from the multiple shift registers into serial data; the selection signals corresponding to each two-to-one selection module in the shift registers are independent of each other;

[0006] Each signal input terminal of the tree-structured serializer is connected to the signal output terminals of multiple shift registers.

[0007] Preferably, the plurality of shift registers includes: 2 a There are N shift registers with identical configurations, where N ≥ 2, and the tree-structured serializer is used to transfer 2... a A multi-to-one serializer that converts N bits of parallel data into 1 bit of serial data.

[0008] Preferably, the N-bit shift register includes: N D flip-flops and N-1 two-to-one signal selection modules;

[0009] In this system, the CLK terminals of all N D flip-flops are used to receive the CLK clock signal. The D terminal of the j-th D flip-flop is connected to the output terminal of the j-th 2-to-1 signal selection module, and the Q terminal of the (j+1)-th D flip-flop is connected to the second input terminal of the j-th 2-to-1 signal selection module. 1≤j≤N-1. The Q terminal of the 1-th D flip-flop is the signal output terminal of the N-bit shift register. The first input terminal of each 2-to-1 signal selection module and the D terminal of the N-th D flip-flop are used to receive N parallel data.

[0010] Preferably, the expression for the selection signal corresponding to the k-th two-to-one selection module in the N-bit shift register is: SEL <k>=SEL_OUT+BIT <k>,1≤j≤N-1;BIT <k>The number of bits used to represent the parallel-to-serial conversion of the high-speed serializer, SEL_OUT, is obtained by recursively summarizing the output signals of M cascaded D flip-flops; M = N / 2, and the value of M is rounded up.

[0011] Preferably, SEL_OUT = Q1·(S 2，3 ·Q1+S 4，5 ·Q2+...+S 2i，2i+1 Qi+...S 2M，2M+1 ·QM), where Qi is the signal output from the Q terminal of the i-th D flip-flop among the M D flip-flops;

[0012] D1 is the signal input to the D terminal of the first D flip-flop among the M D flip-flops;

[0013] S 2i-1，2i =BIT<2i-1>+BIT<2i>, 1≤i≤M;

[0014] S 2i-1，2i，2i+1 =BIT<2i-1<+BIT<2i>+BIT<2i+1>.

[0015] Preferably, the N-bit shift register is a 10-bit shift register, and the selection signal corresponding to the k-th two-to-one signal selection module in the 10-bit shift register is generated by SEL_OUT and BIT(k) through an OR gate.

[0016] Preferably, SEL_OUT is generated by a D flip-flop module; the D flip-flop module includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first OR gate, a second OR gate, a third OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, and an OR NOT gate;

[0017] In this configuration, the CLK terminals of the first, second, third, fourth, and fifth D flip-flops are all used to receive the CLK clock signal. The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop, the Q terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop, the Q terminal of the third D flip-flop is connected to the D terminal of the fourth D flip-flop, and the Q terminal of the fourth D flip-flop is connected to the D terminal of the fifth D flip-flop. The input signal of the D terminal of the first D flip-flop is D1. The output signals of the Q terminals of the first, second, third, fourth, and fifth D flip-flops are Q1, Q2, Q3, Q4, and Q5, respectively. The two input terminals of the first OR gate are used to receive the bit. <4> and BIT <5> The output of the first OR gate is connected to the first input of the first AND gate. The second input of the first AND gate is used to receive Q2, and the two inputs of the second AND gate are used to receive BIT respectively. <5> And Q3, the two inputs of the third AND gate are respectively used to receive BIT <8> And Q4, the two inputs of the fourth AND gate are respectively used to receive BIT <10> Q5, the output terminals of the first AND gate, the second AND gate, the third AND gate, and the fourth AND gate are respectively connected to the four input terminals of the NOR gate, and the output terminal of the NOR gate is used to output D1;

[0018] The two inputs of the second OR gate are used to receive the bit. <4> and BIT <5> The output of the second OR gate is connected to the first input of the fifth AND gate, the second input of the fifth AND gate is used to receive Q2, and the two inputs of the sixth AND gate are used to receive BIT respectively. <8> And Q4, the two inputs of the seventh AND gate are respectively used to receive BIT <10> Q5, the outputs of the fifth AND gate, the sixth AND gate, and the seventh AND gate are respectively connected to the three inputs of the third OR gate, the output of the third OR gate is connected to the second input of the eighth AND gate, the first input of the eighth AND gate is used to receive Q1, and the output of the eighth AND gate is used to output SEL_OUT.

[0019] Preferably, when BIT <10> When BIT = 1 and both BIT<9:1> are 0, the N-bit shift register is a 10-bit serializer; when BIT <8> When BIT<7:1> and BIT<10:9> are both 0, the N-bit shift register is an 8-bit serializer; when BIT<7:1> and BIT<10:9> are both 0, the N-bit shift register is an 8-bit serializer. <5> When BIT<4:1> and BIT<0:6> are both 0, the N-bit shift register is a 5-bit serializer; when BIT<4:1> and BIT<0:6> are both 0, the N-bit shift register is a 5-bit serializer. <4> When the value is 1 and both BIT<3:1> and BIT<10:5> are 0, the N-bit shift register is a 4-bit serializer.

[0020] Preferably, the multi-to-one serializer includes: a first frequency divider, a second frequency divider, a first two-to-one signal selection module, a second two-to-one signal selection module, a third two-to-one signal selection module, and a sixth D flip-flop;

[0021] In this configuration, the input terminal of the first frequency divider and the CLK terminal of the sixth D flip-flop are both used to receive the CLK clock signal. The output terminal of the first frequency divider is connected to the input terminal of the second frequency divider and the control terminal of the third 2-to-1 signal selection module. The output terminal of the second frequency divider is connected to the control terminals of the first and second 2-to-1 signal selection modules. The two input terminals of the first and second 2-to-1 signal selection modules are used to receive the output signals of four N-bit shift registers. The output terminals of the first and second 2-to-1 signal selection modules are connected to the two input terminals of the third 2-to-1 signal selection module. The output terminal of the third 2-to-1 signal selection module is connected to the D terminal of the sixth D flip-flop. The Q terminal of the sixth D flip-flop is used to output serial data.

[0022] Preferably, the multi-to-one serializer includes: a fourth 2-to-1 signal selection module, a fifth 2-to-1 signal selection module, a sixth 2-to-1 signal selection module, a seventh 2-to-1 signal selection module, an eighth 2-to-1 signal selection module, a ninth 2-to-1 signal selection module, a twelfth 2-to-1 signal selection module, a seventh D flip-flop, a fourth OR gate, a fifth OR gate, a sixth OR gate, a third 2-divider, a fourth 2-divider, and a fifth 2-divider;

[0023] Specifically, the two input terminals of the fourth 2-to-1 signal selection module, the two input terminals of the fifth 2-to-1 signal selection module, the two input terminals of the sixth 2-to-1 signal selection module, and the two input terminals of the seventh 2-to-1 signal selection module are respectively used to receive the output signals of 8 N-bit shift registers. The output terminals of the fourth and fifth 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the eighth 2-to-1 signal selection module. The output terminals of the sixth and seventh 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the ninth 2-to-1 signal selection module. The output terminals of the eighth and ninth 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the twelfth 2-to-1 signal selection module. The output terminal of the twelfth 2-to-1 signal selection module is connected to the D terminal of the seventh D flip-flop. The output terminal of the fourth OR gate is respectively connected to the control terminal of the fourth 2-to-1 signal selection module, the... The control terminals of the fifth 2-to-1 signal selection module, the sixth 2-to-1 signal selection module, and the seventh 2-to-1 signal selection module are connected. The output terminal of the fifth OR gate is connected to the control terminals of the eighth and ninth 2-to-1 signal selection modules, respectively. The output terminal of the sixth OR gate is connected to the control terminal of the twelfth 2-to-1 signal selection module. The CLK terminal of the seventh D flip-flop and the input terminal of the third frequency divider are both used to receive the CLK clock signal. The output terminal of the third frequency divider is connected to the input terminal of the fourth frequency divider and the first input terminal of the sixth OR gate, respectively. The output terminal of the fourth frequency divider is connected to the input terminal of the fifth frequency divider and the first input terminal of the fifth OR gate, respectively. The output terminal of the fifth frequency divider is connected to the first input terminal of the fourth OR gate. The second input terminals of the fourth OR gate, the fifth OR gate, and the sixth OR gate are respectively used to receive the corresponding selection signals. The Q terminal of the seventh D flip-flop is the output terminal of the multiple-to-one serializer.

[0024] When the selection signals received by the second input terminals of the fourth OR gate, the fifth OR gate, and the sixth OR gate are all high, the multi-to-one serializer is a serializer that converts 8 bits of parallel data into 1 bit of serial data.

[0025] When the selection signal received at the second input of the fourth OR gate is low, and the selection signals received at the second inputs of the fifth OR gate and the second input of the sixth OR gate are both high, the multi-to-one serializer is a serializer that converts 4 bits of parallel data into 1 bit of serial data.

[0026] When the selection signals received by the second input terminals of the fourth OR gate and the fifth OR gate are both low, and the selection signal received by the second input terminal of the sixth OR gate is high, the multi-to-one serializer is a serializer that converts 2 bits of parallel data into 1 bit of serial data.

[0027] To address the aforementioned technical problems, the present invention also provides a high-speed interface, including a high-speed serializer with selectable bit length as disclosed above.

[0028] Beneficial effects: In the high-speed serializer with selectable bit length provided by the present invention, multiple shift registers and a tree structure serializer are provided. The selection signals corresponding to the two-to-one signal selection modules in the shift registers are independent of each other, and the tree structure serializer is used to convert the data output by the multiple shift registers into serial data.

[0029] Since the high-speed serializer provided by this invention combines a shift register and a tree-structured serializer, when converting parallel data to serial data of the same bit length, a smaller-bit shift register first converts the parallel data to serial data. Then, the tree-structured serializer converts the serial data output from each shift register into serial data of a larger bit length in parallel. When supporting parallel-to-serial conversion outputs of different bit lengths, only the selection signals of the two-to-one selection modules of the shift register need to be selected, eliminating the need for multiple serializers and significantly reducing the hardware overhead required by the serializer. Furthermore, compared to existing technologies, when implementing parallel-to-serial conversion of the same bit length, the number of D flip-flops in the phase-shift register can be reduced, thereby greatly reducing the power consumption required by the serializer.

[0030] Correspondingly, the high-speed interface provided by this invention also has the above-mentioned beneficial effects. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 A structural diagram of a high-speed serializer with selectable bit width provided in an embodiment of the present invention;

[0033] Figure 2 This is a structural diagram of a shift register in the prior art;

[0034] Figure 3 This is a structural diagram of a multi-to-one serializer provided in an embodiment of the present invention;

[0035] Figure 4 This is a structural diagram of another multi-to-one serializer provided in an embodiment of the present invention;

[0036] Figure 5 This is a structural diagram of an N-bit shift register provided in an embodiment of the present invention;

[0037] Figure 6 for Figure 5 A schematic diagram showing the acquisition of the selection signals corresponding to each signal selection module;

[0038] Figure 7 A schematic diagram of M cascaded D flip-flops;

[0039] Figure 8 Here is a structural diagram of a 10-bit shift register;

[0040] Figure 9 This is a structural diagram of a D flip-flop module provided in an embodiment of the present invention;

[0041] Figure 10 A waveform diagram of a 10-bit serializer;

[0042] Figure 11 This is a waveform diagram of an 8-bit serializer. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please see Figure 1 , Figure 1 The present invention provides a structural diagram of a high-speed serializer with selectable bit width, which includes: a plurality of shift registers 11 and a tree-structured serializer 12 for converting the data output by the plurality of shift registers 11 into serial data; the selection signals corresponding to each two-to-one signal selection module in the shift registers 11 are independent of each other;

[0045] In this configuration, each signal input terminal of the tree-structured serializer 12 is connected to the signal output terminals of multiple shift registers 11.

[0046] In this embodiment, a high-speed serializer with selectable bit width is provided. The high-speed serializer includes multiple shift registers 11 and a tree-structured serializer 12 connected to the multiple shift registers 11. The selection signals corresponding to the two-to-one signal selection modules in each shift register 11 are independent of each other, and the tree-structured serializer 12 is used to convert the data output from the multiple shift registers 11 into serial data.

[0047] Please see Figure 2 , Figure 2 This is a structural diagram of a shift register in the prior art. Figure 2 In this context, MUX represents a 2-to-1 multiplexer selection module, D represents a D flip-flop, CLK represents the clock signal, and SEL represents the selection signal corresponding to each 2-to-1 multiplexer selection module. <0> To D <n-1>This represents n-bit parallel input data, and DOUT represents the output signal of the phase shift register.

[0048] Figure 2 The shift register in the array can perform parallel-to-serial conversion of any number of bits; however, this configuration requires all D flip-flops to operate at the highest clock frequency, resulting in high timing requirements and significant power consumption. Figure 2 In the shift register shown, the selection signal SEL corresponding to each 2-to-1 selection module MUX is the same. Under this setting, only parallel-to-serial conversion output with a fixed number of bits can be achieved, but parallel-to-serial conversion output with different bit numbers cannot be achieved.

[0049] This application improves upon the structure of existing shift registers by making the selection signals of each 2-to-1 multiplexer module independent. Clearly, with this configuration, only the selection signals of each 2-to-1 multiplexer module need to be selected for output, allowing the shift register to support parallel-to-serial conversion outputs of different bit lengths. This eliminates the need for multiple serializers to support parallel-to-serial conversion outputs of different bit lengths, thus significantly reducing the hardware overhead required for the shift register.

[0050] Because the tree-structured serializer 12 can achieve 2 n To convert parallel data into serial data, a shift register 11 is connected to the signal input of the tree-structured serializer 12. The tree-structured serializer 12 can then convert the data output from multiple shift registers 11 into serial data. With this configuration, when implementing parallel-to-serial conversion of the same bit length, compared to using a simple shift register to achieve the same bit length, the number of D flip-flops in the phase-shift register can be reduced, thereby reducing the power consumption of the serializer.

[0051] In other words, since the high-speed serializer provided in this embodiment combines a shift register and a tree-structured serializer, when converting parallel data to serial data of the same bit length, a smaller-bit shift register can first convert the parallel data to serial data. Then, the tree-structured serializer converts the serial data output from each shift register into serial data of a larger bit length in parallel. When supporting parallel-to-serial conversion outputs of different bit lengths, only the selection signals of the two-to-one selection modules of the shift register need to be selected for output, eliminating the need for multiple sets of serializers. This significantly reduces the hardware overhead required by the serializer. Furthermore, compared to existing technologies, when implementing parallel-to-serial conversion of the same bit length, the number of D flip-flops in the phase-shift register can be reduced, thereby greatly reducing the power consumption required by the serializer.

[0052] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the multiple shift registers include: 2 a All N-bit shift registers with identical configurations, where N ≥ 2, and the tree-structured serializer is used to transfer 2 bits. a A multi-to-one serializer that converts parallel data of bits into serial data of 1 bit, where a ≥ 2.

[0053] In practical applications, different combinations of shift registers and multi-to-one serializers can achieve parallel-to-serial conversion with varying bit widths. Here, 'a' represents the number of cascaded stages of the 2-to-1 multiplexer selection module in the tree-structured serializer.

[0054] For example, when a multi-to-one serializer is a 4-to-1 serializer (a 4-to-1 serializer can convert 4 bits of parallel data into 1 bit of serial data), if a 5-bit shift register is connected to each of the four inputs of the 4-to-1 serializer, this combination can convert 20 bits of parallel data into 1 bit of serial data. When the multi-to-one serializer is a 4-to-1 serializer, if a 10-bit shift register is connected to each of the four inputs of the 4-to-1 serializer, this combination can convert 40 bits of parallel data into 1 bit of serial data.

[0055] When the multi-to-one serializer is an 8-to-1 serializer (a 4-to-1 serializer can convert 4 bits of parallel data into 1 bit of serial data), if a 5-bit shift register is connected to each of the 8 inputs of the 8-to-1 serializer, this combination can convert 40 bits of parallel data into 1 bit of serial data. When the multi-to-one serializer is an 8-to-1 serializer, if a 10-bit shift register is connected to each of the 8 inputs of the 8-to-1 serializer, this combination can convert 80 bits of parallel data into 1 bit of serial data.

[0056] As described above, to convert 40 bits of parallel data into 1 bit of serial data, one can use either a 4-to-1 serializer and four 10-bit shift registers, or an 8-to-1 serializer and eight 5-bit shift registers. Of course, in practical applications, other implementations using shift registers and multi-to-1 serializers may exist; the choice should be based on the specific application scenario.

[0057] In other words, to convert parallel data to serial data with a specific number of bits, different combinations of shift registers and multi-to-one serializers can be used. In this case, the number of bits of the multi-to-one serializer and the number and quantity of bits of the shift register should be adaptively selected based on the resource overhead, device footprint, and clock frequency in the actual application scenario.

[0058] In practical applications, common serializers typically need to convert 8-bit, 16-bit, 20-bit, 32-bit, and 40-bit parallel data into serial data, while it is rare to need to convert odd-numbered bits of parallel data, such as 13-bit, 14-bit, 19-bit, and 21-bit, into serial data.

[0059] Therefore, in order to improve the versatility of the high-speed serializer provided in this application in practical applications, the common factor 4 can be extracted. First, a 4-to-1 serializer can be designed. Then, an N-bit shift register can be connected to each of the four input terminals of the 4-to-1 serializer. In this way, 4 bits of N-bit parallel data can be converted into 1 bit of serial data.

[0060] Please see Figure 3 , Figure 3 This is a structural diagram of a multi-to-one serializer provided in an embodiment of the present invention. In a preferred embodiment, the multi-to-one serializer includes: a first frequency divider F1, a second frequency divider F2, a first two-to-one signal selection module MUX1, a second two-to-one signal selection module MUX2, a third two-to-one signal selection module MUX3, and a sixth D flip-flop D6;

[0061] In this system, the input of the first frequency divider F1 and the CLK terminal of the sixth D flip-flop D6 are both used to receive the CLK clock signal. The output of the first frequency divider F1 is connected to the input of the second frequency divider F2 and the control terminal of the third 2-to-1 signal selection module MUX3. The output of the second frequency divider F2 is connected to the control terminals of the first 2-to-1 signal selection module MUX1 and the second 2-to-1 signal selection module MUX2. The two inputs of the first 2-to-1 signal selection module MUX1 and the two inputs of the second 2-to-1 signal selection module MUX2 are used to receive the output signals of four N-bit shift registers. The outputs of the first 2-to-1 signal selection module MUX1 and the second 2-to-1 signal selection module MUX2 are connected to the two inputs of the third 2-to-1 signal selection module MUX3. The output of the third 2-to-1 signal selection module MUX3 is connected to the D terminal of the sixth D flip-flop D6. The Q terminal of the sixth D flip-flop D6 is used to output serial data.

[0062] exist Figure 3 The multi-to-one serializer shown can convert 4 bits of N-bit parallel data into 1 bit of serial data; that is, it is a 4-to-1 serializer. The two inputs of the first 2-to-1 signal selection module MUX1 and the two inputs of the second 2-to-1 signal selection module MUX2 are used to receive the output signals of four N-bit shift registers. Figure 3 In the middle, D <0> D <1> D <2> and D <3> These represent the output signals of four N-bit shift registers. This multi-to-one serializer can convert the 4-bit parallel data output from the four N-bit shift registers into 1-bit serial data.

[0063] Please see Figure 4 , Figure 4 This is a structural diagram of another multi-to-one serializer provided in an embodiment of the present invention. In a preferred embodiment, the multi-to-one serializer includes: a fourth 2-to-1 signal selection module MUX4, a fifth 2-to-1 signal selection module MUX5, a sixth 2-to-1 signal selection module MUX6, a seventh 2-to-1 signal selection module MUX7, an eighth 2-to-1 signal selection module MUX8, a ninth 2-to-1 signal selection module MUX9, a twelfth 2-to-1 signal selection module MUX10, a seventh D flip-flop D7, a fourth OR gate OR4, a fifth OR gate OR5, a sixth OR gate OR6, a third frequency divider F3, a fourth frequency divider F4, and a fifth frequency divider F5.

[0064] Among them, the two input terminals of the fourth 2-to-1 signal selection module MUX4, the two input terminals of the fifth 2-to-1 signal selection module MUX5, the two input terminals of the sixth 2-to-1 signal selection module MUX6, and the two input terminals of the seventh 2-to-1 signal selection module MUX7 are respectively used to receive the output signals of the eight N-bit shift registers. The output terminals of the fourth 2-to-1 signal selection module MUX4 and the fifth 2-to-1 signal selection module MUX5 are respectively connected to the first and second input terminals of the eighth 2-to-1 signal selection module MUX8. The sixth 2-to-1 signal selection module MUX7... The outputs of X6 and the seventh 2-to-1 signal selection module MUX7 are connected to the first and second inputs of the ninth 2-to-1 signal selection module MUX9, respectively. The outputs of the eighth 2-to-1 signal selection module MUX8 and the ninth 2-to-1 signal selection module MUX9 are connected to the first and second inputs of the twelfth 2-to-1 signal selection module MUX10, respectively. The output of the twelfth 2-to-1 signal selection module MUX10 is connected to the D terminal of the seventh D flip-flop D7. The output of the fourth OR gate OR4 is connected to the fourth 2-to-1 signal selection module MUX4. The control terminals of the first, second, and third 2-to-1 signal selection modules are connected to the control terminals of the fifth 2-to-1 signal selection module MUX5, the sixth 2-to-1 signal selection module MUX6, and the seventh 2-to-1 signal selection module MUX7. The output terminal of the fifth OR gate OR5 is connected to the control terminals of the eighth 2-to-1 signal selection module MUX8 and the ninth 2-to-1 signal selection module MUX9, respectively. The output terminal of the sixth OR gate OR6 is connected to the control terminal of the twelfth 1-to-1 signal selection module MUX10. The CLK terminal of the seventh D flip-flop D7 and the input terminal of the third frequency divider F3 are both used to receive the CLK clock signal. The output of the third frequency divider F3 is connected to the input of the fourth frequency divider F4 and the first input of the sixth OR gate OR6. The output of the fourth frequency divider F4 is connected to the input of the fifth frequency divider F5 and the first input of the fifth OR gate OR5. The output of the fifth frequency divider F5 is connected to the first input of the fourth OR gate OR4. The second inputs of the fourth OR gate OR4, the fifth OR gate OR5, and the sixth OR gate OR6 are used to receive the corresponding selection signals. The Q terminal of the seventh D flip-flop D7 is the output of the multi-to-one serializer.

[0065] When the selection signals received at the second input terminals of the fourth OR gate OR4, the fifth OR gate OR5, and the sixth OR gate OR6 are all high, the multi-to-one serializer is a serializer that converts 8 bits of parallel data into 1 bit of serial data.

[0066] When the selection signal received at the second input of the fourth OR gate OR4 is low, and the selection signals received at the second inputs of the fifth OR gate OR5 and the sixth OR gate OR6 are both high, the multi-to-one serializer is a serializer that converts 4 bits of parallel data into 1 bit of serial data.

[0067] When the selection signals received at the second input of the fourth OR gate OR4 and the second input of the fifth OR gate OR5 are both low, and the selection signal received at the second input of the sixth OR gate OR6 is high, the multi-to-one serializer is a serializer that converts 2 bits of parallel data into 1 bit of serial data.

[0068] In this embodiment, a tree-structured serializer with selectable bit depth is provided to improve the flexibility and versatility of the tree-structured serializer in use. That is, this multi-to-one serializer can convert 8 bits of parallel data into 1 bit of serial data, 4 bits of parallel data into 1 bit of serial data, and 2 bits of parallel data into 1 bit of serial data.

[0069] Assume that the output signals of the N-bit shift register received by the two input terminals of the fourth 2-to-1 signal selection module MUX4, the two input terminals of the fifth 2-to-1 signal selection module MUX5, the two input terminals of the sixth 2-to-1 signal selection module MUX6, and the two input terminals of the seventh 2-to-1 signal selection module MUX7 are D respectively. <7> D <6> D <5> D <4> D <3> D <2> D <1> D <0> .

[0070] When the selection signals SEL01, SEL02, and SEL03 received at the second input terminals of the fourth OR gate (OR4), the fifth OR gate (OR5), and the sixth OR gate (OR6) are all high, the corresponding clock signals for the fourth OR gate (OR4), the fifth OR gate (OR5), and the sixth OR gate (OR6) are CLK / 8, CLK / 4, and CLK / 2, respectively. At this time, the multi-to-1 serializer becomes an 8-to-1 serializer, capable of converting D... <7> D <6> D <5> D <4> D <3> D <2> D <1> and D <0> Converted into 1-bit serial data.

[0071] When the selection signal SEL01 received at the second input of the fourth OR gate OR4 is low, and the selection signals SEL02 and SEL03 received at the second inputs of the fifth OR gate OR5 and the sixth OR gate OR6 are both high, the clock signals corresponding to the fourth OR gate OR4, the fifth OR gate OR5, and the sixth OR gate OR6 are 1, CLK / 4, and CLK / 2, respectively. At this time, the multi-to-1 serializer becomes a 4-to-1 serializer, capable of converting D... <6> D <4> D <2> and D <0> Converted into 1-bit serial data.

[0072] When the selection signals SEL01 and SEL02 received at the second inputs of the fourth OR gate OR4 and the fifth OR gate OR5 are both low, and the selection signal SEL03 received at the second input of the sixth OR gate OR6 is high, the clock signals corresponding to the fourth OR gate OR4, the fifth OR gate OR5, and the sixth OR gate OR6 are 1, 1, and CLK / 2, respectively. At this time, the multi-to-1 serializer becomes a 2-to-1 serializer, capable of converting D... <4> and D <0> Converted into 1-bit serial data.

[0073] Please see Figure 5 , Figure 5 This is a structural diagram of an N-bit shift register provided in an embodiment of the present invention. In a preferred embodiment, the N-bit shift register includes: N D flip-flops and N-1 two-to-one multiplexer modules;

[0074] In this system, the CLK terminals of all N D flip-flops are used to receive the CLK clock signal. The D terminal of the j-th D flip-flop is connected to the output terminal of the j-th 2-to-1 signal selection module. The Q terminal of the (j+1)-th D flip-flop is connected to the second input terminal of the j-th 2-to-1 signal selection module. 1≤j≤N-14. The Q terminal of the 1st D flip-flop is the signal output terminal of the N-bit shift register. The first input terminal of each 2-to-1 signal selection module and the D terminal of the Nth D flip-flop are used to receive N parallel data.

[0075] exist Figure 5 The N-bit shift register shown contains N D flip-flops and N-1 2-to-1 multiplexer selection modules (MUX). Each MUX has an independent selection signal, allowing the user to customize the number of bits used for parallel-to-serial conversion within the N-bit shift register. That is, in... Figure 5 In the phase-shift register shown, the selection signal SEL corresponding to each signal selection module MUX is... <1> SEL <2> ...SEL <n-1>and SEL <n>They are independent of each other.

[0076] As a preferred implementation, the expression for the selection signal corresponding to the k-th two-to-one selection module in the N-bit shift register is: SEL <k>=SEL OUT+BIT <k>,1≤k≤N-1;BIT <k>The SEL_OUT is used to represent the number of bits used for parallel-to-serial conversion in a high-speed serializer. It is obtained by recursively summarizing the output signals of M cascaded D flip-flops; M = N / 2, and the value of M is rounded up.

[0077] In this embodiment, in order to obtain the specific expression of the selection signal corresponding to the k-th two-to-one signal selection module in the N-bit shift register, the expression of the selection signal corresponding to the k-th two-to-one signal selection module in the N-bit shift register is obtained by recursively summarizing the output signals of multiple cascaded D flip-flops.

[0078] Specifically, SEL_OUT = Q1·(S 2，3 ·Q1+S 4，5 ·Q2+...+S2i,2i+1·Qi+...S 2M，2M+1 ·QM);

[0079] Qi is the signal output from the Q terminal of the i-th D flip-flop among M D flip-flops;

[0080]

[0081] D1 is the signal input to the D terminal of the first D flip-flop among the M D flip-flops;

[0082] S 2i-1，2i =BIT<2i-1>+BIT<2i>, 1≤i≤M;

[0083] S 2i-1，2i，2i+1 =BIT(2i-1>+BIT<2i>+BIT<2i+1>.

[0084] Please see Figure 6 , Figure 6 for Figure 5 A schematic diagram illustrating the acquisition of the selection signals corresponding to each signal selection module. Figure 6 SEL <k>=SEL OUT+BIT <k>,1≤k≤N-1;BIT <k>The SEL_OUT value, used to represent the number of bits used for parallel-to-serial conversion in a high-speed serializer, is obtained by recursively summarizing the output signals of M cascaded D flip-flops. See also... Figure 7 , Figure 7 This is a schematic diagram of M cascaded D flip-flops.

[0085] In practical applications, if a phase shift register with selectable bit widths of 4 bits, 5 bits, 8 bits, and 10 bits is required, the above expression can be used to determine the selection signals corresponding to each D flip-flop and the 2-to-1 multiplexer in the phase shift register.

[0086] Specifically, since the maximum number of bits for 4-bit, 5-bit, 8-bit, and 10-bit is 10, in the above derivation formula, N = 10, M = N / 2 = 10 / 2 = 5;

[0087] Substituting into the above expression, we can obtain the selection signal corresponding to the k-th two-to-one selection module in the phase shift register as: SEL <k>=SEL_OUT+BIT <k>, 1≤k≤N-1;

[0088] The intermediate signal SEL_OUT = Q1·(S 4，5 ·Q2+S 8，9 ·Q4+S 10，11 ·Q5);

[0089]

[0090] S 2i-1，2i =BIT<2i-1>+BIT<2i>, 1≤i≤5;

[0091] S 2i-1，2i，2i+1 =BIT<2i-1>+BIT<2i>+BIT<2i+1>, 1≤i≤5;

[0092] Simplifying the above formula, we get:

[0093] SEL_OUT=Q1·[(BIT <4> +BIT <5> Q2+BIT <8> Q4+BIT <10> ·Q5];

[0094]

[0095] It should be noted that the above expression only indicates non-zero terms; zero terms are not represented in the expression. For example, when creating a phase-shift register with selectable bit widths of 4, 5, 8, and 10 bits, it indicates that the number of bits is 10. <1> =0, BIT <2> =0, BIT <3> =0, BIT <3> =0, BIT <7> =0, BIT <9> =0, while BIT <4> =1, BIT <5> =1, BIT <8> =1, BIT <10> =1.

[0096] In practical applications, to reduce the structural complexity of the selectable bit-count high-speed serializer and ensure it meets the application requirements of real-world scenarios, the N-bit shift register can be set to a 10-bit shift register. The selection signal corresponding to the k-th 2-to-1 multiplexer in the 10-bit shift register is determined by SEL_OUT and BIT. <k>Produced by OR gate.

[0097] Please see Figure 8 , Figure 8 This is a structural diagram of a 10-bit shift register. Figure 8 In the diagram, D1, D2, D3...D9 and D10 represent D flip-flops in a 10-bit shift register, and MUX1, MUX2...MUX9 represent 2-to-1 multiplexer selection modules in a 10-bit shift register. <1> D <2> ...D <10> These represent the input parallel data. The selection signals corresponding to each 2-to-1 multiplexer module in the 10-bit shift register are independent of each other, and the selection signal SEL corresponding to the k-th 2-to-1 multiplexer module is independent of each other. <k>By SEL_OUT and BIT <k>Produced by OR gate, 1≤k≤9.

[0098] Please see Figure 9 , Figure 9 This is a structural diagram of a D flip-flop module provided in an embodiment of the present invention. In a preferred embodiment, SEL_OUT is generated by the D flip-flop module; the D flip-flop module includes: a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, and a NOR gate.

[0099] In this circuit, the CLK terminals of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, and the fifth D flip-flop D5 are all used to receive the CLK clock signal. The Q terminal of the first D flip-flop D1 is connected to the D terminal of the second D flip-flop D2, the Q terminal of the second D flip-flop D2 is connected to the D terminal of the third D flip-flop D3, the Q terminal of the third D flip-flop D3 is connected to the D terminal of the fourth D flip-flop D4, and the Q terminal of the fourth D flip-flop D4 is connected to the D terminal of the fifth D flip-flop D5. The input signal of the D terminal of the first D flip-flop D1 is D1. The output signals of the Q terminals of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, and the fifth D flip-flop D5 are Q1, Q2, Q3, Q4, and Q5, respectively.

[0100] The two inputs of the first OR gate OR1 are used to receive bits. <4> and BIT <5> The output of the first OR gate (OR1) is connected to the first input of the first AND gate (AND1). The second input of the first AND gate (AND1) is used to receive Q2, and the two inputs of the second AND gate (AND2) are used to receive bits respectively. <5> And Q3, the two inputs of the third AND gate AND3 are used to receive bits. <8> Q4, the two inputs of the fourth AND gate AND4 are used to receive bits. <10> Q5, the outputs of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3, and the fourth AND gate AND4 are respectively connected to the four inputs of the NOR gate NOR, and the output of the NOR gate NOR is used to output D1;

[0101] The two inputs of the second OR gate OR2 are used to receive the bit. <4> and BIT <5> The output of the second OR gate (OR2) is connected to the first input of the fifth AND gate (AND5). The second input of the fifth AND gate (AND5) is used to receive Q2. The two inputs of the sixth AND gate (AND6) are used to receive bits respectively. <8> Q4, and the two inputs of the seventh AND gate AND7 are used to receive bits. <10> Q5, the outputs of the fifth AND gate AND5, the sixth AND gate AND6, and the seventh AND gate AND7 are respectively connected to the three inputs of the third OR gate OR3. The output of the third OR gate OR3 is connected to the second input of the eighth AND gate AND8. The first input of the eighth AND gate AND8 is used to receive Q1, and the output of the eighth AND gate AND8 is used to output SEL_OUT.

[0102] In this embodiment, the structure of the D flip-flop module used to generate SEL_OUT is specifically described. The D flip-flop module consists of five D flip-flops. The input signal of the D terminal of the first D flip-flop D1 is D1, and the output signals of the Q terminals of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, and the fifth D flip-flop D5 are Q1, Q2, Q3, Q4, and Q5, respectively.

[0103] The input signal D1 at the D terminal of the first D flip-flop D1 can be bitped by the first OR gate (OR1), the first AND gate (AND1), the second AND gate (AND2), the third AND gate (AND3), the fourth AND gate (AND4), and the NOR gate (NOR). <4> BIT <5> BIT <8> BIT <10> The signal is obtained by performing logical operations on Q2, Q3, Q4, and Q5, while the intermediate signal SEL_OUT can be obtained through the second OR gate OR2, the third OR gate OR3, and the bit gate. <4> BIT <5> BIT <8> BIT <10> The results are obtained by performing logical operations on Q1, Q2, Q4, and Q5.

[0104] It is important to note that Figure 9 The input signal D1 at the D terminal of the first D flip-flop D1 shown can be obtained from the formula... It is derived that, Figure 8 The selection signal SEL corresponding to the k-th two-to-one selection module. <k>By SEL_OUT and BIT <k>The signal SEL_OUT generated by the OR gate, where 1≤k≤9, can be expressed by the formula SEL_OUT=Q1·[(BIT <4> +BIT <5> Q2+BIT <8> Q4+BIT <10> [Q5] The derivation process for obtaining SEL_OUT can be found in [link to Q5]. Figure 9 The content shown.

[0105] As a preferred implementation, when BIT <10> When BIT = 1 and both BIT<9:1> are 0, the N-bit shift register is a 10-bit serializer; when BIT <8> When BIT = 1 and both BIT<7:1> and BIT<10:9> are 0, the N-bit shift register is an 8-bit serializer; when BIT = 1, the N-bit shift register is an 8-bit serializer. <5> When BIT(4:1>) and BIT(10:6> are both 0, the N-bit shift register is a 5-bit serializer; when BIT(4:1>) is 1, the N-bit shift register is a 5-bit serializer. <4> When the value is 1 and both BIT<3:1> and BIT<10:5> are 0, the N-bit shift register is a 4-bit serializer.

[0106] In this embodiment, when BIT <10> When = 1 and both BIT<9:1> are 0, the N-bit shift register is a 10-bit serializer. See also Figure 10 , Figure 10 This is a waveform diagram of a 10-bit serializer. Figure 10 In this context, D<10:1> represents 10-bit parallel input data, and SEL_OUT represents the selection signal SEL corresponding to the k-th 2-to-1 selection module in the 10-bit serializer. <k>The intermediate signals involved are as follows: SEL_OUT has a pulse width equal to one clock cycle, and SEL_OUT has a period equal to 10 times the clock cycle. CLK represents the clock signal of the 10-bit serializer, and DOUT represents the serialized data after serializing the 10-bit input parallel data.

[0107] When BIT <8> When the bitwise N-bit shift register is 1 and both BIT<7∶1> and BIT<10∶9> are 0, it is an 8-bit serializer. (See also...) Figure 11 , Figure 11 This is a waveform diagram of an 8-bit serializer. Figure 11 In this context, D<8:1> represents 8-bit parallel input data, and SEL_OUT represents the selection signal SEL corresponding to the k-th 2-to-1 selection module in the 8-bit serializer. <k>The intermediate signals involved are as follows: SEL_OUT has a pulse width equal to one clock cycle, and SEL_OUT has a period equal to eight times the clock cycle. CLK represents the clock signal of the 8-bit serializer, and DOUT represents the serialized data after serializing the 8-bit parallel input data.

[0108] When BIT <5> When BIT = 1 and both BIT<4:1> and BIT<10:6> are 0, the N-bit shift register is a 5-bit serializer. <4> When the value is 1 and both BIT<3:1> and BIT<10:5> are 0, the N-bit shift register is a 4-bit serializer. The waveforms of the 5-bit and 4-bit serializers are similar to those of the 10-bit and 8-bit serializers, and will not be described in detail here.

[0109] Accordingly, embodiments of the present invention also provide a high-speed interface, including a high-speed serializer with selectable bit length as disclosed above.

[0110] The high-speed interface provided in this embodiment of the invention has the beneficial effects of the aforementioned optional bit-level high-speed serializer.

[0111] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0112] The above provides a detailed description of a high-speed serializer with selectable bit width and a high-speed interface provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.< / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / n> < / k> < / k> < / k>

Claims

1. A high-speed serializer with selectable bit width, characterized in that, include: Multiple shift registers and a tree-structured serializer for converting the data output from the multiple shift registers into serial data; the selection signals corresponding to each 2-to-1 selection module in the shift registers are independent of each other; Each signal input terminal of the tree-structured serializer is connected to the signal output terminals of multiple shift registers.

2. The high-speed serializer with selectable bit width according to claim 1, characterized in that, Multiple shift registers include: 2 a There are N shift registers with identical configurations, where N ≥ 2, and the tree-structured serializer is used to transfer 2... a A multi-to-one serializer that converts N bits of parallel data into 1 bit of serial data, where a ≥ 2.

3. A high-speed serializer with selectable bit depth according to claim 2, characterized in that, The N-bit shift register includes: N D flip-flops and N-1 two-to-one signal selection modules; In this system, the CLK terminals of all N D flip-flops are used to receive the CLK clock signal. The D terminal of the j-th D flip-flop is connected to the output terminal of the j-th 2-to-1 signal selection module, and the Q terminal of the (j+1)-th D flip-flop is connected to the second input terminal of the j-th 2-to-1 signal selection module. 1≤j≤N-1. The Q terminal of the 1-th D flip-flop is the signal output terminal of the N-bit shift register. The first input terminal of each 2-to-1 signal selection module and the D terminal of the N-th D flip-flop are used to receive N parallel data.

4. A high-speed serializer with selectable bit depth according to claim 2, characterized in that, The expression for the selection signal corresponding to the k-th two-to-one selection module in the N-bit shift register is: SEL <k>=SEL_OUT+BIT <k>,1≤k≤N-1;BIT <k> The number of bits used to represent the parallel-to-serial conversion of the high-speed serializer, SELOUT, is obtained by recursively summarizing the output signals of M cascaded D flip-flops; M = N / 2, and the value of M is rounded up.< / k> < / k> < / k> 5. A high-speed serializer with selectable bit depth according to claim 4, characterized in that, SEL_OUT=Q1·(S 2，3 ·Q1+S 4，5 ·Q2+…+S 2i,2i+1 Qi+…S 2M，2M+1 ·QM), where Qi is the signal output from the Q terminal of the i-th D flip-flop among the M D flip-flops; D1 is the signal input to the D terminal of the first D flip-flop among the M D flip-flops; S 2i-1，2i =BIT<2i-1>+BIT<2i>,1≤i≤M; S 2i-1，2i,2i+1 =BIT<2i-1>+BIT<2i>+BIT<2i+1>。 6. A high-speed serializer with selectable bit depth according to claim 5, characterized in that, The N-bit shift register is specifically a 10-bit shift register, and the selection signal corresponding to the k-th 2-to-1 multiplexer in the 10-bit shift register is composed of SEL_OUT and BIT. <k> Produced by OR gate.< / k> 7. A high-speed serializer with selectable bit depth according to claim 6, characterized in that, SELOUT is generated by a D flip-flop module; the D flip-flop module includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first OR gate, a second OR gate, a third OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, and an OR NOT gate; In this configuration, the CLK terminals of the first, second, third, fourth, and fifth D flip-flops are all used to receive the CLK clock signal. The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop, the Q terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop, the Q terminal of the third D flip-flop is connected to the D terminal of the fourth D flip-flop, and the Q terminal of the fourth D flip-flop is connected to the D terminal of the fifth D flip-flop. The input signal of the D terminal of the first D flip-flop is D1. The output signals of the Q terminals of the first, second, third, fourth, and fifth D flip-flops are Q1, Q2, Q3, Q4, and Q5, respectively. The two input terminals of the first OR gate are used to receive the bit. <4> and BIT <5> The output of the first OR gate is connected to the first input of the first AND gate. The second input of the first AND gate is used to receive g2, and the two inputs of the second AND gate are used to receive BIT respectively. <5> And Q3, the two inputs of the third AND gate are respectively used to receive BIT <8> And Q4, the two inputs of the fourth AND gate are respectively used to receive BIT <10> Q5, the output terminals of the first AND gate, the second AND gate, the third AND gate, and the fourth AND gate are respectively connected to the four input terminals of the NOR gate, and the output terminal of the NOR gate is used to output the input signal D1 of the D terminal of the first D flip-flop; The two inputs of the second OR gate are used to receive the bit. <4> and BIT <5> The output of the second OR gate is connected to the first input of the fifth AND gate, the second input of the fifth AND gate is used to receive Q2, and the two inputs of the sixth AND gate are used to receive BIT respectively. <8> And Q4, the two inputs of the seventh AND gate are respectively used to receive BIT <10> Q5, the output terminals of the fifth AND gate, the sixth AND gate, and the seventh AND gate are respectively connected to the three input terminals of the third OR gate, the output terminal of the third OR gate is connected to the second input terminal of the eighth AND gate, the first input terminal of the eighth AND gate is used to receive Q1, and the output terminal of the eighth AND gate is used to output SELOUT.

8. A high-speed serializer with selectable bit depth according to claim 7, characterized in that, When BIT <10> When BIT = 1 and both BIT<9:1> are 0, the N-bit shift register is a 10-bit serializer; when BIT <8> When BIT<7:1> and BIT<10:9> are both 0, the N-bit shift register is an 8-bit serializer; when BIT<7:1> and BIT<10:9> are both 0, the N-bit shift register is an 8-bit serializer. <5> When BIT<4:1> and BIT<10:6> are both 0, the N-bit shift register is a 5-bit serializer; when BIT<4:1> and BIT<10:6> are both 0, the N-bit shift register is a 5-bit serializer. <4> When the value is 1 and both BIT<3:1> and BIT<10:5> are 0, the N-bit shift register is a 4-bit serializer.

9. A high-speed serializer with selectable bit depth according to claim 2, characterized in that, The multi-to-one serializer includes: a first frequency divider, a second frequency divider, a first two-to-one signal selection module, a second two-to-one signal selection module, a third two-to-one signal selection module, and a sixth D flip-flop; In this configuration, the input terminal of the first frequency divider and the CLK terminal of the sixth D flip-flop are both used to receive the CLK clock signal. The output terminal of the first frequency divider is connected to the input terminal of the second frequency divider and the control terminal of the third 2-to-1 signal selection module. The output terminal of the second frequency divider is connected to the control terminals of the first and second 2-to-1 signal selection modules. The two input terminals of the first and second 2-to-1 signal selection modules are used to receive the output signals of four N-bit shift registers. The output terminals of the first and second 2-to-1 signal selection modules are connected to the two input terminals of the third 2-to-1 signal selection module. The output terminal of the third 2-to-1 signal selection module is connected to the D terminal of the sixth D flip-flop. The Q terminal of the sixth D flip-flop is used to output serial data.

10. A high-speed serializer with selectable bit width according to claim 2, characterized in that, The multi-to-one serializer includes: a fourth 2-to-1 signal selection module, a fifth 2-to-1 signal selection module, a sixth 2-to-1 signal selection module, a seventh 2-to-1 signal selection module, an eighth 2-to-1 signal selection module, a ninth 2-to-1 signal selection module, a twelfth 2-to-1 signal selection module, a seventh D flip-flop, a fourth OR gate, a fifth OR gate, a sixth OR gate, a third 2-divider, a fourth 2-divider, and a fifth 2-divider; Specifically, the two input terminals of the fourth 2-to-1 signal selection module, the two input terminals of the fifth 2-to-1 signal selection module, the two input terminals of the sixth 2-to-1 signal selection module, and the two input terminals of the seventh 2-to-1 signal selection module are respectively used to receive the output signals of 8 N-bit shift registers. The output terminals of the fourth and fifth 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the eighth 2-to-1 signal selection module. The output terminals of the sixth and seventh 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the ninth 2-to-1 signal selection module. The output terminals of the eighth and ninth 2-to-1 signal selection modules are respectively connected to the first and second input terminals of the twelfth 2-to-1 signal selection module. The output terminal of the twelfth 2-to-1 signal selection module is connected to the D terminal of the seventh D flip-flop. The output terminal of the fourth OR gate is respectively connected to the control terminal of the fourth 2-to-1 signal selection module, the... The control terminals of the fifth 2-to-1 signal selection module, the sixth 2-to-1 signal selection module, and the seventh 2-to-1 signal selection module are connected. The output terminal of the fifth OR gate is connected to the control terminals of the eighth and ninth 2-to-1 signal selection modules, respectively. The output terminal of the sixth OR gate is connected to the control terminal of the twelfth 2-to-1 signal selection module. The CLK terminal of the seventh D flip-flop and the input terminal of the third frequency divider are both used to receive the CLK clock signal. The output terminal of the third frequency divider is connected to the input terminal of the fourth frequency divider and the first input terminal of the sixth OR gate, respectively. The output terminal of the fourth frequency divider is connected to the input terminal of the fifth frequency divider and the first input terminal of the fifth OR gate, respectively. The output terminal of the fifth frequency divider is connected to the first input terminal of the fourth OR gate. The second input terminals of the fourth OR gate, the fifth OR gate, and the sixth OR gate are respectively used to receive the corresponding selection signals. The Q terminal of the seventh D flip-flop is the output terminal of the multiple-to-one serializer. When the selection signals received by the second input terminals of the fourth OR gate, the fifth OR gate, and the sixth OR gate are all high, the multi-to-one serializer is a serializer that converts 8 bits of parallel data into 1 bit of serial data. When the selection signal received at the second input of the fourth OR gate is low, and the selection signals received at the second inputs of the fifth OR gate and the sixth OR gate are both high, the multi-to-one serializer is a serializer that converts 4 bits of parallel data into 1 bit of serial data. When the selection signals received by the second input terminals of the fourth OR gate and the fifth OR gate are both low, and the selection signal received by the second input terminal of the sixth OR gate is high, the multi-to-one serializer is a serializer that converts 2 bits of parallel data into 1 bit of serial data.

11. A high-speed interface, characterized in that, Includes a high-speed serializer with an optional number of bits as described in any one of claims 1 to 10.

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