eMMC testing method, device, readable storage medium and electronic device

Abstract

The present invention discloses an eMMC test method, device, readable storage medium and electronic device, which receive a steady-state performance test request of an eMMC chip to be tested; divide the eMMC chip to be tested into regions according to a first preset capacity according to the steady-state performance test request to obtain the divided eMMC chip to be tested; perform data read and write operations on the divided eMMC chip to be tested according to a second preset capacity, and save data read and write results corresponding to the data read and write operations; determine a steady-state performance test result corresponding to the steady-state performance test request based on the data read and write results, and perform testing with capacity as a test dimension, so as to test whether the steady-state performance of the eMMC chip is normal and accurately know whether the steady-state performance has declined, and is more convenient than a test method with time as a test dimension, reduces the tediousness of the test, and thus improves the convenience of the steady-state performance test.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an eMMC testing method, device, readable storage medium and electronic equipment. Background Art

[0002] eMMC chips (Embedded Multi Media Card) are widely used in various mobile electronic devices, and their performance is often tested using Androbench (a benchmark application). When the eMMC chip is used as a single storage device, if the traditional single steady-state performance test method is used, that is, after the test reaches the steady state, the bandwidth, latency, and IOPS (Input / Output Operations Per Second) are tested for a certain period of time (usually set to 6 hours) as the test duration, for users who only want to know whether the steady-state performance has dropped, this test method is too cumbersome and wastes a lot of test resources. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an eMMC testing method, device, readable storage medium and electronic device, which can improve the convenience of steady-state performance testing.

[0004] In order to solve the above technical problems, a technical solution adopted by the present invention is:

[0005] An eMMC testing method, comprising:

[0006] Receive a steady-state performance test request for the eMMC chip to be tested;

[0007] According to the steady-state performance test request, the eMMC chip to be tested is divided into regions according to a first preset capacity to obtain a divided eMMC chip to be tested;

[0008] Performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity, and saving data read and write results corresponding to the data read and write operations;

[0009] A steady-state performance test result corresponding to the steady-state performance test request is determined based on the data reading and writing result.

[0010] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0011] An eMMC testing device, comprising:

[0012] A request receiving module, used to receive a steady-state performance test request of the eMMC chip to be tested;

[0013] A region division module, configured to divide the eMMC chip to be tested into regions according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;

[0014] A test module, used to perform data read and write operations on the divided eMMC chip to be tested according to a second preset capacity, and save data read and write results corresponding to the data read and write operations;

[0015] A result determination module is used to determine the steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.

[0016] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0017] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, each step in the above-mentioned eMMC testing method is implemented.

[0018] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0019] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned eMMC testing method when executing the computer program.

[0020] The beneficial effects of the present invention are as follows: according to the received steady-state performance test request, the eMMC chip to be tested is divided into regions according to the first preset capacity, data read and write operations are performed on the divided eMMC chip to be tested according to the second preset capacity, and the data read and write results corresponding to the data read and write operations are saved, and the steady-state performance test results are determined based on the data read and write results. Unlike the prior art, the steady-state performance test is no longer performed with time as the test dimension, but with capacity as the test dimension. It can test whether the steady-state performance of the eMMC chip is normal, and can also accurately know whether the steady-state performance has declined. Compared with the test method with time as the test dimension, it is more convenient and reduces the tediousness of the test, thereby improving the convenience of the steady-state performance test. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flow chart of the steps of an eMMC testing method according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of an eMMC testing device according to an embodiment of the present invention;

[0023] Figure 3 The figure is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0025] Please refer to Figure 1 , an embodiment of the present invention provides an eMMC testing method, comprising:

[0026] Receive a steady-state performance test request for the eMMC chip to be tested;

[0027] According to the steady-state performance test request, the eMMC chip to be tested is divided into regions according to a first preset capacity to obtain a divided eMMC chip to be tested;

[0028] Performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity, and saving data read and write results corresponding to the data read and write operations;

[0029] A steady-state performance test result corresponding to the steady-state performance test request is determined based on the data reading and writing result.

[0030] From the above description, it can be seen that the beneficial effects of the present invention are: according to the received steady-state performance test request, the eMMC chip to be tested is divided into regions according to the first preset capacity, data read and write operations are performed on the divided eMMC chip to be tested according to the second preset capacity, and the data read and write results corresponding to the data read and write operations are saved, and the steady-state performance test results are determined based on the data read and write results. Unlike the prior art, the steady-state performance test is no longer performed with time as the test dimension, but with capacity as the test dimension. It can not only test whether the steady-state performance of the eMMC chip is normal, but also accurately know whether the steady-state performance has declined. Compared with the test method with time as the test dimension, it is more convenient and reduces the tediousness of the test, thereby improving the convenience of the steady-state performance test.

[0031] Further, before dividing the eMMC chip to be tested into regions according to the first preset capacity according to the steady-state performance test request, the method includes:

[0032] According to the steady-state performance test request, the eMMC chip to be tested is sequentially written a preset number of times according to the first preset test data to obtain the eMMC chip to be tested in a steady state.

[0033] From the above description, it can be seen that by performing a preset number of sequential writes on the entire disk of the eMMC chip to be tested, it is ensured that the eMMC chip to be tested enters a steady state, thereby eliminating the situation where the steady-state performance test fails due to the eMMC chip not being in a steady state, thereby improving the reliability of the steady-state performance test results.

[0034] Further, the steady-state performance test request includes a test index;

[0035] The performing a data read and write operation on the divided eMMC chip to be tested according to the second preset capacity, and saving a data read and write result corresponding to the data read and write operation comprises:

[0036] Determine a test model corresponding to the test indicator according to the test indicator;

[0037] According to the test model, data read and write operations are performed on the divided eMMC chip to be tested according to the second preset capacity, and data read and write results corresponding to the data read and write operations are saved according to the test index.

[0038] From the above description, it can be seen that different test models are determined according to different test indicators, and then data read and write operations are performed on the divided eMMC chip to be tested according to the second preset capacity according to the test model to achieve flexible eMMC steady-state performance testing.

[0039] Further, the test model includes a sequential read-write model and / or a random read-write model;

[0040] The performing data reading and writing operations on the divided eMMC chip to be tested according to the test model according to the second preset capacity includes:

[0041] Sequentially select a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the sequential read-write model, and perform sequential read-write operations on the sequentially selected second preset capacities;

[0042] A second preset capacity is randomly selected from each of the first preset capacities of the divided eMMC chip to be tested according to the random read / write model, and a random read / write operation is performed on the randomly selected second preset capacity.

[0043] From the above description, it can be seen that the test model includes a sequential read and write model and / or a random read and write model. According to the sequential read and write model, the second preset capacity is sequentially selected from each first preset capacity of the eMMC chip to be tested after division, and sequential read and write operations are performed on the sequentially selected second preset capacity. According to the random read and write model, the second preset capacity is randomly selected from each first preset capacity of the eMMC chip to be tested after division, and random read and write operations are performed on the randomly selected second preset capacity. The eMMC chip can be partitioned tested, thereby improving the effectiveness of the steady-state performance test.

[0044] Further, the test indicators include running time indicators;

[0045] Determining a test model corresponding to the test indicator according to the test indicator includes:

[0046] A first sequential read / write model and a first random read / write model corresponding to the run time indicator are determined according to the run time indicator.

[0047] From the above description, it can be seen that when the test indicator includes the running time indicator, the corresponding first sequential read and write model and the first random read and write model are determined, and then a steady-state performance test is performed according to the first sequential read and write model and the first random read and write model, thereby realizing a steady-state performance test with capacity as the test dimension and running time as the test indicator, which can simply and effectively realize the steady-state performance test.

[0048] Further, the test index includes a bandwidth index;

[0049] Determining a test model corresponding to the test indicator according to the test indicator includes:

[0050] A second sequential read / write model corresponding to the bandwidth indicator is determined according to the bandwidth indicator.

[0051] From the above description, it can be seen that when the test indicator includes the bandwidth indicator, the corresponding second-order read-write model can be determined, and then the test is performed according to the second-order read-write model, thereby realizing a steady-state performance test with capacity as the test dimension and bandwidth as the test indicator, and also realizing a simple and effective steady-state performance test.

[0052] Furthermore, the test index includes an IOPS index or a latency index;

[0053] Determining a test model corresponding to the test indicator according to the test indicator includes:

[0054] Determine a second random read / write model corresponding to the IOPS indicator according to the IOPS indicator;

[0055] A third random read / write model corresponding to the latency indicator is determined according to the latency indicator.

[0056] From the above description, it can be seen that in addition to running time and bandwidth, the test indicators can also be IOPS (the number of read and write operations per second) and latency. It can realize the steady-state performance test of eMMC from multiple angles, improve the applicability and flexibility of the test, and testers can make flexible choices based on actual conditions, thereby improving the effectiveness of steady-state performance testing.

[0057] Please refer to Figure 2 Another embodiment of the present invention provides an eMMC testing device, comprising:

[0058] A request receiving module, used to receive a steady-state performance test request of the eMMC chip to be tested;

[0059] A region division module, configured to divide the eMMC chip to be tested into regions according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;

[0060] A test module, used to perform data read and write operations on the divided eMMC chip to be tested according to a second preset capacity, and save data read and write results corresponding to the data read and write operations;

[0061] A result determination module is used to determine the steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.

[0062] Another embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step in the above-mentioned eMMC testing method is implemented.

[0063] Please refer to Figure 3 Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned eMMC test method when executing the computer program.

[0064] The above-mentioned eMMC test method, device, readable storage medium and electronic device of the present invention can be applied to the test scenario of eMMC chip, and are described below through specific implementation methods:

[0065] Embodiment 1

[0066] Please refer to Figure 1 , an eMMC testing method of this embodiment includes:

[0067] S0. According to the steady-state performance test request, the eMMC chip to be tested is sequentially written for a preset number of times according to the first preset test data to obtain the eMMC chip to be tested in a steady state;

[0068] The preset number of times can be set according to the actual situation, as long as the eMMC chip to be tested can enter a steady state. In this embodiment, the preset number of times is 2 times;

[0069] Specifically, the eMMC chip to be tested is placed in a card reader, connected to a PC (the PC is an Ubuntu system), and the eMMC chip to be tested is sequentially written twice in full disk order using an FIO tool (I / O tool) according to the steady-state performance test request and the first preset test data to obtain the eMMC chip to be tested in a steady state;

[0070] S1. Receive a steady-state performance test request of the eMMC chip to be tested;

[0071] Wherein, the steady-state performance test request includes a test index;

[0072] The test indicators include running time indicators, bandwidth indicators, IOPS indicators or latency indicators;

[0073] S2. Divide the eMMC chip to be tested into regions according to the steady-state performance test request and the first preset capacity to obtain the divided eMMC chip to be tested;

[0074] The first preset capacity can be set according to actual conditions. In this embodiment, the first preset capacity is 1G.

[0075] For example, if the capacity of the eMMC chip to be tested is 64G, the eMMC chip to be tested is divided into regions according to 1G, and is sequentially divided into 64 1G capacities to obtain the divided eMMC chip to be tested;

[0076] S3, performing data reading and writing operations on the divided eMMC chip to be tested according to the second preset capacity, and saving data reading and writing results corresponding to the data reading and writing operations, specifically including:

[0077] S31, determining a test model corresponding to the test indicator according to the test indicator;

[0078] Wherein, the test model includes a sequential read-write model and / or a random read-write model;

[0079] S32, performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity according to the test model, and saving data read and write results corresponding to the data read and write operations according to the test index, specifically including:

[0080] S321, sequentially selecting a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the sequential read-write model, and performing sequential read-write operations on the sequentially selected second preset capacities;

[0081] The second preset capacity may refer to the test model of Androbench. In this embodiment, the second preset capacity is 512M.

[0082] S322, randomly selecting a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the random read / write model, and performing a random read / write operation on the randomly selected second preset capacity;

[0083] S323, saving the data reading and writing results corresponding to the data reading and writing operations according to the test indicators;

[0084] S4. Determine a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result;

[0085] In an optional implementation, S3 may be repeatedly executed multiple times to ensure a sufficient number of test samples, thereby improving the reliability of the steady-state performance test results.

[0086] Embodiment 2

[0087] Please refer to Figure 1 The difference between this embodiment and the first embodiment is that the steady-state performance test is implemented according to the running time index, specifically:

[0088] The S31 specifically includes:

[0089] Determine, according to the runtime indicator, a first sequential read / write model and a first random read / write model corresponding to the runtime indicator;

[0090] When the test indicator is the running time indicator, S32 includes S321, S322 and S323: wherein the first sequential read-write model is a 512k sequential read-write model, and the first random read-write model is a 4k random read-write model;

[0091] The S321 is specifically:

[0092] Sequentially selecting a second preset capacity from each of the first preset capacities of the divided eMMC chip to be tested according to the first sequential read-write model, and performing sequential read-write operations on the sequentially selected second preset capacities;

[0093] Specifically, 512M is selected from each 1G capacity of the divided eMMC chip to be tested according to the LBA address (Logic Block Address) sequence, 512k sequential reading is performed on 64 512Ms respectively, and then 512k sequential writing is performed on 64 512Ms respectively;

[0094] The S322 is specifically:

[0095] Randomly selecting a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the first random read / write model, and performing a random read / write operation on the randomly selected second preset capacity;

[0096] Specifically, 512M is randomly selected from each 1G capacity of the divided eMMC chip to be tested, 4k random reads are performed on 64 512Ms respectively, and then 4k random writes are performed on 64 512Ms respectively;

[0097] The S323 is specifically:

[0098] According to the running time indicator, the data reading and writing time result corresponding to the data reading and writing operation is saved;

[0099] Specifically, after 512k sequentially reads each 512M, the sequential read time is saved, and there are 64 sequential read times in total. After 512k sequentially writes each 512M, the sequential write time is saved, and there are 64 sequential write times in total. After 4k randomly reads each 512M, the random read time is saved, and there are 64 random read times in total. After 4k randomly writes each 512M, the random write time is saved, and there are 64 random write times in total.

[0100] The S4 specifically includes:

[0101] S41, generating a time curve graph according to the data reading and writing time result;

[0102] Specifically, a sequential read time curve graph is generated according to 64 sequential read times, a sequential write time curve graph is generated according to 64 sequential write times, a random read time curve graph is generated according to 64 random read times, and a random write time curve graph is generated according to 64 random write times;

[0103] S42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the time curve graph;

[0104] Specifically, determining the maximum time and the minimum time in each of the time curve graphs, and judging whether the difference between the maximum time and the minimum time in each of the time curve graphs does not exceed a first preset ratio, if so, the steady-state performance test passes, and if not, the steady-state performance test fails;

[0105] Wherein, the first preset ratio is 10%.

[0106] Embodiment 3

[0107] Please refer to Figure 1 The difference between this embodiment and the first or second embodiment is that the steady-state performance test is implemented according to the bandwidth index, specifically:

[0108] The S31 specifically includes:

[0109] Determine a second sequential read-write model corresponding to the bandwidth indicator according to the bandwidth indicator;

[0110] The second sequential read / write model is queue depth 8, 512K sequential read / write;

[0111] The queue depth is assigned a value of 8 through the parameter iodepth in the test tool FIO;

[0112] When the test indicator is a bandwidth indicator, the S32 includes the S321 and the S323:

[0113] The S321 is specifically:

[0114] Sequentially select a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the second sequential read-write model, and perform sequential read-write operations on the sequentially selected second preset capacities;

[0115] Specifically, according to the queue depth of 8, 512M is selected from each 1G capacity of the divided eMMC chip to be tested according to the LBA address order, 512k sequential reading is performed on 64 512Ms respectively, and then 512k sequential writing is performed on 64 512Ms respectively;

[0116] The S323 is specifically:

[0117] Save the data read and write bandwidth result corresponding to the data read and write operation according to the bandwidth indicator;

[0118] Specifically, after 512k sequentially reads each 512M, the sequential read bandwidth is saved, and there are 64 sequential read bandwidths in total. After 512k sequentially writes each 512M, the sequential write bandwidth is saved, and there are 64 sequential write bandwidths in total.

[0119] The S4 specifically includes:

[0120] S41, generating a bandwidth curve graph according to the data reading and writing bandwidth result;

[0121] Specifically, a sequential read bandwidth curve graph is generated according to 64 sequential read times, and a sequential write bandwidth curve graph is generated according to 64 sequential write times;

[0122] S42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the bandwidth curve graph;

[0123] Specifically, determining the maximum bandwidth and the minimum bandwidth in each bandwidth curve graph, and judging whether the difference between the maximum bandwidth and the minimum bandwidth in each bandwidth curve graph does not exceed the second preset ratio, if so, the steady-state performance test passes, if not, the steady-state performance test fails;

[0124] Wherein, the second preset ratio is 10%.

[0125] Embodiment 4

[0126] Please refer to Figure 1 The difference between this embodiment and the first, second or third embodiment is that the steady-state performance test is implemented according to the IOPS index, specifically:

[0127] The S31 specifically includes:

[0128] Determine a second random read / write model corresponding to the IOPS indicator according to the IOPS indicator;

[0129] The second random read / write model is queue depth 8, 4K random read / write;

[0130] When the test indicator is the IOPS indicator, the S32 includes the S322 and the S323:

[0131] The S322 is specifically:

[0132] Randomly selecting a second preset capacity from each of the first preset capacities of the divided eMMC chip to be tested according to the second random read / write model, and performing a random read / write operation on the randomly selected second preset capacity;

[0133] Specifically, according to the queue depth of 8, 512M is randomly selected from each 1G capacity of the divided eMMC chip to be tested, 4k random reads are performed on 64 512Ms respectively, and then 4k random writes are performed on 64 512Ms respectively;

[0134] The S323 is specifically:

[0135] The data read and write IOPS result corresponding to the data read and write operation is saved according to the IOPS indicator;

[0136] Specifically, after 4k random reads each 512M, the random read IOPS is saved, with a total of 64 random read IOPS. After 4k random writes each 512M, the random write IOPS is saved, with a total of 64 random write IOPS.

[0137] The S4 specifically includes:

[0138] S41, generating an IOPS curve graph according to the data reading and writing IOPS results;

[0139] Specifically, a random read IOPS curve graph is generated according to 64 random read IOPSs, and a random write IOPS curve graph is generated according to 64 random write IOPSs;

[0140] S42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the IOPS curve graph;

[0141] Specifically, determining the maximum IOPS and the minimum IOPS in each of the IOPS curve graphs, and judging whether the difference between the maximum IOPS and the minimum IOPS in each of the IOPS curve graphs does not exceed a third preset ratio, if so, the steady-state performance test passes, and if not, the steady-state performance test fails;

[0142] Wherein, the third preset ratio is 10%.

[0143] Embodiment 5

[0144] Please refer to Figure 1 The difference between this embodiment and the first, second, third or fourth embodiment is that the steady-state performance test is implemented according to the delay index, specifically:

[0145] The S31 specifically includes:

[0146] Determine a third random read / write model corresponding to the latency indicator according to the latency indicator;

[0147] The third random read / write model is queue depth 1, 4k random read / write;

[0148] When the test indicator is the delay indicator, the S32 includes the S322 and the S323:

[0149] The S322 is specifically:

[0150] Randomly selecting a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the third random read / write model, and performing a random read / write operation on the randomly selected second preset capacity;

[0151] Specifically, according to the queue depth 1, 512M is randomly selected from each 1G capacity of the divided eMMC chip to be tested, 4k random reads are performed on 64 512Ms respectively, and then 4k random writes are performed on 64 512Ms respectively;

[0152] The S323 is specifically:

[0153] Save the data read and write delay result corresponding to the data read and write operation according to the delay indicator;

[0154] Specifically, after 4k random reads each 512M, the random read latency is saved, with a total of 64 random read latency records. After 4k random writes each 512M, the random write latency is saved, with a total of 64 random write latency records.

[0155] The S4 specifically includes:

[0156] S41, generating a delay curve graph according to the data reading and writing delay results;

[0157] Specifically, a random read latency curve is generated according to 64 random read latencies, and a random write latency curve is generated according to 64 random write latencies;

[0158] S42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the delay curve graph;

[0159] Specifically, determine the maximum delay and the minimum delay in each of the delay curve graphs, and judge whether the difference between the maximum delay and the minimum delay in each of the delay curve graphs does not exceed a fourth preset ratio, if so, the steady-state performance test passes, if not, the steady-state performance test fails;

[0160] Wherein, the fourth preset ratio is 10%.

[0161] Embodiment 6

[0162] Please refer to Figure 2 , an eMMC testing device, comprising:

[0163] A request receiving module, used to receive a steady-state performance test request of the eMMC chip to be tested;

[0164] A region division module, configured to divide the eMMC chip to be tested into regions according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;

[0165] A test module, used to perform data read and write operations on the divided eMMC chip to be tested according to a second preset capacity, and save data read and write results corresponding to the data read and write operations;

[0166] A result determination module is used to determine the steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.

[0167] Embodiment 7

[0168] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, each step of the eMMC test method in Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, or Embodiment 5 can be implemented.

[0169] Embodiment 8

[0170] Please refer to Figure 3 , an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, each step of the eMMC test method in Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, or Embodiment 5 is implemented.

[0171] In summary, the present invention provides an eMMC test method, device, readable storage medium and electronic device, which divide the eMMC chip to be tested into regions according to a first preset capacity according to a steady-state performance test request of the eMMC chip to be tested received, and obtains the divided eMMC chip to be tested; wherein the steady-state performance test request includes a test indicator, the test indicator includes a running time indicator, a bandwidth indicator, an IOPS indicator or a latency indicator, a test model is determined according to the test indicator, the test model includes a sequential read-write model and / or a random read-write model, and data read and write operations are performed on the divided eMMC chip to be tested according to the second preset capacity according to the test model, and the data read and write operations are saved according to the test indicator. The method comprises the following steps: performing corresponding data read and write results, determining a steady-state performance test result corresponding to the steady-state performance test request based on the data read and write results; determining different test models according to different test indicators, and then performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity according to the test model, so as to be able to perform partition testing on the eMMC chip and realize flexible eMMC steady-state performance testing; testing with capacity as the test dimension can not only test whether the steady-state performance of the eMMC chip is normal, but also accurately know whether the steady-state performance has declined, and is more convenient than the test method with time as the test dimension, which reduces the tediousness of the test, thereby improving the convenience of the steady-state performance test.

[0172] In the above embodiments provided in the present application, it should be understood that the disclosed methods, devices, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple components or modules can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or components or modules, which can be electrical, mechanical or other forms.

[0173] The components described as separate components may or may not be physically separated, and the components shown as components may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0174] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each component may exist physically separately, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0175] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0176] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0177] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0178] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An eMMC testing method, characterized in that: include: Receive a steady-state performance test request for the eMMC chip to be tested; According to the steady-state performance test request, the eMMC chip to be tested is divided into regions according to a first preset capacity to obtain a divided eMMC chip to be tested; Performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity, and saving data read and write results corresponding to the data read and write operations; Determine a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result; The step of dividing the eMMC chip to be tested into regions according to the first preset capacity according to the steady-state performance test request includes: According to the steady-state performance test request, the eMMC chip to be tested is sequentially written for a preset number of times according to the first preset test data to obtain the eMMC chip to be tested in a steady state; The steady-state performance test request includes a test index; The performing a data read and write operation on the divided eMMC chip to be tested according to the second preset capacity, and saving a data read and write result corresponding to the data read and write operation comprises: Determine a test model corresponding to the test indicator according to the test indicator; Performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity according to the test model, and saving data read and write results corresponding to the data read and write operations according to the test index; The test model includes a sequential read-write model and / or a random read-write model; The performing data reading and writing operations on the divided eMMC chip to be tested according to the test model according to the second preset capacity includes: Sequentially select a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the sequential read-write model, and perform sequential read-write operations on the sequentially selected second preset capacities; A second preset capacity is randomly selected from each of the first preset capacities of the divided eMMC chip to be tested according to the random read / write model, and a random read / write operation is performed on the randomly selected second preset capacity.

2. A eMMC testing method according to claim 1, characterised in that, The test indicators include running time indicators; Determining a test model corresponding to the test indicator according to the test indicator includes: A first sequential read / write model and a first random read / write model corresponding to the run time indicator are determined according to the run time indicator.

3. A eMMC testing method according to claim 1, characterised in that, The test index includes a bandwidth index; Determining a test model corresponding to the test indicator according to the test indicator includes: A second sequential read / write model corresponding to the bandwidth indicator is determined according to the bandwidth indicator.

4. An eMMC testing method according to claim 1, characterized in that, The test index includes an IOPS index or a latency index; Determining a test model corresponding to the test indicator according to the test indicator includes: Determine a second random read / write model corresponding to the IOPS indicator according to the IOPS indicator; A third random read / write model corresponding to the latency indicator is determined according to the latency indicator.

5. An eMMC testing device, characterized in that: include: A request receiving module, used to receive a steady-state performance test request of the eMMC chip to be tested; A region division module, configured to divide the eMMC chip to be tested into regions according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested; A test module, used to perform data read and write operations on the divided eMMC chip to be tested according to a second preset capacity, and save data read and write results corresponding to the data read and write operations; A result determination module, used to determine the steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result; The step of dividing the eMMC chip to be tested into regions according to the first preset capacity according to the steady-state performance test request includes: According to the steady-state performance test request, the eMMC chip to be tested is sequentially written for a preset number of times according to the first preset test data to obtain the eMMC chip to be tested in a steady state; The steady-state performance test request includes a test index; The performing a data read and write operation on the divided eMMC chip to be tested according to the second preset capacity, and saving a data read and write result corresponding to the data read and write operation comprises: Determine a test model corresponding to the test indicator according to the test indicator; Performing data read and write operations on the divided eMMC chip to be tested according to the second preset capacity according to the test model, and saving data read and write results corresponding to the data read and write operations according to the test index; The test model includes a sequential read-write model and / or a random read-write model; The performing data reading and writing operations on the divided eMMC chip to be tested according to the test model according to the second preset capacity includes: Sequentially select a second preset capacity from each of the first preset capacities of the divided eMMC chips to be tested according to the sequential read-write model, and perform sequential read-write operations on the sequentially selected second preset capacities; A second preset capacity is randomly selected from each of the first preset capacities of the divided eMMC chip to be tested according to the random read / write model, and a random read / write operation is performed on the randomly selected second preset capacity.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step in an eMMC testing method as claimed in any one of claims 1 to 4 is implemented.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, each step in the eMMC testing method according to any one of claims 1 to 4 is implemented.

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