A novel single event hardening flip-flop circuit

Abstract

The application discloses a novel single-event-hardened flip-flop circuit, which comprises a master-stage latch and a slave-stage latch connected in parallel between a first transmission channel and a second transmission channel, wherein the first input and output ends of the master-stage latch and the slave-stage latch are connected with the first transmission channel, and the second input and output ends of the master-stage latch and the slave-stage latch are connected with the second transmission channel; a delay element is arranged in the feedback loop of the master-stage latch and / or the slave-stage latch; the delay element is used for keeping the level of the second node of the feedback loop unchanged when the first node of the feedback loop is affected by single particle incidence during the data holding stage of the latch in which the delay element is arranged, and the level of the first node is recovered after the ionizing radiation is finished. The master-stage latch and the slave-stage latch are connected in parallel, and the delay element is arranged in the latch, so that the flip-flop circuit with the advantages of low production cost, small occupied area, high data transmission speed and good single-event-upset resistance is obtained.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a novel single-event hardened trigger circuit. Background Technology

[0002] In a radiation environment, charged particles incident on a digital circuit chip will induce ionizing radiation, generating a certain number of electron-hole pairs around the particle's trajectory. When enough electron-hole pairs are deposited along the incident direction of the particles, the current caused by the electron-hole pairs collected by the depletion layer will cause the drain level to flip, forming a single-event upset.

[0003] Traditional hardening methods include Dual Inter-locked Storage Cell (DICE) and Guard-gates DICE (GDICE), which are implemented by adding transmission channels and storage nodes and using an interlocking structure. A DICE is essentially a four-node storage unit, with data written from two nodes and the voltage levels at the other two nodes generated by feedback, ultimately forming a four-point interlocking structure.

[0004] However, traditional hardening methods increase the number of transistors in the circuit due to the addition of storage nodes and interlocking structures, resulting in increased area overhead. Simultaneously, the added interlocking structures slow down data transmission speed. Furthermore, when the radiation energy is high or the transistors used in the triggers are small, traditional hardening structures cannot recover the node levels caused by ionizing radiation through the interlocking structures, thus leading to single-event upsets. Summary of the Invention

[0005] This application provides a novel single-event hardened trigger circuit, which uses a master-level latch and a slave-level latch in parallel and adds a delay element within the latch, resulting in a trigger circuit with low production cost, small footprint, fast transmission speed, and good single-event upset resistance.

[0006] In a first aspect, the present invention provides the following technical solution through an embodiment of the present invention:

[0007] A novel single-event hardened trigger circuit includes: a master latch and a slave latch connected in parallel between a first transmission channel and a second transmission channel. The first input / output terminals of the master latch and the slave latch are connected to the first transmission channel, and the second input / output terminals of the master latch and the slave latch are connected to the second transmission channel. A delay element is provided in the feedback loop of the master latch and / or the slave latch. The delay element is used to maintain the level of the second node of the feedback loop unchanged when the first node of the latch feedback loop is affected by single-event incident radiation during the data holding phase of the latch, and restore the level of the first node after the ionizing radiation ends.

[0008] Preferably, the trigger circuit further includes: a first inverter, a second inverter, a third inverter, a first clock gate sub-circuit, a second clock gate sub-circuit, a third clock gate sub-circuit, and a fourth clock gate sub-circuit; the input terminals of the first inverter and the first clock gate sub-circuit serve as the input terminals of the trigger circuit; the first inverter is connected in series with the third clock gate sub-circuit, the fourth clock gate sub-circuit, and the third inverter in sequence; the output terminal of the first clock gate sub-circuit is connected in series with the second clock gate sub-circuit and the second inverter in sequence; the second inverter serves as the first output terminal of the trigger circuit; and the output terminal of the third inverter serves as the second output terminal of the trigger circuit; the master latch is connected between the output terminals of the first clock gate sub-circuit and the third clock gate sub-circuit; and the slave latch is connected between the output terminals of the second clock gate sub-circuit and the fourth clock gate sub-circuit.

[0009] Preferably, the delay element includes a resistor and a gate switch, the resistor and the gate switch are connected in parallel, the first terminal of the resistor and the gate switch serve as the input terminal of the delay element, and the second terminal of the resistor and the gate switch serve as the output terminal of the delay element; the gate switch is used to disconnect during the data holding process of the latch, and when the first node of the latch feedback loop is affected by single-particle incident radiation, the level of the second node of the feedback loop remains unchanged, and the level of the first node is restored after the ionizing radiation ends.

[0010] Preferably, the delay element further includes a capacitor and a gate switch. One end of the capacitor is connected in series with one end of the gate switch, and the other end of the gate switch serves as the input and output of the delay element. The other end of the capacitor is connected to a fixed voltage level. The gate switch is used to close during the data holding process of the latch. When the first node of the latch feedback loop is affected by a single-particle incident event, the load characteristics of the delay element are used to keep the voltage level of the second node of the feedback loop unchanged. After the ionizing radiation ends, the voltage level of the first node is restored.

[0011] Preferably, the delay element is provided in the feedback loop of the master stage latch, and the master stage latch includes a fourth inverter and a fifth inverter; the fourth inverter and the fifth inverter are connected in parallel, the input terminal of the fourth inverter and the output terminal of the fifth inverter serve as the first input-output terminal of the master stage latch, and the output terminal of the fourth inverter and the input terminal of the fifth inverter serve as the second input-output terminal of the master stage latch; the delay element is provided in the branch where the fourth inverter is located and / or the branch where the fifth inverter is located.

[0012] Preferably, the branch containing the fourth inverter and the fifth inverter is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the first node of the master stage latch feedback loop and the input terminal of the fourth inverter, and the second delay element is disposed between the second node of the master stage latch feedback loop and the input terminal of the fifth inverter.

[0013] Preferably, the branch containing the fourth inverter is provided with the delay element, which is located between the first node of the main stage latch feedback loop and the input terminal of the fourth inverter.

[0014] Preferably, the branch containing the fifth inverter is provided with the delay element, which is located at the second node of the main stage latch feedback loop and connected to the input terminal of the fifth inverter.

[0015] Preferably, the delay element is provided in the feedback loop of the slave latch, and the slave latch includes a sixth inverter and a seventh inverter; the sixth inverter and the seventh inverter are connected in parallel, the input terminal of the sixth inverter and the output terminal of the seventh inverter serve as the first input-output terminal of the slave latch, and the output terminal of the sixth inverter and the input terminal of the seventh inverter serve as the second input-output terminal of the slave latch; the delay element is provided in the branch where the sixth inverter is located and / or the branch where the seventh inverter is located.

[0016] Preferably, the branch containing the sixth inverter and the seventh inverter is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the first node of the slave latch feedback loop and the input terminal of the sixth inverter, and the second delay element is disposed between the second node of the slave latch feedback loop and the input terminal of the seventh inverter.

[0017] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0018] This invention provides a novel single-event hardened trigger circuit, comprising: a master-level latch and a slave-level latch connected in parallel between a first transmission channel and a second transmission channel. The first input / output terminals of the master-level latch and the slave-level latch are connected to the first transmission channel, and the second input / output terminals of the master-level latch and the slave-level latch are connected to the second transmission channel. This circuit, by incorporating delay elements in the master-level latch and / or the slave-level latch, ensures that during the data holding phase of the trigger, when the first node of the latch feedback loop experiences a level flip due to single-event radiation, the delay load characteristic of the delay element maintains the level of the second node of the feedback loop unchanged until the ionizing radiation ends. After the ionizing radiation ends, the level of the first node affected by single-event radiation is restored. This application employs a cascaded master-level latch and slave-level latch via a gated clock circuit, allowing data to be transmitted directly through both channels simultaneously without passing through the master-slave latch feedback loop, thus improving circuit speed. A delay element is added to the latch so that during the data holding phase of the trigger, when a node (first) experiences a level flip due to single-event radiation, the load delay characteristic of the delay element maintains the level of the node (second) at the other end of the feedback loop unchanged until the ionizing radiation ends and the level of the first node is restored. Simultaneously, when the trigger circuit is subjected to high-energy radiation, or when the transistors used in the trigger have small dimensions, when the first node experiences a level flip due to single-event radiation, the load delay characteristic of the delay element can also maintain the level of the second node unchanged, and the level of the first node will be restored after the ionizing radiation ends. This provides a trigger circuit with low production cost, small footprint, high transmission speed, and good single-event upset resistance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a structural diagram of a single-event hardened trigger circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the single-particle hardened trigger circuit provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of a first type of delay element provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the structure of a second delay element provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of a first type of master stage latch including a delay element provided by an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of a second type of master stage latch including a delay element provided in an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of a third type of master stage latch including a delay element provided in an embodiment of the present invention;

[0027] Figure 8 Various structural schematic diagrams of logic input circuits provided in embodiments of the present invention;

[0028] Figure 9 Various structural schematic diagrams of the first clock gate sub-circuit provided in the embodiments of the present invention. Detailed Implementation

[0029] The flip-flop consists of a master-level latch structure and a slave-level latch structure. The master-level and slave-level latch structures are identical (a feedback loop composed of an inverter and a gating circuit). The clock is latched at high and low levels by time-division control of the gating circuit. As a structure with storage and memory functions in the flip-flop circuit, the latch becomes the core of the single-event hardening design of the flip-flop.

[0030] The applicant's research revealed that traditional hardening methods, DICE and GDICE, achieve their effects by adding transmission channels and storage nodes, and employing interlocking structures. DICE is essentially a four-node storage unit; data is written to two nodes, and the voltage levels of the other two nodes are generated by feedback, ultimately forming a four-node interlocking structure. The GDICE structure, building upon the interlocking of the DICE structure, adds a pair of protection gates to each storage node. When the inputs at the two nodes differ, the output has high impedance; therefore, if one of the adjacent nodes of a node flips, its output remains unchanged. Their hardening principle is that when a node flips due to a single-particle incident event, the adjacent two nodes, through interlocking, restore the node's voltage level after the ionizing radiation ends. However, traditional hardening methods, due to the addition of storage nodes and interlocking structures, increase the number of transistors in the circuit, increasing area overhead, and the trigger circuits show poor hardening performance under high-energy radiation.

[0031] Therefore, this application provides a novel single-event hardened trigger circuit, which uses a master-level latch and a slave-level latch in parallel and adds a delay element in the latch, resulting in a trigger circuit with low production cost, small footprint, fast transmission speed and good single-event upset resistance.

[0032] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0033] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:

[0034] A novel single-event hardened trigger circuit is characterized by comprising: a master latch and a slave latch connected in parallel between a first transmission channel and a second transmission channel; the first input / output terminals of the master latch and the slave latch are connected to the first transmission channel, and the second input / output terminals of the master latch and the slave latch are connected to the second transmission channel; a delay element is provided in the feedback loop of the master latch and / or the slave latch; the delay element is used to maintain the level of the second node of the feedback loop unchanged when the first node of the latch feedback loop is affected by single-event incident radiation during the data holding phase of the latch, and restore the level of the first node after the ionizing radiation ends.

[0035] It should be noted that the single-event hardened trigger circuit provided in this application is applicable to rising-edge / falling-edge D flip-flop circuits, and can also be applied to other types of flip-flops, such as registers. Furthermore, this application can be applied to single-event hardening of other sequential circuits such as high / low-level latch circuits. The following description uses a rising-edge D flip-flop as an example to illustrate the single-event hardened trigger circuit.

[0036] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0037] Firstly, the embodiments of the present invention provide a novel single-event hardened trigger circuit, specifically, as follows: Figure 1 As shown, it includes: a master latch 10 and a slave latch 20 connected in parallel between the first transmission channel X1 and the second transmission channel X2. The first input / output terminal (first node Inout1) of the master latch 10 is connected to the first transmission channel X1, the first input / output terminal (third node Inout3) of the slave latch 20 is connected to the first transmission channel X1, the second input / output terminal (second node Inout2) of the master latch 10 is connected to the second transmission channel X2, and the second input / output terminal (fourth node Inout4) of the slave latch 20 is connected to the second transmission channel X2.

[0038] In this embodiment, the trigger circuit processes the data into two inverted data signals, "1" and "0". These two data signals are transmitted to the two nodes (Inout1 and Inout2) of the master latch when the clock is low, and to the two nodes (Inout3 and Inout4) of the slave latch when the clock turns high (rising edge). The transmission method of the slave latch is the same as that of the master latch. Here, the two storage nodes (Inout1 and Inout2) of the latch feedback structure are both inputs and outputs. The branches containing these two nodes are considered as two channels, and data is transmitted directly through both channels simultaneously.

[0039] In a specific embodiment, such as Figure 2 As shown, the trigger circuit may specifically include: a first inverter 401, a second inverter 402, a third inverter 403, a first clock gate sub-circuit 404, a second clock gate sub-circuit 405, a third clock gate sub-circuit 406, and a fourth clock gate sub-circuit 407.

[0040] The input terminals of the first inverter 401 and the first clock gate circuit 404 serve as the input terminals of the flip-flop circuit. The first inverter 401 is connected in series with the third clock gate circuit 406, the fourth clock gate circuit 407, and the third inverter 403. The output terminal of the first clock gate circuit 404 is connected in series with the second clock gate circuit 405 and the second inverter 402. The second inverter 402 serves as the first output terminal of the flip-flop circuit, and the output terminal of the third inverter 403 serves as the second output terminal of the flip-flop circuit. The first output terminal is the Qn terminal of the flip-flop circuit, and the second output terminal is the Q terminal of the flip-flop circuit.

[0041] The master latch 10 is connected between the output of the first clock gate sub-circuit 404 and the output of the third clock gate sub-circuit 406, and the slave latch 20 is connected between the output of the second clock gate sub-circuit 405 and the output of the fourth clock gate sub-circuit 407.

[0042] Of course, as another optional embodiment, the trigger circuit provided in this application may include: a first inverter 401, a second inverter 402, a third inverter 403, an eighth inverter 408, a first clock gate sub-circuit 404, a second clock gate sub-circuit 405, a third clock gate sub-circuit 406, and a fourth clock gate sub-circuit 407.

[0043] The input terminals of the first inverter 401 and the first clock gate circuit 404 serve as the input terminals of the flip-flop circuit. The first inverter 401 is connected to the third clock gate circuit 406. The first output terminal of the first clock gate circuit 404 is connected in series with the second clock gate circuit 405 and the second inverter 402. The second output terminal of the first clock gate circuit 404 is connected in series with the eighth inverter 408, the fourth clock gate circuit 407, and the third inverter 403. The second inverter 402 serves as the first output terminal of the flip-flop circuit, and the output terminal of the third inverter 403 serves as the second output terminal of the flip-flop circuit. The first output terminal is the Qn terminal of the flip-flop circuit, and the second output terminal is the Q terminal of the flip-flop circuit.

[0044] The master latch 10 is connected between the output of the first clock gate sub-circuit 404 and the output of the third clock gate sub-circuit 406, and the slave latch 20 is connected between the output of the second clock gate sub-circuit 405 and the output of the fourth clock gate sub-circuit 407.

[0045] Specifically, taking the channel from the input terminal to the first output terminal (Qn) of the rising-edge D flip-flop circuit as an example, the working principle of the data channel will be explained:

[0046] When the clock is low, the first clock gate circuit 404 is turned on, the master latch is in data transmission state, and data will be transmitted from the input terminal to the output point Inout1 of the master latch and then into the master latch. At this time, the second clock gate circuit 405 is turned off, the slave latch is in data latching state, and the output point Inout3 of the slave latch maintains the data from the previous stage.

[0047] When the clock transitions from low to high (i.e., the rising edge of the clock), the second clock gate circuit 405 turns on, the slave latch is in data transmission mode, and data is transferred from the master latch output point Inout1 to the slave output Inout3 and then into the slave latch. At this time, the first clock gate circuit 404 turns off, the master latch is in data latching mode, and the master latch output point Inout1 maintains the data from the previous stage.

[0048] The above two stages complete the data transfer process from the input to the output of a circuit.

[0049] The channel from the input terminal to the second output terminal (Q) of the trigger circuit operates on the same principle as the channel from the input terminal to the first output terminal (Qn), except that the data signal levels are reversed.

[0050] Specifically, when the clock is low, the third clock gate circuit 406 is turned on, the master latch is in data transmission state, and data will be transmitted from the input to the output point Inout2 of the master latch and then into the master latch. At this time, the fourth clock gate circuit 407 is turned off, the slave latch is in data latching state, and the slave latch output point Inout4 maintains the data from the previous stage.

[0051] When the clock transitions from low to high (i.e., the rising edge of the clock), the fourth clock gate sub-circuit 407 turns on, the slave latch is in data transmission mode, and data is transferred from the master latch output point Inout2 to the slave output Inout4 and then into the slave latch. At this time, the third clock gate sub-circuit 406 turns off, the master latch is in data latching mode, and the master latch output point Inout2 maintains the data from the previous stage.

[0052] In this embodiment, at least one delay element 30 is provided in the feedback loop of the master latch 10 and / or the slave latch 20. The delay element 30 is used to maintain the level of the second node of the feedback loop unchanged when the first node of the latch feedback loop experiences a level flip due to a single-event incident event during the data holding phase of the latch, and restores the level of the first node after the ionizing radiation ends. Alternatively, when the second node of the latch feedback loop experiences a level flip due to a single-event incident event, the level of the first node of the feedback loop remains unchanged, and the level of the second node is restored after the ionizing radiation ends.

[0053] It should be noted that the delay capability of the delay element here will be designed based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor process used in the trigger. Furthermore, since the master-level latch and the slave-level latch are time-division controlled, the control terminals (c and cn) of the delay element where the master-level latch is located are reversed compared to the control terminals (c and cn) of the delay element where the slave-level latch is located.

[0054] Specifically, as an optional embodiment, such as Figure 3 As shown, the delay element 30 may include a resistor 301 and a gate switch 302. The resistor 301 and the gate switch 302 are connected in parallel. The first end of the resistor 301 and the gate switch 302 serves as the input end of the delay element 30, and the second end of the resistor 301 and the gate switch 302 serves as the output end of the delay element 30.

[0055] In this case, the gate switch 302 is used to close the gate switch of the delay element 30 during the data transmission phase of the latch, thereby short-circuiting the two ends of the resistor 301, causing the load to fail, and the data will be transmitted directly through the gate switch.

[0056] Specifically, the gate switch 302 is used to disconnect the latch during the data holding phase, with the resistor active. When the first node of the latch feedback loop experiences a level flip due to a single-particle incident radiation, the level of the second node of the feedback loop remains unchanged. The level of the first node is restored after the ionizing radiation ends. It should be noted that the resistance value of resistor 301 can be determined based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor used in the trigger.

[0057] For example, taking the delay switch set in the master latch as an example, during the data holding phase of the master latch, the gate switch 302 is open, and the delay element will be equivalent to a passive load. When the first node of the feedback loop of the master latch ( Figure 3 When the level of point A is flipped due to the influence of a single particle incident, the level needs to be transmitted through resistor 301, which delays the time for data transmission to reach point B. This allows the level of the second node of the feedback loop to remain unchanged for a certain period of time. After the ionizing radiation ends, the level of the first node (point A) is restored, thereby achieving the purpose of latch hardening, which is also the purpose of trigger circuit hardening.

[0058] As another alternative embodiment, such as Figure 4 As shown, the delay element 30 may include a capacitor 303 and a gate switch 304. One end of the capacitor 303 is connected in series with one end of the gate switch 304. The other end of the gate switch 304 serves as both the input and output of the delay element 30. The other end of the capacitor 303 is connected to a fixed voltage level (power supply or ground). The gate switch 304 is used to disconnect the gate of the delay element 30 during the data transmission phase of the latch, thereby disconnecting the capacitor 303 and rendering the capacitive load ineffective.

[0059] Specifically, the gate switch 304 is used to close during the data holding phase of the latch, with the capacitor active. When the first node of the latch feedback loop experiences a level flip due to a single-particle incident event, the load characteristics of the delay element are used to maintain the level of the second node of the feedback loop unchanged. The level of the first node is restored after the ionizing radiation ends.

[0060] It should be noted that the capacitance value of capacitor 303 here can be determined based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor process used in the trigger.

[0061] For example, taking a delay switch set in a slave latch as an example, during the data holding phase of the slave latch, the gate switch 304 is closed, and voltage will pass through capacitor 303. The delay element will be equivalent to a passive load. When the first node of the feedback loop of the slave latch ( Figure 4 When the voltage level of the A / B point is reversed due to the single-particle incident radiation, the capacitor charges / discharges the voltage, causing a time delay in the data transmission to the second node. This means that the voltage level of the second node of the feedback loop can be kept unchanged for a certain period of time. After the ionizing radiation ends, the voltage level of the first node (A / B point) is restored, thereby achieving the purpose of latch hardening, which is also the purpose of trigger circuit hardening.

[0062] Of course, in addition to the two types of delay elements mentioned above, other devices can also be used to construct delay elements, such as a delay element that includes a diode. This application does not limit the specific delay element used.

[0063] It should be noted that the aforementioned gate switch 302 or 304 can be a clock gate composed of PMOS and NMOS, or a PMOS clock gate or an NMOS clock gate. Of course, other gate switches suitable for this application can also be used, and this application does not impose any restrictions.

[0064] As an optional embodiment, the feedback loop of the master latch 10 is provided with a delay element 30, and the master latch 10 includes a fourth inverter 101 and a fifth inverter 102.

[0065] The fourth inverter 101 and the fifth inverter 102 are connected in parallel. The input terminal of the fourth inverter 101 and the output terminal of the fifth inverter 102 serve as the first input and output terminals of the master stage latch 10, and the output terminal of the fourth inverter 101 and the input terminal of the fifth inverter 102 serve as the second input and output terminals of the master stage latch 10. The branch where the fourth inverter 101 is located and / or the branch where the fifth inverter 102 is located are provided with delay elements 30.

[0066] Since the data does not need to be transmitted through the latch feedback loop, the data transmission speed of the trigger circuit is further accelerated.

[0067] Of course, as another optional embodiment, the master-level latch may also include a fourth inverter and a fifth clock gate sub-circuit, wherein the fourth inverter and the fifth clock gate sub-circuit are connected in parallel, the input terminal of the fourth inverter and the output terminal of the fifth clock gate sub-circuit serve as the first input / output terminals of the master-level latch, and the output terminal of the fourth inverter and the input terminal of the fifth clock gate sub-circuit serve as the second input / output terminals of the master-level latch; the branch containing the fourth inverter and / or the branch containing the fifth clock gate sub-circuit is provided with a delay element; the gate switch of the fifth clock gate sub-circuit and the master-level clock gate element (e.g., such as...) Figure 2 The gate switches of the first clock gate sub-circuit and the third clock gate sub-circuit are reversed. This application describes a main-stage latch that includes a fourth inverter and a fifth inverter.

[0068] In a preferred embodiment, when both the branch containing the fourth inverter 101 and the fifth inverter 102 are provided with delay elements 30, the delay elements 30 include: a first delay element 305 and a second delay element 306, such as... Figure 5 As shown, the first delay element 305 is disposed between the first node of the master stage latch feedback loop and the input terminal of the fourth inverter 101, and the second delay element 306 is disposed between the second node of the master stage latch feedback loop and the input terminal of the fifth inverter 102.

[0069] Optionally, if only the branch containing the fourth inverter 101 has a delay element 30, such as Figure 6 As shown, the delay element 30 is disposed between the first node of the main stage latch feedback loop and the input of the fourth inverter 101.

[0070] When only the branch containing the fifth inverter 102 has a delay element 30, such as Figure 7 As shown, the delay element 30 is disposed between the first node of the main stage latch feedback loop and the input of the fifth inverter 102.

[0071] As another optional embodiment, a delay element 30 is provided in the feedback loop of the slave latch 20, and the slave latch 20 includes a sixth inverter 201 and a seventh inverter 202.

[0072] The sixth inverter 201 and the seventh inverter 202 are connected in parallel. The input terminal of the sixth inverter 201 and the output terminal of the seventh inverter 202 serve as the first input and output terminals of the slave latch 20, and the output terminal of the sixth inverter 201 and the input terminal of the seventh inverter 202 serve as the second input and output terminals of the slave latch 20. The branch where the sixth inverter 201 is located and / or the branch where the seventh inverter 202 is located are provided with a delay element 30.

[0073] Similarly, in a preferred embodiment, the branches containing the sixth inverter 201 and the seventh inverter 202 are each provided with a delay element 30. The delay element 30 includes a first delay element 305 and a second delay element 306. The first delay element 305 is disposed between the first node of the slave latch feedback loop and the input terminal of the sixth inverter 201, and the second delay element 306 is disposed between the second node of the slave latch feedback loop and the input terminal of the seventh inverter 202.

[0074] Optionally, only the branch containing the sixth inverter 201 is provided with a delay element 30, and the delay element 30 is located at the first node of the slave latch feedback loop and connected to the input terminal of the sixth inverter 201.

[0075] Only the branch containing the seventh inverter 202 is equipped with a delay element 30. The delay element 30 is located at the first node of the slave latch feedback loop and connected to the input terminal of the seventh inverter 202.

[0076] Preferably, the trigger circuit provided in this application may also be: both the feedback loop of the master latch 10 and the feedback loop of the slave latch 20 are provided with delay elements 30, the master latch 10 includes a fourth inverter 101 and a fifth inverter 102, and the master latch 20 includes a sixth inverter 201 and a seventh inverter 202.

[0077] The branch containing the fourth inverter 101 and / or the branch containing the fifth inverter 102 is provided with a delay element, and the branch containing the sixth inverter 201 and / or the branch containing the seventh inverter 202 is provided with a delay element.

[0078] Preferably, the branch containing the fourth inverter 101 and the branch containing the fifth inverter 102 are both equipped with delay elements, and the branch containing the sixth inverter 201 and the branch containing the seventh inverter 202 are both equipped with delay elements.

[0079] Optionally, only the branch containing the fourth inverter 101 and the branch containing the sixth inverter 201 are provided with delay elements; only the branch containing the fifth inverter 102 and the branch containing the seventh inverter 202 are provided with delay elements; only the branch containing the fourth inverter 101 and the branch containing the seventh inverter 202 are provided with delay elements; only the branch containing the fifth inverter 102 and the branch containing the sixth inverter 201 are provided with delay elements.

[0080] Therefore, regardless of whether it is a master-level latch or a slave-level latch, the method of adding a delay element in the latch feedback loop in this application can include: (a) adding two delay elements in the feedback loop, with the delay elements located before two inverters (e.g., the fourth inverter and the fifth inverter); (b) adding one delay element in the feedback loop, with the delay element located before one of the inverters (e.g., the fourth inverter); (c) adding one delay element in the feedback loop, with the delay element located before another inverter (e.g., the fifth inverter).

[0081] Among them, targeting Figure 3 For the delay element including resistor and gate switch shown, during the data transmission phase, the gate switch of the delay element is closed, which disables the passive load (i.e., short-circuit the two ends of the resistor) and does not affect the data transmission speed; during the data holding phase, the gate switch is open, and the delay element is equivalent to a passive load (resistor).

[0082] against Figure 4 For the delay element including the capacitor and the gate switch shown, during the data transmission phase, the gate switch of the delay element is opened, which disables the passive load (i.e., the capacitor is open-circuited) and does not affect the data transmission speed; during the data holding phase, the gate switch is closed, and the delay element is equivalent to a passive load (capacitor).

[0083] Optionally, such as Figure 8 As shown in a, the logic input circuit 40 can be a D flip-flop.

[0084] As another alternative embodiment, such as Figure 8 As shown in b, c, and d, the logic input circuit 40 can be a synchronous reset D flip-flop, a D scan flip-flop, or a synchronous reset D scan flip-flop, etc. Of course, other flip-flops with different structures suitable for this application can also be used, and this application does not impose any restrictions.

[0085] As an alternative embodiment, such as Figure 9 As shown in a, the clock gate sub-circuit mentioned in this application can be a clock gate element.

[0086] As another alternative embodiment, such as Figure 9As shown in b and c, the clock gate circuit can be a clock gate circuit composed of PMOS and NMOS transistors. Of course, other clock gate circuits with different structures suitable for this application can also be used, and this application does not impose any restrictions.

[0087] This application provides a novel single-event hardened trigger circuit. By cascading a master-level latch and a slave-level latch through a gated clock circuit, and adding a delay element in the latch feedback loop, it can adapt to different radiation energies and different process dimensions by adjusting the delay element (e.g., ...). Figure 3 The resistance value shown or Figure 4 The capacitance value shown can achieve single-event immunity for the flip-flop. Since the delay element controlled by the clock has a small load during data transmission, the data transmission speed of the flip-flop is unaffected. The flip-flop transmits data through two separate paths during the data transmission phase, without going through the feedback structure of the latch, thus achieving a faster transmission speed than traditional flip-flops. Therefore, this application only requires a small increase in area overhead to achieve a good ruggedization effect on the flip-flop circuit. It solves the problem that traditional ruggedization methods have large area overhead and are prone to single-event upsets due to ruggedization defects when exposed to high-energy radiation or when the transistors used in the flip-flop have small dimensions.

[0088] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0089] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0090] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A single event hardening flip-flop circuit, comprising: The application relates to a flip-flop circuit, comprising: a master stage latch and a slave stage latch connected in parallel between a first transmission channel and a second transmission channel, a first input / output terminal of the master stage latch and the slave stage latch being connected with the first transmission channel, and a second input / output terminal of the master stage latch and the slave stage latch being connected with the second transmission channel; a delay element arranged in a feedback loop of the master stage latch and / or the slave stage latch; the delay element is used to keep the level of a second node of the feedback loop unchanged when a first node of the feedback loop is affected by single particle incidence during data holding of the latch, and the level of the first node is recovered after ionizing radiation ends; the delay element comprises a resistance and a gate switch, the resistance and the gate switch are connected in parallel, a first end of the resistance and the gate switch is an input terminal of the delay element, and a second end of the resistance and the gate switch is an output terminal of the delay element, and the gate switch is used to be disconnected during data holding of the latch; alternatively, the delay element further comprises a capacitor and a gate switch, one end of the capacitor and one end of the gate switch are connected in series, the other end of the gate switch is an input terminal and an output terminal of the delay element, the other end of the capacitor is connected with a fixed level, and the gate switch is used to be closed during data holding of the latch.

2. The single event hardening flip-flop circuit of claim 1, wherein, The application further relates to a flip-flop circuit, comprising: a first inverter, a second inverter, a third inverter, a first clock gating sub-circuit, a second clock gating sub-circuit, a third clock gating sub-circuit and a fourth clock gating sub-circuit; an input terminal of the first inverter and an input terminal of the first clock gating sub-circuit are input terminals of the flip-flop circuit, the first inverter is connected in series with the third clock gating sub-circuit, the fourth clock gating sub-circuit and the third inverter in sequence, an output terminal of the first clock gating sub-circuit is connected in series with the second clock gating sub-circuit and the second inverter in sequence, the second inverter is a first output terminal of the flip-flop circuit, and an output terminal of the third inverter is a second output terminal of the flip-flop circuit; the master stage latch is connected between an output terminal of the first clock gating sub-circuit and an output terminal of the third clock gating sub-circuit, and the slave stage latch is connected between an output terminal of the second clock gating sub-circuit and an output terminal of the fourth clock gating sub-circuit.

3. The single event hardening flip-flop circuit of claim 1, wherein, the delay element is arranged in a feedback loop of the master stage latch, and the master stage latch comprises a fourth inverter and a fifth inverter; the fourth inverter and the fifth inverter are connected in parallel, an input terminal of the fourth inverter and an output terminal of the fifth inverter are a first input / output terminal of the master stage latch, and an output terminal of the fourth inverter and an input terminal of the fifth inverter are a second input / output terminal of the master stage latch; the branch where the fourth inverter is located and / or the branch where the fifth inverter is located are provided with the delay element.

4. The single event hardening flip-flop circuit of claim 3, wherein, The branch where the fourth inverter is located is provided with the delay element, and the delay element is arranged between the first node of the main stage latch feedback loop and the input end of the fourth inverter.

5. The single event hardening flip flop circuit of claim 3, wherein, The branch where the fourth inverter is located is provided with the delay element, and the delay element is arranged between the first node of the main stage latch feedback loop and the input end of the fourth inverter.

6. The single event hardening flip flop circuit of claim 3, wherein, The branch where the fifth inverter is located is provided with the delay element, and the delay element is arranged between the second node of the main stage latch feedback loop and the input end of the fifth inverter.

7. The single event hardening flip flop circuit of claim 1, wherein, The feedback loop of the slave stage latch is provided with the delay element, and the slave stage latch comprises a sixth inverter and a seventh inverter. The sixth inverter and the seventh inverter are connected in parallel, the input end of the sixth inverter and the output end of the seventh inverter serve as a first input and output end of the slave stage latch, and the output end of the sixth inverter and the input end of the seventh inverter serve as a second input and output end of the slave stage latch. The branch where the sixth inverter is located and / or the branch where the seventh inverter is located is provided with the delay element.

8. The single event hardening flip-flop circuit of claim 7, wherein, The branch where the sixth inverter and the seventh inverter are located is provided with the delay element, and the delay element comprises a first delay element and a second delay element, the first delay element is arranged between the first node of the slave stage latch feedback loop and the input end of the sixth inverter, and the second delay element is arranged between the second node of the slave stage latch feedback loop and the input end of the seventh inverter.

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