An anti-single event upset latch circuit

Abstract

The application discloses an anti-single event upset latch circuit, which comprises a first inverter, a first gated inverter, a second gated inverter and a first delay element. The first delay element is connected to a branch of the first inverter in a latch feedback loop. When the latch enters a data transfer stage, the first delay element is disabled, so that no load is added and the data transfer speed is not reduced. When the latch enters a data retention stage, the first delay element is enabled. Based on the load delay characteristic of the first delay element, the latch is prevented from locking an error level, so that single event immunity is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an anti-single event upset latch circuit. BACKGROUND

[0002] In a radiation environment, the charged particles incident from outside will cause ionizing radiation, and a certain number of electron-hole pairs will be generated around the trajectory of the particles. When the number of deposited electron-hole pairs along the particle incident direction is sufficient, the current caused by the electron-hole pairs collected by the depletion layer will cause the flip of the drain level, forming a single event upset. The level occurring in the combinational logic unit is restored when the single event upset ends; when the particle upset occurs in the sequential logic unit (such as flip-flop, latch, etc.) or memory storage array, the upset is locked due to the existence of the feedback structure in the storage unit, and the level cannot be restored. As the structure with storage memory function in the flip-flop circuit, the latch becomes the core of the design of the anti-single event upset of the digital circuit, and the latch needs to be reinforced to ensure that the single event upset can be restored after the ionizing radiation ends, and the single event immunity is realized.

[0003] As shown in Figure 1 The preferred way of reinforcing the latch is to add a delay element (resistor or capacitor) with load delay characteristics in the branch of the first inverter of the latch feedback loop. When the node level at one end of the feedback loop with the delay element in the latch is affected by the single particle incident, the load delay characteristics of the delay element will maintain the node level at the other end of the feedback loop unchanged, and the affected node level will be restored after the ionizing radiation ends, realizing the single event immunity of the latch. However Figure 1 In the circuit shown, a load is added during the data transmission stage of the latch, which reduces the data transfer speed. SUMMARY

[0004] The present application provides an anti-single event upset latch circuit, which solves the technical problems of latch single event reinforcement and slow circuit data transfer speed.

[0005] The present application provides the following technical solutions:

[0006] An anti-single event upset latch circuit, comprising a first inverter, a first gated inverter, a second gated inverter and a first delay element;

[0007] The output end of the second gated inverter is connected to the input end of the first inverter, the input end of the first inverter is also connected to the output end of the first gated inverter, the output end of the first inverter is connected to the input end of the first gated inverter, and the first delay element is located in the branch of the first inverter, and the first delay element has load delay characteristics;

[0008] The control end of the first gate inverter, the control end of the second gate inverter and the control end of the first delay element are connected to an external clock control signal, the first gate inverter is turned off and the first delay element is disabled when the second gate inverter is turned on, and the first gate inverter is turned on and the first delay element is enabled when the second gate inverter is turned off.

[0009] Preferably, the first delay element comprises a resistor and a first switch tube;

[0010] The resistor is connected in series to the branch where the first inverter is located, the first switch tube is connected in parallel to the resistor, the control end of the first switch tube is connected to the external clock control signal, and the first switch tube is turned on when the second gate inverter is turned on, and the first switch tube is turned off when the second gate inverter is turned off.

[0011] Preferably, the first delay element comprises a capacitor and a second switch tube;

[0012] The branch where the first inverter is located is connected to a fixed level through the second switch tube and the capacitor connected in series, the control end of the second switch tube is connected to the external clock control signal, and the second switch tube is turned off when the second gate inverter is turned on, and the second switch tube is turned on when the second gate inverter is turned off.

[0013] Preferably, the anti-single event upset latch circuit further comprises a second delay element, the second delay element has a load delay characteristic, the second delay element is always enabled, and the second delay element is located in the branch where the first gate inverter is located;

[0014] The first delay element connects a line between the output end of the first inverter and the input end of the first gate inverter, and the second delay element connects a line between the output end of the first gate inverter and the input end of the first inverter;

[0015] Or

[0016] The first delay element connects a line between the output end of the first gate inverter and the input end of the first inverter, and the second delay element connects a line between the output end of the first inverter and the input end of the first gate inverter.

[0017] Preferably, the second delay element is a resistor;

[0018] The resistor is connected in series to the branch where the first gate inverter is located.

[0019] Preferably, the second delay element is a capacitor;

[0020] The branch where the first gate inverter is located is fixed to a constant level through the capacitor.

[0021] Preferably, the anti-single event upset latch circuit further comprises a second delay element having a load delay characteristic, the second delay element being disabled when the second gate inverter is turned on and enabled when the second gate inverter is turned off.

[0022] The first delay element connects a line between the output of the first inverter and the input of the first gate inverter, and the second delay element connects a line between the output of the first gate inverter and the input of the first inverter.

[0023] Or

[0024] The first delay element connects a line between the output of the first gate inverter and the input of the first inverter, and the second delay element connects a line between the output of the first inverter and the input of the first gate inverter.

[0025] Preferably, the second delay element is the same as the first delay element.

[0026] Preferably, the first gate inverter comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor.

[0027] An external high level is connected to an external low level through the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor in series, the gate of the second MOS transistor is connected to the gate of the third MOS transistor and is the input of the first gate inverter, the common end of the output of the second MOS transistor and the output of the third MOS transistor is the output of the first gate inverter, the first MOS transistor and the second MOS transistor are PMOS which are turned on at a low level, and the third MOS transistor and the fourth MOS transistor are NMOS which are turned on at a high level.

[0028] Preferably, the first gate inverter comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor.

[0029] An external high level is connected to an external low level through the fifth MOS transistor and the sixth MOS transistor in series, the gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor and is the input of the first gate inverter, the fifth MOS transistor is PMOS which is turned on at a low level, and the sixth MOS transistor is NMOS which is turned on at a high level.

[0030] The seventh MOS transistor and the eighth MOS transistor are connected in parallel, the output end of the fifth MOS transistor and the output end of the sixth MOS transistor are connected to the input end of the seventh MOS transistor and the input end of the eighth MOS transistor, the output end of the seventh MOS transistor is connected to the output end of the eighth MOS transistor and is also the output end of the first gate inverter, the on level of the seventh MOS transistor and the eighth MOS transistor is opposite, and the control logic of the seventh MOS transistor and the eighth MOS transistor is opposite.

[0031] The technical scheme provided by the present application has at least the following technical effects or advantages:

[0032] The first delay element is connected in the branch of the first inverter in the latch feedback loop, when the latch enters the data transmission stage, the first delay element is disabled, and will not increase the load and reduce the data transmission speed; when the latch enters the data retention stage, the first delay element is effective, and the load delay characteristic based on the first delay element avoids the latch of the error level, thereby realizing single particle immunity. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0034] Figure 1 A circuit diagram of the anti-single event upset latch;

[0035] Figure 2 A partial circuit diagram of the ordinary non-hardened latch;

[0036] Figure 3 Another partial circuit diagram of the ordinary non-hardened latch;

[0037] Figure 4 A circuit diagram of the first gate inverter and the second gate inverter in the embodiment of the present application;

[0038] Figure 5 Another circuit diagram of the first gate inverter and the second gate inverter in the embodiment of the present application;

[0039] Figure 6 A circuit diagram of the anti-single event upset latch in the embodiment of the present application;

[0040] Figure 7 A circuit diagram of the first delay element in the embodiment of the present application;

[0041] Figure 8 A specific circuit diagram of Figure 7 ;

[0042] Figure 9 Another circuit diagram of the first delay element in the embodiment of the present application;

[0043] Figure 10 The specific circuit diagram of Figure 9

[0044] Figure 11 Another circuit diagram of the anti-single event upset latch in the embodiment of the present application;

[0045] Figure 12 Another circuit diagram of the anti-single event upset latch in the embodiment of the present application. DETAILED DESCRIPTION

[0046] The embodiment of the present application provides an anti-single event upset latch circuit, and solves the technical problem of slow data transmission speed when the latch is single event hardened.

[0047] In order to better understand the technical scheme of the present application, the technical scheme of the present application will be described in detail below in combination with the drawings in the specification and the specific embodiments.

[0048] Firstly, the term "and / or" appearing in the present text is only used to describe the association relationship of the associated objects, and represents that there can be three kinds of relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present text generally represents an "or" relationship between the front and rear associated objects.

[0049] As shown in Figure 2 The ordinary unhardened latch circuit includes a first inverter, a fourth inverter, a fifth inverter, a first gated inverter, and a second gated inverter. The input end of the second gated inverter is the D end of the latch, the output end of the second gated inverter is connected to the input end of the first inverter and the input end of the fourth inverter, the output end of the fourth inverter is the Q end of the latch, the output end of the first inverter is also connected to the input end of the fifth inverter, the output end of the fifth inverter is the Qn end of the latch, the output end of the first inverter is also connected to the input end of the first gated inverter, and the output end of the first gated inverter is also connected to the input end of the first inverter.

[0050] ​The control end of the first gate inverter and the control end of the second gate inverter are connected to an external clock control signal, the second gate inverter is turned on when the first gate inverter is turned off, and the first gate inverter is turned on when the second gate inverter is turned off. When the external clock control signal is high, the second gate inverter is turned on, the first gate inverter is turned off, and the latch is in a data transfer stage; when the external clock control signal is low, the second gate inverter is turned off, the first gate inverter is turned on, and the latch is in a data retention stage. When the external clock control signal is low, the second gate inverter is turned on, the first gate inverter is turned off, and the latch is in a data transfer stage; when the external clock control signal is high, the second gate inverter is turned off, the first gate inverter is turned on, and the latch is in a data retention stage. The type of the latch is not limited here.

[0051] Generally, as shown in Figure 3 The common non-hardened latch circuit further includes a second inverter and a third inverter. The input end of the second inverter is connected to the external clock control signal, the output end of the second inverter is connected to the input end of the third inverter, the output end of the second inverter outputs a first clock control signal, and the output end of the third inverter outputs a second clock control signal. The first gate inverter and the second gate inverter are controlled by the first clock control signal and the second clock control signal.

[0052] For the specific circuit of the first gate inverter, as shown in Figure 4 The first gate inverter can include a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. An external high level is connected to an external low level through the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube in series. The gate of the second MOS tube is connected to the gate of the third MOS tube and is also the input end of the first gate inverter. The common end of the output end of the second MOS tube and the output end of the third MOS tube is the output end of the first gate inverter. The first MOS tube and the second MOS tube are PMOS with low-level conduction, and the third MOS tube and the fourth MOS tube are NMOS with high-level conduction.

[0053] Figure 4 In the circuit, the gate of the first MOS tube and the gate of the fourth MOS tube are used as the control end of the first gate inverter. When the gate of the first MOS tube is connected to the first clock control signal and the gate of the fourth MOS tube is connected to the second clock control signal, the latch enters a data retention stage when the external clock control signal is high. At this time, the second gate inverter is turned on, the first gate inverter is turned off, and the latch is in a data transfer stage. Figure 4By modifying the circuit so that the gate of the first MOSFET is connected to the second clock control signal and the gate of the fourth MOSFET is connected to the first clock control signal, the specific circuit of the second gated inverter can be obtained. When the gate of the first MOSFET is connected to the second clock control signal and the gate of the fourth MOSFET is connected to the first clock control signal, the latch enters the data holding stage when the external clock control signal is low. Figure 4 By modifying the circuit so that the gate of the first MOSFET is connected to the first clock control signal and the gate of the fourth MOSFET is connected to the second clock control signal, the specific circuit of the second gated inverter can be obtained.

[0054] like Figure 5 As shown, the first gated inverter may further include a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. An external high-level signal is sequentially connected to an external low-level signal via the fifth and sixth MOSFETs connected in series. The gate of the fifth MOSFET is connected to the gate of the sixth MOSFET and both serve as inputs to the first gated inverter. The fifth MOSFET is a PMOS transistor that conducts at low levels, and the sixth MOSFET is an NMOS transistor that conducts at high levels. The seventh and eighth MOSFETs are connected in parallel. The common terminal of the outputs of the fifth and sixth MOSFETs is connected to the inputs of both the seventh and eighth MOSFETs. The output of the seventh MOSFET is connected to the output of the eighth MOSFET and both serve as outputs to the first gated inverter. The conduction levels of the seventh and eighth MOSFETs are opposite, and their control logic is also opposite.

[0055] Figure 5 In the circuit, the gates of the seventh and eighth MOSFETs serve together as the control terminals of the first gated inverter. When the seventh MOSFET is a PMOS, the eighth MOSFET is an NMOS; conversely, when the seventh MOSFET is an NMOS, the eighth MOSFET is a PMOS. Taking the seventh MOSFET as a PMOS and the eighth MOSFET as an NMOS as an example, when the gate of the seventh MOSFET is connected to the first clock control signal and the gate of the eighth MOSFET is connected to the second clock control signal, the latch enters the data holding stage when the external clock control signal is high. Figure 5 By modifying the circuit so that the gate of the seventh MOSFET is connected to the second clock control signal and the gate of the eighth MOSFET is connected to the first clock control signal, the specific circuit of the second gated inverter can be obtained. When the gate of the seventh MOSFET is connected to the second clock control signal and the gate of the eighth MOSFET is connected to the first clock control signal, the latch enters the data holding stage when the external clock control signal is low. Figure 5 By modifying the circuit so that the gate of the seventh MOSFET is connected to the first clock control signal and the gate of the eighth MOSFET is connected to the second clock control signal, the specific circuit of the second gated inverter can be obtained.

[0056] Since the seventh MOS transistor and the eighth MOS transistor are turned on and turned off at the same time, only one of the seventh MOS transistor and the eighth MOS transistor can be reserved, such as the seventh MOS transistor, but it is necessary to ensure that the seventh MOS transistor in the first gate inverter and the second gate inverter meets: when the control signal of the seventh MOS transistor in the first gate inverter is the first clock control signal, the control signal of the seventh MOS transistor in the second gate inverter is the second clock control signal; when the control signal of the seventh MOS transistor in the first gate inverter is the second clock control signal, the control signal of the seventh MOS transistor in the second gate inverter is the first clock control signal.

[0057] The single event upset occurs at the connection node of the feedback loop composed of the first inverter and the first gate inverter, that is, the connection between the output end of the first gate inverter and the input end of the first inverter or the connection between the output end of the first inverter and the input end of the first gate inverter. When the latch is in the data retention stage, if a single event upset occurs, the feedback loop composed of the first inverter and the first gate inverter will lock the upset and the level cannot be restored. The preferred way to reinforce the latch is Figure 1 The circuit shown in the figure, but Figure 1 The resistance increases the load in the data transmission stage of the latch, which reduces the data transfer speed.

[0058] The single event upset resistant latch circuit of the embodiment includes a common unhardened latch circuit and a first delay element. As shown in the figure, Figure 6 The first delay element is located in the branch of the first inverter, and the first delay element has a load delay characteristic. The control end of the first delay element is connected to an external clock control signal, the first delay element is disabled when the second gate inverter is turned on and the first gate inverter is turned off, and the first delay element is enabled when the second gate inverter is turned off and the first gate inverter is turned on.

[0059] Specifically, the first delay element can include a resistance and a first switch tube, or include a capacitor and a second switch tube, or the first delay element is a gate diode. When the first delay element includes a resistance and a first switch tube, as shown in the figure, Figure 7 The resistance is connected in series in the branch of the first inverter, the first switch tube is connected in parallel with the resistance, the control end of the first switch tube is connected to an external clock control signal, the first switch tube is turned on when the second gate inverter is turned on, and the first switch tube is turned off when the second gate inverter is turned off. As shown in the figure, Figure 8As shown, the first switch tube can include a ninth MOS tube and a tenth MOS tube in parallel, the on level of the ninth MOS tube is opposite to that of the tenth MOS tube, and the control logic of the ninth MOS tube is opposite to that of the tenth MOS tube. When the ninth MOS tube is PMOS and the tenth MOS tube is NMOS, or when the ninth MOS tube is NMOS and the tenth MOS tube is PMOS. Taking the ninth MOS tube as PMOS and the tenth MOS tube as NMOS as an example, when the gate of the ninth MOS tube is connected to the first clock control signal and the gate of the tenth MOS tube is connected to the second clock control signal, the latch enters the data transfer stage when the external clock control signal is high; when the gate of the ninth MOS tube is connected to the second clock control signal and the gate of the tenth MOS tube is connected to the first clock control signal, the latch enters the data transfer stage when the external clock control signal is low. Since the ninth MOS tube and the tenth MOS tube are turned on and turned off at the same time, one of them can also be omitted.

[0060] In the data transfer stage of the latch, the first switch tube is turned on, the resistance is short-circuited, the resistance is disabled, the load is not increased, and the data transfer speed is not reduced; in the data retention stage of the latch, the first switch tube is turned off, the resistance is effective, and single particle immunity is achieved.

[0061] When the first delay element includes a capacitor and a second switch tube, as shown in Figure 9 As shown, the branch where the first inverter is located is connected in sequence to a second switch tube, a capacitor and a fixed level, the control end of the second switch tube is connected to an external clock control signal, the second switch tube is turned off when the second gate-controlled inverter is turned on, and the second switch tube is turned on when the second gate-controlled inverter is turned off. Among them, the second switch tube, the capacitor and the fixed level are connected in sequence, and the connection order of the second switch tube and the capacitor cannot be changed. As shown in Figure 10 As shown, the second switch tube can include an eleventh MOS tube and a twelfth MOS tube in parallel. When the eleventh MOS tube is PMOS and the twelfth MOS tube is NMOS, or when the eleventh MOS tube is NMOS and the twelfth MOS tube is PMOS. Since the eleventh MOS tube and the twelfth MOS tube are turned on and turned off at the same time, one of them can also be omitted. In the data transfer stage of the latch, the second switch tube is turned off, the capacitor is disconnected, the capacitor is disabled, the load is not increased, and the data transfer speed is not reduced; in the data retention stage of the latch, the second switch tube is turned on, the capacitor is effective, and single particle immunity is achieved.

[0062] Since the first delay element can only harden the elements located in front of it in the signal flow, the single particle immunity effect is weak. Therefore, the present embodiment provides two schemes to enhance the single particle immunity effect, the first one is as shown in Figure 11As shown in the figure, the anti-single event upset latch circuit of the embodiment further comprises a second delay element, the second delay element has a load delay characteristic, the second delay element is always effective, and the second delay element is located in the branch where the first gated inverter is located.

[0063] The first delay element is connected to a line between an output end of the first inverter and an input end of the first gated inverter, and the second delay element is connected to a line between an output end of the first gated inverter and an input end of the first inverter.

[0064] Or

[0065] The first delay element is connected to a line between an output end of the first gated inverter and an input end of the first inverter, and the second delay element is connected to a line between an output end of the first inverter and an input end of the first gated inverter.

[0066] The second delay element can be a resistor or a capacitor. When the second delay element is a resistor, the resistor is connected in series to the branch where the first gated inverter is located. When the second delay element is a capacitor, the branch where the first gated inverter is located is connected to a fixed level through the capacitor. In this way, the first inverter and the first gated inverter can be reinforced at the same time, and the single event immunity effect is good. The fixed level in the embodiment can be a power supply or a ground.

[0067] The second kind as Figure 12 As shown in the figure, the anti-single event upset latch circuit further comprises a second delay element, the second delay element has a load delay characteristic, the second delay element is invalid when the second gated inverter is turned on and the second delay element is effective when the second gated inverter is turned off;

[0068] The first delay element is connected to a line between an output end of the first inverter and an input end of the first gated inverter, and the second delay element is connected to a line between an output end of the first gated inverter and an input end of the first inverter.

[0069] Or

[0070] The first delay element is connected to a line between an output end of the first gated inverter and an input end of the first inverter, and the second delay element is connected to a line between an output end of the first inverter and an input end of the first gated inverter.

[0071] The second delay element can be located in the branch where the first gated inverter is located or in the branch where the first inverter is located, and the implementation mode of the second delay element can be the same as that of the first delay element, which will not be described here.

[0072] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that the appended claims include all such modifications and variations as fall within the scope of the present application.

[0073] It is apparent that those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. It is therefore intended that the present application cover all such changes and modifications that are within its scope.

Claims

1. A single event upset immune latch circuit, comprising: The first inverter, the first gate inverter, the second gate inverter and the first delay element are included; The output end of the second gate inverter is connected with the input end of the first inverter, the input end of the first inverter is also connected with the output end of the first gate inverter, the output end of the first inverter is connected with the input end of the first gate inverter, and the first delay element is located in the branch of the first inverter, and the first delay element has a load delay characteristic; The control end of the first gate inverter, the control end of the second gate inverter and the control end of the first delay element are connected with an external clock control signal, the first gate inverter is turned off and the first delay element is disabled when the second gate inverter is turned on, and the first gate inverter is turned on and the first delay element is enabled when the second gate inverter is turned off; The first delay element includes a resistor and a first switch tube, the resistor is connected in series in the branch of the first inverter, the first switch tube is connected in parallel with the resistor, the control end of the first switch tube is connected with the external clock control signal, the first switch tube is turned on when the second gate inverter is turned on, and the first switch tube is turned off when the second gate inverter is turned off; Or, The first delay element includes a capacitor and a second switch tube, the branch of the first inverter is connected with a fixed level through the second switch tube and the capacitor connected in series, the control end of the second switch tube is connected with the external clock control signal, the second switch tube is turned off when the second gate inverter is turned on, and the second switch tube is turned on when the second gate inverter is turned off.

2. The anti-single event upset latch circuit of claim 1, wherein, A second delay element is further included, the second delay element has a load delay characteristic, the second delay element is always enabled, and the second delay element is located in the branch of the first gate inverter; The first delay element is connected with a line between the output end of the first inverter and the input end of the first gate inverter, and the second delay element is connected with a line between the output end of the first gate inverter and the input end of the first inverter; Or The first delay element is connected with a line between the output end of the first gate inverter and the input end of the first inverter, and the second delay element is connected with a line between the output end of the first inverter and the input end of the first gate inverter.

3. The anti-single event upset latch circuit of claim 2, wherein, The second delay element is a resistor; The resistor is connected in series in the branch of the first gate inverter.

4. The anti-single event upset latch circuit of claim 2, wherein, The second delay element is a capacitor; The branch of the first gate inverter is connected with a fixed level through the capacitor.

5. The anti-single event upset latch circuit of claim 1, wherein, A second delay element is further included, the second delay element has a load delay characteristic, the second delay element is disabled when the second gate inverter is turned on, and the second delay element is enabled when the second gate inverter is turned off; The first delay element is connected with a line between the output end of the first inverter and the input end of the first gate inverter, and the second delay element is connected with a line between the output end of the first gate inverter and the input end of the first inverter; Or The first delay element connects a line between the output of the first gate inverter and the input of the first inverter, and the second delay element connects a line between the output of the first inverter and the input of the first gate inverter.

6. The anti-single event upset latch circuit of claim 5, wherein, The second delay element is the same as the first delay element.

7. The anti-single event upset latch circuit of claim 1, wherein, The first gate inverter comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube. An external high level is connected to an external low level through the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube in series, the gate of the second MOS tube is connected to the gate of the third MOS tube and is the input of the first gate inverter, the common end of the output of the second MOS tube and the output of the third MOS tube is the output of the first gate inverter, the first MOS tube and the second MOS tube are PMOS which are turned on at low level, and the third MOS tube and the fourth MOS tube are NMOS which are turned on at high level.

8. The anti-single event upset latch circuit of claim 1, wherein, The first gate inverter comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube. An external high level is connected to an external low level through the fifth MOS tube and the sixth MOS tube in series, the gate of the fifth MOS tube is connected to the gate of the sixth MOS tube and is the input of the first gate inverter, the fifth MOS tube is PMOS which is turned on at low level, and the sixth MOS tube is NMOS which is turned on at high level. The seventh MOS tube and the eighth MOS tube are connected in parallel, the common end of the output of the fifth MOS tube and the output of the sixth MOS tube is connected to the input of the seventh MOS tube and the input of the eighth MOS tube, the output of the seventh MOS tube is connected to the output of the eighth MOS tube and is the output of the first gate inverter, the turn-on level of the seventh MOS tube and the eighth MOS tube is opposite, and the control logic of the seventh MOS tube and the eighth MOS tube is opposite.

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