FPGA-based multi-channel signal selection method, system, electronic device and storage medium

Abstract

The application provides a kind of multi-channel signal selection method, system, electronic device and storage medium based on FPGA, comprising: presetting truth table in FPGA internal register, determining the data address corresponding to each service board;Receive control instruction, configure the storage information of control instruction in FPGA internal register;According to the mapping relationship between the data address of control instruction and the address element item of truth table, the data information of control instruction is sent to the corresponding service board;After the corresponding data information is received by the service board, send or do not send response signal within at least 2 clock cycles;Access each service board in turn, when obtaining response signal, establish communication connection with the service board.The system is mainly provided with main control board and external service board, wherein the main control board mainly includes FPGA and clock chip, FPGA can realize the interaction of signal to outside, clock chip provides clock for FPGA to guarantee the normal sampling of chip, and service board card can realize different functions according to actual needs.

Description

Technical Field

[0001] This invention belongs to the field of selection algorithms, specifically relating to a multi-channel signal selection method, system, electronic device, and storage medium based on FPGA. Background Technology

[0002] In the transmission of digital signals, it is sometimes necessary to select a specific data stream from multiple input data streams to complete the transmission of that stream. Traditionally, this is achieved using a multiplexer, but multiplexers present the following problems that need to be addressed:

[0003] 1. The increased complexity of hardware design requires designers to be more cautious.

[0004] A multiplexer typically has one input and multiple outputs. Circuit design requires consideration of both input and output signals; PCB routing must take into account routing complexity, including trace length, spacing, and available space, while also considering the impact of additional components on signal generation.

[0005] 2. Poor scalability; requires careful consideration based on application scenarios.

[0006] Multiplexers come in various specifications, such as 1-to-2, 1-to-4, and 1-to-8. Once a specific specification is used, the hardware is fixed, and changes can only be made by modifying the design. Inconsistencies between the initial design and the actual usage can lead to missing functionality or wasted resources. For some products, the actual application scenarios are highly variable, which can cause problems in the initial design, potentially resulting in over-design or under-design. Summary of the Invention

[0007] To address the aforementioned deficiencies or improvement needs of existing technologies, this invention provides a method, system, electronic device, and storage medium for multi-channel signal selection based on FPGA. This invention utilizes the FPGA hardware description language (Verilog HDL) to achieve intelligent selection of multiple input data channels. In this invention, the system mainly consists of a main control board and external service boards. The main control board can selectively control multiple service boards. The main control board primarily includes a controller, an FPGA, and a clock chip. The controller is used for signal control, acquisition, and processing; the FPGA is used for signal interaction; and the clock chip provides clock signals to the controller and FPGA, ensuring proper sampling. Multiple service boards can implement different functions according to actual needs.

[0008] To achieve the above objectives, according to a first aspect of the present invention, a multi-channel signal selection method based on FPGA is provided, the method comprising:

[0009] A truth table with at least one address element set to "0" or "1" is preset in the FPGA internal register to determine the data address corresponding to each service board;

[0010] Receive at least one control instruction, configure the storage information of the control instruction in the internal register of the FPGA, the storage information including data address and data information;

[0011] Based on the mapping relationship between the data address of the control instruction and the address element of the truth table, the data information of the control instruction is sent to the corresponding service board;

[0012] After receiving the corresponding data information, the service board may or may not send an acknowledgment signal within at least two clock cycles.

[0013] Each service board is accessed sequentially, and a communication connection is established with the service board when a response signal is received.

[0014] Furthermore, the number of address element items is set according to the number of service boards.

[0015] Furthermore, the data information includes the length of the data packet and the start bit.

[0016] Furthermore, the number of service boards is 8, and the number of address element items is 3.

[0017] Further, receiving at least one control instruction and configuring the storage information of the control instruction in the internal register of the FPGA includes:

[0018] The control instructions include multiple control sub-instructions. The storage information of the multiple control sub-instructions is configured in the internal register of the FPGA, and each control sub-instruction corresponds to a data address.

[0019] Furthermore, the step of sequentially accessing each service board and establishing a communication connection with that service board upon receiving a response signal includes:

[0020] When the FPGA receives an acknowledgment signal within two clock cycles, it establishes a communication connection with the service board. After the communication is established, a first interrupt signal is generated, thereby enabling access to the next service board.

[0021] If the FPGA does not receive an acknowledgment signal within two clock cycles, a second interrupt signal is generated, thereby enabling access to the next service board.

[0022] According to a second aspect of the present invention, an FPGA-based multi-channel signal selection system is provided, the system comprising a main control board and multiple service boards; wherein the main control board comprises at least one FPGA;

[0023] The FPGA includes:

[0024] The preset module is used to preset a truth table in the internal register with at least one address element as "0" or "1" to determine the data address corresponding to each service board.

[0025] A configuration module is configured to receive at least one control instruction and configure the storage information of the control instruction in the internal register, wherein the storage information includes a data address and data information;

[0026] The mapping module is used to send the data information of the control instruction to the corresponding service board according to the mapping relationship between the data address of the control instruction and the address element of the truth table;

[0027] The access module is used to access each service board sequentially and establish a communication connection with the service board when a response signal is received.

[0028] The service board is used to receive the corresponding data information and then send or not send an acknowledgment signal within at least two clock cycles.

[0029] Furthermore, the number of address element items is set according to the number of service boards.

[0030] According to a third aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0031] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0032] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0033] (I) This invention provides a method, system, electronic device, and storage medium for multi-channel signal selection based on FPGA. This invention utilizes the FPGA hardware description language (Verilog HDL) to achieve intelligent selection of multiple input data channels. The system mainly consists of a main control board and external service boards, with multiple service boards that can be configured. The main control board primarily includes an FPGA and an external clock chip. The FPGA enables signal interaction, while the clock chip provides the clock signal to the FPGA, ensuring proper sampling. Service boards can implement different functions according to actual needs. Furthermore, a controller can be configured on the main control board. The controller can control, acquire, and process signals, and issue control commands to the FPGA. The FPGA then configures the control command information and issues it to different service boards.

[0034] (II) This invention provides a method, system, electronic device, and storage medium for multiplexing signals based on an FPGA. After receiving a control command, the FPGA configures its internal registers. Once configured, the FPGA sends the control command to an external service board. Upon receiving the control command from the FPGA, the service board responds with a signal within two clock cycles. If no response signal is received, the FPGA considers the service board to have no signal to transmit and does not process it, continuing to query subsequent service boards. If a response signal is received, it is considered "Ready" and returns a response to the FPGA. The FPGA then establishes a connection with the service board and performs data communication. After communication is completed, an interrupt signal is generated, and the FPGA continues to send control commands to the next service board. Attached Figure Description

[0035] Figure 1 This is a flowchart of a multi-channel signal selection method based on FPGA implemented according to the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0037] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0038] It should be noted that the terms "first" and "second" used in this invention merely distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" can be interchanged in a specific order or sequence where permissible. It should be understood that the objects distinguished by "first" and "second" can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those described or illustrated herein.

[0039] According to one specific embodiment of this application, such as Figure 1As shown, a multi-channel signal selection method based on FPGA is provided. This embodiment is designed for data communication across eight service boards. To enable traversal of each service board and ensure efficiency, a clock is used to control the signals. It is stipulated that if the FPGA does not receive an acknowledgment signal within two clock cycles, it is considered that the service board has no data communication requirement, and resources are released to other service boards that need them. The implementation process is as follows:

[0040] S1: Pre-set a truth table in the FPGA internal register with at least one address element as "0" or "1" to determine the data address corresponding to each service board;

[0041] S2: Receive at least one control instruction and configure the storage information of the control instruction in the FPGA internal register. The storage information includes the data address and data information.

[0042] S3: Based on the mapping relationship between the data address of the control instruction and the address element of the truth table, send the data information of the control instruction to the corresponding service board;

[0043] S4: After receiving the corresponding data information, the service board may or may not send an acknowledgment signal within at least 2 clock cycles;

[0044] S5: Access each service board sequentially, and establish a communication connection with the service board when a response signal is received.

[0045] Specifically, in step S1, since the truth table contains address elements that are either "0" or "1", the number of address elements is set according to the number of service boards, thus distinguishing the addresses of the service boards. In this embodiment, the FPGA sends control commands to external service boards. Because there are many service boards, they need to be distinguished and stored in a register in the form of a truth table. This embodiment supports 8 service boards, so the number of address elements is set to 3. The truth table format is shown in Table 1 below. This embodiment supports 8 service boards and can be expanded or reduced according to actual needs. Therefore, this application does not require modification of the hardware circuit; the selection of service boards can be achieved using only the FPGA.

[0046] Table 1 Truth Table for Business Board 8

[0047]

[0048]

[0049] Specifically, in step S2, after receiving the control command, the FPGA configures its internal registers. A controller can be designed when designing the system, and the controller can send control commands to the FPGA. Both the controller and the FPGA can be located on the main control board. The controller can control, acquire, and process signals, while the FPGA can handle external signal interaction. Service boards can implement different functions according to actual needs.

[0050] More specifically, the data information includes the length of the data packet and the start bit.

[0051] Specifically, in step S3, the data information of the control instruction is sent to the corresponding service board according to the mapping relationship between the data address of the control instruction and the address element of the truth table. The data address in the control instruction corresponding to each service board is preset. After the data address in the control instruction is extracted in step S2, it is matched with the truth table. For example, the data address in the control instruction corresponding to service board 1 is "000". When the control instruction is obtained to configure the data address, the data address is extracted as "000". After matching it with the truth table, it is determined to be service board 1. That is, a mapping relationship is established between the data address of the control instruction and the address element of the truth table.

[0052] More specifically, in practice, the control instructions are composite control instructions, that is, the control instructions include multiple control sub-instructions. Different control sub-instructions correspond to different service boards. Therefore, it is necessary to configure the storage information of multiple control sub-instructions in the FPGA's internal registers, and each control sub-instruction corresponds to a data address.

[0053] Specifically, steps S4 and S5 include:

[0054] 1. When the FPGA receives an acknowledgment signal within 2 clock cycles, it establishes a communication connection with the service board. After the communication is established, a first interrupt signal is generated, thereby enabling access to the next service board.

[0055] II. If the FPGA does not receive an acknowledgment signal within 2 clock cycles, a second interrupt signal is generated, thereby enabling access to the next service board.

[0056] More specifically, after receiving a control command from the FPGA, the service board responds with a signal within two clock cycles. If no response signal is received, the FPGA considers that the service board has no signal to transmit and does not process it, continuing to query subsequent service boards. If a response signal is received, it is considered ready and returns a message to the FPGA. The FPGA then establishes a connection with the service board and begins data communication.

[0057] More specifically, the process of steps S4 and S5 is repeated until all business boards are accessed, ensuring that external data can be processed in a timely and effective manner.

[0058] More specifically, to achieve dynamic switching, two clock cycles are specified here. In practical applications, and when designing the corresponding system, a clock module can be designed. As mentioned above, a main control board can be designed, connecting multiple service boards to it. The main control board has a controller and an FPGA. The controller can send corresponding instructions to the FPGA. The FPGA, after configuring the relevant instructions, sends them to the corresponding service boards. The controller can control, acquire, and process signals, while the FPGA can handle external signal interaction. Service boards can implement different functions according to actual needs. Furthermore, a clock module can be set on the main control board, connected to both the controller and the FPGA. In this example, data communication is designed for eight service boards. To traverse each service board and ensure efficiency, signals are controlled by a clock. It can be specified that if the FPGA does not receive a response signal within two clock cycles, it is considered that the service board has no data communication requirement, and resources are released to other service boards that need them. To achieve dynamic switching, two clock cycles are specified here, but in practical applications, this can be adjusted according to specific circumstances. The advantages of specifying two clock cycles are mainly:

[0059] (i) Control is based on a clock, which is convenient. The clock here is provided by an external chip. As long as the external chip is working, there is a clock signal, which is easy to sample.

[0060] (ii) Specify a fixed time. After this time, the system can repeat the previous operation, which can ensure effective control of the system and prevent it from being in an infinite loop.

[0061] (iii) Two clock cycles consume fewer system resources, which can ensure system efficiency.

[0062] Specifically, each service board is accessed sequentially, and a communication connection is established with that service board when a response signal is received, including:

[0063] According to another specific embodiment of the present invention, an FPGA-based multi-channel signal selection system is provided. The system is designed and formed based on the above method. The system includes a main control board and multiple service boards; wherein, the main control board includes at least one FPGA.

[0064] FPGA includes:

[0065] The preset module is used to preset a truth table in the internal register with at least one address element as "0" or "1" to determine the data address corresponding to each service board.

[0066] The configuration module is used to receive at least one control instruction and configure the storage information of the control instruction in the internal register. The storage information includes the data address and data information.

[0067] The mapping module is used to send the data information of the control command to the corresponding service board according to the mapping relationship between the data address of the control command and the address element of the truth table;

[0068] The access module is used to access each service board sequentially and establish a communication connection with the service board when a response signal is received.

[0069] The service board is used to receive the corresponding data information and then send or not send an acknowledgment signal within at least two clock cycles.

[0070] More specifically, as described above, a main control board can be designed, connecting multiple service boards to it. The main control board includes a controller, an FPGA, and a clock module. The controller sends corresponding instructions to the FPGA, which then configures these instructions and sends them to the appropriate service boards. The controller controls, acquires, and processes signals, while the FPGA handles external signal interaction. Service boards can implement different functions as needed. The clock module connects to both the controller and the FPGA. The main control board communicates with multiple service boards. To enable traversal of each service board and ensure efficiency, signals are controlled via a clock. It can be stipulated that if the FPGA does not receive a response signal within two clock cycles, it considers that the service board has no data communication requirement and releases resources to other service boards that need it. Two clock cycles are specified here for dynamic switching; however, this can be adjusted according to specific circumstances in practical applications.

[0071] More specifically, the configuration module is used for:

[0072] The control instructions include multiple control sub-instructions. The storage information of the multiple control sub-instructions is configured in the internal register of the FPGA, and each control sub-instruction corresponds to a data address.

[0073] More specifically, the access module is used for:

[0074] When the FPGA receives an acknowledgment signal within two clock cycles, it establishes a communication connection with the service board. After the communication is established, a first interrupt signal is generated, thereby enabling access to the next service board.

[0075] If the FPGA does not receive an acknowledgment signal within two clock cycles, a second interrupt signal is generated, thereby enabling access to the next service board.

[0076] More specifically, the number of address element items is set according to the number of service boards. There are 8 service boards, and the number of address element items is 3.

[0077] More specifically, the data information includes the length of the data packet and the start bit.

[0078] According to another specific embodiment of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0079] According to another specific embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method described above.

[0080] It should be understood that any process or method description in the methods, flowcharts, or otherwise described herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of the invention pertain.

[0081] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0082] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0083] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0084] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0085] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for selecting multiple signals based on FPGA, characterized in that, The method includes: A truth table with at least one address element set to "0" or "1" is preset in the FPGA internal register to determine the data address corresponding to each service board; Receive at least one control instruction, configure the storage information of the control instruction in the internal register of the FPGA, the storage information including data address and data information; Based on the mapping relationship between the data address of the control instruction and the address element of the truth table, the data information of the control instruction is sent to the corresponding service board; After receiving the corresponding data information, the service board may or may not send an acknowledgment signal within at least two clock cycles. Each service board is accessed sequentially, and a communication connection is established with that service board when a response signal is received; the sequential access to each service board and the establishment of a communication connection with that service board when a response signal is received includes: When the FPGA receives an acknowledgment signal within two clock cycles, it establishes a communication connection with the service board. After the communication is established, a first interrupt signal is generated, thereby enabling access to the next service board. If the FPGA does not receive an acknowledgment signal within two clock cycles, a second interrupt signal is generated, thereby enabling access to the next service board.

2. The multi-channel signal selection method according to claim 1, characterized in that, The number of address element items is set according to the number of service boards.

3. The multi-channel signal selection method according to claim 1, characterized in that, The data information includes the length of the data packet and the start bit.

4. The multi-channel signal selection method according to claim 1, characterized in that, The number of service boards is 8, and the number of address element items is 3.

5. The multiplex signal selection method according to any one of claims 1 to 4, characterized in that, The step of receiving at least one control instruction and configuring the storage information of the control instruction in the internal register of the FPGA includes: The control instructions include multiple control sub-instructions. The storage information of the multiple control sub-instructions is configured in the internal register of the FPGA, and each control sub-instruction corresponds to a data address.

6. A multi-channel signal selection system based on FPGA, characterized in that, The system includes a main control board and multiple service boards; wherein the main control board includes at least one FPGA; The FPGA includes: The preset module is used to preset a truth table in the internal register with at least one address element as "0" or "1" to determine the data address corresponding to each service board. A configuration module is configured to receive at least one control instruction and configure the storage information of the control instruction in the internal register, wherein the storage information includes a data address and data information; The mapping module is used to send the data information of the control instruction to the corresponding service board according to the mapping relationship between the data address of the control instruction and the address element of the truth table; The access module is used to access each service board sequentially and establish a communication connection with the service board when a response signal is received. The service board is used to receive the corresponding data information and send or not send an acknowledgment signal within at least 2 clock cycles. When the FPGA obtains the acknowledgment signal within 2 clock cycles, a communication connection with the service board is established. After the communication is established, a first interrupt signal is generated, thereby enabling access to the next service board. If the FPGA does not receive an acknowledgment signal within two clock cycles, a second interrupt signal is generated, thereby enabling access to the next service board.

7. The multiplex signal selection system according to claim 6, characterized in that, The number of address element items is set according to the number of service boards.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-5.

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