Memory device and operating method using zero-pulse smart verification

Abstract

A memory device and method of operation are provided. The device includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and is also arranged into a string and configured to hold a threshold voltage within a common range of threshold voltages. Control circuitry coupled to the plurality of word lines and the string is configured to determine an erase upper tail voltage of a distribution of the threshold voltages of the memory cells after an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuitry is also configured to calculate, based on the erase upper tail voltage, a program voltage to be applied to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation.

Description

Technical Field

[0001] This application relates to the operation of non-volatile memory devices. Background Technology

[0002] This section provides background information on the technology associated with this disclosure and therefore is not necessarily prior art.

[0003] Semiconductor memories are used in a wide variety of electronic devices. For example, non-volatile semiconductor memories are used in cell phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable programmable read-only memory (EEPROM) and flash memory are among the most popular types of non-volatile semiconductor memories.

[0004] Some non-volatile memories utilize a floating gate positioned above a semiconductor substrate and insulated from the channel region within the substrate. The floating gate is located between the source and drain regions. A control gate is positioned above and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. In other words, the minimum voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

[0005] Some non-volatile memories utilize charge trapping layers to store information. One such example has an oxide-nitride-oxide (ONO) region, where a nitride (e.g., SiN) acts as a charge trapping layer to store information. When this memory cell is programmed, electrons are stored in the charge trapping layer.

[0006] Non-volatile memory can have either a 2D or 3D architecture. Ultra-high-density memory devices using 3D stacked memory structures with strings of memory cells have been adopted. Sometimes, such a memory device is referred to as a Bit-Cost Scalable-on-Chip (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductor and insulating layers. The conductor layers can act as word lines. Memory holes are drilled in the layers to simultaneously define many memory layers. NAND strings are then formed by filling the memory holes with appropriate materials. Straight NAND strings extend within a single memory hole, while tubular or U-shaped NAND strings (P-BiCS) contain a pair of vertical columns of memory cells extending within two memory holes and joined by a conduit connection. The conduit connection can be made of undoped polysilicon. A back gate can surround the conduit connection to control the conduction of the conduit connection. The control gate of the memory cell is provided by the conductor layer.

[0007] Before programming certain non-volatile memory devices, such as NAND flash memory devices, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate. For others, the erase operation removes electrons from the charge trapping layer. After erasing, it is necessary to determine the programming voltage to be used to program the memory cells in the programming operation. As the memory cells are repeatedly programmed and erased, the programming voltage used may need to be adjusted accordingly. Summary of the Invention

[0008] This section provides a general overview of the disclosure and is not a complete disclosure of its full scope or all of its features and advantages.

[0009] One objective of this disclosure is to provide a memory device and a method for operating the memory device that solves and overcomes the above-mentioned disadvantages.

[0010] Accordingly, one aspect of this disclosure provides an apparatus comprising a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are also arranged in a string and configured to maintain a threshold voltage within a common range of threshold voltages defining a threshold window. Control circuitry is coupled to the plurality of word lines and the string. The control circuitry is configured to determine an erase upper tail voltage, which represents the distribution of threshold voltages of the memory cells after an erase operation. The erase upper tail voltage corresponds to a loop condition of the memory cells. The control circuitry is also configured to calculate, based on the erase upper tail voltage, a programming voltage to be applied during a programming operation to each of the selected word lines associated with the memory cells to program the memory cells.

[0011] According to another aspect of this disclosure, a controller communicates with a memory device comprising blocks of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are arranged in a string and configured to maintain a threshold voltage within a common range of threshold voltages defining a threshold window. The controller is configured to determine an erase upper tail voltage, representing the distribution of threshold voltages of the memory cells after an erase operation. The erase upper tail voltage corresponds to a loop condition of the memory cells. The controller is further configured to calculate, based on the erase upper tail voltage, a programming voltage to be applied during a programming operation to each of the selected word lines associated with the memory cells to program the memory cells.

[0012] According to an additional aspect of this disclosure, a method of operating a memory device is provided. The memory device includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are arranged in a string and configured to maintain a threshold voltage within a common range of threshold voltages defining a threshold window. The method includes a step of determining an erase upper tail voltage, which is a distribution of threshold voltages of the memory cells after an erase operation, the erase upper tail voltage corresponding to a loop condition of the memory cells. The method continues with a step of calculating a programming voltage, based on the erase upper tail voltage, to be applied during a programming operation to each of a selection of the plurality of word lines associated with the memory cells to program the memory cells.

[0013] Other applicability will become apparent from the description provided herein. The descriptions and specific examples in this overview are intended for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0014] The accompanying drawings described herein are for illustrative purposes only, and not for all possible embodiments, and are not intended to limit the scope of this disclosure.

[0015] Figure 1A This is a top view of a NAND string according to aspects of this disclosure;

[0016] Figure 1B Based on the aspects of this disclosure Figure 1A The equivalent circuit diagram of the NAND string;

[0017] Figure 2 Based on the aspects of this disclosure Figure 1A A cross-sectional view of the NAND string;

[0018] Figure 3 For example, the block BLK0 depicting aspects of this disclosure Figure 1A-2 The three NAND strings shown in the image;

[0019] Figure 4 This is based on the inclusion of aspects of this disclosure. Figure 3 Block diagram of array 400 of NAND flash memory cells of BLK0 and additional blocks BLK1 and BLK2;

[0020] Figure 5A This is a block diagram depicting one embodiment of a sensing block according to aspects of this disclosure;

[0021] Figure 5B It is included in the aspects of this disclosure. Figure 4 Block diagram of a 400 array of non-volatile memory system;

[0022] Figure 6 This is a flowchart describing one embodiment of a method for programming a non-volatile memory according to aspects of this disclosure;

[0023] Figure 7 A binary memory with a group of cells is shown according to an aspect of this disclosure, wherein each cell is in one of two possible states;

[0024] Figure 8 This is a flowchart describing one embodiment of a method for erasing memory cells according to aspects of this disclosure;

[0025] Figure 9A Plot the P-well voltage versus time and the word line voltage versus time.

[0026] Figure 9B An embodiment of the process of performing a scan of memory cells in a block (or other unit) to determine an upper tail threshold voltage after a test or first erase pulse, according to aspects of this disclosure;

[0027] Figure 9C The diagram depicts a P-well voltage versus time and a word line voltage versus time for two different erase voltages applied to a P-well associated with a memory cell to erase the memory cell, according to aspects of this disclosure.

[0028] Figure 9D An embodiment of the process of performing a scan of memory cells in a block to determine the upper tail threshold voltage after a test erase, according to aspects of this disclosure;

[0029] Figure 10 This is a flowchart describing a process for verifying that a memory cell has been erased according to aspects of this disclosure;

[0030] Figure 11A The illustration shows an example distribution of threshold voltages for memory cells in blocks with different cycling conditions prior to an erase operation, according to aspects of this disclosure. Figure 11B The diagram shows an example distribution of threshold voltages for memory cells in blocks with different cycling conditions after the first erase pulse. Figure 11C The diagram shows an example distribution of threshold voltages for memory cells in blocks with different cyclic conditions after the second erase pulse. Figure 11D The diagram shows an instance distribution of threshold voltages for memory cells in blocks with different loop conditions before the start of programming operations. Figure 11E The diagram illustrates an example distribution of threshold voltages for memory cells in blocks with different cycle conditions after the control circuit has determined the position for erasing the upper tail portion. Figure 11FThe diagram shows an example distribution of the threshold voltages of memory cells in blocks with different loop conditions after the memory cells have been programmed during the programming operation by the control circuit.

[0031] Figure 12 This is a graph showing the correlation between the programming and erasing speeds of memory cells under different cyclic conditions according to aspects of this disclosure;

[0032] Figure 13 This illustrates the average lower tail of the programming operation after programming voltage for both a new memory device and a memory device that has undergone 75,000 programming and erasing cycles, according to aspects of this disclosure; and

[0033] Figure 14 The steps of a method for operating a memory device according to aspects of this disclosure are shown. Detailed Implementation

[0034] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, specific circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0035] Generally, this disclosure relates to a type of nonvolatile memory device well-suited for use in many applications. The nonvolatile memory devices and associated operating methods of this disclosure will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided only to sufficiently illustrate the concepts, features, advantages, and objectives of the invention to allow those skilled in the art to understand and practice this disclosure. Specifically, exemplary embodiments are provided so that this disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Numerous specific details, such as examples of particular components, apparatus, and methods, are enumerated to provide a thorough understanding of embodiments of this disclosure. Those skilled in the art will understand that the specific details are not necessary, the exemplary embodiments may be implemented in many different forms, and should not be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0036] In some memory devices or apparatuses, memory cells are joined together, for example, by joining NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) on the drain side of the NAND string connected to a bit line, and one or more source-side SG transistors (SGS transistors) on the source side of the NAND string connected to a source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) that acts as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings, and in other ways as well.

[0037] In a 3D memory architecture, memory cells can be arranged in a stacked vertical string, wherein the stack comprises alternating conductive and dielectric layers. The conductive layers act as word lines connecting the memory cells. Memory cells can contain data memory cells eligible to store user data and dummy or non-data memory cells not eligible to store user data.

[0038] Before programming a particular non-volatile memory device, the memory cell is typically erased. For some devices, the erase operation removes electrons from the floating gate of the memory cell being erased. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0039] During the programming operation, memory cells are programmed according to the word line programming order. For example, programming can begin with the word line on the source side of the block and proceed to the word line on the drain side of the block. In one approach, each word line is programmed before the next word line is programmed. For example, the first word line WL0 is programmed using one or more programming pulses until programming is complete. Next, the second word line WL1 is programmed using one or more programming pulses until programming is complete, and so on. The programming pulses may consist of a set of increasing programming voltages applied to the word line in the corresponding programming loop or program-verify iteration. A verification operation or stage can be performed after each programming voltage to determine whether the memory cell has been programmed. Upon completion of programming of a memory cell, the memory cell can be locked to prevent further programming while programming of other memory cells continues in subsequent programming loops.

[0040] Each memory cell can be associated with a data state based on the data written in the programming command. Based on its data state, the memory cell will remain in an erase state or be programmed into a programmed data state. For example, in a one-bit memory device per cell, there are two data states: an erase state and a programmed state (see...). Figure 7 ).

[0041] After a memory cell is programmed, data can be read back during a read operation. A read operation may involve applying a series of read voltages to a word line while sensing circuitry determines whether a cell connected to the word line is in a conductive or non-conductive state. If the cell is in a non-conductive state, the memory cell's threshold voltage Vt or Vth exceeds the read voltage. The read voltage is set to a level between the threshold voltage levels expected in adjacent data states.

[0042] As a programming voltage is applied to the word line associated with the memory cell being programmed during the programming operation, it is necessary to determine the programming voltage VPGM (the voltage applied to the corresponding word line) to be used to program the memory cell during the programming operation. As the memory cell is cycled (i.e., repeatedly programmed and erased), the programming voltage used may need to be adjusted. One method for determining the programming voltage is to use one or more pulses of the programming voltage, followed by reading or verifying the threshold voltage of the selected memory cell (this method can be called "smart verification"). Nevertheless, applying one or more pulses to determine the correct programming voltage can significantly affect the speed of the programming operation.

[0043] The techniques disclosed in this paper can be applied to 3D NAND, but are not limited to it. NAND flash memory structures can arrange multiple transistors in series between two select gates. The series-connected transistors and select gates are called a NAND string. Figure 1A This is a top view showing a NAND string. Figure 1B It is its equivalent circuit. Figure 1A and 1BThe NAND string depicted includes four transistors 100, 102, 104, and 106 connected in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. Select gate 122 is controlled by applying an appropriate voltage to control gate 122CG. Each of transistors 100, 102, 104, and 106 has a control gate and a floating gate. Transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0. In one embodiment, transistors 100, 102, 104, and 106 are each a memory cell. In other embodiments, the memory cell may contain multiple transistors or may differ from the depicted case. Select gate 120 is connected to select line SGD. Select gate 122 is connected to select line SGS.

[0044] Figure 2 A cross-sectional view of one embodiment of the NAND string described above is provided. Figure 2This refers to 2D NAND strings formed in a substrate. The transistors of the NAND string are formed in a p-well region 140. The p-well region can be located within an n-well region 142 of a p-type substrate 144. Each transistor comprises a stacked gate structure consisting of a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The floating gate is formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, where an inter-polysilicon dielectric layer separates the control gate and the floating gate. The control gates of memory cells (100, 102, 104, and 106) form word lines. N+ doped layers 130, 132, 134, 136, and 138 are shared between adjacent cells, thereby connecting the cells in series to form a NAND string. These N+ doped layers form the source and drain of each of the cells. For example, N+ doped layer 130 acts as the drain of transistor 122 and the source of transistor 106, N+ doped layer 132 acts as the drain of transistor 106 and the source of transistor 104, N+ doped layer 134 acts as the drain of transistor 104 and the source of transistor 102, N+ doped layer 136 acts as the drain of transistor 102 and the source of transistor 100, and N+ doped layer 138 acts as the drain of transistor 100 and the source of transistor 120. N+ doped layer 126 is connected to the bit line of the NAND string, while N+ doped layer 128 is connected to the common source line of multiple NAND strings.

[0045] It should be noted that, although Figure 1A-2 The illustration shows four memory cells in a NAND string, but the use of four transistors is provided only as an example. NAND strings used with the techniques described herein may have fewer than four memory cells or more than four memory cells. For example, some NAND strings will contain 8, 16, 32, 64 or more memory cells.

[0046] Each memory cell can store data represented in analog or digital form. When storing one bit of digital data, the possible threshold voltage range of the memory cell is divided into two ranges, which are assigned logic data "1" and "0". In one example of NAND flash memory, the voltage threshold is negative after erasing the memory cell and is defined as logic "1". The threshold voltage is positive after a programming operation and is defined as logic "0". When the threshold voltage is negative and a read operation is attempted by applying 0V to the control gate, the memory cell is turned on to indicate that a positive logic 1 is stored. When the threshold voltage is positive and a read operation is attempted by applying 0V to the control gate, the memory cell is not turned on, indicating that a logic 0 is stored.

[0047] Memory cells can also store multiple states, and thus multiple bits of digital data. When storing multiple data states, the threshold voltage window is divided into the number of states. For example, if four states are used, there will be four threshold voltage ranges assigned to the data values ​​"11", "10", "01", and "00". In one example of NAND-type memory, the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for states "10", "01", and "00". In some implementations, Gray code assignment is used to assign data values ​​(e.g., logic states) to threshold ranges such that if the threshold voltage of the floating gate is incorrectly shifted to its adjacent physical state, only one bit will be affected. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage range depends on the data encoding scheme employed by the memory cell.

[0048] Other types of non-volatile memory besides NAND flash memory can also be used with the technology of this invention.

[0049] Another type of memory cell available in flash EEPROM systems utilizes a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are captured and stored in a finite region. This stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. Similar cells can be configured in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0050] In another approach, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charges of the other data bits are located in the dielectric layer adjacent to the source. Multi-state data storage is achieved by individually reading the binary states of spatially separated charge storage regions within the dielectric.

[0051] Figure 3 Describing, for example Figure 1A-2The diagram shows three instance NAND strings in block BLK0. BLK0 contains several NAND strings NS0, NS1, NS2, ... and corresponding bit lines, such as BL0, BL1, BL2, ... which communicate with corresponding sense amplifiers SA0, SA1, SA2, ... BLK0 includes a set of non-volatile memory elements. One end of each NAND string is connected to a Select Gate Drain (SGD) transistor, and the control gate of the SGD transistor is connected via a common SGD line. The other end of the NAND string is connected to a Select Gate Source (SGS) transistor, which is in turn connected to a common source line (SL). Several word lines WL0-WL63 extend between the SGS transistor and the SGD transistor. WL0 is an edge word line adjacent to the source side (SS) of the block, and WL63 is an edge word line adjacent to the drain side (DS) of the block.

[0052] Example NAND string NS0 includes memory elements 301, ..., 302-306, ..., 307 and corresponding control gates CG63, ..., CG32-CG28, ..., CG0. SGS transistor 308 has control gate CGsgs and SGD transistor 300 has control gate CGsgd. Another example NAND string NS1 includes memory elements 311, ..., 312-316, ..., 317, SGS transistor 318, and SGD transistor 310. Another example NAND string NS2 includes memory elements 321, ..., 322-326, ..., 327, SGS transistor 328, and SGD transistor 320. NAND strings NS0, NS2, ... are even-numbered, while NAND strings NS1, NS3 (not shown), ... are odd-numbered. Similarly, bit lines BL0, BL2, ... are even-numbered, while NAND strings BL1, BL3 (not shown), ... are odd-numbered. Storage elements can store user data and / or non-user data.

[0053] Figure 4 It includes Figure 3 A block diagram of an array 400 of NAND flash memory cells, including BLK0 and additional blocks BLK1 and BLK2. Along each column, bit lines (BL) are coupled to the drain terminal of the drain-select gate of the NAND string. Along each row of the NAND string, source lines (SL) can connect to all the source terminals of the source-select gate of the NAND string (e.g., at SE0 of NS0).

[0054] The array of memory elements is divided into a large number of blocks (e.g., BLK0-BLK2), each block containing one or more NAND strings communicating with a common set of word lines, SGS lines, and SGD lines. Each NAND string also communicates with a corresponding bit line. For example, BLK0 contains NAND strings NS0, NS1, ..., NSn-1 communicating with BL0, BL1, ..., BLn-1 and with SGS and SGD lines of WL0-WL63, respectively. BLK1 contains NAND strings NSa0, NSa1, ..., NSa-1 communicating with BL0, BL1, ..., BLn-1 and with WL0a-WL63a, SGSa, and SGDa, respectively. BLK2 contains NAND strings NSb0, NSb1, ..., NSbn-1 communicating with BL0, BL1, ..., BLn-1 and with WL0b-WL63b, SGSb, and SGDb, respectively.

[0055] As is common in flash EEPROM systems, a block is the unit of erasure. That is, each block contains the minimum number of storage elements that are erased together. Each block is typically divided into several pages. A page is the smallest unit of programming. One or more data pages are typically stored in a row of storage elements. For example, a row typically contains several interleaved pages or pages that may constitute a single page. All storage elements of a page will be read or programmed together. In addition, a page may store user data from one or more sectors. A sector is a logical concept used by the host as a convenient unit for user data; it typically does not contain overhead data, which is confined to the controller. Overhead data may contain an error correction code (ECC) calculated based on the user data in the sector. A portion of the controller (described below) calculates the ECC while data is being programmed into the array and also checks the ECC while data is being read from the array. Alternatively, the ECC and / or other overhead data may be stored in different pages or even different blocks than the user data they relate to.

[0056] User data sectors are typically 512 bytes, corresponding to the sector size in a disk drive. Additional overhead data is typically an extra 16-20 bytes. Large numbers of pages form blocks, starting from page 8 and continuing up to, for example, 32, 64, or more pages. In some embodiments, rows of the NAND string comprise blocks.

[0057] In one embodiment, a memory cell is erased by raising the p-well to an erase voltage (e.g., 15-20V) for a sufficient period of time and grounding or applying a low bias (e.g., 1V) on the word line of the selected block while the source and bit lines are floating. Due to capacitive cross-coupling (“cross” means coupling from adjacent memory elements), the bit lines, select lines, and common source are also raised to a large fraction of the erase voltage. Therefore, a strong electric field is applied to the tunnel oxide layer of the selected memory cell, and the data in the selected memory cell is erased as electrons from the floating gate are emitted to the substrate side. As electrons move from the floating gate to the p-well region, the threshold voltage of the selected cell decreases. Erasure can be performed on the entire memory array, a single block, or another unit of a cell. In one embodiment, different techniques are used to erase 3D NAND. 3D NAND will be discussed further below.

[0058] Figure 5A This is a block diagram depicting one embodiment of a sensing block 500. Individual sensing blocks 500 are divided into a core portion (referred to as sensing module 580) and a common portion 590. In one embodiment, there is an individual sensing module 580 for each bit and a common portion 590 for a group of multiple sensing modules 580. In one instance, the sensing block 500 will include a common portion 590 and eight sensing modules 580. Each of the sensing modules in the group will communicate with its associated common portion via a data bus 572.

[0059] Sensing module 580 includes sensing circuitry 571 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. Sensing module 580 also includes a bit line latch 582 for setting voltage conditions on the connected bit line. For example, a predetermined state latched in bit line latch 582 will cause the connected bit line to be pulled to a specified programming-disabled state (e.g., 1.5 V to 3 V). As an example, flag = 0 disables programming, while flag = 1 does not disable programming.

[0060] The common portion 590 includes a processor 592, three sets of instance data latches 594, and an I / O interface 598 coupled between the sets of data latches 594 and the data bus 521. One set of data latches can be provided for each sensing module, and three data latches identified by DL1, DL2, and DL3 can be provided for each set. The use of the data latches is further discussed below.

[0061] Processor 592 performs calculations. For example, one of its functions is to determine data stored in a sensed memory element and store the determined data in the set of data latches. At least some of the data latches in the set (e.g., 594) are used to store data bits determined by processor 592 during a read operation. At least some of the data latches in the set are also used to store data bits imported from data bus 521 during a programming operation. The imported data bits represent write data intended to be programmed into memory. I / O interface 598 provides an interface between data latches 594-697 and data bus 521.

[0062] In one embodiment, data is stored in latches DL1 and DL2 at the start of the programming operation. For example, lower page data may be stored in DL1, and upper page data may be stored in DL2. In one embodiment, lower page data read from a memory cell during IDL is stored in latch DL1. DL3 can be used to store a verification state, such as a lock state during programming. For example, when the Vt of a memory cell has been verified to have reached its target level, latch DL3 can be set to indicate this state, thus preventing further programming of the memory cell. Note that this describes programming two bits per memory cell. In one embodiment, latches DL1 and DL2 are used to store two bits read from the memory cell during a read operation. It should be noted that more than two bits per memory cell may exist. An additional latch may exist for each additional bit to be stored per memory cell.

[0063] During a read or other sensing operation, state machine 512 controls the supply of different control gate voltages to the addressed memory element. As the sensing module 580 steps through various control gate voltages corresponding to different memory states supported by the memory, it may break at one of these voltages and provide an output from sensing module 580 to processor 592 via bus 572. At this time, processor 592 determines the resulting memory state by considering the break event of the sensing module and information about the control gate voltage applied via input line 593 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in a data latch (e.g., 594). In another embodiment of the core portion, bit line latch 582 acts as both a latch for latching the output of sensing module 580 and a bit line latch as described above.

[0064] Some implementations may include multiple processors 592. In one embodiment, each processor 592 will include output lines (not depicted) such that each of the output lines is wired-OR'd together. In some embodiments, the output lines are inverted before being connected to the wired-OR'd line. This configuration allows for rapid determination of when the programming process is complete during the programming verification process, as the state machine receiving the wired-OR'd line can determine when all the bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero of that bit is sent to the wired-OR'd line (or data 1 is inverted). When all bits output data 0 (or data 1 is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing modules, the state machine needs to read the wired-OR'd line eight times, or logic can be added to the processor 592 to accumulate the results of the associated bit lines, so that the state machine only needs to read the wired-OR'd line once. Similarly, by correctly selecting the logic level, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0065] During programming or verification, the data to be programmed is stored from the data bus 521 in the set of data latches 594-597. Under the control of the state machine, the programming operation involves a series of programming voltage pulses being applied to the control gate of the addressed memory element. Each programming pulse is followed by a readback (verification) to determine whether the memory element has been programmed to the desired memory state. The processor 592 monitors the readback memory state relative to the desired memory state. When both are consistent, the processor 592 sets the bit line latch 582 such that the bit line is pulled to a specified programming-disabled state. This prevents further programming of the memory element coupled to the bit line, even if a programming pulse appears on its control gate. In other embodiments, the processor initially loads the bit line latch 582, and the sensing circuitry sets it to a disabled value during the verification process.

[0066] In one embodiment, each set of data latch stacks 594-597 contains a data latch stack corresponding to the sensing module 580. In one embodiment, there are three data latches per sensing module 580. All DL1 and DL2 data latches corresponding to the read / write blocks of the storage element can be connected together to form a block shift register, allowing data blocks to be input or output serially.

[0067] In one embodiment, one purpose of the DL1 and DL2 latches is to store the data to be programmed into a storage element. For example, the storage element may store two bits per storage element. In one embodiment, the lower page data is initially stored in the DL1 latch, and the upper page data is initially stored in the DL2 latch.

[0068] In one embodiment, each storage element stores three bits. In this case, an additional data latch may be present. Figure 5A (Not depicted in the text) is used to initially store the third bit of the data to be programmed into the storage element. In one embodiment, the storage element stores four bits per storage element, where two additional data latches may be present ( Figure 5A (Not depicted) is used to initially store the third and fourth bits of the data to be programmed into the storage element. Each storage element can store more than four bits, in which case a data latch can exist for each bit.

[0069] Additional information regarding read operations and sense amplifiers can be found in: (1) U.S. Patent No. 7,196,931, “Non-Volatile Memory and Method with Reduced Source Line Bias Errors”; (2) U.S. Patent No. 7,023,736, “Non-Volatile Memory and Method with Improved Sensing”; (3) U.S. Patent No. 7,046,568, “Memory Sensing Circuit and Method for Low Voltage Operation”; (4) U.S. Patent No. 7,196,928, “Compensating for Coupling during Read Operations of Non-Volatile Memory”; and (5) U.S. Patent No. 7,327,619, “Reference Sense Amplifier for Non-Volatile Memory”. (for Non-Volatile Memory). All five patent documents listed above are incorporated herein by reference in their entirety.

[0070] Figure 5B It includes Figure 4A block diagram of a non-volatile memory system of array 400. Memory array 400 may comprise a 2D architecture or a 3D architecture. An example of a 3D architecture is a BiCS architecture. A 3D architecture may comprise 3D vertical NAND strings. Memory cells in a 3D vertical NAND string may contain an ONO layer for storing information. Information may be stored in a charge trapping layer, such as, but not limited to, SiN. It should be noted that the ONO layer can be used to store information from both 2D and 2D NAND, as well as other architectures. Therefore, floating gates can be used to store information, but are not required.

[0071] According to one embodiment of the present invention, a non-volatile memory system includes a memory device 596 having read / write circuitry for reading and programming memory cell pages in parallel. The memory device 596 may include one or more memory dies 598. The memory die 598 includes a two-dimensional array of memory cells 400, a control circuitry system 510, and read / write circuitry 565. The memory array 400 is addressable by word lines via a row decoder 530 and by bit lines via a column decoder 560. The read / write circuitry 565 includes a plurality of sensing blocks 500 and allows for parallel reading or programming of memory cell pages. Typically, a controller 550 is included in the same memory device 596 (e.g., a removable memory card) as the one or more memory dies 598. Commands and data are transmitted between a host 570 and the controller 550 via line 520 and between the controller and the one or more memory dies 598 via line 518.

[0072] Control circuitry 510 cooperates with read / write circuitry 565 to perform memory operations on memory array 400. Control circuitry 510 includes state machine 512, memory 513, on-chip address decoder 514, register 515, and power control module 516. State machine 512 provides chip-level control of memory operations. Memory 513 stores raw write data, modified write data, and status bits for use by state machine 512. On-chip address decoder 514 provides an address interface between the hardware address used by the host or memory controller and the hardware address used by decoders 530 and 560. Register 515 can be used to record the voltage used when programming or erasing memory device 596. Power control module 516 controls the power and voltage supplied to word lines and bit lines during memory operations. In another approach, dual row / column decoders and read / write circuitry are used. For example, the control circuit may be considered to include one or more of components 510, 512, 513, 514, 515, 516, 530, 550, 560, and 565.

[0073] Figure 6This is a flowchart illustrating one embodiment of a method for programming non-volatile memory. At step 640, the memory cells to be programmed are erased. Step 640 may include erasing more memory cells than those to be programmed (e.g., in blocks or other units). Figure 8 An embodiment of erasing memory cells is depicted. At step 642, soft programming is performed to narrow the distribution of erase threshold voltages of the memory cells to be erased. As a result of the erasure process, some memory cells may be in a deeper erase state than necessary. Soft programming may apply small programming pulses to shift the threshold voltage of the memory cells to be erased closer to the erase verification level. Figure 6 At step 650, a "data load" command is issued by controller 550 and input to the command circuitry, allowing data to be input to the data input / output buffer. At step 652, address data specifying the page address is input from the controller or host to the line controller or decoder 514. The input data is identified as a page address and latched via state machine 512, influenced by an address latch signal input to the command circuitry. At step 654, the programming data page of the addressed page is input to the data input / output buffer for programming. For example, in one embodiment, 512 bytes of data may be input. The data is latched in an appropriate register for selecting the positioning line. In some embodiments, the data is also latched in a second register for selecting the positioning line for verification purposes. At step 656, a "programming" command is issued by the controller and input to the data input / output buffer. The command is latched by state machine 512 via a command latch signal input to the command circuitry.

[0074] When triggered by a “programming” command, the data latched in step 654 is programmed into the selected memory cell controlled by state machine 512 using step pulses applied to the appropriate word line. At step 658, the programming pulse voltage level Vpgm or VPGM applied to the selected sub-line is initialized to the start pulse (e.g., 12V), and the program counter PC maintained by state machine 512 is initialized to 0. At step 660, a first Vpgm pulse is applied to the selected sub-line. If a logic “0” is stored in a specific data latch, indicating that the corresponding memory cell should be programmed, the corresponding bit line is grounded. Conversely, if a logic “1” is stored in a specific latch, indicating that the corresponding memory cell should remain in its current data state, the corresponding bit line is connected to VDD to disable programming.

[0075] At step 662, the state of the selected memory cell is verified. If the target threshold voltage of the selected cell has reached an appropriate level, the data stored in the corresponding data latch is changed to logic "1". If the threshold voltage has not yet reached an appropriate level, the data stored in the corresponding data latch remains unchanged. In this way, the bit line with logic "1" stored in its corresponding data latch does not need to be programmed. When all data latches are storing logic "1", the state machine knows that all selected cells have been programmed. At step 664, it is checked whether all data latches are storing logic "1". If so, the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. At step 666, the state "PASS" is reported.

[0076] If it is determined at step 664 that not all data latches are storing logic "1", the programming process continues. At step 668, the program counter PC is checked against a programming limit value. One example of a programming limit value is 20; however, other values ​​may be used in various implementations. If the program counter PC is not less than 20, at step 669 it is determined whether the number of bits that have not been successfully programmed is equal to or less than a predetermined number. If the number of bits that have not been successfully programmed is equal to or less than the predetermined number, the programming process is marked as successful and a successful status is reported at step 671. Bits that have not been successfully programmed can be corrected using error correction during the read process. However, if the number of bits that have not been successfully programmed is greater than the predetermined number, the programming process is marked as failed, and a failure status is reported at step 670. If the program counter PC is less than 20, at step 672 the Vpgm level is incremented by a step and the program counter PC is incremented. After step 672, the process loops back to step 760 to apply the next Vpgm pulse.

[0077] Figure 6 The flowchart depicts a single-pass programming method applicable to binary storage. For example, in a two-pass programming method applicable to multi-level storage, multiple programming or verification steps can be used in a single iteration of the flowchart. Steps 658-672 can be performed for each pass of the programming operation. In the first pass, one or more programming impulses can be applied, and the results are verified to determine if the cell is in an appropriate intermediate state. In the second pass, one or more programming impulses can be applied, and the results are verified to determine if the cell is in an appropriate final state.

[0078] At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more threshold voltage distributions of the programmed memory cell or within the threshold voltage distribution of the erased memory cell.

[0079] Figure 7This diagram illustrates a binary memory with a group of cells, where each cell is in one of two possible states. The threshold window for each memory cell is divided into two distinct regions by a single boundary level. (Example:) Figure 7 As shown in (a), during the read operation, the read boundary level rV1 between the lower and upper regions is used to determine which region the cell's threshold level is located in. If the cell's threshold is in the lower region, the cell is in an "erase" state, and if the cell's threshold is in the upper region, the cell is in a "program" state. Figure 7 (b) shows that all cells of the memory are initially in the "erase" state. Figure 7 (c) shows some cells programmed to the "programming" state. The memory state is decoded using a 1-bit or binary code. For example, a bit value "1" indicates the "erase" state, and "0" indicates the "programming" state. Programming is typically performed by applying one or more programming voltage pulses. After each pulse, the sensing cell checks whether the threshold has moved beyond the check boundary level vV1. Memory with this cell partitioning is called "binary" memory or single-level cell ("SLC") memory. It will be seen that binary or SLC memory operates with a wide error tolerance because the entire threshold window is occupied by only two zones.

[0080] Figure 8 An embodiment of the process 800 for erasing memory cells is described. Figure 8 Process 800 is used for implementation Figure 6 One technique is step 640. In optional step 802, the memory cells are programmed to a certain minimum threshold voltage. As an example, essentially all memory cells are programmed to a Vt at least one volt higher than the measurable Vt window (a common range of threshold voltages). The measurable Vt window is the range of Vt used to store valid data on a particular memory device. The bottom of the window varies depending on factors such as whether negative Vt sensing is used. In an implementation without negative sensing of Vt, the start of the measurable Vt window is approximately 0V. In an implementation using negative sensing, the start of the measurable Vt window can become almost negative to -Vdd. For example, using negative sensing, for a Vdd of 2.2V, the start of the measurable Vt window is approximately -1.6V. In one implementation, negative sensing is performed as follows: The source and P-well are maintained at 1.6V. The drain is maintained at 1.6V + Vb1, where Vb1 is the voltage to which the bit line is pre-charged. As an example, Vb1 is 0.4V. In this type of negative sensing, there is no bulk effect because the source and P-well remain at the same voltage. In one embodiment, negative Vt sensing is performed by applying a negative voltage to the control gate.

[0081] One reason for performing step 802 is to pre-adjust the memory cells before the trial erase or the first erase pulse to allow for a more accurate determination of the reference point on the threshold distribution after the trial erase. In one embodiment, the reference point is referred to herein as the “upper tail Vt” because it is typically located at the very upper end of the Vt distribution. Subsequent steps of process 800 determine the count based on how many memory cells have a Vt higher than the read reference voltage applied to the memory cells after the trial erase has been performed. In one embodiment, the counting is performed on a NAND string basis. That is, if one or more memory cells in a NAND string meet the condition, then the NAND string is counted. However, it is not necessary to perform the counting on a NAND string basis. After the pulse applied in step 802, the lowest Vt of substantially all memory cells should be higher than the read reference voltage to ensure that the memory cells to be counted later will be those erased by the trial erase pulse.

[0082] In step 804, a trial or first erase of the memory cells is performed. In one embodiment, the magnitude of the trial erase voltage is low enough to ensure that the upper portion of the erase distribution is within the measurable Vt window, such that a certain read reference voltage can be applied to the memory cells to determine how many memory cells have a Vt higher than the read reference voltage. It should be noted that a portion of the Vt distribution may be lower than the lowest measurable Vt, as long as the upper portion is within the measurable Vt window. A later step in process 800 applies a read voltage and determines a count of how many NAND strings have a Vt higher than the read voltage. The upper tail Vt will be determined based on those counts.

[0083] It should be noted that erasing some memory devices becomes more difficult over time. Therefore, the characteristics (e.g., magnitude) of the test erase pulse can vary with memory device usage (e.g., erase / programming cycles). For some devices, the increase in the difficulty of erasing memory cells may be approximately logarithmic. Therefore, adjustments to the test erase pulse can be made, for example, at 100 cycles, 1K cycles, or 10K cycles. In some embodiments, the number of erase / programming cycles is tracked and the test erase pulse is adjusted based on it. Tracking can be based on a block-by-block basis, but is not required. It should be noted that due to wear leveling procedures, it may be possible to use the same test erase pulse for all blocks of a given device at any given time during the product's lifespan, as similar wear levels in each block can be assumed.

[0084] The upper tail Vt is the point near the upper end of the Vt distribution. The upper tail Vt can be defined by ignoring a certain number of peripheral Vts. For example, approximately 31 memory cells have a Vt to the right of the upper tail Vt. The upper tail Vt can be defined based on any number other than 31. If counting is performed based on NAND strings, a certain number of NAND strings are ignored. As an example, NAND strings are examined to determine if a given NAND string has at least one memory cell with a Vt higher than the read reference voltage. The read reference voltage is adjusted until approximately 31 memory cells in the NAND strings have at least one memory cell with a Vt higher than the read reference voltage. Therefore, approximately 31 NAND strings have at least one memory cell with a Vt higher than the upper tail Vt. It should be noted that approximately 75,000 NAND strings may exist in a block. The upper tail Vt can also be defined based on statistical data. For example, if the Vt distribution is characterized by a mean and standard deviation, then the upper tail Vt can be defined as a certain real number of standard deviations above the mean.

[0085] In one embodiment, a trial erase is achieved by raising the p-well to an erase voltage for a sufficient time period and grounding the word line of the selected block while the source and bit lines are floating. Due to capacitive coupling, unselected word lines, bit lines, select lines, and common source lines are also raised to a significant fraction of the erase voltage. A strong electric field is thus applied to the tunnel oxide layer of the selected memory cell, and the data in the selected memory cell is erased as electrons from the floating gate are emitted to the substrate side via the Wohl-Nordheim tunneling mechanism. As electrons move from the floating gate to the p-well region, the Vt of the selected cell decreases. Erasure can be performed on the entire memory array, a single block, or another unit of a cell.

[0086] In step 806, the upper tail Vt is determined at a specific bit level of interest. The bit level of interest refers to how much Vt is ignored. For example, since some peripheral Vts are expected to exist in the Vt distribution, a certain number of outliers can be ignored. As previously discussed, a single Vt can be determined for the entire NAND string. Therefore, in one embodiment, the bit level of interest refers to how many memory cells in the NAND string are allowed to have a Vt higher than the upper tail Vt. The upper tail Vt serves as a reference point for later calculations.

[0087] In one implementation, the level of concern is based on the number of NAND strings “ignored” by the memory device 596 during erase verification. That is, erase verification will pass even if a certain number of NAND strings have one or more memory cells with a Vt greater than the target level. As an example, the memory device 596 may allow 31 NAND strings in each block to have one or more memory cells with a Vt greater than the target level. Typically, the device performs erase verification on a NAND string basis. That is, an erase verification voltage is applied to each word line in the block. Each memory cell in a given NAND string should be turned on for erase verification to pass. In one embodiment, the limitation condition for passing erase verification is that no more than a certain number of NAND strings fail verification. While the Vt of individual memory cells in those NAND strings that fail verification can be checked to determine if multiple memory cells caused the verification failure, this is not required. It should be noted that a certain number of memory cells with a Vt greater than the target level does not pose a data integrity problem because ECC can correct for these values. That is, if a later read operation finds that some of the memory cells are actually in a high state, then ECC will correct for the problem. However, other techniques can be used to determine the upper tail portion of Vt. See below for reference. Figure 9A , 9B The discussions of 9C and 9D further clarify the details of the upper tail Vt.

[0088] In step 808, a second erase voltage is determined based on the test erase voltage and the upper tail Vt. In one embodiment, the second erase voltage (VE2) is determined based on the following equation.

[0089] Equation 1: VE2 = VE1 + (VU1 / S) + M

[0090] Equation 2: S = ΔVT / ΔVE

[0091] In Equation 1, VE1 is the test erase voltage from step 804, and VU1 is the upper tail Vt determined in step 806. The parameter “S” is based on how the memory cell responds to the erase voltage. That is, S is how far the upper tail Vt is expected to shift for each unit increase in the erase voltage. Equation 2 defines S as the shift of the upper tail Vt for each 1 V increase in the erase voltage. In one embodiment, the parameter S is calculated based on testing of a sample memory device and can be used for all similar memory devices. Therefore, it is not necessary to determine S in the field. However, S can be determined or modified in the field. Furthermore, different values ​​of S can be used for different memory devices with the same design. For example, S can be fine-tuned to account for semiconductor process variations in different batches of memory devices. It is even possible to fine-tune the parameter S for each memory device. For example, when manufacturing a memory device, tests can be performed to determine the sensitivity of the memory cells on that particular memory device to the erase pulse. The value used for S can be programmed into a particular memory device based on the test results.

[0092] It should be noted that the sensitivity of memory cells to the erase voltage may vary. This variation can occur between memory cells, blocks, dies, batches, etc. The parameter "M" in Equation 1 is the margin number to ensure that the second erase is strong enough to account for possible variations. The value of M is chosen to ensure that those memory cells less sensitive to the erase voltage are fully erased. It is possible that some memory cells will be over-erased to a small extent. For example, memory cells more sensitive to the erase voltage than the average level may be over-erased. However, it is acceptable to over-erase some memory cells.

[0093] It should be noted that, just like parameter S, parameter M can be fine-tuned on a per-device basis, a per-batch basis, and so on. Furthermore, although parameter M can be programmed into a memory device during manufacturing, a suitable value for M can also be determined on-site. And the value programmed into the device during manufacturing can be fine-tuned on-site.

[0094] Furthermore, it should be noted that the actual determination of the second erase voltage can be performed through calculation or table lookup. For example, in one embodiment, the inputs to the table are the upper tail voltage and the test erase voltage. The output of the table is the second erase voltage.

[0095] In step 810, a second erase is performed using the erase voltage determined in step 808. In one embodiment, the second erase is achieved by raising the p-well to the erase voltage for a sufficient time period and grounding the word lines of the selected block while the source and bit lines float. In one embodiment, the erase is completed at this point without an erase verification operation. Therefore, the second erase can be completed with a single erase pulse. Verifying the erase threshold distribution is not required. However, erase verification may be performed optionally. It should be noted that if an erase verification operation is performed, then negative Vt may have to be sensed. However, in embodiments where the final erase Vt distribution is not verified, negative Vt sensing is not required.

[0096] After an erase operation, some memory cells may be in an erased state deeper than necessary. Soft programming, as small programming pulses, can be used to gently push up the Vt of some of the erased memory cells. Specifically, soft programming gently pushes up the Vt of the most deeply erased memory cells so that the erase threshold distribution is compact.

[0097] In optional step 812, the soft programming voltage is determined based on the second erase voltage. During block cycles, there is a correlation between the voltage required to erase memory cells and the voltage required to program those memory cells. In some embodiments, as the number of program / erase cycles increases, erasing becomes more difficult and programming becomes easier. Therefore, knowing the value of the erase voltage required to erase the block to a sufficiently deep level allows for the calculation of the correct value of the soft programming pulses that can tighten the erase distribution. In one embodiment, the soft programming voltage is determined based on the following equation:

[0098] Vsp = Vref - Ve² * K Equation 3

[0099] In Equation 3, Ve2 is the magnitude of the second erase voltage. The parameter Vref is a reference voltage, and K is a constant. Suitable values ​​for Vref and K can be determined based on tests performed on a sample device. In one embodiment, the soft-programming voltage is determined by applying, for example, Equation 3. In another embodiment, the value of the soft-programming pulse is obtained using a lookup table based on the second erase voltage.

[0100] It should be noted that if the soft programming pulse is too weak, it will not help tighten the erase distribution, and if the soft programming pulse is too strong, it can program memory cells out of the erased state and into one or more programmed states. However, a soft programming pulse with appropriate amplitude will tighten the erase distribution. The aforementioned possible reason is that memory cells with higher coupling ratios are easier to erase and program compared to cells with lower coupling ratios. Cells with higher coupling ratios will end at the lower part of the erase distribution after the erase pulse. A soft programming pulse with appropriate amplitude will gently push the Vt of these cells before the remaining memory cells begin programming, thus tightening the erase distribution. But if the soft programming pulse is too strong, all memory cells will begin programming, and the tightening effect will be lost.

[0101] In optional step 814, a soft-programming voltage is used to compact the erase threshold distribution. In some implementations, there is no verification of the soft programming. Because there is no verification, only a single soft-programming pulse is applied. However, verification of the soft programming can be performed.

[0102] In one embodiment, a new block with a low cycle count is erased using a single erase pulse without using... Figure 8 The process is 800. After erasing becomes more difficult and a single pulse is no longer sufficient to erase the block, use... Figure 8 The process is 800.

[0103] Figure 9A P-well voltage versus time and word line voltage versus time are plotted. The P-well voltage plot depicts two different erase voltage pulses applied to the P-well to erase a memory cell. The other plot depicts the voltage applied to the word line during a scan to search for the upper tail Vt. In simpler terms, the plots depict the application of a trial erase pulse followed by a bit scan for the upper tail Vt. The bit scan involves applying a first read voltage to the word line, followed by a bit scan operation, where a count is made based on how many memory cells failed to turn on in response to the read voltage. Based on the count, the read voltage is adjusted up or down and reapplied to the word line. In one embodiment, each read takes approximately 20 microseconds and each bit scan takes approximately 12 microseconds. The upper tail Vt is determined based on the result of the bit scan. A second erase pulse is determined based on the upper tail Vt. The second erase voltage is then applied to the P-well of the memory cell.

[0104] Figure 9B This describes one embodiment of a process 900 that involves scanning memory cells in a block (or other unit) after a trial erase to determine the upper tail Vt. Process 900 is for implementation... Figure 8 Step 806 is a technique. (Refer to...) Figure 9A The discussion process is 900 words. To be precise, Figure 9AThe lower part of the graph depicts the instance voltage applied to the word line during the bisection search for the upper tail Vt.

[0105] In step 902, a first read voltage is determined based on the window in which the bisection search will be performed. The window used for the bisection search is sufficiently wide such that the upper tail Vt is expected to be within the window. In one embodiment, the window range is from 0 to 4 volts. In another embodiment, the window range is from 0 to 6 volts. The window does not need to start at 0 volts, but it should begin at a voltage within the measurable Vt window. For example, if negative Vt sensing is used, then the measurable Vt window can begin below 0 volts. Figure 9B In the example depicted, based on a window ranging from 0 to 4 volts, the first read voltage is 2 volts.

[0106] In step 904, a first read voltage is applied to the word line of the memory cell. The first read voltage can be applied to each word line simultaneously. Therefore, the first read is intended to read a condition for each entire NAND string, rather than a condition for each memory cell on the NAND string. However, it is not required that the first read voltage be applied to each word line simultaneously. Therefore, each memory cell can be read individually.

[0107] In step 906, a bit scan begins to count how many memory cells in the NAND string have one or more memory cells with a Vt higher than the read voltage. The bit scan determines how many memory cells in the NAND string have failed to turn on in response to a first read voltage. In one embodiment, the bit scan stops once a certain count is reached. For example, if the upper tail Vt is defined based on allowing 31 NAND strings to have one or more memory cells with a Vt higher than a certain point, then the counting can stop once that level is reached. Counting is not required on a NAND string basis. Figure 9B In this context, the time period marked "bit scan" refers to the period during which counting is currently taking place.

[0108] Another technique for performing a bit scan is to start the search from a single point (e.g., a center point) and alternately move away from that point. The scan continues until a transition is reached. The transition is defined based on the number of NAND strings that fail to turn on. As an example, the transition is based on whether 31 or fewer NAND strings fail to turn on. For illustration, the following sequence of voltages is applied:

[0109] 2.0, 2.1, 1.9, 2.2, 1.8, 2.3, 1.7, 2.4, 1.6

[0110] It should be noted that each consecutive voltage is on the opposite side of the starting point. In the example above, the transition occurs when 1.6 volts are applied. Therefore, the upper tail is determined to be between 1.6 and 1.7 volts. As another example, if the transition occurs when 2.4 volts are applied, then the upper tail will be between 2.3 and 2.4 volts. It should be noted that in this embodiment, the center point is selected based on the expected value that the upper tail might be. Therefore, this scan can be extremely efficient.

[0111] In one embodiment, counting is performed "on-chip." Therefore, for example, data does not need to be transferred from memory die 598 to controller 550 to perform the counting. By avoiding this data transfer, counting can be performed extremely quickly. In one embodiment, the counting performed on-chip may only reach a finite value. For example, the on-chip circuitry may be able to count up to 32, 64, or some other value. After the count is reached, the counter overflows. The count defining the upper tail Vt may be located at the point of counter overflow. However, the upper tail Vt may be defined as a smaller number.

[0112] In one embodiment, on-chip counting is performed in two phases. In the first phase, different groups of NAND strings are examined. A value of 1 or 0 is determined for each NAND string group based on whether at least one memory cell in a given NAND string group has a voltage Vt higher than the current read voltage. If the count of a NAND string group exceeds a limit, the scan stops. In the second phase, each group with a value of 1 is examined to determine how many NAND strings have one or more memory cells with a voltage Vt higher than the current read voltage. If the counter overflows during the second phase, the counting stops.

[0113] Therefore, if the count overflows (step 908), then the bit scan stops (910). Otherwise, the bit scan continues until all NAND strings have been read.

[0114] In step 912, a determination is made as to whether another read voltage should be applied. For example, refer to... Figure 9A Five read voltages are applied. The search can use more or fewer iterations to achieve different resolutions. If the upper tail Vt is not found within the search window, the search window can be expanded and the process repeated 900. For example, it is possible that the upper tail Vt is higher than 4 volts. However, the trial erase voltage of the selection step is used to ensure that the upper tail Vt distribution is within a 4V range starting from the beginning of the measurable Vt window. The 4V window should be sufficient to cover the range of block-to-block, die-to-die, wafer-to-wafer, and batch-to-batch variations at any cycle point. If the upper tail Vt does fall outside the 4V window, the window can be extended, for example, to 6V.

[0115] If no further read voltages are applied, the upper tail Vt is stored in step 914. It should be noted that since the last two read voltages “span” the upper tail Vt, the stored value can be either of the last two read voltages or any value in between. In one embodiment, the average of the two values ​​spanning the upper tail Vt is obtained and used as the upper tail Vt value. If the desired resolution has not yet been achieved, control proceeds to step 916.

[0116] In step 916, it is determined whether the upper tail Vt is higher or lower than the last read voltage. In some embodiments, the count from the bit scan will be at or below the maximum value (e.g., 32). In these embodiments, a count less than 32 indicates that the upper tail Vt is less than the applied last read voltage. Therefore, the read voltage is reduced (e.g., from 2V to 1V). After reducing the read voltage (step 918), control is passed to step 904 to apply the new read voltage to the word line.

[0117] On the other hand, if the count is exceeded, the read voltage is increased (e.g., from 1 V to 1.5 V). After the read voltage is increased (step 920), control is passed to step 1104 to apply the new read voltage to the word line.

[0118] In one embodiment, a linear search is performed on the upper tail Vt. Figure 9C The diagram depicts the P-well voltage and the word line voltage applied to the memory cell during a linear scan of the upper tail Vt. Two different erase voltages are applied to the P-well to erase the memory cell. In simple terms, a trial erase pulse is applied, followed by a linear search for the upper tail Vt. A second erase voltage is then applied to the P-well of the memory cell. The linear search involves applying a first read voltage to the word line, followed by a bit scan operation, where a count is made of how many NAND strings have at least one memory that failed to respond to the read voltage. In the depicted embodiment, a next read voltage is applied before determining the count. The read voltage is increased until the upper tail Vt is found.

[0119] Figure 9D This describes one embodiment of a process 980 in which a scan of memory cells in a block is performed after a trial erase to determine the upper tail Vt. The process is for implementation. Figure 8 Step 806 is a technique. (Refer to...) Figure 9C Discussion Figure 9D .

[0120] In step 982, a read voltage is applied to the word line of the memory cell. The first read voltage can be applied to each word line simultaneously. Therefore, the first read is intended to read a condition for each entire NAND string, rather than a condition for each memory cell on the NAND string. However, it is not required that the first read voltage be applied to each word line simultaneously. Therefore, each memory cell can be read individually.

[0121] In step 984, a bit scan based on the result of the first read begins. That is, counting begins on the number of NAND strings having one or more memory cells with a voltage Vt higher than the read voltage. It should be noted that the next read voltage can be applied while counting continues, as the magnitude of the next read voltage is independent of the count. This is in Figure 9C The process is described in detail, where the first scan is depicted to occur during the second read. In process 980, this is described in step 992 as increasing the read voltage by a step size and returning to step 982. In step 986, the bit scan is complete. If the count of the NAND strings reaches a certain level, then the bit scan stops. For example, if 31 NAND strings are found to have memory cells with a voltage Vt higher than the read voltage, then the bit scan stops.

[0122] In step 988, a determination is made as to whether the upper tail Vt has been found at the desired resolution. See [link / reference] Figure 9C The initial read voltage is located at the lower end of the window. Therefore, it is expected that the maximum count will be reached for the first read. That is, it is expected that the upper tail Vt will be higher than the first read voltage. When the read voltage is greater than the upper tail Vt, the count will not be reached, indicating that the upper tail Vt is between this read and the previous read. If a higher resolution is desired, then a read voltage somewhere between the last two read voltages is selected, and control is passed to step 982 to apply a new read voltage.

[0123] Otherwise, the upper tail voltage is determined in step 990 based on the last two read voltages. Furthermore, since a new read can begin when a bit scan starts, the last read can be aborted.

[0124] Simultaneous multi-threshold (SMT) sensing can also be employed. During SMT sensing, two or more different bias conditions can be used to simultaneously sense two different threshold voltages. For example, a single verification reference voltage can be applied to a selected sub-line, while one bias condition is used for memory cells positively verified to a first state, and a second bias condition is used for memory cells positively verified to a second state. An example of different bias conditions is sensing the conduction current of a bit line at different time lengths. In this document, this sensing time is referred to as “FSENSE”. Using two (or more) different FSENSEs allows different threshold voltages to be sensed while the same verification reference voltage is applied to the selected sub-line. Therefore, this can be referred to as “simultaneous multi-threshold” sensing.

[0125] Using SMT sensing saves time during programming verification. However, when reading memory cells later, the bias conditions used for each memory cell being read are unknown. Therefore, all memory cells can be read using the same bias conditions. For example, all memory cells can be read using a nominal (e.g., short) FSENSE. Therefore, memory cells verified using a longer FSENSE will be read using a different FSENSE than the one used during verification.

[0126] It should be noted that memory cells can respond differently to bias condition reads that differ from those used during use and verification. For example, they may exhibit different threshold voltage shifts. Ideally, as a result of different bias conditions (e.g., sensing time), all memory cells would experience the same threshold voltage shift. However, this may not be the case. This can lead to variations in the threshold voltage shift of memory cells read under bias conditions different from those used for verification.

[0127] Figure 10 This is a flowchart describing a process 1000 for verifying that a memory cell has been erased. In one embodiment, steps 810 and 812 of process 800 are used... Figure 10 The process 1000. In step 1002, a set of erase verification conditions are applied to the memory cell. In one embodiment, a source follower sensing is employed. Step 1002 includes discharging the bit line to ground, which can be achieved by turning on the drain-side selected gate (SGD). Subsequently, a voltage higher than zero (e.g., 2.2V) is applied to the common source line and a voltage (e.g., 0V) is applied to the word line. Charge accumulates on the bit line of a given NAND string until the body effect disconnects at least one memory cell in the NAND string.

[0128] In step 1004, each cell in the NAND string is sensed to determine whether all memory cells on the NAND string have been sufficiently erased. Step 1004 is executed after a predetermined time period of waiting for charge to accumulate on the bit lines. In one embodiment, the voltage applied to the bit lines is compared to a reference value to determine whether any memory cell in the corresponding NAND string has a Vt value higher than a target value. The target value can be negative. In some embodiments, the memory cells are erased to up to -3V.

[0129] In one embodiment, if it is detected that Vt of each memory cell on the NAND string has reached the target level, then the data stored in the corresponding data latch is changed to logic "1". If it is detected that the NAND string has at least one memory cell with Vt that has not yet reached the appropriate target level, then the data stored in the corresponding data latch is not changed.

[0130] In step 1006, a determination is made as to whether a sufficient number of NAND strings have passed the erase verification. In one implementation, a certain number of NAND strings are allowed to fail the erase verification. For example, assuming fewer than 32 NAND strings fail the erase verification, then the overall erase verification passes. If the erase passes, control is passed to step 812.

[0131] If the erase verification fails in step 1006, then the erase voltage is increased in step 1010. The erase voltage can be increased by any desired amount, such as 0.2 V, 0.5 V, 1.0 V, etc. The new erase voltage is applied in step 1012. Subsequently, step 1002 is executed again. It should be noted that erase verification can be performed without source follower technology.

[0132] As discussed earlier, while one or more programming pulses can be used to determine the correct programming voltage (VPGM) level, this solution may not be ideal. Specifically, using multiple programming pulses to determine the appropriate programming voltage may result in a slower programming operation than if multiple programming pulses were not required.

[0133] Therefore, this document describes a memory device (e.g., Figure 5B The memory device 596 in the memory includes a memory element or memory cell (e.g., Figure 3 The blocks of storage elements 301, ..., 302-306, ..., 307 in the memory (e.g., Figure 3 BLK0 in the memory cell), where each memory cell is connected to multiple word lines (e.g., Figure 3 One of WL0-WL63 in the series. Memory cells are arranged in a string (e.g., Figure 3The device includes strings NS0, NS1, ..., NSn-1, each configured to maintain a threshold voltage Vt or Vth within a common threshold voltage range that defines a threshold window. The device also includes control circuitry coupled to the plurality of word lines and strings (e.g., ...). Figure 5B (Components 510, 512, 513, 514, 515, 516, 530, 550, 560, 565). The control circuit is configured to determine an erase upper tail voltage, which is the distribution of threshold voltages of the memory cell after an erase operation. The erase upper tail voltage corresponds to the loop condition of the memory cell. The control circuit is also configured to calculate, based on the erase upper tail voltage, a programming voltage to be applied to each of the selected word lines associated with the memory cell during a programming operation to program the memory cell.

[0134] As described above, an erase operation may include multiple erase pulses, such as an initial or first erase pulse and a second erase pulse. Therefore, the erase upper tail voltage includes the initial erase upper tail voltage or the first pulse erase upper tail voltage of the memory cell before the erase operation is completed, and the erase upper tail voltage also includes the final erase upper tail voltage of one of the memory cells in the string after the erase operation is completed.

[0135] Figure 11A The diagram illustrates the distribution of threshold voltages of memory cells prior to erase operations on new blocks (i.e., blocks manufactured after production and having undergone little or no write / erase (W / E) cycles), blocks that have undergone 50,000 W / E cycles, and blocks that have undergone 120,000 W / E cycles. Next, a first erase pulse is applied at the start of the erase phase. Therefore, the control circuitry is also configured to apply the first erase pulse to each of the selected word lines of the plurality of memory cells being erased during the erase operation. Figure 11B The diagram illustrates the distribution of threshold voltages in memory cells after the first erase pulse for a new block, a block that has undergone 50,000 W / E cycles, and a block that has undergone 120,000 W / E cycles. The control circuitry is also configured to determine an initial erase upper tail voltage based on the distribution of threshold voltages in the memory cells being erased after the first erase pulse. Furthermore, the control circuitry is configured to derive the cycling conditions for the memory cells being erased based on the initial erase upper tail voltage. This derivation is possible because blocks with higher cycles have slower erase speeds (e.g., resulting in higher initial erase upper tail voltages).

[0136] Return to reference Figure 4For example, each of the strings (e.g., NS0, NS1, etc.) is connected to a bit line (e.g., BL0, BL1, etc.), which is also coupled to the control circuitry. Multiple erase verifications can be used to detect the top tail position. This may include multiple BSPF criteria or multiple FSENSE times. Therefore, the control circuitry is also configured to determine the initial erase top tail voltage based on at least one of the bit scan operations and using multiple sensing times (i.e., FSENSE). As described above, for a bit scan operation, a count can be made of memory cells that fail to turn on in response to a specific read voltage (or attempt a read voltage and then increase or decrease it). Alternatively, for FSENSE, the control circuitry senses the conduction current of the bit lines for multiple sensing times while applying a verification reference voltage to each of the selected word lines to determine the threshold voltage of the memory cell being erased.

[0137] The control circuitry can then calculate the voltage of the second erase pulse based on the loop conditions, such that the final erase upper tail record or reflects the loop conditions. Blocks with more loops will have a higher upper tail (i.e., an upper tail associated with a relatively high threshold voltage), while newer blocks will have a lower upper tail (i.e., an upper tail associated with a relatively low threshold voltage). Therefore, the control circuitry applies a second erase pulse to a selected of the plurality of word lines during the erase operation based on the loop conditions to shift the threshold voltage of the memory cell being erased to have a final upper tail or a final erase upper tail voltage. Figure 11C The diagram shows an example distribution of the threshold voltage of a memory cell after the second erase pulse for a new block, a block that has undergone 50,000 W / E cycles, and a block that has undergone 120,000 W / E cycles. Figure 11C In the example shown, the final erase voltage of the upper tail of a new block can be 0.4V, the final erase voltage of the upper tail of a medium-cycle block can be 0.6V, and the final erase voltage of the upper tail of a high-cycle block can be 0.8V. Therefore, the device described herein uses a first pulse to erase the upper tail to determine the cyclic conditions of the block, and then uses that information to erase the final upper tail to the desired position (i.e., voltage). The erasure operation ends with a second erase pulse. However, it should be understood that the control circuitry can alternatively be configured to apply more than two erase pulses.

[0138] Figure 11DThe diagram illustrates an example distribution of threshold voltages for memory cells prior to the start of programming operations for a new block, a block that has undergone 50,000 W / E cycles, and a block that has undergone 120,000 W / E cycles. Before the programming operation, the memory device (e.g., control circuitry) can determine the block's cycling condition by reading the erase top tail position and determining the VPGM for the block to ensure that all utilized programming voltages are adjusted to the cycling condition. Therefore, the control circuitry is also configured to determine the final erase top tail voltage by continuously reading memory cells. Once the erase top tail position (e.g., the final erase top tail voltage) is verified, the block's cycling condition is decoded. Figure 11E The diagram shows an example distribution of the threshold voltage of a memory cell after the control circuit has determined the erase top and tail positions for a new block, a block that has undergone 50,000 W / E cycles, and a block that has undergone 120,000 W / E cycles.

[0139] Similar to the determination of the initial erase top tail voltage, the control circuitry is configured to determine the final erase top tail voltage based on at least one of the bit scan operations and using multiple sensing times. Therefore, for a bit scan operation, memory cells that fail to turn on in response to a specific read voltage (or attempt a read voltage and then increase or decrease it) can be counted. On the other hand, for the multiple sensing times, the control circuitry senses the conduction current of the bit lines during these multiple sensing times, while simultaneously verifying a reference voltage applied to each of the selected word lines to determine the threshold voltage of the memory cell being erased. Regardless of how it is determined, the top tail position will reveal the number of block cycles.

[0140] The control circuitry is also configured to calculate the programming voltage based on the final erase upper tail voltage. The programming voltage can also depend on the desired programming speed. Specifically, the programming voltage is modulated to account for changes in the programming speed with each write / erase (W / E) cycle (adaptive VPGM). After the programming voltage is determined, the control circuitry is configured to apply the programming voltage to each of the selected word lines of the memory cell (e.g., string 0) during the programming operation to program the memory cell. Figure 11FThe diagram illustrates the distribution of threshold voltages in memory cells after the control circuitry has programmed the memory cells during programming operations for new blocks, blocks that have undergone 50,000 write / erase (W / E) cycles, and blocks that have undergone 120,000 W / E cycles. While new blocks are described as having undergone no or only a minimal number of write / erase (W / E) cycles, and other blocks are described as having undergone 50,000 or 120,000 W / E cycles, it should be understood that these quantities of W / E cycles are provided only as examples, and other quantities of W / E cycles can alternatively describe new blocks, blocks with medium cycles, and blocks with high cycles.

[0141] The control circuit may also include a programmable voltage register (e.g., Figure 5B (Register 515). Additionally, the plurality of word lines can be grouped within word line regions. Therefore, the control circuitry is also configured to store a programming voltage in a programming voltage register. When a memory cell connected to each of the selected word lines within one of the word line regions is programmed, the programming voltage stored in the programming voltage register can subsequently be applied to each of the selected word lines (e.g., strings 1-4). When other strings in a block of memory cells are programmed in another programming operation, the programming voltage stored in the programming voltage register can also be applied to the selected word lines.

[0142] For individual word line erase top-to-bottom detection, certain offsets can be used to compensate for word line-to-word line variations, or an offset can be applied during the erase phase so that all word line erase top-to-bottom or erase top-to-bottom voltages (e.g., initial erase top-to-bottom voltage and / or final erase top-to-bottom voltage) will be at the same position (i.e., the threshold voltage Vt). Therefore, the control circuit can be further configured to determine and apply an offset to at least one of the first and second erase pulses during the erase operation. This offset ensures that at least one of the initial erase top-to-bottom voltage and the final erase top-to-bottom voltage is at approximately the same position within the threshold window.

[0143] Figure 12This is a graph showing the correlation between the programming and erasing speeds of memory cells under different cycling conditions. Specifically, it plots the evolution at room temperature of the average differential threshold voltage Vt (dVt) of the memory device evaluated after a programming operation compared to a new memory device at a specific programming voltage fine-tuning setting (VPGMSLCTrim-0.5V), relative to the average differential threshold voltage Vt (dVt) of the memory device evaluated after an erasing operation compared to a new memory device at a specific erasing voltage (VERA=14.8V), which is the difference between the threshold voltage Vt of the memory cell of the memory device evaluated after an erasing operation compared to the threshold voltage Vt of the new memory device. The evaluation or test involves subjecting the memory cells being evaluated to repeated programming and erasing operations (0 cycles, 10,000 (10k) cycles, 20,000 (20k) cycles, 30,000 (30k) cycles, 40,000 (40k) cycles, 50,000 (50k) cycles, ... 120,000 (120k) cycles), and each cluster shown is from a programming and erasing (WE) condition. The programming operations used in the evaluation are performed pulse-by-pulse, and the erasing operations are also performed pulse-by-pulse. The tests consist of a total of four memory devices, each with two blocks, and all strings. Figure 12 The data shown is only for word line WL47; however, similar correlations are shown for other word lines. As illustrated, there is an excellent correlation between the changes in programming and erasing speeds after the programming and erasing (WE) operations. More specifically, in the data shown, the programming speed appears to be approximately 1.2 times the erasing speed, depending on the programming and erasing (WE) operations. Therefore, due to this correlation, for each dVt after an erase operation, the corresponding programming voltage VPGM can be calculated depending on the number of cycles that the memory device's cells have undergone.

[0144] Figure 13 This is a graph showing the average lower tail (desired lower tail position) versus programming voltage after a programming operation for a new memory device and a memory device that has undergone 75,000 program and erase cycles. The data shown is after the first programming pulse of the programming operation. The programming slope (approximately 0.6 volts) is the same for both new blocks and blocks that have undergone 75,000 program and erase cycles. As shown, the programming speed (programming operation speed) of the cycled block (the block that has undergone 75,000 program and erase cycles) is approximately 0.3 volts faster than that of the new cycled block. Therefore, the programming voltage VPGM can be based on the lower tail, which is related to the cycle condition or how many cycles the memory cells of the memory device have undergone.

[0145] Now for reference Figure 14 The method also provides a way to operate a memory device. As discussed above, the memory device comprises a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and the memory cells are arranged in a string. Each of the memory cells is configured to maintain a threshold voltage within a common threshold voltage range that defines a threshold window. Therefore, the method includes step 1100 of determining an erase upper tail voltage, which is a distribution of the threshold voltage of the memory cells after an erase operation, the erase upper tail voltage corresponding to a loop condition of the memory cells. The method continues with step 1102 of calculating a programming voltage, based on the erase upper tail voltage, to be applied during a programming operation to each of the selected word lines associated with the memory cells to program the memory cells.

[0146] Because an erase operation can include multiple erase pulses, such as an initial or first erase pulse and a second erase pulse, the erase upper tail voltage includes the initial erase upper tail voltage of the memory cell before the erase operation is completed. Therefore, the method also includes the step of applying a first erase pulse to each of the selected word lines connected to the memory cell being erased during the erase operation. The method continues by determining the initial erase upper tail voltage as a distribution of threshold voltages of the memory cell being erased after the first erase pulse.

[0147] The method further includes a step of inferring the loop condition of the memory cell being erased based on the initial erase top tail voltage. Next, during the erase operation, a second erase pulse is applied to a selected of the plurality of word lines based on the loop condition to shift the threshold voltage of the memory cell being erased to have a final erase top tail voltage.

[0148] Furthermore, the erase upper tail voltage includes the final erase upper tail voltage of a memory cell in the string after the erase operation has been completed. Therefore, the method also includes the step of determining the final erase upper tail voltage by continuously reading the memory cells. The method continues with the step of calculating a programming voltage based on the final erase upper tail voltage. The next step of the method is to apply a programming voltage to each of the selected word lines of the memory cell in the string during the programming operation to program the memory cell.

[0149] The method may further include a step of determining and applying an offset to at least one of the first and second erase pulses during the erase operation to ensure that at least one of the initial erase upper tail voltage and the final erase upper tail voltage is in approximately the same position within a threshold window.

[0150] As mentioned above, the memory device may include a programming voltage register and the plurality of word lines may be grouped in a word line region. Therefore, the method may further include the step of storing a programming voltage to be applied to each of the plurality of word lines in the programming voltage register when, in another programming operation, a memory cell connected to each of the selected word lines within one of the word line regions and other string memory cells in a string of memory cell blocks are programmed.

[0151] It is obvious that changes may be made to the description and illustration herein without departing from the scope defined in the appended claims. The foregoing description of embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting of this disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable and may be used in chosen embodiments where applicable, even if not specifically shown or described. Individual elements or features of a particular embodiment may also be varied in various ways. These variations are not intended to be considered as departing from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

[0152] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a / an” and “described” as used herein are intended to also include the plural forms. The terms “comprising,” “including,” and “having” are inclusive and therefore define the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Unless expressly determined as a sequence of execution, the method steps, processes, and operations described herein should not be construed as requiring them to be performed in the particular order discussed or described. It should also be understood that additional or alternative steps may be employed.

[0153] When an element or layer is referred to as being "on" another element or layer, "engaged" to another element or layer, "connected" to another element or layer, or "coupled" to another element or layer, it may be directly on, engaged to, connected to, or coupled to another element or layer, or there may be intermediate elements or layers present. In contrast, when an element is referred to as being "directly on" another element or layer, "directly engaged" to another element or layer, "directly connected" to another element or layer, or "directly coupled" to another element or layer, there may be no intermediate elements or layers present. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0154] Although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms may simply be used to distinguish one element, component, area, layer, or part from another area, layer, or segment. Terms such as “first,” “second,” and other numerical terms, when used herein, do not imply order or sequence unless the context clearly indicates otherwise. Therefore, without departing from the teaching of the illustrative specific examples, the first element, component, area, layer, or segment discussed below may be referred to as the second element, component, area, layer, or segment.

[0155] Spatial relative terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” “top,” and “bottom” may be used herein for ease of description to describe the relationship of one element or feature to another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms may be intended to cover different orientations of the device in use or operation. For example, if the device in the figure were inverted, the orientation of an element described as “below” or “under” other elements or features would become “above” other elements or features. Therefore, the example term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

Claims

1. A memory device comprising: A block of memory cells, each of which is connected to one of a plurality of word lines and arranged in a string, and configured to keep the threshold voltage within a common range of threshold voltages that define a threshold window; Control circuitry, coupled to the plurality of word lines and the string, and configured to: During the erase operation, a first erase pulse is applied to each of the selected word lines of the plurality of word lines connected to the memory cell being erased. An initial erase upper tail voltage is determined based on the distribution of the threshold voltage of the memory cell after the first erase pulse of the erase operation, the initial erase upper tail voltage corresponding to the loop condition of the memory cell. During the erase operation, a second erase pulse, based on the cycle condition, is applied to each of the selected word lines to shift the threshold voltage of the memory cell being erased to a final erase upper tail voltage, wherein the cycle condition is recorded in the final erase upper tail itself. Based on the final erase upper tail voltage, a programming voltage will be calculated that will be applied during the programming operation to each of the selected word lines associated with the memory cell to program the memory cell.

2. The memory device of claim 1, wherein the control circuitry is further configured to: The cycle condition for the memory cell being erased is derived based on the initial erase upper and lower tail voltages.

3. The memory device of claim 2, wherein the control circuitry is further configured to determine and apply an offset to at least one of the first erase pulse and the second erase pulse during the erase operation to ensure that at least one of the initial erase upper tail voltage and the final erase upper tail voltage is at approximately the same position in the threshold window.

4. The memory device of claim 1, wherein each of the strings is connected to a bit line coupled to the control circuitry, and the control circuitry is further configured to determine the initial erase upper tail voltage based on at least one of the following: a bit scan operation in which memory cells that fail to turn on in response to a specific read voltage are counted; and conducting currents of the bit lines are sensed at multiple sensing times while a verification reference voltage is applied to each of the selected word lines to determine the threshold voltage of the memory cell being erased.

5. The memory device of claim 1, wherein the control circuitry includes a programming voltage register, and the plurality of word lines are grouped in a word line region, and the control circuitry is further configured to store the programming voltage to be applied to each of the selected words in the plurality of word lines in the programming voltage register when programming memory cells of strings of strings connected to each of the selected words in one of the word line regions and memory cells of other strings of strings in the block.

6. The memory device of claim 1, wherein the control circuitry is further configured to: The final erase upper and lower tail voltages are determined by continuously reading the memory cells. During the programming operation, the programming voltage is applied to each of the selected word lines of the memory cell having the final erase upper tail voltage to program the memory cell.

7. The memory device of claim 6, wherein each of the strings is connected to a bit line coupled to the control circuitry, and the control circuitry is further configured to determine the final erase upper tail voltage based on at least one of: a bit scan operation in which memory cells that fail to turn on in response to a specific read voltage are counted; and conducting currents of the bit lines are sensed at multiple sensing times while a verification reference voltage is applied to each of the selected word lines to determine the threshold voltage of the memory cell being erased.

8. A controller communicating with a memory device comprising a block of multiple memory cells, each of the memory cells being connected to one of a plurality of word lines and arranged in series and configured to maintain a threshold voltage within a common range of threshold voltages defining a threshold window, the controller being configured to: The memory device is instructed to apply a first erase pulse to each of the selected word lines of the plurality of word lines connected to the memory cell being erased during an erase operation. An initial erase upper tail voltage is determined based on the distribution of the threshold voltage of the memory cell after the first erase pulse of the erase operation, the initial erase upper tail voltage corresponding to the loop condition of the memory cell. The memory device is instructed to apply a second erase pulse, calculated based on the cycle condition, to one of the selected word lines during the erase operation to shift the threshold voltage of the memory cell being erased to a final erase upper tail voltage, wherein the cycle condition is recorded in the final erase upper tail itself. Based on the erase upper tail voltage, a programming voltage will be calculated that will be applied to each of the selected word lines associated with the memory cell during the programming operation to program the memory cell.

9. The controller of claim 8, wherein the controller is further configured to: The cycle condition for the memory cell being erased is derived based on the initial erase upper and lower tail voltages.

10. The controller of claim 9, wherein the controller is further configured to determine and apply an offset to at least one of the first erase pulse and the second erase pulse during the erase operation to ensure that at least one of the initial erase upper tail voltage and the final erase upper tail voltage is in approximately the same position within the threshold window.

11. The controller of claim 8, wherein the controller communicates with a programming voltage register and the plurality of word lines are grouped in a word line region, and the controller is further configured to store the programming voltage to be applied to each of the plurality of word lines in the programming voltage register when, in another programming operation, memory units of strings of strings connected to each of the selected word lines in one of the word line regions and memory units of other strings of strings in the block are programmed.

12. The controller of claim 8, wherein the controller is further configured to: The final erase upper tail voltage is determined by continuously instructing the memory device to read the memory cells, and The memory device is instructed to apply the programming voltage to each of the selected word lines of the memory cell having the final erase upper tail voltage during the programming operation to program the memory cell.

13. A method of operating a memory device comprising a block of multiple memory cells, each of the memory cells being connected to one of a plurality of word lines and arranged in series and configured to maintain a threshold voltage within a common range of threshold voltages defining a threshold window, the method comprising the steps of: During the erase operation, a first erase pulse is applied to each of the selected word lines of the plurality of word lines connected to the memory cell being erased. An initial erase upper tail voltage is determined as the distribution of the threshold voltage of the memory cell after the first erase pulse of the erase operation, the initial erase upper tail voltage corresponding to the loop condition of the memory cell; During the erase operation, a second erase pulse, based on the cycle condition, is applied to the selected of the plurality of word lines to shift the threshold voltage of the memory cell being erased to a final erase upper tail voltage, the final erase upper tail voltage of which records the cycle condition in the final erase upper tail itself. as well as Based on the final erase upper tail voltage, a programming voltage will be calculated that will be applied during the programming operation to each of the selected word lines associated with the memory cell to program the memory cell.

14. The method of claim 13, wherein the method further comprises the following steps: The cycle condition for the memory cell being erased is derived based on the initial erase upper and lower tail voltages.

15. The method of claim 14, wherein the method further comprises the step of determining and applying an offset to at least one of the first erase pulse and the second erase pulse during the erase operation to ensure that at least one of the initial erase upper tail voltage and the final erase upper tail voltage is in approximately the same position in the threshold window.

16. The method of claim 13, wherein the memory device includes a programming voltage register and the plurality of word lines are grouped in a word line region, and the method further includes the step of storing the programming voltage to be applied to each of the plurality of word lines in the programming voltage register when, in another programming operation, memory cells of strings of strings connected to each of the selected word lines in one of the word line regions and memory cells of other strings of strings in the block are programmed.

17. The method of claim 13, wherein the method further comprises the following steps: The final erase upper tail voltage is determined by continuously reading the memory cells; and During the programming operation, the programming voltage is applied to each of the selected word lines of the memory cell having the final erase upper tail voltage to program the memory cell.

Images