Memory and method of operating the same

Abstract

This disclosure relates to the field of semiconductor technology, providing a memory and its operating method to mitigate the damage caused by row hammer attacks. The memory includes a memory array and a control circuit. The control circuit is configured to, upon meeting preset conditions, respond to a command address signal and a mode control signal to enter a first mode, whereby it begins updating the count memory cell corresponding to the active word line at a first moment, and begins pre-charging the active word line at a second moment, using the count data as the count value for row hammer refresh; or, upon not meeting preset conditions, respond to the command address signal and the mode control signal to enter a second mode, whereby it does not perform an update operation on the count memory cell corresponding to the active word line, and begins pre-charging the active word line at a second moment, using the activation count value of the active word line in a dynamic lookup table as the count value for row hammer refresh. This achieves a balance between flexible configuration and reliability assurance, mitigating the damage caused by row hammer attacks.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a memory and a method of operating the same. Background Technology

[0002] As semiconductor process nodes continue to shrink and memory integration density continues to increase, the spacing between memory cells and word lines is significantly narrowed, leading to a sharp increase in parasitic capacitive coupling effects between adjacent word lines. When the number of accesses to a row in memory exceeds a threshold, it may cause data anomalies in nearby rows, a phenomenon commonly known as row hammering. Therefore, mitigating the harm caused by row hammering has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a method for operating the same.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] On one hand, embodiments of this disclosure provide a memory, including: a memory array and a control circuit;

[0006] The storage array includes multiple word lines and multiple storage units connected to each word line. The multiple storage units include multiple main storage units for storing valid data and at least one counting storage unit. The counting storage unit is configured to store count data associated with the number of accesses of the corresponding word line.

[0007] The control circuit is configured to: when a preset condition is met, in response to a command address signal and a mode control signal, enter a first mode, start updating the count data in the counting storage unit corresponding to the active word line among the multiple word lines at a first moment, start precharging the active word line at a second moment, and use the updated count data stored in the counting storage unit as the count value for row hammer refresh;

[0008] or,

[0009] When the preset conditions are not met, in response to the command address signal and the mode control signal, the system enters the second mode. The system does not perform the update operation of the count data in the count storage unit corresponding to the active word line among the multiple word lines. At the second moment, the system performs a pre-charge operation on the active word line and uses the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh.

[0010] In some embodiments, the control circuit is further configured to: when a preset condition is met, in response to a command address signal and a mode control signal, enter a third mode, not perform the update operation of the counting data on the counting storage unit corresponding to the active word line among the multiple word lines, start a pre-charging operation on the active word line at a first moment, and use the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh.

[0011] In some embodiments, the row pre-charging time of the first mode and the second mode are equal and both are greater than the row pre-charging time of the third mode; wherein, the time interval between the row pre-charging time of the first mode and the second mode and the third mode is the time interval between the first time and the second time.

[0012] In some embodiments, performing the update operation on the count data includes:

[0013] Read the counting data stored in the counting storage unit corresponding to the activated word line;

[0014] Update the read count data;

[0015] The updated count data is written into the count storage unit;

[0016] The preset condition means that the time interval between the end of the update operation and the second time is greater than or equal to a preset duration.

[0017] In some embodiments, the mode control signal includes a first mode control signal and a second mode control signal; the control circuit is specifically configured to: enter the first mode in response to the first mode control signal being at a first level.

[0018] or,

[0019] In response to the first mode control signal being in the second level state and the second mode control signal being in the second level state, the second mode is entered;

[0020] or,

[0021] In response to the first mode control signal being in the second level state and the second mode control signal being in the first level state, the system enters the third mode.

[0022] In some embodiments, the control circuit includes a first signal decoding circuit, a second signal decoding circuit, a first sub-control circuit, and a second sub-control circuit;

[0023] The first signal decoding circuit is configured to receive the command address signal and decode the command address signal to obtain a first precharge signal and a second precharge signal;

[0024] The second signal decoding circuit is configured to receive a first mode control signal and a second mode control signal, and generate a first control signal and a second control signal based on the first mode control signal and the second mode control signal;

[0025] The first sub-control circuit is configured to: receive the first pre-charge signal, the second pre-charge signal, the first control signal, and the second control signal, and generate a first sub-activation signal and a second sub-activation signal;

[0026] The second sub-control circuit is configured to: receive the first sub-activation signal and the second sub-activation signal, and enter the first mode, the second mode, or the third mode based on the first sub-activation signal and the second sub-activation signal; wherein the first sub-activation signal is used to indicate the update operation to be performed on the counting storage unit, and the second sub-activation signal is used to indicate the access operation to be performed on the activation word line.

[0027] In some embodiments, the second sub-control circuit is specifically configured as follows:

[0028] In the first mode, at the first moment, based on the first sub-activation signal being in an active level state and the second sub-activation signal being in an inactive level state, the update operation of the count data is started on the count storage unit corresponding to the active word line among the multiple word lines; at the second moment, based on the first sub-activation signal switching from the active level state to the inactive level state and the second sub-activation signal switching from the inactive level state to the active level state, the pre-charge operation is started on the active word line, and the updated count data stored in the count storage unit is used as the count value of the row hammer refresh;

[0029] or,

[0030] In the second mode, at the first moment, since both the first sub-activation signal and the second sub-activation signal are in an invalid level state, the update operation of the count data is not performed on the count storage unit corresponding to the active word line among the multiple word lines; at the second moment, since the first sub-activation signal is still in the invalid level state and the second sub-activation signal switches from the invalid level state to the active level state, the pre-charge operation is started on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value of the row hammer refresh;

[0031] or,

[0032] In the third mode, at the first moment, based on the first sub-activation signal being in an invalid level state and the second sub-activation signal being in an active level state, a pre-charge operation is started on the activation word line, and the activation count value of the activation word line stored in the dynamic lookup table is used as the count value for row hammer refresh.

[0033] In some embodiments, the first sub-control circuit includes an AND-OR-NOT gate and an AND gate; wherein, the two input terminals of the AND gate are respectively used to receive the first control signal and the first pre-charge signal, and the output terminal of the AND gate is used to output the first sub-activation signal;

[0034] The two AND logic inputs of the AND-OR-NOT gate are used to receive the inverted signals of the first pre-charge signal and the second control signal, respectively. The OR logic input of the AND-OR-NOT gate is used to receive the second pre-charge signal. The output of the AND-OR-NOT gate is used to output the second sub-activation signal.

[0035] In some embodiments, the memory further includes an alarm circuit, which includes a selector, a plurality of first-in-first-out (FIFO) registers, and a comparator;

[0036] The selector is configured to respond to the first mode control signal by outputting, in the first mode, the updated count data stored in the count storage unit corresponding to the target word line among the multiple word lines, or in the second mode, the active count value stored in the dynamic lookup table corresponding to the target word line among the multiple word lines; the inputs of the multiple first-in-first-out FIFO registers are connected to the output of the selector, and the input of the comparator is connected to the output of the multiple first-in-first-out FIFO registers;

[0037] The comparator is configured to output an alarm message when the count data or the activation count value is greater than or equal to a preset threshold.

[0038] In some embodiments, the control circuit is further configured to: in a first mode, determine a target word line among multiple word lines based on the updated count data stored in the count storage unit, perform a row hammer refresh operation on the victim line adjacent to the target word line, and reset the count data stored in the count storage unit corresponding to the target word line;

[0039] or,

[0040] In the second and third modes, under the timing window of the global refresh signal, the target word line among multiple word lines is determined according to the activation count value stored in the dynamic lookup table, and a row hammer refresh operation is performed on the victim line adjacent to the target word line.

[0041] On the other hand, embodiments of this disclosure provide an operation method for a memory, the memory including: a memory array and a control circuit, the memory array including multiple word lines and multiple memory cells connected to each word line, the multiple memory cells including multiple main memory cells for storing valid data and at least one counting memory cell, the counting memory cell being configured to store count data associated with the access count of a corresponding word line; the operation method includes:

[0042] When the preset conditions are met, in response to the command address signal and the mode control signal, the system enters the first mode. At the first moment, the system performs the update operation of the count data in the counting storage unit corresponding to the active word line among the multiple word lines. At the second moment, the system performs the pre-charge operation in the active word line and uses the updated count data stored in the counting storage unit as the count value for row hammer refresh.

[0043] or,

[0044] When the preset conditions are not met, in response to the command address signal and the mode control signal, the second mode is entered. The count data update operation is not performed on the count storage unit corresponding to the active word line among the multiple word lines. At the second moment, the pre-charge operation is performed on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value of the row hammer refresh.

[0045] In some embodiments, the operating method further includes:

[0046] When the preset conditions are met, in response to the command signal and the mode control signal at the first moment, the third mode is entered. The counting data update operation is not performed on the counting storage unit corresponding to the active word line among the multiple word lines. At the first moment, the active word line is pre-charged and the active count value of the active word line stored in the table is dynamically searched as the count value of the row hammer refresh.

[0047] In some embodiments, the operating method further includes:

[0048] Receive the command address signal, and decode the command address signal to obtain a first precharge signal and a second precharge signal;

[0049] Receive a first mode control signal and a second mode control signal, and generate a first control signal and a second control signal based on the first mode control signal and the second mode control signal;

[0050] The system receives the first precharge signal, the second precharge signal, the first control signal, and the second control signal, generates a first sub-activation signal and a second sub-activation signal, and enters the first mode, the second mode, or the third mode based on the first sub-activation signal and the second sub-activation signal; wherein the first sub-activation signal is used to indicate that the update operation is performed on the counting storage unit, and the second sub-activation signal is used to indicate that the access operation is performed on the activation word line.

[0051] In some embodiments, in the first mode, at the first moment, the first sub-activation signal is in an active level state, and the second sub-activation signal is in an inactive level state; at the second moment, the first sub-activation signal switches from the active level state to the inactive level state, and the second sub-activation signal switches from the inactive level state to the active level state.

[0052] In the second mode, at the first moment, both the first sub-activation signal and the second sub-activation signal are in the invalid level state; at the second moment, the first sub-activation signal is still in the invalid level state, and the second sub-activation signal switches from the invalid level state to the valid level state.

[0053] In the third mode, at the first moment, the first sub-activation signal is in the invalid level state, and the second sub-activation signal is in the valid level state.

[0054] In some embodiments, the operating method further includes:

[0055] In response to the first mode control signal, the updated count data stored in the count storage unit corresponding to the target word line among the multiple word lines is output in the first mode, or the active count value stored in the dynamic lookup table corresponding to the target word line among the multiple word lines is output in the second mode.

[0056] When the number of count data or the number of active count values ​​is greater than or equal to a preset threshold, an alarm message is output.

[0057] This disclosure provides a memory comprising: a memory array and a control circuit; the memory array includes multiple word lines and multiple memory cells connected to each word line, the multiple memory cells including multiple main memory cells for storing valid data and at least one counting memory cell, the counting memory cell being configured to store counting data associated with the access count of the corresponding word line; the control circuit is configured to: when a preset condition is met, in response to a command address signal and a mode control signal, enter a first mode, and at a first moment, perform a counting data update operation on the counting memory cell corresponding to the active word line among the multiple word lines, and at a second moment, perform a pre-charge operation on the active word line, and use the updated counting data stored in the counting memory cell as the count value for row hammer refresh; or, when the preset condition is not met, in response to a command address signal and a mode control signal, enter a second mode, and do not perform a counting data update operation on the counting memory cell corresponding to the active word line among the multiple word lines, and at a second moment, perform a pre-charge operation on the active word line, and use the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh. Thus, the memory control circuit in this disclosure, based on command address signals and mode control signals, can flexibly switch between the first mode and the second mode under different conditions of satisfying or not satisfying preset conditions. It dynamically decides whether to perform a count update operation on the count storage unit corresponding to the active word line, and further uses the updated count data stored in the count storage unit or the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh. This architecture supports the selective enabling and disabling of the Per Row Activation Counting (PRAC) function. While ensuring the real-time response of commands, even if the PRAC function is selectively disabled, row hammer refresh protection can still be maintained by relying on alternative methods, effectively preventing the loss of hammered row and victim row data, thereby achieving a balance between flexible configuration and reliability assurance, and significantly mitigating the damage caused by row hammering. Attached Figure Description

[0058] Figure 1 A block diagram of a memory provided in an embodiment of this disclosure;

[0059] Figure 2 Control timing diagrams for each signal in the first mode provided in this embodiment of the present disclosure;

[0060] Figure 3 This is a control timing diagram of each signal in the second mode provided in the embodiments of this disclosure;

[0061] Figure 4 This is a control timing diagram of a command signal provided in an embodiment of the present disclosure;

[0062] Figure 5 A block diagram of a control circuit provided in an embodiment of this disclosure;

[0063] Figure 6 A schematic diagram of the circuit structure of a first sub-control circuit provided in an embodiment of this disclosure;

[0064] Figure 7 This is one of the control timing diagrams for each signal under different modes provided in the embodiments of this disclosure;

[0065] Figure 8 This is a schematic diagram of the structure of an alarm circuit provided in an embodiment of the present disclosure;

[0066] Figure 9 This is the second control timing diagram of each signal under different modes provided in the embodiments of this disclosure;

[0067] Figure 10 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. Detailed Implementation

[0068] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0069] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0070] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0071] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices or units, and are not used to limit the order of the functions performed by these devices or units or their interdependence.

[0072] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0073] To mitigate the damage caused by row hammering, some memory systems have introduced Per Row Activation Counting (PRAC) to record the number of activations for each word line / row, enabling more accurate recording, monitoring, and intervention of row hammering damage. However, due to limitations in manufacturing processes, memory systems supporting PRAC still face numerous challenges in practical use.

[0074] The present disclosure provides the following implementation methods.

[0075] Figure 1 A block diagram of a memory is provided for embodiments of this disclosure, such as... Figure 1 As shown, the memory 100 includes a memory array 102 and a control circuit 104. In this embodiment of the present disclosure, the memory array 102 includes multiple word lines (WL) and multiple memory cells connected to each word line. The multiple memory cells include multiple main memory cells for storing valid data and at least one count cell, which is configured to store count data associated with the number of accesses of the corresponding word line.

[0076] In some implementations, memory 100 is a sixth-generation low-power double data rate (LPDDR6) memory, a sixth-generation double data rate (DDR6) memory, etc.

[0077] In some implementations, valid data refers to data input from outside the memory that needs to be stored in the main memory, such as normal data.

[0078] In some implementations, the number of counting storage units connected to the same word line can be one or more. In practical applications, the number of counting storage units can be flexibly configured according to the amount of data to be stored.

[0079] In some embodiments, the control circuit 104 is configured to: when a preset condition is met, in response to a command address signal and a mode control signal, enter a first mode, start updating the counting data of the counting storage unit corresponding to the active word line among the multiple word lines at a first moment, start precharging the active word line at a second moment, and use the updated counting data stored in the counting storage unit as the counting value for the row hammer refresh; or, when the preset condition is not met, in response to a command address signal and a mode control signal, enter a second mode, not update the counting data of the counting storage unit corresponding to the active word line among the multiple word lines, start precharging the active word line at a second moment, and use the activation count value of the active word line stored in the dynamic lookup table as the counting value for the row hammer refresh.

[0080] For example, such as Figure 1 and Figure 2 As shown, the control circuit 104 is configured to: when the preset conditions are met, in response to the command address signal and the mode control signal, enter the first mode, start at the first time T1 to perform the update operation of the counting storage unit corresponding to the active word line among the multiple word lines, start at the second time T2 to perform the pre-charge operation of the active word line, and use the updated counting data stored in the counting storage unit as the count value of the row hammer refresh (RHR).

[0081] Here, the operation of updating the counting data includes: reading the counting data stored in the counting storage unit corresponding to the active word line; updating the read counting data; and writing the updated counting data into the counting storage unit.

[0082] The duration of the Read-Modify-Write (RMW) operation on the count data is the first preset duration tACU. The end time of the update operation is the end time of writing the updated count data into the count storage unit. After the end time of the update operation, there will be a write recovery time (tWR). At the second moment T2 after the write recovery time tWR, a precharge operation is performed on the active word line, and the updated count data stored in the count storage unit is used as the count value for row hammer refresh.

[0083] In some implementations, the preset condition indicates the time when the update operation ends. Figure 2 (not shown in the image) and the second time T2 (reference) Figure 2 The time interval between the two operations is greater than or equal to a preset duration. In other words, the preset condition means that the write recovery time tWR of the above RMW operation is greater than or equal to the preset duration.

[0084] Due to technological limitations, memory may experience insufficient write recovery time (tWR). In such cases, the data written to the counting memory during the aforementioned RMW operation may be incomplete, or the written rows may fail to recover properly, leading to data errors or loss. By setting the preset condition that the write recovery time (tWR) of the RMW operation is greater than or equal to a preset duration, the PRAC function can be executed with sufficient write recovery time, balancing the reliability of count data writing and mitigating the damage caused by row hammering.

[0085] In some implementations, considering that insufficient timing margin for reading the counting memory unit or other factors causing PRAC function failure (such as counting memory unit failure) may lead to reduced reliability of the counting data when performing the RMW operation to update the counting data corresponding to the active word line, the aforementioned preset conditions may further include: the duration of the reading phase of the RMW operation being greater than or equal to a preset reading duration or the number of faulty units in the counting memory unit being less than or equal to a first preset threshold, to ensure the reliability of the counting data and thus ensure the reliability of the row hammer refresh.

[0086] In other implementations, operating temperature also significantly affects the writing of counting data. In low-temperature environments, the actual write recovery time (tWR) will be prolonged, exceeding the factory-preset write recovery time. If the memory still operates according to the preset write recovery time, it may cause the pre-charge operation on the active word line to begin before the writing of the counting data in the RMW operation is complete. Consequently, the data written to the counting memory cell by the RMW operation will be incomplete, resulting in data loss. Therefore, another preset condition is that the operating temperature of the memory is greater than or equal to a second preset threshold.

[0087] In this embodiment of the disclosure, the row precharge time (tRP) is the sum of the first preset duration tACU, the write recovery time tWR, and the second preset duration tRP1. The time interval between the start time (second time T2) of the precharge operation on the active word line and the end time (third time T3) of the precharge operation on the active word line is denoted as the second preset duration tRP1, representing the duration of the precharge operation on the active word line.

[0088] In some embodiments, such as Figure 1 and Figure 3 As shown, the control circuit 104 is configured to: when the preset conditions are not met, in response to the command address signal and the mode control signal, enter the second mode, not perform the count data update operation on the count storage unit corresponding to the active word line among the multiple word lines, start the pre-charge operation on the active word line at the second time T2, and use the activation count value of the active word line stored in the dynamic lookup table as the count value of the row hammer refresh.

[0089] In some implementations, the Dynamic Look-Up Table (DULT) is a row hammer monitoring mechanism based on probability sampling. The DULT employs a random sampling mechanism; in other words, it does not track the activation count of all rows. Instead, it randomly samples the addresses of activated rows, for example, using a hardware random number generator or pseudo-random algorithm to sample and record the addresses of activated rows with a specific probability. Only when a sample hits is the row address recorded in the DULT and the activation count accumulated. When the cumulative activation count of any row address in the table reaches a preset row hammer refresh threshold, the control circuit can trigger a row hammer refresh based on the DULT, refreshing the adjacent victim rows. This mitigates the risk of data corruption probabilistically without interrupting normal read / write operations.

[0090] exist Figure 3 During the execution of the second mode as shown, the row precharge time (tRP) is the sum of the first preset duration tACU, the write recovery time tWR (not shown), and the second preset duration tRP1.

[0091] It should be noted that, due to the failure to meet the preset conditions, although the precharge operation on the active word line begins at the second time T2 after the first preset duration tACU and write recovery time tWR in the second mode, the RMW operation is not performed at all during the second mode. Thus, when the preset conditions are not met (e.g., the write recovery time tWR of the RMW operation is less than the preset duration), the PRAC function can be selectively disabled, and the RMW operation can be avoided. This prevents counting data errors or loss caused by the write recovery time tWR of the RMW operation being less than the preset duration, and allows for an alternative method to mitigate the damage caused by row hammering.

[0092] The memory provided in this embodiment can flexibly switch between a first mode and a second mode based on command address signals and mode control signals, depending on whether preset conditions are met or not. It dynamically decides whether to perform a count update operation on the count storage unit corresponding to the active word line, and further uses the updated count data stored in the count storage unit or the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh. This architecture supports the selective enabling and disabling of the row-by-row activation counting function. While ensuring real-time command response, even if the PRAC function is selectively disabled, row hammer refresh protection can still be maintained through alternative methods, effectively preventing the loss of hammer-attacked and victimized row information. This achieves a balance between flexible configuration and reliability assurance, significantly mitigating the damage caused by row hammer attacks.

[0093] Figure 4 Figure (a) is a control timing diagram of command signals in a third mode provided in an embodiment of this disclosure. Figure 4 Figure (b) is a control timing diagram of the command signal in a first mode provided in an embodiment of the present disclosure.

[0094] In some embodiments, such as Figure 1 and Figure 4 As shown in Figure (a), the control circuit 104 is further configured to: when preset conditions are met, respond to the command address signal and the mode control signal, enter a third mode, and not perform a count data update operation on the counting storage unit corresponding to the active word line among the multiple word lines. At the first moment T1, a pre-charge operation is performed on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value for row hammer refresh. The first moment is the moment when the operation begins based on the externally sent pre-charge command PRE. In some embodiments, based on testing requirements or actual user scenarios, the memory 100 supports the mode of fifth-generation low-power double data rate (LPDDR5) memory (or supports fifth-generation double data rate DDR5 memory), and can selectively disable the PRAC function based on the command address signal and the mode control signal when preset conditions are met, thus not performing RMW operation, thereby flexibly adjusting the row hammer protection strategy while maintaining standard compatibility.

[0095] exist Figure 4 During the execution of the third mode as shown in Figure (a), the counting data update operation is not performed on the counting storage unit corresponding to the active word line among the multiple word lines. The pre-charging operation is performed on the active word line starting at the first time T1, and the pre-charging operation ends at the fourth time T4 after a pre-charging time tRP2.

[0096] exist Figure 4 In the execution of the first mode as shown in Figure (b), at the first time T1, the counting data update operation is performed on the counting storage unit corresponding to the active word line among the multiple word lines. At the second time T2, the pre-charging operation is performed on the active word line. After a second preset time tRP1, the pre-charging operation on the active word line ends at the third time T3.

[0097] In some embodiments, such as Figure 4 As shown, the third time T3 and the fourth time T4 are the same time.

[0098] In some embodiments, reference Figure 2 , Figure 3 and Figure 4The row precharge time tRP of the first mode and the second mode are equal and both are greater than the row precharge time tRP2 of the third mode; wherein, the time interval between the row precharge time of the first mode, the second mode and the third mode is the time interval between the first time T1 and the second time T2.

[0099] In some implementations, the pre-charging duration for the active word line is equal in the first, second, and third modes, that is, Figure 2 , Figure 3 as well as Figure 4 The second preset duration tRP1 shown in Figure (b) is related to... Figure 4 The row precharge time tRP2 shown in (a) is equal.

[0100] In some implementations, the first preset duration tACU is 22ns, and the second preset duration tRP1 and the line precharge time tRP2 in the third mode are both 18ns.

[0101] exist Figure 4 During the execution of the third mode, the preset conditions were met. However, based on testing requirements or actual user scenarios, the PRAC function was selectively disabled in the third mode. No RMW operation was performed throughout the process, and pre-charging of the active word line began at the first moment T1, without waiting for the first preset duration tACU. This reduces the waiting time for initiating the pre-charging operation, maintains compatibility with LPDDR5 functionality, and mitigates the damage caused by row hammering through an alternative approach.

[0102] Table 1

[0103]

[0104] In some embodiments, as shown in Table 1, the mode control signal includes a first mode control signal cm1_ro_PracDis and a second mode control signal cm1_ro_PracDisRW; the control circuit is specifically configured to: enter a first mode in response to the first mode control signal cm1_ro_PracDis being at a first level.

[0105] or,

[0106] In response to the first mode control signal cm1_ro_PracDis being in the second level state and the second mode control signal cm1_ro_PracDisRW being in the second level state, the second mode is entered;

[0107] or,

[0108] In response to the first mode control signal cm1_ro_PracDis being in the second level state and the second mode control signal cm1_ro_PracDisRW being in the first level state, the system enters the third mode.

[0109] Here, the first level state is logic low level "0", and the second level state is logic high level "1".

[0110] It should be noted that the correspondence between the level states of the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW shown in Table 1 and the first, second, and third modes is merely an illustrative example. The level states of the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW can change, and this should not unduly limit the scope of protection of this disclosure. Furthermore, this correspondence can also be of other types, as long as the changes in the level states of the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW can correspond to different modes. For example, the first level state can be a logic high level "1", the second level state can be a logic low level "0", and the combination of level states formed by the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW can be used to distinguish between the first, second, and third modes.

[0111] also, Figure 2 and Figure 3 The signals RasEn, WL, PracOn, and PracWr in the RMW operation are shown. RasEn enables the Row Address Strobe (RAS) operation, WL enables the word line (on or off), PracOn enables PRAC, PracRd enables the read operation, and PracWr enables the write operation. CSL enables the column address strobe, Yio enables the global data line, LatR latches the read data in the RMW operation, and LatW latches the write data in the RMW operation.

[0112] Here, there can be multiple high-level pulses for the signal PracWr, for example, two.

[0113] Figure 4 Figure (a) and Figure 4 In Figure (b), the CMD signal line represents the command signal obtained by decoding the received external command address signal (CommandAddress, CA). Figure 4 In Figure (b), the Internal CMD signal line represents the internal command signal, iACT represents the internal activation signal, iRD represents the internal read signal, iWR represents the internal write signal, and iPRE represents the internal precharge signal.

[0114] In some embodiments, such as Figure 5 As shown, the control circuit 104 includes a first signal decoding circuit 106, a second signal decoding circuit 108, a first sub-control circuit 110, and a second sub-control circuit 112. The first signal decoding circuit 106 is configured to receive a command address signal CA, decode the command address signal CA to obtain a first precharge signal PreCmd_ACU and a second precharge signal PreCmd. The second signal decoding circuit 108 is configured to receive a first mode control signal cm1_ro_PracDis and a second mode control signal cm1_ro_PracDisRW, and generate a first control signal MdPRACEn and a second control signal MdPRACEn based on the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW. DisRW; The first sub-control circuit 110 is configured to: receive a first precharge signal PreCmd_ACU, a second precharge signal PreCmd, a first control signal MdPRACEn, and a second control signal MdPRACEnDisRW, and generate a first sub-activation signal RAST_ACU and a second sub-activation signal RAST; The second sub-control circuit 112 is configured to: receive the first sub-activation signal RAST_ACU and the second sub-activation signal RAST, and based on the first sub-activation signal RAST_ACU and the second sub-activation signal RAST, enter a first mode, a second mode, or a third mode; wherein, the first sub-activation signal RAST_ACU is used to indicate that an update operation is performed on the counting memory cell, and the second sub-activation signal RAST is used to indicate that an access operation is performed on the active word line.

[0115] In some implementations, as shown in Table 1, when the first mode control signal cm1_ro_PracDis is in the first level state and the second mode control signal cm1_ro_PracDisRW is in the first level state or the second level state, the first mode is entered, and both the first control signal MdPRACEn and the second control signal MdPRACEnDisRW are in the second level state.

[0116] In some implementations, as shown in Table 1, when the first mode control signal cm1_ro_PracDis is in the second level state and the second mode control signal cm1_ro_PracDisRW is in the first level state, the third mode is entered, and both the first control signal MdPRACEn and the second control signal MdPRACEnDisRW are in the first level state.

[0117] In some implementations, as shown in Table 1, when both the first mode control signal cm1_ro_PracDis and the second mode control signal cm1_ro_PracDisRW are in the second level state, the second mode is entered, the first control signal MdPRACEn is in the first level state, and the second control signal MdPRACEnDisRW is in the second level state.

[0118] In some embodiments, such as Figure 5 and Figure 7 As shown, the second sub-control circuit 112 is specifically configured as follows: In the first mode, at the first moment, based on the first sub-activation signal RAST_ACU being in an active level state and the second sub-activation signal RAST being in an inactive level state, the counting storage unit corresponding to the active word line among the multiple word lines begins to perform a counting data update operation; at the second moment, based on the first sub-activation signal RAST_ACU switching from an active level state to an inactive level state and the second sub-activation signal RAST switching from an inactive level state to an active level state, a pre-charge operation is performed on the active word line, and the updated counting data stored in the counting storage unit is used as the counting value for row hammer refresh; in this mode, both the first control signal MdPRACEn and the second control signal MdPRACEnDisRW are in the second level state.

[0119] In some embodiments, such as Figure 5 and Figure 7 As shown, the second sub-control circuit 112 is specifically configured as follows: In the second mode, at the first moment, based on the fact that both the first sub-activation signal RAST_ACU and the second sub-activation signal RAST are in an invalid level state, no update operation is performed on the counting storage unit corresponding to the active word line among the multiple word lines; at the second moment, based on the fact that the first sub-activation signal RAST_ACU is still in an invalid level state and the second sub-activation signal RAST has switched from an invalid level state to an active level state, a pre-charge operation is started on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value for row hammer refresh; in this mode, the first control signal MdPRACEn is in a first level state, and the second control signal MdPRACEnDisRW is in a second level state.

[0120] In some embodiments, such as Figure 5 and Figure 7 As shown, the second sub-control circuit 112 is specifically configured to: in the third mode, not perform a count data update operation on the count storage unit corresponding to the active word line among the multiple word lines; at the first moment, based on the first sub-activation signal RAST_ACU being in an invalid level state and the second sub-activation signal RAST being in an active level state, start performing a pre-charge operation on the active word line, and use the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh. In this mode, both the first control signal MdPRACEn and the second control signal MdPRACEnDisRW are in the first level state.

[0121] Here, the second sub-control circuit, based on the effective or ineffective level states of the first and second sub-activation signals, selects whether to perform a count data update operation on the counting storage unit corresponding to the active word line among multiple word lines in different modes, and accordingly selects the count value for row hammer refresh. In this way, the RMW operation can be flexibly switched based on the first and second activation signals, and the count data or the activation count value can be selected as the count value for row hammer refresh, achieving a balance between flexible configuration and reliability assurance, and significantly mitigating the damage caused by row hammer strikes.

[0122] Figure 7 Examples of valid logic level states (logic high) and invalid logic level states (logic low) are provided, but this should not unduly limit the scope of this disclosure.

[0123] In some embodiments, such as Figure 6 As shown, the first sub-control circuit 110 includes an AND-OR-NOT gate 1104 and an AND gate 1102; wherein, the two input terminals of the AND gate 1102 are respectively used to receive the first control signal MdPRACEn and the first pre-charge signal PreCmd_ACU, and the output terminal of the AND gate is used to output the first sub-activation signal RAST_ACU; the two AND logic input terminals of the AND-OR-NOT gate 1104 are respectively used to receive the inverted signals of the first pre-charge signal PreCmd_ACU and the second control signal MdPRACEnDisRW, the OR logic input terminal of the AND-OR-NOT gate 1104 is used to receive the second pre-charge signal PreCmd, and the output terminal of the AND-OR-NOT gate 1104 is used to output the second sub-activation signal RAST.

[0124] For example, when both the first control signal MdPRACEn and the first precharge signal PreCmd_ACU are in the second level state, the first sub-activation signal RAST_ACU, which is in the effective level, is generated.

[0125] For example, when the second precharge signal PreCmd is in a first level state and the first precharge signal PreCmd_ACU and the second control signal MdPRACEnDisRW are in one of the following states, a second sub-activation signal RAST at an effective level is generated:

[0126] The first precharge signal PreCmd_ACU and the second control signal MdPRACEnDisRW are both in the second level state, the first precharge signal PreCmd_ACU and the second control signal MdPRACEnDisRW are both in the first level state, or the first precharge signal PreCmd_ACU is in the first level state and the second control signal MdPRACEnDisRW is in the second level state.

[0127] In some embodiments, such as Figure 8 As shown, the memory also includes an alarm circuit 114, which includes a selector 1142, multiple first-in-first-out (FIFO) registers, and a comparator 1144. The selector 1142 is configured to respond to a first mode control signal cm1_ro_PracDis, in the first mode outputting the updated count data Acu stored in the counting memory cell corresponding to the target word line among the multiple word lines, or in the second mode outputting the activation count value Actcmd stored in the dynamic lookup table corresponding to the target word line among the multiple word lines. The inputs of the multiple FIFO registers (e.g., FIFO0, FIFO1, FIFO2, FIFO3, FIFO4, and FIFO5) are connected to the output of the selector 1142, and the input of the comparator 1144 is connected to the output of the multiple FIFO registers. The comparator 1144 is configured to output an alarm message Alert when the count data Acu or the activation count value Actcmd is greater than or equal to a preset threshold.

[0128] In some embodiments, when the cumulative number of activations of a target word line (e.g., count data Acu or activation count value Actcmd) exceeds a pre-threshold, it indicates that the access frequency of that line has exceeded the safety window. In this case, an alarm message must be output to trigger error reporting or enter an emergency protection state to ensure the operational security of the memory. Conversely, as long as the count value does not exceed (or equal to) the threshold, there is no need to initiate the alarm process.

[0129] Here, the target word line is one of multiple active word lines.

[0130] In some embodiments, such as Figure 9As shown in Figure (a), the control circuit is further configured to: in the first mode, determine the target word line among multiple word lines based on the updated count data stored in the count storage unit, perform a row hammer refresh operation on the victim line adjacent to the target word line, and reset the count data stored in the count storage unit corresponding to the target word line; for example, based on the count data stored in the count storage units corresponding to multiple word lines, the word line with the largest count data can be determined as the target word line. The control circuit responds to the row hammer refresh commands RHRa and RHRb, respectively, and performs refresh operations on the two victim lines adjacent to the target word line. After successfully performing the row hammer refresh operation on the adjacent victim lines, the row hammer effect caused by the repeated activation of the target word line is eliminated, the charge state of the adjacent storage units returns to normal, and the data integrity risk is thus eliminated. Therefore, the control circuit will respond to an externally or internally generated reset command (Reset) to clear or initialize the accumulated activation count in the count storage unit corresponding to the target word line, thereby releasing count resources and preparing for the next round of periodic row activation monitoring, ensuring that the PRAC mechanism can continuously and accurately track high-frequency access patterns.

[0131] like Figure 9 As shown in Figures (b) and (c), the control circuit is further configured to: in the second and third modes, under the timing window of the global refresh signal (Refresh all banks, REFab), determine the target word line among multiple word lines based on the activation count value stored in the dynamic lookup table, and perform row hammer refresh operations on the victim rows adjacent to the target word line. Within the global refresh command trigger refresh timing window, the control circuit filters out high-frequency access target word lines (Aggressor Rows) based on the activation frequency of each word line recorded in the dynamic lookup table. Subsequently, within the ample margin period of the REFab timing window, the control circuit responds to the row hammer refresh commands RHRa and RHRb to refresh the two victim rows adjacent to the target word line, and selectively performs row hammer refresh operations on the victim rows adjacent to the target word line. In this way, row hammer protection is completed by reusing the timing window of existing refresh commands, without requiring additional external bus bandwidth or a separate refresh cycle, significantly improving the overall system efficiency and resource utilization while ensuring data reliability.

[0132] Here, the global refresh signal REFab is a periodic refresh command that triggers a periodic refresh operation on all banks to retain the charge stored in the storage cells and prevent data loss.

[0133] It should be noted that, Figure 9 Figure (b) shows the control timing diagram for each signal in the second mode. Figure 9 Figure (c) shows the control timing diagram of each signal in the third mode. Figure 9 The RHR Flag shown represents the enable signal for the row hammer refresh operation. Figure 9 Figures (a), (b), and (c) show eight command signals, namely the first periodic refresh command 1st REF CMD, the second periodic refresh command 2nd REF CMD, ... the fifth periodic refresh command 5th REF CMD, the sixth periodic refresh command 6th REF CMD, the seventh periodic refresh command 7th REF CMD, and the eighth periodic refresh command 8th REF CMD.

[0134] In some embodiments, Figure 9 The CMD signal lines shown in Figures (a), (b), and (c) can also represent internal command signals.

[0135] On the other hand, based on the same inventive concept, this disclosure provides a method for operating a memory, as shown in the following embodiments. Since the principle by which this method solves the problem is similar to that of the memory embodiments described above, the implementation of this method can refer to the implementation of the memory embodiments described above, and repeated details will not be described again.

[0136] Memory 100 (reference) Figure 1 This includes: storage array 102 (reference) Figure 1 ) and control circuit 104 (reference) Figure 1 Storage array 100 (reference) Figure 1 It includes multiple word lines and multiple storage units connected to each word line. The multiple storage units include multiple main storage units for storing valid data and at least one counting storage unit, which is configured to store count data associated with the number of accesses of the corresponding word line.

[0137] Figure 10 This is a flowchart illustrating a memory operation method provided in an embodiment of the present disclosure, as shown below. Figure 10 As shown, the memory operation method specifically includes the following steps:

[0138] Step S1010: Determine whether the preset conditions are met;

[0139] Step S1020: When the preset conditions are met, in response to the command address signal and the mode control signal, enter the first mode, start the update operation of the counting storage unit corresponding to the active word line among the multiple word lines at the first moment, start the pre-charge operation of the active word line at the second moment, and use the updated counting data stored in the counting storage unit as the counting value of the row hammer refresh.

[0140] or,

[0141] Step S1030: When the preset conditions are not met, in response to the command address signal and the mode control signal, enter the second mode, do not perform the count data update operation on the count storage unit corresponding to the active word line among the multiple word lines, start the pre-charge operation on the active word line at the second moment, and use the activation count value of the active word line stored in the dynamic lookup table as the count value of the row hammer refresh.

[0142] It should be understood that Figure 10 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 10 The steps shown can be adjusted in order according to actual needs.

[0143] In some embodiments, the method of operating the memory further includes:

[0144] When the preset conditions are met, the system responds to the command signal and the mode control signal at the first moment and enters the third mode. It does not perform the count data update operation on the count storage unit corresponding to the active word line among the multiple word lines. Instead, it starts to precharge the active word line at the first moment and uses the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh.

[0145] In some embodiments, the method of operating the memory further includes:

[0146] Receive the command address signal, decode the command address signal to obtain the first precharge signal and the second precharge signal;

[0147] Receive a first mode control signal and a second mode control signal, and generate a first control signal and a second control signal based on the first mode control signal and the second mode control signal;

[0148] The system receives a first precharge signal, a second precharge signal, a first control signal, and a second control signal, generates a first sub-activation signal and a second sub-activation signal, and enters a first mode, a second mode, or a third mode based on the first sub-activation signal and the second sub-activation signal; wherein the first sub-activation signal is used to indicate that an update operation is performed on the counting storage unit, and the second sub-activation signal is used to indicate that an access operation is performed on the activation word line.

[0149] In some embodiments, in a first mode, at a first moment, the first sub-activation signal is in an active level state, and the second sub-activation signal is in an inactive level state; at a second moment, the first sub-activation signal switches from an active level state to an inactive level state, and the second activation signal switches from an inactive level state to an active level state.

[0150] In the second mode, at the first moment, both the first sub-activation signal and the second sub-activation signal are in an invalid level state; at the second moment, the first sub-activation signal is still in an invalid level state, and the second sub-activation signal switches from an invalid level state to an active level state.

[0151] In the third mode, at the first moment, the first sub-activation signal is in an invalid level state, and the second sub-activation signal is in an active level state.

[0152] In some implementations, at the fourth time T4 (reference) Figure 4 The first sub-activation signal is still in an invalid level state, and the second sub-activation signal switches from an active level state to an invalid level state.

[0153] In this way, the RMW operation can be flexibly switched based on the first and second activation sub-signals, and the corresponding count data or activation count value can be selected as the count value for row hammer refresh, achieving a balance between flexible configuration and reliability assurance, and significantly mitigating the damage caused by row hammer strikes.

[0154] In some embodiments, the method of operating the memory further includes:

[0155] In response to the first mode control signal, the updated count data stored in the count storage unit corresponding to the target word line among the multiple word lines is output in the first mode, or the active count value stored in the dynamic lookup table corresponding to the target word line among the multiple word lines is output in the second mode.

[0156] An alarm message is output when the number of count data or the number of activated count values ​​is greater than or equal to a preset threshold.

[0157] In some embodiments, the memory operation method further includes: in a first mode, determining a target word line among multiple word lines based on the updated count data stored in the count storage unit, performing a row hammer refresh operation on the victim line adjacent to the target word line, and resetting the count data stored in the count storage unit corresponding to the target word line;

[0158] or,

[0159] In the second and third modes, under the timing window of the global refresh signal, the target word line among multiple word lines is determined based on the activation count value stored in the dynamic lookup table, and a row hammer refresh operation is performed on the victim line adjacent to the target word line.

[0160] The operation method of the memory mentioned in the above embodiments has been described in detail in the foregoing embodiments concerning the memory, and will not be repeated here for the sake of brevity.

[0161] This disclosure also provides an exemplary embodiment of an electronic device, which includes the aforementioned memory. The electronic device may be a mobile phone, tablet computer, personal computer, server, smartwatch, smart glasses, personal digital assistant, or in-vehicle computer, among other electronic devices.

[0162] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0163] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: Storage array and control circuitry; The storage array includes multiple word lines and multiple storage units connected to each word line. The multiple storage units include multiple main storage units for storing valid data and at least one counting storage unit. The counting storage unit is configured to store count data associated with the number of accesses of the corresponding word line. The control circuit is configured to: when a preset condition is met, in response to a command address signal and a mode control signal, enter a first mode, start updating the count data in the counting storage unit corresponding to the active word line among the multiple word lines at a first moment, start precharging the active word line at a second moment, and use the updated count data stored in the counting storage unit as the count value for row hammer refresh; or, When the preset conditions are not met, in response to the command address signal and the mode control signal, the system enters the second mode. The system does not perform the update operation of the count data in the count storage unit corresponding to the active word line among the multiple word lines. At the second moment, the system performs a pre-charge operation on the active word line and uses the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh.

2. The memory of claim 1, wherein, The control circuit is further configured to: when a preset condition is met, in response to the command address signal and the mode control signal, enter a third mode, not perform the update operation of the counting data on the counting storage unit corresponding to the active word line among the multiple word lines, start the pre-charging operation on the active word line at the first moment, and use the activation count value of the active word line stored in the dynamic lookup table as the count value for row hammer refresh.

3. The memory according to claim 2, characterized in that, The row pre-charging time of the first mode and the second mode are equal and both are greater than the row pre-charging time of the third mode; wherein, the time interval between the row pre-charging time of the first mode and the second mode and the third mode is the time interval between the first time and the second time.

4. The memory of claim 1, wherein, The operation of updating the count data includes: Read the counting data stored in the counting storage unit corresponding to the activated word line; Update the read count data; The updated count data is written into the count storage unit; The preset condition means that the time interval between the end of the update operation and the second time is greater than or equal to a preset duration.

5. The memory according to claim 2, characterized in that, The mode control signal includes a first mode control signal and a second mode control signal; the control circuit is specifically configured to enter the first mode in response to the first mode control signal being at a first level. or, In response to the first mode control signal being in the second level state and the second mode control signal being in the second level state, the second mode is entered; or, In response to the first mode control signal being in the second level state and the second mode control signal being in the first level state, the system enters the third mode.

6. The memory of claim 5, wherein, The control circuit includes a first signal decoding circuit, a second signal decoding circuit, a first sub-control circuit, and a second sub-control circuit. The first signal decoding circuit is configured to receive the command address signal and decode the command address signal to obtain a first precharge signal and a second precharge signal; The second signal decoding circuit is configured to receive a first mode control signal and a second mode control signal, and generate a first control signal and a second control signal based on the first mode control signal and the second mode control signal; The first sub-control circuit is configured to: receive the first pre-charge signal, the second pre-charge signal, the first control signal, and the second control signal, and generate a first sub-activation signal and a second sub-activation signal; The second sub-control circuit is configured to: receive the first sub-activation signal and the second sub-activation signal, and enter the first mode, the second mode, or the third mode based on the first sub-activation signal and the second sub-activation signal; wherein the first sub-activation signal is used to indicate the update operation to be performed on the counting storage unit, and the second sub-activation signal is used to indicate the access operation to be performed on the activation word line.

7. The memory of claim 6, wherein, The second sub-control circuit is specifically configured as follows: In the first mode, at the first moment, based on the first sub-activation signal being in an active level state and the second sub-activation signal being in an inactive level state, the update operation of the count data is started on the count storage unit corresponding to the active word line among the multiple word lines; at the second moment, based on the first sub-activation signal switching from the active level state to the inactive level state and the second sub-activation signal switching from the inactive level state to the active level state, the pre-charge operation is started on the active word line, and the updated count data stored in the count storage unit is used as the count value of the row hammer refresh; or, In the second mode, at the first moment, since both the first sub-activation signal and the second sub-activation signal are in an invalid level state, the update operation of the count data is not performed on the count storage unit corresponding to the active word line among the multiple word lines; at the second moment, since the first sub-activation signal is still in the invalid level state and the second sub-activation signal switches from the invalid level state to the active level state, the pre-charge operation is started on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value of the row hammer refresh; or, In the third mode, at the first moment, based on the first sub-activation signal being in an invalid level state and the second sub-activation signal being in an active level state, a pre-charge operation is started on the activation word line, and the activation count value of the activation word line stored in the dynamic lookup table is used as the count value for row hammer refresh.

8. The memory according to claim 7, characterized in that, The first sub-control circuit includes an AND-OR-NOT gate and an AND gate; wherein, the two input terminals of the AND gate are respectively used to receive the first control signal and the first pre-charge signal, and the output terminal of the AND gate is used to output the first sub-activation signal; The two AND logic inputs of the AND-OR-NOT gate are used to receive the inverted signals of the first pre-charge signal and the second control signal, respectively. The OR logic input of the AND-OR-NOT gate is used to receive the second pre-charge signal. The output of the AND-OR-NOT gate is used to output the second sub-activation signal.

9. The memory of claim 6, wherein, The memory also includes an alarm circuit, which includes a selector, multiple first-in-first-out (FIFO) registers, and a comparator. The selector is configured to respond to the first mode control signal by outputting the updated count data stored in the count storage unit corresponding to the target word line among the multiple word lines in the first mode, or by outputting the activation count value stored in the dynamic lookup table corresponding to the target word line among the multiple word lines in the second mode. The inputs of the plurality of first-in-first-out (FIFO) registers are connected to the output of the selector, and the input of the comparator is connected to the output of the plurality of FIFO registers; the comparator is configured to output an alarm message when the count data or the active count value is greater than or equal to a preset threshold.

10. The memory of claim 2, wherein, The control circuit is further configured to: in the first mode, determine the target word line among multiple word lines based on the updated counting data stored in the counting storage unit, perform a row hammer refresh operation on the victim line adjacent to the target word line, and reset the counting data stored in the counting storage unit corresponding to the target word line; or, In the second and third modes, under the timing window of the global refresh signal, the target word line among multiple word lines is determined according to the activation count value stored in the dynamic lookup table, and a row hammer refresh operation is performed on the victim line adjacent to the target word line.

11. A method of operating a memory, comprising: The memory includes a memory array and control circuitry. The memory array includes multiple word lines and multiple memory cells connected to each word line. The multiple memory cells include multiple main memory cells for storing valid data and at least one counting memory cell. The counting memory cell is configured to store count data associated with the access count of a corresponding word line. The operation method includes: When the preset conditions are met, in response to the command address signal and the mode control signal, the system enters the first mode. At the first moment, the system performs the update operation of the count data in the counting storage unit corresponding to the active word line among the multiple word lines. At the second moment, the system performs the pre-charge operation in the active word line and uses the updated count data stored in the counting storage unit as the count value for row hammer refresh. or, When the preset conditions are not met, in response to the command address signal and the mode control signal, the second mode is entered. The count data update operation is not performed on the count storage unit corresponding to the active word line among the multiple word lines. At the second moment, the pre-charge operation is performed on the active word line, and the activation count value of the active word line stored in the dynamic lookup table is used as the count value of the row hammer refresh.

12. The method of operating the memory according to claim 11, characterized in that, The operation method further includes: When the preset conditions are met, in response to the command address signal and the mode control signal, the third mode is entered. The counting data update operation is not performed on the counting storage unit corresponding to the active word line among the multiple word lines. The pre-charging operation is performed on the active word line at the first moment, and the activation count value of the active word line stored in the table is dynamically searched as the count value of the row hammer refresh.

13. The operating method of memory according to claim 12, wherein, The operation method further includes: Receive the command address signal, and decode the command address signal to obtain a first precharge signal and a second precharge signal; Receive a first mode control signal and a second mode control signal, and generate a first control signal and a second control signal based on the first mode control signal and the second mode control signal; The system receives the first precharge signal, the second precharge signal, the first control signal, and the second control signal, generates a first sub-activation signal and a second sub-activation signal, and enters the first mode, the second mode, or the third mode based on the first sub-activation signal and the second sub-activation signal; wherein the first sub-activation signal is used to indicate that the update operation is performed on the counting storage unit, and the second sub-activation signal is used to indicate that the access operation is performed on the activation word line.

14. The method of operating the memory according to claim 13, characterized in that, In the first mode, at the first moment, the first sub-activation signal is at an active level, and the second sub-activation signal is at an inactive level. At the second moment, the first sub-activation signal switches from the active level state to the inactive level state, and the second sub-activation signal switches from the inactive level state to the active level state. In the second mode, at the first moment, both the first sub-activation signal and the second sub-activation signal are in the invalid level state; At the second moment, the first sub-activation signal is still in the invalid level state, and the second sub-activation signal switches from the invalid level state to the valid level state; In the third mode, at the first moment, the first sub-activation signal is in the invalid level state, and the second sub-activation signal is in the valid level state.

15. The operating method of memory according to claim 13, wherein, The operation method further includes: In response to the first mode control signal, the updated count data stored in the count storage unit corresponding to the target word line among the multiple word lines is output in the first mode, or the active count value stored in the dynamic lookup table corresponding to the target word line among the multiple word lines is output in the second mode. When the number of count data or the number of active count values ​​is greater than or equal to a preset threshold, an alarm message is output.

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