Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device equipped with highly integrated memory cells and a method for manufacturing the same. [Solution] A method for manufacturing a semiconductor device includes the steps of: forming an alternating stack AS20 of sacrificial pad sheets 62 and inter-pad insulating layers 61 stacked vertically and spaced apart on the upper part of a substrate; forming preliminary contact holes penetrating the alternating stack; forming sacrificial plugs to fill the preliminary contact holes; performing a post-processing step on the sacrificial plugs to form sacrificial plug patterns 66A4, 66B3, 66C2 of different heights and sacrificial recesses H1, H2, H3 of different depths; forming a contact liner layer on the side walls of the sacrificial recesses; removing the sacrificial plug patterns to form contact holes; forming contact plugs to fill the contact holes; and removing the sacrificial pad sheets to form pad openings.

Claims

1. The steps include forming an alternating stack of sacrificial pad sheets and inter-pad insulating layers stacked vertically and spaced apart from each other on the upper part of the substrate, The steps include forming preliminary contact holes that penetrate the alternating stacks, The steps include forming a sacrificial plug to fill the aforementioned pre-contact hole, The steps include performing a post-processing step on the sacrificial plug to form sacrificial plug patterns of different heights and sacrificial recesses of different depths, The steps include forming a contact liner layer on the side wall of the sacrificial recess, The steps include removing the sacrificial plug pattern to form a contact hole, The steps include forming a contact plug that fills the contact hole, The steps include removing the sacrificial pad sheet to form a pad opening, The steps include forming pads in each of the aforementioned pad openings, A method for manufacturing a semiconductor device containing [a specific component].

2. The aforementioned post-processing step is: The steps include: performing an impurity doping process to form a sacrificial doping portion at the upper end of the sacrificial plug; The steps include: performing a recess process to remove the sacrificial doping portion; A method for manufacturing a semiconductor device according to claim 1, including the following:

3. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial plug includes undoped polysilicon.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial pad sheet includes single-crystal silicon.

5. The steps include forming a first alternating stack having horizontal conductive lines on the upper part of the substrate, The steps include: horizontally separating from the first alternating stack and forming a second alternating stack of sacrificial pad sheets and inter-pad insulating layers; The steps include forming preliminary contact holes that penetrate the second alternating stack, The steps include forming a sacrificial plug to fill the aforementioned pre-contact hole, The steps include performing a post-processing step on the sacrificial plug to form sacrificial plug patterns of different heights and sacrificial recesses of different depths, The steps include forming a contact liner layer on the side wall of the sacrificial recess, The steps include removing the sacrificial plug pattern to form a contact hole, The steps include forming a contact plug that fills the contact hole, The steps include removing the sacrificial pad sheet to form a pad opening that exposes the end of the horizontal conductive line, The step of forming pads in the pad openings, each connected to the horizontal conductive lines, A method for manufacturing a semiconductor device containing [a specific component].

6. The aforementioned post-processing step is: The steps include: performing an impurity doping process to form a sacrificial doping portion at the upper end of the sacrificial plug; The steps include: performing a recess process to remove the sacrificial doping portion; A method for manufacturing a semiconductor device according to claim 5, including the method described above.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the sacrificial plug includes undoped polysilicon.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the sacrificial pad sheet includes single-crystal silicon.

9. The step of forming a first alternating stack having the horizontal conductive line is: The steps include forming nanosheet target layers stacked vertically and spaced apart from each other on the upper part of the substrate, The steps include forming a flat plate-type sheet by trimming a first portion of the nanosheet target layer, The steps include forming a horizontal conductive line extending while surrounding the flat plate-type sheet, A method for manufacturing a semiconductor device according to claim 6, including the following:

10. After the step of forming the horizontal conductive line, The steps include forming a vertical conductive line that is commonly connected to the flat plate type sheet, The steps include horizontally recessing a second portion such as the nanosheet target layer to form a fan-shaped sheet, The steps include selectively growing contact nodes on each side surface of the fan-shaped sheet, The steps include forming a data storage element connected to each of the aforementioned contact nodes, A method for manufacturing a semiconductor device according to claim 9, including the following:

11. Substructure and A cell array region comprising a plurality of gate-all-around structures with horizontal conductive lines stacked vertically along a first direction from the upper part of the lower structure, A connecting region including a stack of multiple pads, each connected to the aforementioned horizontal conductive line and having the same horizontal length as each other, Multiple contact structures connected to the aforementioned pad, A semiconductor device equipped with a semiconductor device.

12. Each of the aforementioned contact structures is Multiple contact plugs that penetrate the stack of the aforementioned pads, The system comprises a contact spacer disposed on the side wall between the pad and the contact plug, The semiconductor device according to claim 11, wherein the pads are electrically connected to the contact plugs, etc., at each level.

13. The semiconductor device according to claim 11, wherein each of the horizontal conductive lines has an extension portion that extends to the connecting region, and the extension portion has an inner space.

14. The pad has an edge portion that is electrically connected to the extension portion of the horizontal conductive line, The semiconductor device according to claim 13, wherein the edge portion of the pad is located within the inner space of the extended portion of the horizontal conductive line.

15. The aforementioned cell array region is Multiple nanosheets arranged at the same horizontal level, A vertical conductive line connected to one side of the nanosheet, Data storage elements connected to the other side of the nanosheet, Furthermore, The semiconductor device according to claim 11, wherein each of the horizontal conductive lines has a structure that surrounds the nanosheets of the same horizontal level.

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