Chip, preparation method thereof, and electronic device

Abstract

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used to improve the storage density of embedded memories. The chip comprises a plurality of memory cell groups. A memory cell group comprises a first transistor and two memory cells. A memory cell comprises a second transistor and a storage element, and the first transistor and the second transistor each comprise an active structure, and the active structure of the first transistor is located between the active structures of the second transistors of the two memory cells. The active structure comprises a channel region, a first contact region and a second contact region. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell, and the second contact region of the first transistor is connected to the first contact region of the second transistor of the other memory cell; wherein in the same memory cell group, when the memory cells are in a working state, the first transistor is in an off state. The above chip is applied to an electronic device, thereby improving the performance of the electronic device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, and an electronic device. Background Technology

[0002] Compared to standalone memory, embedded memory offers faster access speeds and higher bandwidth, leading to its widespread adoption. Newer non-volatile memories, such as magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and resistive random access memory (RRAM), possess excellent miniaturization capabilities and are gradually becoming strong competitors in embedded non-volatile memory (eNVM).

[0003] For embedded memory, storage density and the area occupied by a single bit cell are key indicators of its competitiveness. How to reduce the area occupied by storage cells and increase storage density in embedded memory has become one of the most pressing problems to be solved in this field. Summary of the Invention

[0004] This application provides a chip and its fabrication method, as well as an electronic device, for reducing the area occupied by the storage unit and increasing the storage density of the embedded memory.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a chip is provided. The chip includes multiple memory cell groups; each memory cell group includes a first transistor and two memory cells.

[0007] A memory cell includes a second transistor and a memory element. Both the first and second transistors include active structures, each comprising a channel region, a first contact region, and a second contact region, with the channel region located between the first and second contact regions. Within the same memory cell, the first contact region of the second transistor is connected to the memory element. The active structure of the first transistor is located between the active structures of the second transistors in two memory cells, and the first contact region of the first transistor is connected to the first contact region of the second transistor in one memory cell, while the second contact region of the first transistor is connected to the first contact region of the second transistor in another memory cell. Within the same group of memory cells, when the memory cell is in an active state, the first transistor is in an off state.

[0008] The chip provided in this application includes multiple memory cell groups, each memory cell group including one first transistor and two memory cells. Within the same memory cell group, when a memory cell is in an active state, the first transistor is in an off state. In this way, the first transistor does not affect the operating state of the memory cell. Even if the active structure of the first transistor is located between the active structures of two second transistors, and the first contact area of ​​the first transistor is connected to the first contact area of ​​the second transistor in one memory cell, and the second contact area of ​​the first transistor is connected to the first contact area of ​​the second transistor in another memory cell, the charge carriers in the active structure of one second transistor will not be transferred to the active structure of the other second transistor through the active structure of the first transistor. During the operation of the memory cell, the first transistor effectively isolates the two second transistors located in the same memory cell group from each other.

[0009] In the chip provided in this application embodiment, the active structures of two second transistors corresponding to two memory cells in the same memory cell group are separated only by the active structure of a first transistor. By controlling the first transistor to be in a turned-off state, the two second transistors in the same memory cell group are isolated from each other. Compared with the related technology that uses a physical isolation structure to increase the distance between two adjacent memory cells to achieve insulation between adjacent memory cells, this application embodiment uses the first transistor to achieve electrical insulation between two memory cells in the same memory cell group. The size of the active structure of the first transistor is not limited by the physical insulation distance, and the size of the active structure can be smaller, thereby making the spacing between the two memory cells in the same memory cell group smaller, making the equivalent area occupied by a single memory cell smaller, and thus effectively increasing the density of memory cells in the chip.

[0010] In some embodiments, within the same group of memory cells, the active structures of the first transistor and the active structures of the second transistors of the two memory cells are arranged along a first direction. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell along the first direction, and the second contact region of the first transistor is also connected to the first contact region of the second transistor of another memory cell along the first direction.

[0011] In some embodiments, at least two memory cell groups are arranged along a first direction. In two adjacent memory cell groups along the first direction, the second contact regions of two second transistors located between two first transistors are connected.

[0012] In some embodiments, the first transistor further includes a first gate located on the channel region of the first transistor; the second transistor further includes a second gate located on the channel region of the second transistor. The chip also includes multiple transmission lines, including a first transmission line and a second transmission line. The first transmission line is connected to the first gate; the second transmission line is connected to the second gate, and in the same memory cell group, the second gate of the second transistor of one memory cell is connected to one second transmission line, and the second gate of the second transistor of another memory cell is connected to another second transmission line.

[0013] The first transmission line transmits a first control signal to the first transistor, and the second transmission line transmits a second control signal to the second transistor. The first control signal controls the first transistor to turn on and off, so that the first transistor is turned off when the memory cell is in an active state. The second control signal controls the second transistor to turn on and off, thereby enabling access to the corresponding memory cell.

[0014] In some embodiments, multiple transmission lines are arranged on the same layer, and all of the transmission lines extend along a second direction and are arranged along a first direction. In the first direction, the multiple transmission lines are arranged at equal intervals. The first direction intersects the second direction. In this embodiment, the multiple transmission lines are arranged on the same layer, allowing multiple transmission lines to be fabricated simultaneously during chip fabrication, which simplifies the fabrication process and improves fabrication efficiency. The equidistant arrangement of multiple transmission lines helps reduce the difficulty of fabrication processes (e.g., photolithography), enabling the fabrication process to be applicable to advanced process nodes.

[0015] In some embodiments, any three adjacent transmission lines in the first direction include one first transmission line and two second transmission lines. Thus, the arrangement of the first and second transmission lines in the first direction follows the same pattern as the arrangement of the first and second transistors, facilitating the connection between the first transmission line and the first gate of the first transistor, and also facilitating the connection between the second transmission line and the second gate of the second transistor.

[0016] In some embodiments, the size of the storage cell in the first direction is 1.5 times the spacing between two adjacent transmission lines in the first direction.

[0017] In some embodiments, the chip includes a circuit structure layer and an interconnect structure layer. A first transistor and a second transistor are located in the circuit structure layer. The interconnect structure layer is located on one side of the circuit structure layer. The interconnect structure layer includes a plurality of conductive transport layers. The plurality of conductive transport layers are stacked along the thickness direction of the chip. A storage element is located between the first contact region of the second transistor and the conductive transport layer.

[0018] In some embodiments, the plurality of conductive transport layers include interconnection layers and interconnection contact layers. The interconnection contact layers include a plurality of conductive patterns and a plurality of conductive pillars. The conductive patterns in two adjacent interconnection layers are connected by at least one conductive pillar. The storage element is located between the first contact region of the second transistor and the interconnection layer, or the storage element is located between the first contact region of the second transistor and the interconnection contact layer.

[0019] In some embodiments, the storage element includes a first electrode and a second electrode disposed opposite to each other, the first electrode being in contact with a first contact area of ​​a second transistor, and the second electrode being in contact with a conductive transport layer.

[0020] In some embodiments, the chip further includes a transition structure layer located between the circuit structure layer and the interconnect structure layer. The transition structure layer includes a first dielectric layer, a second dielectric layer, and a first transition structure. The first dielectric layer is located on the side of the second dielectric layer near the circuit structure layer. The first transition structure penetrates the first dielectric layer and is in contact with the first contact area of ​​the second transistor.

[0021] The storage element extends through the second dielectric layer and includes a first electrode and a second electrode disposed opposite to each other. The first electrode is in contact with the first transition structure, and the second electrode is in contact with the conductive transport layer.

[0022] In some embodiments, the storage element includes a first electrode and a second electrode disposed opposite to each other, the first electrode being in contact with one of a plurality of conductive transport layers and the second electrode being in contact with another of the plurality of conductive transport layers.

[0023] In some embodiments, the chip includes a transition structure layer located between a circuit structure layer and an interconnect structure layer. The transition structure layer includes a first dielectric layer, a second dielectric layer, a second transition structure, and a first contact post. The first dielectric layer is located on the side of the second dielectric layer closest to the circuit structure layer. The second transition structure penetrates the first dielectric layer, and the first contact post penetrates the second dielectric layer. One end of the second transition structure contacts a first contact area of ​​the second transistor, and the other end of the second transition structure contacts the first contact post. A first electrode is connected to the first contact area of ​​the second transistor through a conductive transport layer, the first contact post, and the second transition structure.

[0024] In some embodiments, the transition structure layer further includes a third transition structure, a second contact post, a third contact post, and a fourth contact post. The third transition structure penetrates the first dielectric layer, and the second, third, and fourth contact posts all penetrate the second dielectric layer. One end of the third transition structure is in contact with the second contact post, and the other end of the third transition structure is in contact with the second contact region of the second transistor. The third contact post is in contact with the first gate of the first transistor, and the fourth contact post is in contact with the second gate of the second transistor.

[0025] In some embodiments, the storage element includes a first electrode, a second electrode, and an insulating layer, wherein the first electrode, the insulating layer, and the second electrode are stacked along the thickness direction of the chip; the first electrode is connected to a first contact area of ​​the second transistor, and the second electrode is located on the side of the first electrode away from the second transistor.

[0026] In some embodiments, the storage element includes a first electrode, a second electrode, and an insulating layer. The first electrode is connected to a first contact area of ​​a second transistor. The first electrode forms a first groove. The insulating layer covers the bottom and sidewalls of the first groove and forms a second groove. The second electrode covers the bottom and sidewalls of the second groove.

[0027] In some embodiments, the active structures of both the first transistor and the second transistor are fin-shaped and extend along a first direction. The active structures in a plurality of memory cell groups arranged along the first direction are sequentially connected to form fins.

[0028] In some embodiments, the chip further includes logic circuitry, which includes logic transistors. Both the first transistor and the second transistor are disposed on the same layer as the logic transistors.

[0029] Secondly, a method for fabricating a chip is provided. The chip includes multiple memory cell groups, each memory cell group including a first transistor and two memory cells. The fabrication method includes:

[0030] Multiple active structures are formed, including a channel region, a first contact region, and a second contact region, with the channel region located between the first contact region and the second contact region.

[0031] Multiple first gates and multiple second gates are formed; the multiple first gates and multiple second gates are respectively located on the channel regions of multiple active structures; the multiple first gates and multiple active structures form multiple first transistors, and the multiple second gates and multiple active structures form multiple second transistors; the active structure of the first transistor is located between the active structures of two second transistors; the first contact region of the first transistor is connected to the first contact region of one second transistor, and the second contact region of the first transistor is connected to the first contact region of another second transistor.

[0032] Multiple storage elements are formed; the storage elements are connected to the first contact area of ​​the second transistor; the storage elements and the second transistor form a storage cell.

[0033] Thirdly, an electronic device is provided. The electronic device includes a circuit board and a chip as described in any of the above embodiments, the chip being located on the circuit board and electrically connected to the circuit board.

[0034] The technical effects of any of the design methods in the second and third aspects can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0036] Figure 1 An architectural diagram of an electronic device provided in an embodiment of this application;

[0037] Figure 2 An architecture diagram of a memory provided for an embodiment of this application;

[0038] Figure 3 A circuit structure diagram of a storage array provided in an embodiment of this application;

[0039] Figure 4 A top view schematic diagram of a chip provided in an embodiment of this application;

[0040] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the chip at point M-M';

[0041] Figure 6 for Figure 4The diagram shows a cross-sectional view of the chip at N-N'.

[0042] Figure 7 A circuit structure diagram of a chip provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0045] Figure 10 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0046] Figure 11 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0048] Figure 13 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0049] Figure 14 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0050] Figure 15 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0051] Figure 16 This application provides a flowchart of chip fabrication.

[0052] Figure 17 for Figure 16 A top view of the chip during fabrication in step S100;

[0053] Figure 18 for Figure 16 A top view of the chip fabricated during step S200;

[0054] Figure 19 This is a top view of the chip during the fabrication process corresponding to step S400;

[0055] Figure 20 for Figure 19 The diagram shows a cross-sectional view of the chip at I-I'.

[0056] Figure 21 The diagram shows the structure of the first and second masks, as well as the distribution of the transition structure.

[0057] Figure 22A This is a top view of the chip during the fabrication process corresponding to step S500;

[0058] Figure 22B for Figure 22A The diagram shows a cross-sectional view of the chip at E-E'.

[0059] Figure 23 This is a schematic diagram of the chip structure during the fabrication process corresponding to step S310;

[0060] Figure 24 This is a top view of the chip during the fabrication process corresponding to step S320;

[0061] Figure 25 for Figure 24 The diagram shows a cross-sectional view of the chip at F-F'.

[0062] Figure 26 This is a schematic diagram of the chip structure during the fabrication process corresponding to step S330;

[0063] Figure 27 This is a top view of the chip during the fabrication process corresponding to step S340;

[0064] Figure 28 for Figure 27 The diagram shows a cross-sectional view of the chip at J-J'.

[0065] Figure 29 Another chip fabrication flowchart is provided for embodiments of this application. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0067] In the following embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] In the embodiments of this application, "upper", "lower", "left" and "right" are not limited to the orientation of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0069] In this application, unless the context otherwise requires, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to," throughout the specification and claims. In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0070] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0071] This application provides an electronic device, which may include consumer electronics, home electronics, automotive electronics, financial electronics, servers, workstations, etc. Consumer electronics include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearables (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics include smart door locks, televisions, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. Automotive electronics include car navigation systems, car DVDs, etc. Financial electronics include ATMs and self-service electronic devices, etc.

[0072] Figure 1 This is an architectural diagram of an electronic device provided as an embodiment of this application. (For example...) Figure 1As shown, the electronic device 100 includes a bus 110 and a system-on-chip (SoC) 120 connected to the bus 110. The SoC 120 can be used to process data, such as processing application data, processing image data, and caching temporary data.

[0073] In one possible implementation, SoC 120 may include an application processor (AP) 121 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first RAM 123 for caching high-speed data.

[0074] The first RAM 123 can be static random access memory (SRAM) or embedded flash (eflash), etc. The AP 121, GPU 122 and the first RAM 123 can be integrated into a single die, or they can be disposed in multiple dies.

[0075] The electronic device 100 may also include a second RAM 130 connected to the SOC 120 via a bus 110. The second RAM 130 may be Dynamic Random Access Memory (DRAM). The second RAM 130 can be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is typically larger than that of the first RAM 123, but its read speed is typically slower than that of the first RAM 123.

[0076] In addition, the electronic device 100 may also include a communication chip 140 and a power management chip 150 connected to the SOC 120 via a bus 110. The communication chip 140 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 150 may be used to supply power to other chips.

[0077] In one possible implementation, the SoC 120 and the second RAM 130 can be packaged in a single package structure, such as 2.5D or 3D packaging, to achieve faster inter-chip data transfer rates and reduce chip footprint.

[0078] The electronic device 100 may also include a circuit board, to which the aforementioned SoC 120, second RAM 130, communication chip 140, and power management chip 150 can be electrically connected. The circuit board may be, for example, a flexible printed circuit board (FPC).

[0079] Figure 2 This is an architectural diagram of a memory 200 provided in an embodiment of this application. The memory can be applied to the above-mentioned electronic device as a first RAM 123 or as a second RAM 130.

[0080] like Figure 2 As shown, the memory 200 includes a memory array 210 and a controller 220. The controller 220 is connected to the memory array 210 and is used to access the memory array 210 and control the read and write operations of the memory array 210.

[0081] Figure 2 The illustrated memory array 210 and controller 220 have various possible package structures. In some examples, the memory array 210 and controller 220 are two independent chips, each integrated on a substrate. In still other examples, the memory array 210 and controller 220 can be two independent chips stacked together. For example, the memory array 210 and controller 220 can be connected via through-silicon vias (TSVs) or redistribution layers (RDLs). In yet other examples, the memory array 210 and controller 220 can also be integrated into the same chip.

[0082] Figure 3 This is a circuit diagram of a memory array provided in an embodiment of this application. Figure 3 As shown, in some embodiments, the storage array 210 may include a plurality of arrayed storage cells 211, wherein each storage cell 211 may be used to store 1 bit or more bits of data.

[0083] For example, such as Figure 3 As shown, the memory cell 211 includes a transistor T and a capacitor C connected together. The memory cell 211 may include one or more transistors, or one or more capacitors C. Figure 3 The example given is a memory cell 211 comprising a transistor T and a capacitor C connected together.

[0084] The storage array 210 may also include electrode lines such as word lines (WL) and bit lines (BL). Each storage cell 211 can be electrically connected to a corresponding word line (WL) and bit line (BL). Different storage cells 211 can be electrically connected via word lines (WL) or bit lines (BL). One or more of the aforementioned word lines (WL) and bit lines (BL) are used to select the storage cell 211 in the storage array 210 that is waiting to be read or written by receiving a control level output from the control circuit, thereby realizing data read and write operations.

[0085] For example, controller 220 may include Figure 2 One or more of the following circuit structures are shown: decoder 221, driver 222, timing controller 223, buffer 224, or input / output driver 225.

[0086] The decoder 221 decodes the received address to determine the memory cell 211 to be accessed. The driver 222 controls the signal line level based on the decoding result generated by the decoder 221, thereby enabling access to the specified memory cell 211. The buffer 224 buffers the read data, for example, using a first-in-first-out (FIFO) buffering method. The timing controller 223 controls the timing of the buffer 224 and controls the driver 222 to drive the signal lines in the memory array 210. The input / output driver 225 drives the transmission signals, such as the received data signal and the data signal to be sent, enabling the data signal to be transmitted over long distances.

[0087] The aforementioned memory array 210, decoder 221, driver 222, timing controller 223, buffer 224, and input / output driver 225 can be integrated into one chip or into multiple chips respectively.

[0088] The memory 200 involved in the embodiments of this application can be dynamic random access memory (DRAM), such as embedded dynamic random access memory (eDRAM). Alternatively, the memory 200 involved in the embodiments of this application can be non-volatile memory, such as magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), flash memory, etc. For example, it can be embedded magnetoresistive random access memory, embedded ferroelectric random access memory, embedded resistive random access memory, or embedded flash memory.

[0089] Compared to standalone memory, embedded memory offers faster access speeds and higher bandwidth, leading to its widespread adoption. Storage density and the area occupied by storage cells are crucial indicators of the competitiveness of embedded memory. Improving the storage density and reducing the area occupied by storage cells is one of the pressing problems to be solved in this field.

[0090] This application provides a chip that may include an embedded memory and logic circuits for implementing other functions. For example, the chip may include an embedded memory and a central processing unit (CPU), with the embedded memory and CPU integrated on the same substrate.

[0091] Figure 4 This is a partial top view of a chip provided in an embodiment of this application. Figure 5 for Figure 4 The diagram shows a cross-sectional view of chip 300 at point M-M'. Figure 6 for Figure 4 The diagram shows a cross-sectional view of chip 300 at point N-N'. Figure 7 This is a circuit structure diagram of a chip 300 provided in an embodiment of this application.

[0092] like Figure 4 and Figure 5 As shown, chip 300 includes multiple memory cell groups 310, each memory cell group 310 including a first transistor 301 and two memory cells 302. Each memory cell 302 includes a second transistor 303 and a memory element 304.

[0093] In some examples, memory cell 302 may include a second transistor 303 and a memory element 304. In other examples, memory cell 302 may include a second transistor 303 and multiple memory elements 304.

[0094] Both the first transistor 301 and the second transistor 303 include an active area (AA). The active area (AA) of both transistors 301 and 303 includes a channel region A1, a first contact region A2, and a second contact region A3. The channel region A1 is located between the first contact region A2 and the second contact region A3. In the same memory cell 302, the first contact region A2 of the second transistor 303 is connected to the memory element 304.

[0095] In this configuration, one of the first contact region A2 and the second contact region A3 serves as the source region of the first transistor 301 or the second transistor 303, and the other of the first contact region A2 and the second contact region A3 serves as the drain region of the first transistor 301 or the second transistor 303.

[0096] The active structure AA of the first transistor 301 is located between the active structures AA of the second transistors 303 of the two memory cells 302, and the first contact area A2 of the first transistor 301 is connected to the first contact area A2 of the second transistor 303 of one memory cell 302, and the second contact area A3 of the first transistor 301 is connected to the first contact area A2 of the second transistor 303 of the other memory cell 302. When the memory cell 302 is in the active state within the same memory cell group 310, the first transistor 301 is in the off state.

[0097] In some examples, such as Figure 4 As shown, both the first transistor 301 and the second transistor 303 can be fin field-effect transistors (FinFETs). In this case, the active structure AA of the first transistor 301 and the second transistor 303 is fin-shaped.

[0098] It is understandable that, in addition to fin field-effect transistors, the first transistor 301 and the second transistor 303 can also be planar metal-oxide-semiconductor (MOS) field-effect transistors (FETs), or gate-all-around (GAA) transistors. Of course, the structural types of the first transistor 301 and the second transistor 303 are not limited to these.

[0099] In some examples, such as Figure 7 As shown, both the first transistor 301 and the second transistor 303 can be NMOS (N-metal-oxide-semiconductor) transistors. In other examples, both the first transistor 301 and the second transistor 303 can be PMOS (P-metal-oxide-semiconductor) transistors. In still other examples, one of the first transistor 301 and the second transistor 303 is an NMOS transistor, and the other is a PMOS transistor.

[0100] In some examples, chip 300 includes an embedded ferroelectric random access memory (RAM). In this case, storage element 304 can be a ferroelectric capacitor. In other examples, chip 300 includes an embedded resistive random access memory (RAM). In this case, storage element 304 can be a resistive switching element. In still other examples, chip 300 includes an embedded magnetoresistive random access memory (MRRAM). In this case, storage element 304 can be a magnetic tunnel junction (MTJ). In still other examples, chip 300 includes an embedded dynamic random access memory (DRAM). In this case, storage element 304 can be a conventional capacitor.

[0101] The first transistor 301 also includes a first gate. In the case that the first transistor 301 is an NMOS (N-metal-oxide-semiconductor) transistor, in order to put the first transistor 301 in the off state, the first gate can receive a low-level voltage, for example, the first gate can be connected to the ground terminal GND. The ground terminal GND is used to provide a 0V voltage.

[0102] When the first transistor 301 is a PMOS (P-metal-oxide-semiconductor) transistor, in order to put the first transistor 301 in the off state, the first gate can receive a high-level voltage, such as being connected to a power supply voltage terminal in the chip. The power supply voltage terminal can provide voltages such as 1.5V, 2V, and 7V.

[0103] The first transistor 301 can be either a normally open transistor or a normally closed transistor.

[0104] "Storage cell 302 is in the working state," meaning the storage cell is in the state of storing information for writing and reading, at which time the second transistor 303 in storage cell 302 is in the turned-on state. It can be understood that when both storage cells 302 in the storage cell group 310 are in the non-working state, the second transistors 303 in both storage cells 302 are in the turned-off state, and even if the first transistor 301 is in the turned-on state, the two second transistors will not affect each other. After the first transistor 301 is turned on, it can also be used to implement some other functions, such as the function of periodically discharging the charge within the storage cell.

[0105] It is understandable that, except when the memory cell 302 in the same memory cell group 310 is in an active state and the first transistor 301 is in an off state, the first transistor 301 can also be in an off state when the memory cell 302 in different memory cell groups 310 is in an active state. That is, when any memory cell in the chip 300 is in an active state, all other first transistors in the chip 300 except the first transistor connected to that memory cell can also be in an off state.

[0106] The chip 300 provided in this embodiment includes multiple memory cell groups 310, each memory cell group 310 including one first transistor 301 and two memory cells 302. In the same memory cell group 310, when a memory cell 302 is in an active state, the first transistor 301 is in an off state. In this way, the first transistor 301 does not affect the working state of the memory cell 302. Even if the active structure AA of the first transistor 301 is located between the active structures AA of two second transistors 303, and the first contact area A2 of the first transistor 301 is connected to the first contact area A2 of the second transistor 303 in one memory cell 302, and the second contact area A3 of the first transistor 301 is connected to the first contact area A2 of the second transistor 303 in another memory cell 302, the charge carriers in the active structure AA of one second transistor 303 will not be transferred to the active structure AA of the other second transistor 303. During the operation of the memory cell, the first transistor 301 can effectively isolate the two second transistors 303 located in the same memory cell group 310.

[0107] In the chip 300 provided in this application embodiment, the active structures AA of the two second transistors 303 corresponding to two memory cells 302 in the same memory cell group 310 are separated only by the active structure AA of the first transistor 301. By controlling the first transistor 301 to be in the off state, the two second transistors 303 in the same memory cell group 310 are isolated from each other. Compared with the related technology, which uses a physical isolation structure to increase the distance between two adjacent memory cells to achieve insulation between two adjacent memory cells, this application embodiment uses the first transistor 301 to achieve electrical insulation between two memory cells 302 in the same memory cell group 310. The size of the active structure AA of the first transistor 301 is not limited by the physical insulation distance, and the size of the active structure AA can be smaller. This allows for a smaller spacing between the two memory cells 302 in the same memory cell group 310, resulting in a smaller equivalent area occupied by a single memory cell 302, thereby effectively increasing the density of memory cells 302 in the chip 300.

[0108] In some embodiments, such as Figure 5 As shown, in the same memory cell group 310, the active structure AA of the first transistor 301 and the active structures AA of the second transistors 303 of the two memory cells 302 are arranged along the first direction X. The first contact area A2 of the first transistor 301 is connected to the first contact area A2 of the second transistor 303 of one memory cell 302 along the first direction X, and the second contact area A3 of the first transistor 301 is also connected to the first contact area A2 of the second transistor 303 of the other memory cell 302 along the first direction X.

[0109] In some embodiments, such as Figure 4 and Figure 6 As shown, at least two memory cell groups 310 are arranged along a first direction X. In two adjacent memory cell groups 310 along the first direction X, the second contact areas A3 of the two second transistors 303 located between the two first transistors 301 are connected. In this way, the spacing between two adjacent memory cells 302 in two adjacent memory cell groups 310 is zero, thereby further reducing the occupied area of ​​the memory cells 302 and increasing the storage density of the chip 300.

[0110] In some examples, such as Figure 4 As shown, the multiple memory cell groups 310 in the chip 300 can be arranged in an array. Multiple memory cell groups 310 located in the same row can be arranged along the first direction X, and multiple memory cell groups 310 located in the same column can be arranged along the second direction Y. Figure 4 Four storage cell groups 310 are shown among multiple storage cell groups 310, arranged in two rows and two columns.

[0111] It is understood that the active structures AA of the second transistors 303 in two adjacent memory cell groups 310 located in the same column are spaced apart, and the active structures AA of the first transistors 301 in two adjacent memory cell groups 310 located in the same column are also spaced apart.

[0112] like Figure 4 As shown, when both the first transistor 301 and the second transistor 303 are fin field-effect transistors, the active structures of both transistors are fin-shaped and extend along the first direction X. The active structures AA in the multiple memory cell groups 310 arranged along the first direction X are sequentially connected to form fins. The chip 300 may include multiple fins, all extending along the first direction X and arranged along the second direction Y.

[0113] The active structures AA in multiple memory cell groups 310 arranged along the first direction X are sequentially connected to form fins. At this time, the active structures AA in the multiple memory cell groups 310 arranged along the first direction X are interconnected to form an integral structure. In the fabrication process of the memory array, fins can be formed first, and then different parts of the fins can be processed using processes such as doping and epitaxial growth to obtain the active structures AA of the first transistor 301 and the second transistor 303 of the multiple memory cell groups 310.

[0114] like Figure 4 As shown, both the first transistor 301 and the second transistor 303 are 1-fin devices, that is, along the width direction of the fin (the second direction Y), the number of fins in the first transistor 301 and the second transistor 303 is 1.

[0115] At this point, in the width direction (second direction Y), the spacing d3 between the active structures AA of two adjacent second transistors (or first transistors) is greater than the minimum fin pitch but less than twice the minimum fin pitch. That is, the size of the memory cell 302 in the second direction Y is greater than the minimum fin pitch but less than twice the minimum fin pitch. Here, "minimum fin pitch" refers to the minimum fin pitch that can be fabricated at the corresponding process node.

[0116] Compared to a scheme where both the first and second transistors are 2-fin devices and the size of the memory cell in the second direction is greater than or equal to twice the minimum fin spacing, the first transistor 301 and the second transistor 303 are both 1-fin devices. This allows for a smaller size of the memory cell (memory cell group) in the second direction, effectively reducing the size of the memory cell group 310 (or memory cell 302) in the second direction. Here, "both the first and second transistors are 2-fin devices" means that along the width direction of the fins, the number of fins in the first and second transistors is two.

[0117] In some embodiments, such as Figure 4 and Figure 5 As shown, the first transistor 301 further includes a first gate G1, which is located on the channel region A1 of the first transistor 301. The second transistor 303 further includes a second gate G2, which is located on the channel region A1 of the second transistor 303.

[0118] It is understandable that although the first gate G1 is located on the channel region A1 of the first transistor 301, the first gate G1 is insulated from the channel region A1. Similarly, although the second gate G2 is located on the channel region A1 of the second transistor 303, the second gate G2 is insulated from the channel region A1. To insulate the first gate G1 from the channel region A1, a gate dielectric layer can be disposed between the first gate G1 and the channel region A1. Likewise, to insulate the second gate G2 from the channel region A1, a gate dielectric layer can also be disposed between the second gate G2 and the channel region A1. Figure 5 The gate dielectric layer is not shown in the other figures.

[0119] Chip 300 also includes multiple transmission lines L, including a first transmission line GL1 and a second transmission line GL2. The first transmission line GL1 is connected to a first gate G1. The second transmission line GL2 is connected to a second gate G2, and in the same memory cell group 310, the second gate G2 of the second transistor 303 of one memory cell 302 is connected to one second transmission line GL2, and the second gate G2 of the second transistor 303 of another memory cell 302 is connected to another second transmission line GL2.

[0120] In some examples, when the first transistor 301 is an NMOS transistor, the first transmission line GL1 can be connected to a low-level voltage terminal to receive a low-level voltage, so that the first transistor 301 is always kept off, thereby effectively isolating two adjacent memory cells 302 whether the memory cell 302 is in the working state or not.

[0121] In other examples, when the first transistor 301 is a PMOS transistor, the first transmission line GL1 can be connected to a high-level voltage terminal to receive a high-level voltage, so that the first transistor 301 is always kept off, thereby effectively isolating two adjacent memory cells 302 whether the memory cell 302 is in the working state or not.

[0122] In some other examples, regardless of whether the first transistor 301 is an NMOS transistor or not, the first transmission line GL1 can receive low-level voltage and high-level voltage, so that when the memory cell 302 is in the working state, the first transistor 301 is in the off state, and when the memory cell 302 is in the non-working state, the first transistor 301 is in the on state.

[0123] It is understandable that, in order to facilitate the separate control of the first transistor 301 and the memory cell 302, the first transmission line GL1 and the second transmission line GL2 are connected to different ports.

[0124] When multiple memory cell groups 310 in chip 300 are arranged in an array, the first gate G1 of multiple memory cell groups 310 located in the same column is connected to the same first transmission line GL1, and the multiple memory cell groups 310 located in the same column correspond to two second transmission lines GL2. One of the two second transmission lines GL2 is connected to the second gate G2 of a memory cell 302, and the other of the two second transmission lines GL2 is connected to the second gate G2 of another memory cell 302.

[0125] In some examples, the number of second transmission lines GL2 is twice the number of first transmission lines GL1.

[0126] In this embodiment, the first transmission line GL1 can transmit a first control signal to the first transistor 301, and the second transmission line GL2 can transmit a second control signal to the second transistor 303. The first control signal is used to control the opening and closing of the first transistor 301, so that the first transistor 301 is turned off when the memory cell 302 is in the working state. The second control signal is used to control the opening and closing of the second transistor 303 to realize access to the corresponding memory cell.

[0127] In some embodiments, such as Figure 4 and Figure 5 As shown, multiple transmission lines L are arranged on the same layer, all extending along the second direction Y and distributed along the first direction X. In the first direction X, the multiple transmission lines L are arranged at equal intervals. For example, as... Figure 4 As shown, in the arrangement direction of multiple transmission lines L (i.e., the first direction X), the spacing between any two adjacent transmission lines L is d1. Figure 4 As shown, the spacing between adjacent first transmission line GL1 and second transmission line GL2 is d1, and the spacing between two adjacent second transmission lines GL2 is also d1.

[0128] In this embodiment, multiple transmission lines L are arranged on the same layer, allowing multiple transmission lines L to be fabricated simultaneously during the fabrication of chip 300. This simplifies the fabrication process and improves fabrication efficiency. The equidistant arrangement of multiple transmission lines L helps reduce the difficulty of the fabrication process (e.g., photolithography), enabling the fabrication process to be applicable to advanced process nodes (e.g., 1X process).

[0129] When multiple transmission lines L are arranged on the same layer and are equidistantly distributed in the first direction X, the size of the storage cell 302 in the first direction X can be 1.5 times the spacing between two adjacent transmission lines L in the first direction X. Compared with the related art, which uses a physical partition structure to separate two adjacent storage cells 302 in the first direction X, the spacing between two connected transmission lines L (or the spacing between two adjacent second transmission lines) in this embodiment is smaller, and the size of the storage cell 302 in the first direction X can also be smaller.

[0130] Among them, see Figure 5 The size of the storage cell 302 in the first direction X is the sum of the size of the second transistor 303 in the first direction X and the size of the storage element 304 in the first direction X.

[0131] In some examples, where multiple transmission lines L are arranged on the same layer and are equidistantly arranged in the first direction X, the size of the storage cell group 310 in the first direction X can be three times the spacing between two adjacent transmission lines L in the first direction X.

[0132] In some examples, multiple transmission lines L can have the same width. That is, the width of the first transmission line GL1 is the same as the width of the second transmission line GL2.

[0133] The "width" refers to the dimension of the multiple transmission lines L in the arrangement direction (first direction X). For example, as shown... Figure 4 As shown, the width of multiple transmission lines L can all be d2. That is, the width of the first transmission line GL1 and the width of the second transmission line GL2 are both d2.

[0134] In this embodiment of the application, there are no restrictions on the specific value of the spacing d1 between the multiple transmission lines L, or the specific value of the width d2 of the multiple transmission lines L. These values ​​can be set according to actual needs.

[0135] In some examples, multiple first transmission lines GL1 can be formed by sequentially connecting the first gates G1 of first transistors 301 located in the same column. Multiple second transmission lines GL2 can be formed by sequentially connecting the second gates G2 of second transistors 303 located in the same column. That is, the portions of multiple first transmission lines GL1 that face the channel region A1 of the first transistor 301 serve as the first gates G1 of the first transistor 301, and the portions of multiple second transmission lines GL2 that face the channel region A1 of the second transistor 303 serve as the second gates G2 of the second transistor 303.

[0136] When the first transmission line GL1 is formed by sequentially connecting the first gates G1 of the first transistors 301 located in the same column, and the second transmission line GL2 is formed by sequentially connecting the second gates G2 of the second transistors 303 located in the same column, as follows: Figure 4 As shown, a storage cell group 310 corresponds to three transmission lines, wherein the first transmission line GL1 is located between two second transmission lines GL2.

[0137] In other examples, the first transmission line GL1 and the first gate G1 are configured independently, and the second transmission line GL2 and the second gate G2 are configured independently. In this case, in order to reduce the area occupied by the memory cell, the first transmission line GL1 and the first gate G1 can be located on different layers, and the second transmission line GL2 and the second gate G2 can be located on different layers.

[0138] In some embodiments, such as Figure 4 As shown, any three adjacent transmission lines L in the first direction X may include one first transmission line GL1 and two second transmission lines GL2.

[0139] In this way, the arrangement of the first transmission line and the second transmission line in the first direction X is the same as the arrangement of the first transistor and the second transistor, which facilitates the connection of the first transmission line GL1 to the first gate G1 of the first transistor 301, and also facilitates the connection between the second transmission line GL2 and the second gate G2 of the second transistor 303.

[0140] In some embodiments, such as Figure 4 , Figure 5 and Figure 6 As shown, the storage element 304 includes a first electrode 305 and a second electrode 306 disposed opposite to each other, and an insulating layer 307 located between the first electrode 305 and the second electrode 306. The first electrode 305 is connected to the first contact area A2 of the second transistor 303.

[0141] In some examples, such as Figure 6As shown, the first electrode 305 forms a first groove U1, the insulating layer 307 covers the bottom and side walls of the first groove U1, and forms a second groove U2, and the second electrode 306 covers the bottom and side walls of the second groove U2. At this time, the facing area between the first electrode 305 and the second electrode 306 is relatively large, the contact area between the first electrode 305 and the insulating layer 307 is relatively large, and the contact area between the second electrode 306 and the insulating layer 307 is also relatively large. When the storage element 304 is a capacitor, the capacitance value of the storage element 304 is relatively large.

[0142] In some examples, such as Figure 6 As shown, the insulating layer 307 can not only be located in the first groove U1, but can also extend to the outside of the first groove U1.

[0143] In other examples, such as Figure 8 As shown, the insulating layer 307 may be located only in the first groove U1.

[0144] In some examples, where the second electrode 306 covers the bottom and side walls of the second groove U2, the second electrode 306 can enclose a third groove. In other examples, such as Figure 6 As shown, when the second electrode 306 covers the bottom wall and side wall of the second groove U2, the second electrode 306 can fill the second groove U2 completely.

[0145] In some possible implementations, such as Figure 6 and Figure 8 As shown, the first electrode 305 may include a first portion 3051 and a second portion 3052 connected together. The first portion 3051 is located on the side of the second portion 3052 closer to the second transistor 303. There is an included angle at the connection between the first portion 3051 and the second portion 3052, which is greater than or equal to 90 degrees and less than 180 degrees. The first portion 3051 serves as the bottom wall of the first groove U1, and the second portion 3052 serves as the side wall of the first groove U1.

[0146] In another possible implementation, such as Figure 9 As shown, the first electrode 305 may further include a third portion 3053. The third portion 3053 is connected to the end of the second portion 3052 away from the first portion 3051, and the third portion 3053 is parallel to the first portion 3051. In this case, the insulating layer 307 can cover not only the first portion 3051 and the second portion 3052, but also the third portion 3053.

[0147] Figure 10 This is a schematic diagram of another chip 300 provided in an embodiment of this application. In some examples, such as... Figure 10As shown, the first electrode 305, the insulating layer 307, and the second electrode 306 are stacked along the thickness direction Z of the chip 300, with the second electrode 306 located on the side of the first electrode 305 away from the second transistor 303. In this configuration, the storage element 304 has a simple structure and is easy to fabricate.

[0148] The above text, combined with the appendix Figures 4 to 10 The structure and shape of the first transistor 301, the second transistor 303, and the storage element 304 in the storage cell group 310 have been described below, in conjunction with the appendix. Figure 6 , Figure 11 , Figure 12 and Figure 13 The positions of the first transistor 301, the second transistor 303, and the storage element 304 in the storage cell group are described.

[0149] In some embodiments, such as Figure 6 , Figures 8 to 15 As shown, chip 300 includes a circuit structure layer 320 and an interconnect structure layer 330. The interconnect structure layer 330 is located on one side of the circuit structure layer 320. The interconnect structure layer 330 includes a plurality of conductive transport layers 33, which are stacked along the thickness direction Z of chip 300. A first transistor 301 (reference) Figure 5 Both the first contact area A2 of the second transistor 303 and the second transistor 303 are located in the circuit structure layer 320. The storage element 304 is located between the first contact area A2 of the second transistor 303 and the conductive transport layer 33.

[0150] In some examples, the circuit structure layer 320 can be fabricated using a front-end of line (FEOL) process, while the interconnect structure 330 can be fabricated using a back-end of line (BEOL) process. The front-end process is primarily used to fabricate devices such as transistors, capacitors, and resistors on the substrate. The back-end process mainly involves fabricating wiring, which connects multiple devices fabricated in the front-end process to form a complete circuit.

[0151] In some embodiments, such as Figure 6 , Figures 8 to 15 As shown, the aforementioned plurality of conductive transport layers 33 may include interconnection layers 331 and interconnection contact layers 332. Interconnection layers 331 include a plurality of conductive patterns 3311, and interconnection contact layers 332 may include a plurality of conductive pillars 3321. The conductive patterns 3311 in adjacent interconnection layers 331 are connected by at least one conductive pillar 3321. The storage element 304 is located between the first contact area A2 of the second transistor 303 and the interconnection layers 331, or the storage element 304 is located between the first contact area A2 of the second transistor 303 and the interconnection contact layers 332.

[0152] It is understood that multiple conductive patterns 3311 located in the same interconnect layer 331 are spaced apart. Multiple conductive pillars 3321 located in the same interconnect contact layer 332 are spaced apart.

[0153] For example, the conductive pattern 3311 can be a metal trace.

[0154] In this embodiment, the number of interconnect routing layers 331 in the interconnect structure layer 330 is not limited, and can be designed according to actual needs. Figure 6 , Figure 11 and Figure 12 The diagram illustrates an interconnect structure layer 330 comprising two interconnect routing layers 331 and one interconnect contact layer 332. Of the two interconnect routing layers 331, the one closer to the circuit structure layer 320 is designated as the first interconnect routing layer 331a, and the one farther from the circuit structure layer 320 is designated as the second interconnect routing layer 331b. Figure 13 The interconnect structure layer 330 is illustrated as an example, comprising three interconnect routing layers 331 and two interconnect contact layers 332. Along the direction away from the circuit structure layer 320, the three interconnect routing layers 331 are sequentially referred to as the first interconnect routing layer 331a, the second interconnect routing layer 331b, and the third interconnect routing layer 331c.

[0155] In some examples, such as Figure 6 As shown, when the memory cell group 310 is arranged in an array, the first gates G1 of multiple first transistors 301 located in the same column are connected to form a first transmission line GL1, and the second gates G2 of multiple second transistors 303 located in the same column are connected to form a second transmission line GL2, the first transmission line GL1 and the second transmission line GL2 can also be located in the circuit structure layer 320.

[0156] In other examples, the first transmission line GL1 and the second transmission line GL2 may be located in the same interconnect layer 331.

[0157] In some examples, such as Figure 6 As shown, the interconnect structure layer 330 may further include a first etch stop layer 333, which is located between adjacent interconnect wiring layers 331 and interconnect contact layers 332. The first etch stop layer 333 can protect the underlying interconnect wiring layer 331 during the fabrication of the interconnect contact layer 332, and similarly, it can protect the underlying interconnect contact layer 332 during the fabrication of the interconnect wiring layer 331.

[0158] In some embodiments, such as Figure 6 , Figures 8 to 15As shown, chip 300 also includes a transition structure layer 340, which is located between circuit structure layer 320 and interconnect structure layer 330. The transition structure layer 340 includes a first dielectric layer 341 and a second dielectric layer 342, with the first dielectric layer 341 located between the second dielectric layer 342 and circuit structure layer 320.

[0159] The transition structure layer 340 can be fabricated using a mid-process. The mid-process is mainly used to fabricate multiple contact structures and / or transition structures, which are used to connect devices formed in the front-end process with traces formed in the back-end process.

[0160] In some examples, such as Figure 6 As shown, the transition structure layer 340 may further include a second etch stop layer 343, which is located between the first dielectric layer 341 and the second dielectric layer 342. The material of the second etch stop layer 343 is different from the material of the first dielectric layer 341, and the material of the second etch stop layer 343 is different from the material of the second dielectric layer 342.

[0161] The second etching stop layer 343 is located between the first dielectric layer 341 and the second dielectric layer 342. It can protect the first dielectric layer 341 and the structures in the first dielectric layer 341 (e.g., the first transition structure, the second transition structure, or the third transition structure) when the second dielectric layer 342 is etched, and prevent the etching process from damaging the first dielectric layer 341 and the structures in the first dielectric layer 341.

[0162] In this embodiment, both the first dielectric layer 341 and the second dielectric layer 342 can be single-layer or multi-layer structures. Alternatively, one of the first dielectric layer 341 and the second dielectric layer 342 can be a single-layer structure, and the other can be a multi-layer structure. When the first dielectric layer 341 or the second dielectric layer 342 is a multi-layer structure, the embodiments of this application do not limit the number of sublayers in the first dielectric layer 341 or the second dielectric layer 342. Figure 6 , Figure 11 and Figure 12 The example uses the first dielectric layer 341 as a multi-layer structure and the second dielectric layer 342 as a single-layer structure.

[0163] In some examples, such as Figure 6 As shown, the first dielectric layer 341 includes a first sublayer 3411 and a second sublayer 3412. The first sublayer 3411 is closer to the circuit structure layer 320 than the second sublayer 3412.

[0164] In some possible implementations, such as Figure 6As shown, the first dielectric layer 341 may further include a third etch stop layer 3413, which is located between the first sublayer 3411 and the second sublayer 3412, and the materials of the first sublayer 3411 and the second sublayer 3412 are different from the materials of the third etch stop layer 3413.

[0165] The third etch stop layer 3413 is located between the first sub-layer 3411 and the second sub-layer 3412. It can protect the first sub-layer 3411 and the structures located in the first sub-layer 3411 (such as the first gate and the second gate) when the second sub-layer 3412 is etched, and prevent the etching process from damaging the first sub-layer 3411 and the structures located in the first sub-layer 3411.

[0166] In some embodiments, such as Figure 6 As shown, the interconnect structure layer 330 may further include a fourth etch stop layer 334, which is located between the interconnect trace layer 331 and the second dielectric layer 342 of the transition structure layer 340. The material of the fourth etch stop layer 334 is different from the material of the second dielectric layer 342.

[0167] The fourth etch stop layer 334 is located between the interconnect structure layer 330 and the transition structure layer 340. It can protect the transition structure layer 340 during the fabrication of the interconnect structure layer 330 and prevent the etching process from damaging the transition structure layer 340.

[0168] In some embodiments, such as Figure 11 As shown, the first electrode 305 is in contact with the first contact area A2 of the second transistor 303, and the second electrode 306 is in contact with the conductive transport layer 33. Figure 11 The diagram illustrates the contact between the second electrode 306 and the interconnect contact layer 332 as an example. Specifically, the second electrode 306 contacts the conductive pillar 3321 in the interconnect contact layer 332. Alternatively, the second electrode 306 can also contact the interconnect trace layer 331. In this case, the second electrode 306 contacts the conductive pattern 3311 in the interconnect trace layer 331.

[0169] When the interconnect structure layer 330 includes multiple interconnect trace layers 331 and multiple interconnect contact layers 332, the second electrode 306 can contact any of the multiple interconnect trace layers 331 or any of the multiple interconnect contact layers 332.

[0170] In some other embodiments, such as Figure 6 and Figure 12As shown, the transition structure layer 340 also includes a first transition structure CT1, which penetrates the first dielectric layer 341 and is in contact with the first contact area A2 of the second transistor 303. The storage element 304 penetrates the second dielectric layer 342, and the first electrode 305 of the storage element 304 is in contact with the first transition structure CT1, while the second electrode 306 of the storage element 304 is in contact with the conductive transport layer 33. Figure 6 The diagram illustrates the contact between the second electrode 306 and the interconnect layer 331 as an example. Figure 12 The diagram illustrates the contact between the second electrode 306 and the interconnect contact layer 332 as an example.

[0171] It is understood that when the interconnect structure layer 330 includes multiple interconnect trace layers 331, and the second electrode 306 is in contact with an interconnect trace layer 331, the second electrode 306 can be in contact with any one of the multiple interconnect trace layers 331. When the interconnect structure layer 330 includes multiple interconnect contact layers 332, the second electrode 306 can be in contact with any one of the multiple interconnect contact layers 332.

[0172] In other embodiments, such as Figure 13 As shown, the first electrode 305 is in contact with one of the conductive transport layers 33, and the second electrode 306 is in contact with another of the plurality of conductive transport layers 33. Figure 13 The diagram illustrates the situation by taking the first electrode 305 in contact with the first interconnect layer 331a and the second electrode 306 in contact with the third interconnect layer 331c as an example.

[0173] It is understandable that when the first electrode 305 and the second electrode 306 are connected to different interconnect layers, the interconnect layer 331 that is in contact with the first electrode 305 is closer to the second transistor 303 than the interconnect layer 331 that is connected to the second electrode 306. The two interconnect layers 331 that are in contact with the memory element 304 can be adjacent interconnect layers 331 or non-adjacent interconnect layers 331.

[0174] like Figure 13As shown, when the first electrode 305 is in contact with the conductive transport layer 33, in order to achieve electrical connection between the first electrode 305 and the first contact area A2 of the second transistor 303, the transition structure layer 340 may further include a second transition structure CT2 and a first contact post VD1. The second transition structure CT2 penetrates the first dielectric layer 341, and the first contact post VD1 penetrates the second dielectric layer 342. One end of the second transition structure CT2 is in contact with the first contact area A2 of the second transistor 303, and the other end of the second transition structure CT2 is in contact with the first contact post VD1. The first electrode 305 is connected to the first contact area A2 of the second transistor 303 through the conductive transport layer 33, the first contact post VD1, and the second transition structure CT1.

[0175] It is understandable that one end of the first contact post VD1 is in contact with the second transition structure CT1, and the other end of the first contact post VD1 is in contact with the conductive transport layer 33 that is closest to the transition structure layer 340 among the multiple conductive transport layers 33.

[0176] In some examples, such as Figure 13 As shown, the first electrode 305 and the first contact post VD1 can be in contact with the conductive pattern 3311 in the same interconnect layer 331, or the first electrode 305 and the first contact post VD1 can be in contact with the conductive post 3321 in the same interconnect contact layer 332.

[0177] In other examples, the first electrode 305 and the first contact post VD1 can be in contact with different conductive transport layers 33, respectively. For example, the first electrode 305 and the first contact post VD1 can be in contact with two adjacent interconnect layers 331. In this case, the first electrode 305 and the first contact post VD1 can be connected through the conductive patterns 3311 in the two adjacent interconnect layers 331 and the conductive posts 3321 in the interconnect contact layer 332 located between the two adjacent interconnect layers 331.

[0178] In some embodiments, continue reading Figure 4 , Figure 5 and Figure 7 The chip 300 may also include multiple bit lines BL, which are connected to the second contact area A3 of the second transistor 303.

[0179] When multiple memory cell groups 310 in chip 300 are arranged in an array, the second contact area A3 of the second transistor 303 of multiple memory cell groups 310 located in the same row is connected to the same bit line BL.

[0180] The extension direction of bit line BL is different from the extension direction of transmission line L. For example, as shown... Figure 4 As shown, multiple bit lines BL can all extend along the first direction X and be arranged along the second direction Y.

[0181] In some examples, multiple bit lines BL can be arranged at equal intervals in the second direction Y, and the width of the multiple lines BL can be the same. This setting helps to reduce the difficulty of the fabrication process (e.g., photolithography), making the fabrication process applicable to advanced process nodes (e.g., 1X process).

[0182] In some examples, such as Figure 5 As shown, multiple bit lines BL can be located in the same interconnect layer 331 (e.g., the second interconnect layer 331b). In this case, multiple bit lines BL can be fabricated simultaneously during the fabrication process of chip 300, which helps to simplify the fabrication process of chip 300 and improve the fabrication efficiency of chip 300.

[0183] In some embodiments, such as Figure 5 and Figure 6 As shown, the transition structure layer 340 may also include a third transition structure CT3 and a second contact post VD2.

[0184] The third transition structure CT3 penetrates the first dielectric layer 341, and the second contact post VD2 penetrates the second dielectric layer 342. One end of the third transition structure CT3 is in contact with the second contact region A3 of the second transistor 303, and the other end of the third transition structure CT3 is in contact with the second contact post VD2. One end of the second contact post VD2 is in contact with the third transition structure CT3, and the other end of the second contact post VD2 is connected to the bit line BL.

[0185] In the case where the transition structure layer 340 includes a second etch stop layer 343, the second contact post VD2 also penetrates the second etch stop layer 343.

[0186] In some examples, the bit line BL can be located in the interconnect layer 331 closest to the circuit structure layer 320 (i.e., the first interconnect layer 331a) among multiple interconnect layers 331. In this case, the bit line BL can be in direct contact with the second contact post VD2.

[0187] In other examples, the bit line BL may be located in other interconnect layers 331. "Other interconnect layers" refers to the remaining interconnect layers 331 other than the interconnect layer 331 closest to the circuit structure layer 320 (i.e., the first interconnect layer 331a). In this case, the bit line BL can be connected (electrically connected) to the second contact post VD2 via the conductive pattern 3311 in the interconnect layer 331 and the conductive post 3321 in the interconnect contact layer 332.

[0188] In some embodiments, such as Figure 14As shown, the transition structure layer 340 may further include a third contact post VD3 and a fourth contact post VD4, both of which penetrate the second dielectric layer 342 and a portion of the first dielectric layer 341. One end of the third contact post VD3 can contact the first gate G1 of the first transistor 301, and the other end of the third contact post VD3 contacts the conductive transport layer 33 closest to the transition structure layer 340. One end of the fourth contact post VD4 can contact the second gate G2 of the first transistor 301, and the other end of the fourth contact post VD4 contacts the conductive transport layer 33 closest to the transition structure layer 340.

[0189] Specifically, when the conductive transport layer 33 is an interconnection layer 331, the third contact post VD3 and the fourth contact post VD4 are respectively connected to different conductive patterns 3311 in the interconnection layer 331. When the conductive transport layer 33 is an interconnection contact layer 332, the third contact post VD3 and the fourth contact post VD4 are respectively connected to different conductive posts 3321 in the interconnection contact layer 332.

[0190] In some embodiments, see Figure 4 , Figure 5 and Figure 7 The chip 300 may also include at least one board line PL. The board line PL is connected to the second electrode 306 of the memory element 304. The board line PL is located in the interconnect layer 331.

[0191] Among them, such as Figure 5 As shown, board line PL and bit line BL can be located in different interconnect routing layers 331. Alternatively, board line PL and bit line BL can be located in the same interconnect routing layer 331. It is understood that when board line PL and bit line BL are located in the same interconnect routing layer 331, board line PL and bit line BL are spaced apart and insulated from each other.

[0192] In some examples, the board line PL can be in the form of a strip or a sheet. When the board line PL is in the form of a strip, the board line PL can connect storage elements 304 of multiple storage cells 302 located in the same column or row.

[0193] When the board line PL is in the form of a strip, multiple board lines PL can extend along a first direction and be arranged along a second direction, with one board line PL connecting multiple memory elements located in the same row. Alternatively, multiple board lines PL can extend along a second direction and be arranged along a first direction, with one board line PL connecting multiple memory elements located in the same column.

[0194] When the plate line PL is in sheet form, such as Figure 4 and Figure 5 As shown, the board line PL can connect to the storage elements 304 of multiple adjacent storage cells 302.

[0195] In some examples, multiple storage elements 304 in the same storage cell group can be connected to the same board line PL.

[0196] In some examples, the number of board lines PL can be twice the number of the first transmission lines, and the number of board lines PL is the same as the number of the second transmission lines. In this case, the board lines PL and the second transmission lines are connected to the memory cells in the same column.

[0197] In some embodiments, such as Figure 15 As shown, chip 300 also includes logic circuit 350. Logic circuit 350 includes logic transistor 351. A first transistor (not shown) and a second transistor 303 are both disposed on the same layer as logic transistor 351.

[0198] like Figure 15 As shown, the first transistor (not shown), the second transistor 303, and the logic transistor 351 can all be located in the circuit structure layer 320. In order to separate the second transistor 303 from the logic transistor 351, the circuit structure layer 320 may also include a partition 360, which can be located between the active structure of the logic transistor 351 and the active structure AA of the second transistor. The material of the partition 360 can be, for example, an insulating material.

[0199] Figure 16 This is a flowchart illustrating a method for fabricating a chip 300 according to an embodiment of this application. The chip includes multiple memory cell groups, each memory cell group comprising a first transistor and two memory cells. Figure 16 As shown, the preparation method includes steps S100 to S300.

[0200] S100, such as Figure 17 As shown, multiple active structures AA are formed, each active structure AA including a channel region A1, a first contact region A2, and a second contact region A3. The channel region A1 is located between the first contact region A2 and the second contact region A3.

[0201] For example, multiple active structures AA may be formed on substrate 101. The material of substrate 101 may include, for example, silicon.

[0202] For example, multiple active structures AA are arranged in an array, with multiple active structures AA located in the same row in direct contact, and multiple active structures AA located in the same column spaced apart. For instance, multiple active structures AA located in the same row can be arranged along a first direction X, and multiple active structures AA located in the same column can be arranged along a second direction Y.

[0203] like Figure 17 As shown, the active structure AA can be fin-shaped, and multiple active structures AA located in the same row can be directly connected to form a fin.

[0204] S200, such as Figure 18 As shown, multiple first gates G1 and multiple second gates G2 are formed. The multiple first gates G1 and multiple second gates G2 are respectively located on the channel region A1 of multiple active structures AA. The multiple first gates G1 and multiple active structures AA form multiple first transistors 301. The multiple second gates G2 and multiple active structures AA form multiple second transistors 303. The active structure AA of the first transistor 301 is located between the active structures AA of two second transistors 303. (See reference...) Figure 5 The first contact area A2 of the first transistor 301 is connected to the first contact area A2 of a second transistor 303, and the second contact area A3 of the first transistor 301 is connected to the first contact area A2 of another second transistor 303.

[0205] like Figure 18 As shown, the first gate G1 and the second gate G2 are both disposed across the active structure AA. That is, the first gate G1 and the second gate G2 include not only the portion located on the active structure AA, but also the portion located on the substrate 101.

[0206] For example, a plurality of first gates G1 and a plurality of second gates G2 can be formed using chemical vapor deposition and etching processes.

[0207] For example, the first gates G1 of a plurality of first transistors 301 located in the same column can be connected to form a first transmission line GL1. The second gates G2 of a plurality of second transistors 303 located in the same column can be connected to form a second transmission line GL2. At this time, the first transmission line GL1 and the second transmission line GL2 can both extend along the second direction Y and be arranged along the first direction X.

[0208] In some embodiments, such as Figures 19 to 22B As shown, before step S300, the preparation method further includes steps S400 and S500.

[0209] S400, such as Figure 19 and Figure 20 As shown, a first dielectric layer 341 is formed on the first transistor (not shown) and the second transistor 303, and a plurality of transition structures CT are formed through the first dielectric layer 341.

[0210] In some examples, the first dielectric layer 341 has a multi-layer structure. For example, as... Figure 20 As shown, the first dielectric layer 341 may include a first sublayer 3411, a second sublayer 3412, and a third etch stop layer 3413. The materials of the first sublayer 3411 and the second sublayer 3412 are different from the material of the third etch stop layer 3413.

[0211] The plurality of transition structures CT may include a first transition structure CT1 and a third transition structure CT3. The first transition structure CT1 is in contact with the first contact area A2 of the second transistor 303, and the third transition structure CT3 is in contact with the second contact area A3 of the second transistor 303. Alternatively, see [link to relevant documentation]. Figure 13 Multiple transition structures may also include a second transition structure CT2 and a third transition structure CT3. The second transition structure CT2 and the third transition structure CT3 are in contact with the first contact area A2 and the second contact area A3 of the second transistor 303, respectively. Alternatively, see [link to relevant documentation]. Figure 11 Multiple transition structures can also include only the third transition structure CT3. The third transition structure CT3 is in contact with the second contact area A3.

[0212] In some examples, multiple transition structures (CTs) can be arranged in an array, where the multiple transition structures can be arranged in a row along a first direction and in a column along a second direction.

[0213] To ensure accurate signal transmission, multiple CT scanners with different switching structures need to be mutually insulated. In this case, such as... Figure 19 As shown, in order to separate multiple transition structures (CTs) arranged in the second direction Y, multiple spacer sections (CTCs) can be formed simultaneously with the formation of the multiple transition structures (CTs). The multiple spacer sections (CTCs) are located between two adjacent transition structures (CTs) in the second direction Y.

[0214] In some examples, refer to Figure 19 and Figure 21 The first mask is used to form a transition pattern in the first dielectric layer 341, and the second mask is used to form a spacer CTC. The spacer is used to separate the transition pattern, and finally multiple independent transition structures CT are formed in the first dielectric layer 341.

[0215] The first mask may include a plurality of first openings, all of which extend along a second direction and are arranged in the first direction. The second mask may include a plurality of second openings, all of which extend along the first direction and are arranged in the second direction.

[0216] S500, such as Figure 22A and Figure 22B As shown, a second dielectric layer 342 is formed on the side of the first dielectric layer 341 away from the first transistor (not shown) and the second transistor 303, and a plurality of contact pillars VD penetrate the second dielectric layer 342.

[0217] The second dielectric layer 342 can be a single-layer structure or a multi-layer structure.

[0218] In some examples, a second etch stop layer 343 may be formed on the side of the first dielectric layer away from the first and second transistors before the second dielectric layer 342 is formed. In this case, the plurality of contact pillars VD penetrate not only the second dielectric layer 342 but also the second etch stop layer 343.

[0219] In some examples, such as Figure 22B As shown, the plurality of contact posts VD may include a second contact post VD2, a third contact post (not shown), and a fourth contact post VD4. The second contact post VD2 is in contact with the third transition structure CT3. The third contact post is in contact with the first gate (not shown), and the fourth contact post VD4 is in contact with the second gate G2. In other examples, see [reference needed]. Figure 13 The multiple contact posts may include a first contact post VD1, a second contact post VD2, a third contact post (not shown), and a fourth contact post VD4. The first contact post VD1 is in contact with the second transition structure CT2. The second contact post VD2 is in contact with the third transition structure CT3. The third contact post is in contact with the first gate, and the fourth contact post is in contact with the second gate.

[0220] S300, forming multiple memory elements 304. The memory elements are connected to the first contact area of ​​the second transistor, and the memory elements and the second transistor form a memory cell.

[0221] In some examples, such as Figures 23 to 27 As shown, step S300 may include steps S310 to S340.

[0222] S310, such as Figure 23 As shown, the second dielectric layer 342 is etched to form a groove U0. The groove U0 exposes the first transition structure CT1.

[0223] For example, a dry etching process can be used to etch the second dielectric layer 342. When a second etch stop layer 343 is provided between the first dielectric layer 341 and the second dielectric layer 342, the groove U0 also penetrates the second etch stop layer 343.

[0224] In some examples, a fourth etch stop layer 334 may be formed on the side of the second dielectric layer 342 away from the first dielectric layer 341 before etching the second dielectric layer 342, to protect the second contact post, the third contact post, and the fourth contact post. In this case, the groove U0 can also penetrate the fourth etch stop layer 334.

[0225] S320, such as Figure 24 and Figure 25 As shown, a first electrode 305 is formed in the groove U0, and the first electrode 305 covers the bottom wall and side wall of the groove U0. The first electrode 305 surrounds the first groove U1.

[0226] For example, a deposition process (e.g., chemical vapor deposition) and an etching process (e.g., dry etching) can be used to form the first electrode 305 in the groove U0.

[0227] S330, such as Figure 26 As shown, an insulating dielectric layer 102 and a conductive layer 103 are sequentially formed in the first groove U1. The insulating dielectric layer 102 is located not only on the bottom wall and side wall of the first groove U1, but also on the side of the second dielectric layer 342 (fourth etch stop layer 334) away from the first dielectric layer 341. The insulating dielectric layer 102 surrounds the second groove U2. The conductive layer 103 fills the second groove U2 and covers the surface of the insulating dielectric layer 102 away from the second dielectric layer 342.

[0228] In some instances, the material of the insulating dielectric layer 102 may include a high dielectric constant material, such as alumina or hafnium oxide. Here, "high dielectric constant material" refers to a material with a dielectric constant value higher than that of silicon dioxide.

[0229] S340, such as Figure 27 and Figure 28 As shown, the insulating dielectric layer 102 and the conductive layer 103 are etched to form the insulating layer 307 and the second electrode 306, respectively.

[0230] For example, a dry etching process can be used to etch the insulating dielectric layer 102 and the conductive layer 103. Figure 27 The edges of the insulating layer 307 and the second electrode 306 are shown in the dashed box.

[0231] In some examples, after forming the insulating layer 307 and the second electrode 306, a planarization layer 104 can also be formed. The planarization layer 104 can cover not only the second electrode 306, but also the surface of the second dielectric layer 342 (or the fourth etch stop layer 334) away from the first dielectric layer 341. The planarization layer 104 can improve the yield of subsequent film layers.

[0232] It is understood that steps S310 to S340 are described using the case where the storage element 304 is located in the transition structure layer 340 and is connected to the first transition structure CT1 through the second dielectric layer 342 as an example. For cases where the storage element 304 is located in the transition structure layer 340, penetrates the first dielectric layer 341 and the second dielectric layer 342, and is in direct contact with the first contact area A2 of the second transistor 303, or where the storage element 304 is located in the interconnect structure layer 330, and the first electrode 305 and the second electrode 306 are respectively in contact with the two interconnect trace layers 331, the specific steps in step S300 may differ from steps S310 to S340.

[0233] In some embodiments, such as Figure 29 As shown, after step S300, the preparation method may further include step S600.

[0234] S600, see reference Figure 4 and Figure 5 An interconnect structure layer 330 is formed on the side of the plurality of memory elements 304 away from the second transistor 303. The plurality of interconnect structure layers 330 includes a plurality of conductive transport layers 33.

[0235] The beneficial effects achieved by the preparation method provided in this application are the same as the technical effects achieved by the chip provided in the above embodiments, and will not be repeated here.

[0236] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0237] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, It includes multiple memory cell groups; each memory cell group includes a first transistor and two memory cells, and each memory cell includes a second transistor and a memory element. Both the first transistor and the second transistor include an active structure, and the active structure of both the first transistor and the second transistor includes a channel region, a first contact region and a second contact region, wherein the channel region is located between the first contact region and the second contact region; in the same memory cell, the first contact region of the second transistor is connected to the memory element; The active structure of the first transistor is located between the active structures of the second transistors of the two memory cells, and the first contact area of ​​the first transistor is connected to the first contact area of ​​the second transistor of one memory cell, and the second contact area of ​​the first transistor is connected to the first contact area of ​​the second transistor of the other memory cell. In the same group of memory cells, when the memory cell is in the working state, the first transistor is in the off state.

2. The chip according to claim 1, characterized in that, In the same group of memory cells, the active structures of the first transistor and the active structures of the second transistors of the two memory cells are arranged along a first direction; The first contact area of ​​the first transistor is connected to the first contact area of ​​the second transistor of one of the memory cells along a first direction, and the second contact area of ​​the first transistor is also connected to the first contact area of ​​the second transistor of another memory cell along the first direction.

3. The chip according to claim 2, characterized in that, At least two of the said storage cell groups are arranged along the first direction; In two adjacent memory cell groups in the first direction, the second contact areas of the two second transistors located between the two first transistors are connected.

4. The chip according to any one of claims 1 to 3, characterized in that, The first transistor further includes a first gate located on the channel region of the first transistor; the second transistor further includes a second gate located on the channel region of the second transistor; the chip further includes: Multiple transmission lines, including a first transmission line and a second transmission line; the first transmission line is connected to the first gate; the second transmission line is connected to the second gate, and in the same memory cell group, the second gate of the second transistor of one memory cell is connected to a second transmission line, and the second gate of the second transistor of another memory cell is connected to another second transmission line.

5. The chip according to claim 4, characterized in that, The multiple transmission lines are arranged on the same layer, and all of the multiple transmission lines extend along the second direction and are arranged along the first direction; in the first direction, the multiple transmission lines are arranged at equal intervals; wherein, the first direction and the second direction intersect.

6. The chip according to claim 5, characterized in that, Any three adjacent transmission lines in the first direction include one first transmission line and two second transmission lines.

7. The chip according to claim 5 or 6, characterized in that, The size of the storage cell in the first direction is 1.5 times the spacing between two adjacent transmission lines in the first direction.

8. The chip according to any one of claims 1 to 7, characterized in that, include: Circuit structure layer; The first transistor and the second transistor are located in the circuit structure layer; An interconnect structure layer is located on one side of the circuit structure layer; the interconnect structure layer includes multiple conductive transport layers; the multiple conductive transport layers are stacked along the thickness direction of the chip; The storage element is located between the first contact area of ​​the second transistor and the conductive transport layer.

9. The chip according to claim 8, characterized in that, The plurality of conductive transport layers include interconnection trace layers and interconnection contact layers. The interconnection contact layers include a plurality of conductive patterns and a plurality of conductive pillars. The conductive patterns in two adjacent interconnection trace layers are connected by at least one conductive pillar. The storage element is located between the first contact area of ​​the second transistor and the interconnect layer, or the storage element is located between the first contact area of ​​the second transistor and the interconnect contact layer.

10. The chip according to claim 8 or 9, characterized in that, The storage element includes a first electrode and a second electrode disposed opposite to each other, the first electrode being in contact with a first contact area of ​​the second transistor, and the second electrode being in contact with the conductive transport layer.

11. The chip according to claim 8 or 9, characterized in that, The chip further includes a transition structure layer, which is located between the circuit structure layer and the interconnect structure layer. The transition structure layer includes a first dielectric layer, a second dielectric layer and a first transition structure. The first dielectric layer is located on the side of the second dielectric layer close to the circuit structure layer. The first transition structure penetrates the first dielectric layer and is in contact with the first contact area of ​​the second transistor. The storage element penetrates the second dielectric layer and includes a first electrode and a second electrode disposed opposite to each other. The first electrode is in contact with the first transition structure, and the second electrode is in contact with the conductive transport layer.

12. The chip according to claim 8 or 9, characterized in that, The storage element includes a first electrode and a second electrode disposed opposite to each other, the first electrode being in contact with one of the plurality of conductive transport layers, and the second electrode being in contact with the other of the plurality of conductive transport layers.

13. The chip according to claim 12, characterized in that, The chip includes a transition structure layer located between the circuit structure layer and the interconnect structure layer. The transition structure layer includes a first dielectric layer, a second dielectric layer, a second transition structure, and a first contact post. The first dielectric layer is located on the side of the second dielectric layer close to the circuit structure layer. The second transition structure penetrates the first dielectric layer. The first contact post penetrates the second dielectric layer. One end of the second transition structure is in contact with the first contact area of ​​the second transistor, and the other end of the second transition structure is in contact with the first contact post. The first electrode is connected to the first contact area of ​​the second transistor through the conductive transport layer, the first contact post, and the second transition structure.

14. The chip according to claim 11 or 13, characterized in that, The transition structure layer also includes a third transition structure, a second contact post, a third contact post, and a fourth contact post; The third transition structure penetrates the first dielectric layer, and the second contact post, the third contact post, and the fourth contact post all penetrate the second dielectric layer; One end of the third transition structure is in contact with the second contact post, and the other end of the third transition structure is in contact with the second contact area of ​​the second transistor; the third contact post is in contact with the first gate of the first transistor, and the fourth contact post is in contact with the second gate of the second transistor.

15. The chip according to any one of claims 1 to 14, characterized in that, The storage element includes a first electrode, a second electrode, and an insulating layer, wherein the first electrode, the insulating layer, and the second electrode are stacked along the thickness direction of the chip; the first electrode is connected to a first contact area of ​​the second transistor, and the second electrode is located on the side of the first electrode away from the second transistor.

16. The chip according to any one of claims 1 to 14, characterized in that, The storage element includes a first electrode, a second electrode, and an insulating layer. The first electrode is connected to a first contact area of ​​the second transistor. The first electrode forms a first groove. The insulating layer covers the bottom and side walls of the first groove and forms a second groove. The second electrode covers the bottom and side walls of the second groove.

17. The chip according to any one of claims 1 to 16, characterized in that, The active structures of the first transistor and the second transistor are both fin-shaped and extend along a first direction; the active structures in the multiple memory cell groups arranged along the first direction are connected in sequence to form fins.

18. The chip according to any one of claims 1 to 17, characterized in that, The chip also includes logic circuitry, which includes logic transistors; the first transistor and the second transistor are both disposed on the same layer as the logic transistors.

19. A method for fabricating a chip, characterized in that, The chip includes multiple memory cell groups, each memory cell group including a first transistor and two memory cells, and the fabrication method includes: Multiple active structures are formed, each active structure including a channel region, a first contact region, and a second contact region, wherein the channel region is located between the first contact region and the second contact region; A plurality of first gates and a plurality of second gates are formed; the plurality of first gates and the plurality of second gates are respectively located on the channel regions of a plurality of active structures; the plurality of first gates and the plurality of active structures form a plurality of first transistors, and the plurality of second gates and the plurality of active structures form a plurality of second transistors; the active structure of the first transistor is located between the active structures of two second transistors; the first contact region of the first transistor is connected to the first contact region of one second transistor, and the second contact region of the first transistor is connected to the first contact region of another second transistor; Multiple storage elements are formed; the storage elements are connected to the first contact area of ​​the second transistor; the storage elements and the second transistor form a storage cell.

20. An electronic device, characterized in that, include: Circuit board; The chip as described in any one of claims 1 to 18; the chip is located on the circuit board and is electrically connected to the circuit board.

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