Memory bad block management method, control method, and memory system

Abstract

Embodiments of the present disclosure disclose a memory bad block management method, a control method and a memory system. The memory includes a die, the die includes a plurality of memory surfaces, each memory surface includes a plurality of block storage areas, and a set of the plurality of block storage areas located at the same position in different memory surfaces in the die constitutes a virtual block group; the memory includes a hidden area, a storage area and a reserved area; wherein the reserved area includes an (n+1)th virtual block group to an mth virtual block group; n is less than m, and n and m are both natural numbers; the method includes: when a bad block in the storage area is detected, determining a target memory surface where the bad block is located; when all first replacement blocks in the hidden area of the target memory surface are occupied, determining the (n+1)th virtual block group of the reserved area as a current bad block replacement group, and replacing the current bad block with a second replacement block located in the target memory surface in the (n+1)th virtual block group as a target replacement block; and releasing the second replacement blocks in the (n+1)th virtual block group except the target replacement block.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuits, and particularly to a bad block management method, control method, and memory system for a memory. Background Technology

[0002] NAND flash memory, as a type of non-volatile memory, has advantages such as low cost, high capacity, and fast rewrite speed. During the use of NAND flash memory, bad blocks may be generated. In order to ensure the normal use of NAND flash memory, bad block management (BBM) is required.

[0003] In related technologies, skipping or replacement strategies can be used to manage bad blocks. Compared to skipping strategies, NAND flash memory using replacement strategies exhibits more stable performance. However, replacing strategies lead to wasted block storage areas in NAND flash memory, reducing the usable space. Therefore, how to better manage bad blocks to reduce wasted block storage areas and increase usable space has become an urgent technical problem to be solved. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a bad block management method for a memory is provided. The memory includes a die, the die includes multiple storage surfaces, each storage surface includes multiple block storage areas, and a set of multiple block storage areas located at the same position in different storage surfaces within the die constitutes a virtual block group. The memory includes a hidden region, a storage region, and a reserved region; wherein the reserved region includes virtual block groups n+1 to m; n is less than m, and n and m are both natural numbers; the method includes:

[0005] When a bad block is detected in the storage area, the target storage surface where the bad block is located is determined;

[0006] When all the first replacement blocks in the hidden area of ​​the target storage surface are occupied, the (n+1)th virtual block group in the reserved area is determined as the current bad block replacement group, and the second replacement block in the (n+1)th virtual block group located in the target storage surface is used as the target replacement block to replace the current bad block;

[0007] Release the second replacement block in the (n+1)th virtual block group, excluding the target replacement block; wherein the released second replacement block is used to store data.

[0008] According to a second aspect of the present disclosure, a method for controlling a memory is provided, characterized in that, when a bad block is detected in a storage area of ​​the memory, the bad block is managed by a management method provided in the first aspect of the present disclosure, the control method comprising:

[0009] Obtain the address of the target replacement block;

[0010] Based on the address of the target replacement block, a control signal is applied to the target replacement block.

[0011] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0012] The memory includes: a die, the die including multiple storage surfaces, each storage surface including multiple block storage areas, and a set of multiple block storage areas located at the same position in different storage surfaces within the die constituting a virtual block group; the memory includes a hidden region, a storage region, and a reserved region; wherein, the reserved region includes the (n+1)th virtual block group to the mth virtual block group; n is less than m, and n and m are both natural numbers;

[0013] A memory controller includes: coupled to the memory and configured to perform a bad block management method provided in a first aspect of the present disclosure, or configured to perform a control method provided in a second aspect of the present disclosure. Attached Figure Description

[0014] Figure 1a and Figure 1b This is a schematic diagram illustrating bad block management in a memory according to an exemplary embodiment;

[0015] Figure 2 This is a flowchart illustrating a bad block management method for a memory according to an embodiment of the present disclosure;

[0016] Figure 3a and Figure 3b This is a schematic diagram illustrating bad block management in a memory according to an embodiment of the present disclosure;

[0017] Figure 4 This is a flowchart illustrating a memory control method according to an embodiment of the present disclosure;

[0018] Figure 5 This is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0019] Figure 6a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0020] Figure 6bThis is a schematic diagram of a solid-state drive (SSD) according to an embodiment of the present disclosure.

[0021] Figure 7 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0022] Figure 8 This is a partial cross-sectional view of a memory cell array including NAND memory strings, according to an embodiment of the present disclosure;

[0023] Figure 9 This is a block diagram of a memory including a memory cell array and peripheral circuitry, according to embodiments of the present disclosure. Detailed Implementation

[0024] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0025] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0026] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0028] Bad blocks in NAND flash memory can be categorized by their origin into two main types: Factory Bad Blocks, which are bad blocks generated during the manufacturing process due to manufacturing defects; and Growing Bad Blocks, which are bad blocks generated during use due to wear and tear from erasing and rewriting. Bad block management is necessary to ensure the normal operation of NAND flash memory.

[0029] Figure 1a and Figure 1b This is a schematic diagram illustrating bad block management in a memory according to an exemplary embodiment. The memory includes multiple dies, each die including multiple storage planes, and each storage plane including multiple block storage areas.

[0030] Because there are numerous block storage areas in a memory, managing each block storage area individually would increase management complexity and reduce efficiency. Therefore, a virtual block (VB) is formed by grouping multiple block storage areas located at the same position on different storage planes within the memory die, and block storage areas are allocated and used on a VB-by-virtual block basis to reduce the complexity of block storage area management.

[0031] For example, refer to Figure 1a and Figure 1b As shown, taking a memory consisting of one die (e.g., die 0), die 0 having four storage surfaces (referred to as storage surface 0, storage surface 1, storage surface 2, and storage surface 3 in sequence), and each storage surface having (m+1) block storage areas as an example, the collection of block storage areas located in the same row in different storage surfaces within die 0 can be formed into a virtual block group. In this way, the 4*(m+1) block storage areas in the memory can be divided into (m+1) virtual block groups (referred to as virtual block group 0, virtual block group 1, ..., virtual block group m in sequence), and each virtual block group includes four block storage areas.

[0032] Similarly, when a memory includes two dies (e.g., die 0 and die 1), each die includes four storage surfaces, and each storage surface includes (m+1) block storage areas, the set of block storage areas located in the same row in different storage surfaces of the memory can be formed into a virtual block group. In this way, 8*(m+1) block storage areas can be divided into (m+1) virtual block groups, and each virtual block group includes 8 block storage areas.

[0033] Furthermore, the multiple virtual block groups in the memory can be divided into: user area and hidden area. The block storage areas in the user area are used for information storage, while the block storage areas in the hidden area are used to replace factory-damaged or growing bad blocks in the user area. The boundary of the user area is determined by the storage surface containing the largest number of factory-damaged blocks. It is understandable that the storage surface containing the largest number of factory-damaged blocks has the largest number of block storage areas already used for replacement (denoted as replaced blocks).

[0034] For example, refer to Figure 1a As shown, the number of replaced blocks on storage surface 1 inside die 1 is 6, that is, storage surface 1 includes 6 factory-damaged blocks. Thus, virtual block groups 0 to 5, which include the replaced blocks, can be defined as hidden areas, and virtual block groups 6 to 1 can be defined as user areas.

[0035] During memory use, when a bad block is generated in the user area, it can be replaced by a first replacement block (orphan block) located in the hidden area on the same storage plane as the bad block. When an operation needs to be performed on the bad block, the physical block address (pba) and its physical cluster address (pca) of the first replacement block used to replace the bad block can be found according to the remap table, and the operation can be performed on the first replacement block. It can be understood that the block storage area located in the hidden area is called the first replacement block.

[0036] However, the number of first replacement blocks in the hidden region is limited. When all the first replacement blocks on a certain storage plane are occupied, if bad blocks continue to be generated in the user area of ​​that storage plane, they can be replaced by first replacement blocks located on different storage planes than the bad blocks. In this case, the storage plane where the bad blocks are located and the storage plane where the first replacement blocks used to replace the bad blocks are located cannot perform multi-plane operations.

[0037] Taking die 1 as an example, refer to Figure 1b As shown, the first replacement blocks in the hidden area of ​​storage plane 1 are all occupied. When bad blocks appear in the user area of ​​storage plane 1, if the first replacement blocks in the hidden area of ​​storage plane 0 are used to replace the bad blocks in storage plane 1, then storage plane 0 and storage plane 1 cannot perform multi-plane operations. The reason is that in response to operations on storage plane 0 and storage plane 1, the operations will be repeated in storage plane 1, resulting in additional overhead.

[0038] Therefore, in related technologies, a revoke block group comprising multiple virtual block groups is set up in the user area. When the first replacement blocks of a storage plane are all occupied and a bad block appears on that storage plane, replacement can be performed on a unit of a virtual block group. The block storage area in the revoke block group can be called the second replacement block. Specifically, the bad block can be replaced using the second replacement block located on the storage plane where the bad block is located within the virtual block group. Furthermore, to ensure that the number of second replacement blocks available for replacing bad blocks on the storage plane is greater than or equal to 2, a new virtual block group is required as the revoke block group to ensure that the block storage area in each storage plane within the revoke block group is greater than or equal to 2. It is understood that the block storage area located within the revoke block group is called the second replacement block.

[0039] It should be noted that although a portion of the virtual block group is reserved in the user area for use as a block group to replace growing bad blocks generated during memory use, the virtual block group occupied in the user area will result in a reduction in the actual storage space used to store data.

[0040] For example, refer to Figure 1a and Figure 1b As shown, the undo block group consists of virtual block group n+1 and virtual block group n+2. All the first replacement blocks of storage surface 1 in die 1 are occupied. When a bad block is generated in storage surface 1 of die 1, it can be replaced using virtual block group n+1 of the undo block group. Specifically, the bad block is replaced by the second replacement block in virtual block group n+1 located on the storage surface where the bad block is located, and a new virtual block group n+3 is used as the undo block group. In other words, after this replacement, the undo block group consists of virtual block group n+2 and virtual block group n+3.

[0041] It should be noted that before the above replacement, the block storage area in virtual block group n+3 can be used as a storage block for storing information. After the replacement, an additional virtual block group in the user area will be used for the undoing of the block group, resulting in a further reduction in the actual storage space used for storing data.

[0042] The above replacement method, which uses a virtual block group as a unit, can guarantee the parallelism of multi-plane operations in the memory. However, if a certain storage plane has poor performance and produces many bad blocks, more virtual block groups need to be used as replacement block groups. On the other hand, for storage planes with better performance and fewer bad blocks, it is not necessary to use so many block storage areas as second replacement blocks to replace potential bad blocks. This will lead to a waste of block storage resources in the user area, reducing the usable storage space and thus limiting the memory's storage capacity.

[0043] Furthermore, the more dies a memory contains, and the more block storage areas each virtual block group includes, the greater the loss of storage capacity in the user area will be when replacing a virtual block group. This loss is particularly noticeable for 4x8x universal flash storage.

[0044] In view of this, embodiments of the present disclosure provide a method for bad block management of a memory.

[0045] Figure 2 This is a flowchart illustrating a bad block management method for a memory according to an embodiment of the present disclosure. The memory includes a die, which includes multiple storage surfaces. Each storage surface includes multiple block storage areas. A set of multiple block storage areas located at the same position in different storage surfaces within the die constitutes a virtual block group. The memory includes a hidden region, a storage region, and a reserved region. The reserved region includes virtual block groups n+1 to m, where n is less than m, and both n and m are natural numbers. The bad block management method includes the following steps:

[0046] S110: When a bad block is detected in a storage area, determine the target storage surface where the bad block is located;

[0047] S120: When all the first replacement blocks in the hidden area of ​​the target storage surface are occupied, determine the (n+1)th virtual block group in the reserved area as the current bad block replacement group, and use the second replacement block in the (n+1)th virtual block group located in the target storage surface as the target replacement block to replace the current bad block.

[0048] S130: Release the second replacement block in the (n+1)th virtual block group, excluding the target replacement block; wherein the released second replacement block is used to store data.

[0049] For example, refer to Figure 3a As shown, the memory may include a die 1, and die 1 may include four memory surfaces (denoted as memory surface 0, memory surface 1, memory surface 2, and memory surface 3). Although Figure 3a An example of die 1 including four memory surfaces is shown, but this disclosure is not limited thereto. In other embodiments, die 1 may include five or more memory surfaces. For example, die 1 may include eight memory surfaces. For ease of description and illustration, the following will refer to... Figure 3a The following explanation uses die 1, which has four storage surfaces, as an example.

[0050] For example, refer to Figure 3a As shown, each storage surface includes m block storage areas, where m is a natural number. Further, each block storage area includes multiple page storage areas, and each page storage area includes multiple storage units. In this embodiment, the storage units can be non-volatile storage units.

[0051] The storage unit may include: a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data, etc. It should be emphasized that the storage unit may also store more bits of data, and this disclosure does not impose any limitations.

[0052] For example, refer to Figure 3a As shown, each storage surface can include (m+1) block storage areas. The set of block storage areas in the same row of storage surface 0, storage surface 1, storage surface 2 and storage surface 3 in die 1 can be formed into a virtual block group. In this way, the 4*(m+1) block storage areas in die 1 can be divided into (m+1) virtual block groups (denoted as virtual block group 0, virtual block group 1, ... virtual block group m), and each virtual block group includes 4 block storage areas.

[0053] For example, a virtual block group may include a set of block storage areas with the same number located in different storage planes within the die. For instance, (m+1) block storage areas in each storage plane can be numbered and sequentially labeled as block storage area 0, block storage area 1, ..., block storage area m. Each block storage area 1 in storage planes 0 to 3 is located in the same position, that is, the set of each block storage area 1 numbered 1 in storage planes 0 to 3 constitutes virtual block group 1. Other block storage areas in storage planes 0 to 3 are similar and will not be described in detail here.

[0054] For example, a virtual block group may also include a set of block storage areas located at the same offset in different storage planes within the die. For instance, the first block storage area in each storage plane can be used as a reference (i.e., offset is 0), and the offset of the second block storage area can be recorded as x, the offset of the third block storage area as 2x, ..., the offset of the (m+1)th block storage area as mx, where x is a real number. The block storage areas in storage planes 0 to 3 with an offset of x relative to the first block storage area are located at the same position, that is, the set of block storage areas in storage planes 0 to 3 with an offset of x relative to the first block storage area constitutes virtual block group 1. The other block storage areas in storage planes 0 to 3 are similar and will not be described in detail here.

[0055] For example, refer to Figure 3a As shown, the memory includes a hidden region, a storage region, and a reserved region. The hidden region includes virtual block groups 0 to 5, the storage region includes virtual block groups 6 to n, and the reserved region includes virtual block groups (n+1) to m, where n is less than m and both n and m are natural numbers.

[0056] In practical applications, memory can be partitioned according to its capacity. The memory can be divided into regions not limited to the three types mentioned above; more regions can be used, such as regions comprising at least one virtual block group for garbage collection. Although this example uses virtual block groups as units of memory partitioning, in other examples, memory can also be partitioned using block storage areas as units of memory partitioning.

[0057] Understandably, in this example, the memory can be divided into a hidden region, a storage region, and a reserved region. The hidden region includes multiple first replacement blocks for replacing factory-installed bad blocks or growing bad blocks located on the same storage surface (e.g., bad blocks generated in the storage region). The storage region includes multiple storage blocks for storing data. The reserved region includes multiple second replacement blocks for replacing bad blocks generated in the storage region when all first replacement blocks on the same storage surface are occupied.

[0058] It should be noted that, at the factory, the range of virtual block groups included in the hidden area can be set according to the storage surface with the largest number of replaced blocks. For example, if the number of replaced blocks on storage surface 1 of die 1 is 6, it means that at the factory, there are already 6 first-replacement bad blocks on this storage surface to replace the factory-faulty blocks. In this case, virtual block groups 0 to 5 can be set as the hidden area. In practice, the hidden area can be set according to the number of factory-faulty blocks in the memory, and this disclosure does not impose any limitations on this.

[0059] For example, refer to 3a and Figure 3b As shown, when a bad block A is detected in the storage area of ​​die 1, the target storage surface, i.e., storage surface 1, where the bad block A is located can be determined based on the physical address and / or logical address of the bad block A. Since the first replacement blocks in the hidden area of ​​storage surface 1 are all occupied, the virtual block group n+1 in the reserved area can be determined as the current bad block replacement group, and the second replacement block A' located in storage surface 1 in the virtual block group n+1 is used as the target replacement block to replace the current bad block A.

[0060] It should be emphasized that in this example, a single virtual block group (i.e., virtual block group n+1) is used as the bad block replacement group. However, this disclosure is not limited to this. In other examples, at least two virtual block groups (e.g., virtual block group n+1 and virtual block group n+2) can be used as bad block replacement groups to replace bad blocks appearing in the memory. It is understood that the bad block replacement group may include one virtual block group or multiple virtual block groups.

[0061] For example, refer to 3a and Figure 3b As shown, after replacing the current bad block A with the target replacement block A', the second replacement block located in storage plane 0, storage plane 2 and storage plane 3 in the virtual block group n+1 can be released. The released second replacement block can be used as a storage block for storing data.

[0062] Understandably, the capacity of the reserved area and the storage area can be dynamically adjusted. For example, after releasing the second replacement block in the reserved area, the released second replacement block can be allocated to the storage area, thus increasing the number of block storage units in the storage area used to store data.

[0063] In this embodiment of the disclosure, when all the first replacement blocks in the hidden area of ​​the target storage surface where the bad block is located are occupied, by determining a virtual block group in the reserved area as the current bad block replacement group, using the second replacement block in the bad block replacement group located in the target storage surface as the target replacement block to replace the current bad block, and releasing the second replacement block in the bad block replacement group other than the target replacement block, the utilization rate of the block storage area in the reserved area can be improved, thereby reducing the waste of block storage area resources in the reserved area and helping to increase the usable capacity in the reserved area.

[0064] Compared to replacing bad blocks with a first replacement block in another storage plane, in this embodiment of the present disclosure, replacing bad blocks with a second replacement block located in the same storage plane is beneficial to ensuring the parallelism of multi-plane memory operations, improving the reliability of multi-plane memory operations, and reducing additional overhead.

[0065] In some embodiments, after replacing the current bad block with a target replacement block from the (n+1)th virtual block group, the method further includes:

[0066] Determine the (n+2)th virtual block group in the reserved area as the next bad block replacement group;

[0067] The above step S130 includes:

[0068] An erasure operation is performed on the second replacement block in the (n+1)th virtual block group, excluding the target replacement block, and the erased second replacement block is used as a storage block; wherein, the storage block is used to store data.

[0069] For example, referring to 3b, after replacing the current bad block block A with the second replacement block block A' located in storage surface 1 in virtual block group n+1 as the target replacement block, virtual block group n+2 is determined as the next bad block replacement group. It can be understood that when the next bad block is generated in storage surface 1 in die 1, similar operations to steps S110 to S130 can be performed to replace the next bad block.

[0070] For example, referring to 3b, after replacing the current bad block A with the target replacement block A' in storage plane 1, an erasure operation is performed on the second replacement block located in storage plane 0, storage plane 2 and storage plane 3 in virtual block group n+1, and the erased second replacement block is used as the storage block for storing data.

[0071] It is important to emphasize that when using the freed second replacement block as a storage block for data, before performing programming operations on the freed second replacement block, it is necessary to ensure that the freed second replacement block is in a reset state. By performing an erase operation, the freed second replacement block can be reset to ensure the normal execution of programming operations on the freed second replacement block.

[0072] Compared to related technologies that set at least two virtual block groups in the user area as undo block groups to replace the current bad blocks appearing in the memory, in this embodiment of the disclosure, by determining a virtual block group in the reserved area as a bad block replacement group to replace the current bad blocks, the number of virtual block groups in the reserved area used to replace the current bad blocks appearing in the memory can be reduced.

[0073] Furthermore, compared to related technologies where the number of virtual block groups used to replace the next bad block in the memory increases to at least three after bad block replacement, in this embodiment of the present disclosure, with the capacity occupied by the hidden region remaining unchanged, after replacing the current bad block with the target replacement block, the number of virtual block groups used to replace the next bad block in the memory is still one, which can save space of at least nearly two virtual block groups.

[0074] Furthermore, by using the released second replacement block as a storage block, the capacity of the reserved area can be reduced, thereby increasing the capacity of the storage area, which is beneficial to increasing the capacity of the space actually used for storing information in the memory.

[0075] In some embodiments, the above method is applied to a memory comprising a plurality of dies; wherein each virtual block group comprises a plurality of block storage areas located at the same position in different storage planes within a plurality of dies.

[0076] For example, referring to 3a, the memory also includes a die 0, which includes four memory surfaces (denoted as memory surface 0, memory surface 1, memory surface 2 and memory surface 3).

[0077] For example, referring to 3a, when the memory includes two dies, namely die 0 and die 1, each virtual block group includes multiple block storage areas located in the same positions of storage plane 0, storage plane 1, storage plane 2, and storage plane 3 in die 0 and in the same positions of storage plane 0, storage plane 1, storage plane 2, and storage plane 3 in die 1.

[0078] Understandably, when the memory comprises two dies, each with four memory planes, each virtual block group comprises eight block memory areas. Each block memory area is located at the same position in different memory planes, for example, in the same row.

[0079] It should be noted that die 0 and die 1 are merely illustrative, intended to convey this disclosure to those skilled in the art; however, this disclosure is not limited thereto. A memory may include y dies, each die including z storage surfaces, then each virtual block group includes yz block storage areas, where y and z are both positive integers. In this example, each die includes the same number of storage surfaces, z. In other embodiments, the number of storage surfaces included in each die may be different, for example, z1, z2…z… n Then each virtual block group includes (z1+z2+……+zn ) block storage areas.

[0080] For a memory comprising multiple dies, the embodiments of this disclosure apply the above-described bad block management method for bad block management. Even if each virtual block group comprises multiple block storage areas located at the same position in different storage planes within multiple dies, after bad block replacement is performed on a unit of a virtual block group, the second replacement block other than the target replacement block in the virtual block group is released, and the released second replacement block is used as a storage block for storing data. This can reduce the loss of storage capacity in the user area and is beneficial to increasing the capacity of available space within a memory comprising multiple dies.

[0081] In some embodiments, when replacing the current bad block with a target replacement block in the (n+1)th virtual block group, the above method further includes:

[0082] Determine the address of the target replacement block;

[0083] Generate a target replacement block address table based on the address of the target replacement block;

[0084] Save the target replacement block address table to the bad block table.

[0085] For example, when a bad block A is detected in the storage area of ​​die 1, the address of the bad block A (e.g., physical address or logical address) can be determined based on the location of the bad block A, and the location of the corresponding target replacement block A' can be determined based on the address of the bad block A, that is, the location at the intersection of virtual block group n+1 and storage surface 1, and the address of the target replacement block A' (e.g., physical address or logical address) can be determined based on the location of the target replacement block A'.

[0086] For example, the address of bad block A can be determined, saved to a bad block address table, and refreshed. The address of the target replacement block A' can be determined, saved to the target replacement block address table, and refreshed. A remapping relationship between the refreshed bad block address table and the target replacement block address table can be established, and the address mapping table can be refreshed. The refreshed bad block address table, the target replacement block address table, and the address mapping table are then saved to a bad block table for managing bad blocks in memory. For instance, when a data access request (e.g., a read request) for bad block A is received from the host, the target replacement block A' can be accessed by referring to the updated address mapping table.

[0087] It is understood that, in this embodiment of the present disclosure, by generating a target replacement block address table and saving the target replacement block address table to a bad block table, the target replacement block that replaces the current bad block can be marked, and data access requests can be executed according to the index of the mark. This helps to reduce the probability of errors in reading, programming or erasing in the memory (e.g., the problem of double programming) and improve the reliability of the memory.

[0088] In some embodiments, the above method further includes:

[0089] When a first replacement block is available in the hidden region of the target storage surface, the current bad block is replaced with the first replacement block located in the target storage surface.

[0090] For example, refer to 3a and Figure 3b As shown, when a bad block B is detected in the storage area of ​​die 0, the target storage surface where the bad block B is located, namely storage surface 2 in die 0, can be determined according to the physical address and / or logical address of the bad block B. The bad block B is then replaced by the first replacement block B' in the hidden area of ​​storage surface 2.

[0091] It is understood that in the embodiments of this disclosure, when there is a usable first replacement block in the hidden area of ​​the target storage surface, the current bad block can be replaced by the first replacement block in the hidden area, without using a virtual block group in the reserved area for replacement, and without needing to determine the next bad block replacement group in the reserved area, thus simplifying the complexity of bad block management.

[0092] In some embodiments, when replacing the current bad block with a first replacement block located on the target storage surface, the above method further includes:

[0093] Determine the address of the first replacement block to replace the current bad block;

[0094] Generate a first replacement block address table based on the address of the first replacement block;

[0095] Save the address table of the first replacement block to the bad block table.

[0096] For example, when a bad block B is detected in the storage area of ​​die 0, the address of the bad block B (e.g., physical address or logical address) can be determined according to the location of the bad block B, and the location of the corresponding first replacement block B' can be determined according to the address of the bad block B, that is, the location at the intersection of virtual block group 3 and storage surface 2, and the address of the first replacement block B' (e.g., physical address or logical address) can be determined according to the location of the first replacement block B'.

[0097] Similarly, the address of bad block B can be determined, saved to the bad block address table, and refreshed. The address of the first replacement block B' can be determined, saved to the first replacement block address table, and refreshed. A remapping relationship between the refreshed bad block address table and the first replacement block address table is established, and the address mapping table is refreshed. The refreshed bad block address table, the first replacement block address table, and the address mapping table are then saved to the bad block table for managing bad blocks in memory. For example, when a data access request (e.g., a read request) for bad block B is received from the host, the first replacement block B' can be accessed by referring to the updated address mapping table.

[0098] It is understood that, in this embodiment of the present disclosure, by generating a first replacement block address table and saving the first replacement block address table to a bad block table, the first replacement block that replaces the current bad block can be marked, and data access requests can be executed according to the index of the mark. This helps to reduce the probability of errors in reading, programming or erasing in the memory (e.g., the problem of double programming) and improve the reliability of the memory.

[0099] In some embodiments, when a bad block is detected in a storage area, determining the target storage surface where the bad block is located includes:

[0100] The memory is tested to obtain the test results.

[0101] When the detection results indicate the presence of bad blocks in the storage area, the address of the bad block is determined, and the target storage surface is determined based on the address of the bad block.

[0102] For example, refer to Figure 3b As shown, bad block detection can be performed on the memory and the detection result can be obtained. When the detection result indicates that bad block A appears in die 1, the target storage surface where bad block A is located, i.e. storage surface 1, can be determined according to the physical address and / or logical address of bad block A.

[0103] And / or,

[0104] When the detection result indicates that a bad block B is present in die 0, the target storage plane where the bad block B is located, i.e. storage plane 2, can be determined based on the physical address and / or logical address of the bad block B.

[0105] It is understood that, in the embodiments of this disclosure, by determining the target storage plane where the bad block is located, the bad block can be replaced by the first replacement block or the second replacement block in the target storage plane, so as to ensure the performance of multi-plane operation of the memory and improve the read, program or erase speed of the memory.

[0106] Figure 4 This is a flowchart illustrating a memory control method according to an embodiment of the present disclosure. When a bad block is detected in a storage area of ​​the memory, the bad block is managed using the management method described in any of the above embodiments. The control method includes the following steps:

[0107] S210: Obtain the address of the target replacement block;

[0108] S220: Apply control signals to the target replacement block according to the address of the target replacement block.

[0109] For example, in step S210, when a bad block is detected in the storage area of ​​the memory, the address of the target replacement block can be obtained from the bad block table.

[0110] For example, in step S220, the location of the target replacement block can be determined according to the address of the target replacement block, and the control signal to be applied to the bad block can be applied to the target replacement block.

[0111] In this embodiment of the disclosure, by obtaining the address of the target replacement block, the control signal applied to the bad block can be applied to the target replacement block to replace the bad block according to the index of the address of the target replacement block. This helps to reduce the probability of errors occurring during reading, programming or erasing in the memory and improve the reliability of the memory.

[0112] In some embodiments, the control method described above includes at least one of the following: a programming method for performing a programming operation on a memory; a reading method for performing a reading operation on a memory; and an erasing method for performing an erasing operation on a memory.

[0113] The above-mentioned application of control signals to the target replacement block includes:

[0114] When performing a programming operation on the memory, a programming signal is applied to the target replacement block;

[0115] When performing a read operation on the memory, a read signal is applied to the target replacement block;

[0116] When performing an erase operation on the memory, an erase signal is applied to the target replacement block.

[0117] For example, when performing a programming operation on the memory, the memory can be programmed in units of block storage areas. When the programming verification result indicates that a certain storage area is a bad block, the above-mentioned bad block management method can be executed to replace the bad block with a target replacement block, and the programming signal applied to the bad block can be applied to the target replacement block to replace the bad block in order to complete the programming operation.

[0118] For example, when performing a programming operation on the memory, the memory can be programmed in units of page storage areas. When the programming verification result indicates that a certain page storage area is a bad page, the above-mentioned bad block management method can be executed to replace the bad block with a target replacement block, transfer the data information of the successfully programmed page storage area to the target replacement block, and apply the programming signal of the unprogrammed page storage area to the target replacement block to replace the bad block, so as to complete the programming operation.

[0119] For example, when performing a read operation on the memory, the address of the target replacement block can be determined according to the address mapping table in the bad block table, and the read signal applied to the bad block can be applied to the target replacement block to replace the bad block in order to complete the read operation.

[0120] For example, when performing an erase operation on the memory, the address of the target replacement block can be determined according to the address mapping table in the bad block table, and the erase signal applied to the bad block can be applied to the target replacement block to replace the bad block in order to complete the erase operation.

[0121] Figure 5 This is a schematic diagram illustrating a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 5 As shown, the memory system 100 includes:

[0122] The memory 103 includes: a die, which includes multiple storage surfaces, each storage surface including multiple block storage areas, and a set of multiple block storage areas located at the same position in different storage surfaces within the die constitutes a virtual block group; the memory includes a hidden area, a storage area and a reserved area; wherein, the reserved area includes the (n+1)th virtual block group to the mth virtual block group; n is less than m, and n and m are both natural numbers;

[0123] The memory controller 104 includes: coupled to the memory 103, and configured to perform the bad block management method in any of the above embodiments, or configured to perform the control method in any of the above embodiments.

[0124] System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0125] like Figure 5 As shown, system 100 may include a host 101 and a storage subsystem 102, the storage subsystem 102 having one or more memories 103, and the storage subsystem also including a memory controller 104. The host 101 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 101 may be configured to send data to the memory 103. Alternatively, the host 101 may be configured to receive data from the memory 103.

[0126] Memory 103 can be any memory device disclosed in this disclosure. For example, such as Figure 3a or Figure 3b The memory shown. Memory 103 may be a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device) that may have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0127] In some embodiments, the memory controller 104 is also coupled to the host 101. The memory controller 104 can manage data stored in the memory 103 and communicate with the host 101.

[0128] In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0129] In some embodiments, the memory controller 104 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0130] The memory controller 104 can be configured to control operations of the memory 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions relating to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 104 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 103.

[0131] The memory controller 104 can also perform any other suitable functions, such as formatting the memory 103. The memory controller 104 can communicate with external devices (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0132] The memory controller 104 and one or more memories 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 100 can be implemented and packaged into different types of end electronic products.

[0133] In such Figure 6a In one example shown, the memory controller 104 and a single memory 103 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 5 The memory card connector 204 is coupled to the host 101.

[0134] In such Figure 6b In another example shown, the memory controller 104 and multiple memories 103 may be integrated into a solid-state drive (SSD) 206. The solid-state drive 206 may also include a connection between the solid-state drive 206 and a host (e.g., Figure 5 The solid-state drive connector 208 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0135] It is understood that the memory controller 104 may execute the bad block management method as provided in any embodiment of the present disclosure, or execute the control method as provided in any embodiment of the present disclosure.

[0136] In some embodiments, refer to Figure 5 As shown, the memory controller 104 includes:

[0137] Bad block management module 1041 is used to manage bad blocks generated in memory 103.

[0138] The bad block management module 1041 can map the address of a bad block generated in memory 103 to the address of a target replacement block, and replace the bad block with the target replacement block, which is a normal block.

[0139] The bad block management module 1041 can refresh and update the address mapping table that represents the mapping relationship between logical addresses and physical addresses. Through this refresh and update, the bad block management module 1041 can translate the logical address of a bad block into the physical address of the target replacement block, so that the logical address of the bad block corresponds to the physical address of the target replacement block, and can store the updated address mapping table in the memory controller 104 or the memory 103. Therefore, when a data access request (e.g., a read request) for a bad block is received from the host 101, the memory controller 104 can provide the physical address of the target replacement block to the memory 103 with reference to the updated address mapping table.

[0140] Figure 7 This is a schematic diagram illustrating a memory 300 according to an embodiment of the present disclosure. (Refer to...) Figure 7 As shown, the memory 300 includes:

[0141] The storage cell array 301 includes a plurality of storage cells 306;

[0142] Multiple word lines 318 are coupled to multiple memory cells 306 respectively;

[0143] Peripheral circuitry 302 is coupled to a plurality of word lines 318 and configured to perform the control method of any of the above embodiments on selected memory cell rows among a plurality of memory cells 306.

[0144] The memory cell array 301 may be a NAND flash memory cell array, wherein the memory cell array 301 is provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0145] In some embodiments, each storage cell 306 is a single-level cell having two possible storage states and thus being able to store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range.

[0146] In some embodiments, each storage cell 306 is a cell capable of storing more than a single bit of data in more than four storage states. For example, two bits per cell (also known as a multi-level cell), three bits per cell (also known as a three-level cell), or four bits per cell (also known as a four-level cell) can be stored. Each multi-level cell can be programmed to take a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0147] like Figure 7 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The source select gate 310 and drain select gate 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0148] In some embodiments, the sources of NAND flash memory strings 308 in the same memory area 304 are coupled through the same source line (SL) 314 (e.g., common SL). In other words, according to some implementations, all NAND flash memory strings 308 in the same memory area 304 have an array common source (ACS).

[0149] In some embodiments, the drain-select gate 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).

[0150] In some embodiments, each NAND flash memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 312) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 312 via one or more DSG lines 311. And / or, in some embodiments, each NAND flash memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 310) or a deselect voltage (e.g., 0V) to the corresponding source select gate 310 via one or more SSG lines 315.

[0151] like Figure 7 As shown, the NAND storage string 308 can be organized into multiple block storage areas 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block storage area 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same block storage area 304 are erased simultaneously. To erase memory cells 306 in a selected block storage area, a source line of the selected block storage area and the unselected block storage areas on the same storage plane as the selected block storage area can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0152] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0153] In some embodiments, each word line 318 is coupled to a page memory region 320 of a memory cell 306, the page memory region 320 being the basic data unit for programming operations. The size of a page memory region 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block memory region 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page memory region 320, as well as gate lines coupling the control gates. It is understood that a memory cell row is a plurality of memory cells 306 located in the same page memory region 320.

[0154] Figure 8 A side view of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 8 As shown, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0155] The memory stack layer 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack layer 404 determines the number of memory cells 306 in the memory cell array 301.

[0156] The gate conductive layer 406 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a DSG line 311, at the bottom of the memory stack 404 as an SSG line 315, or between the DSG line 311 and the SSG line 315 as a word line 318.

[0157] like Figure 8 As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as storage film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polycrystalline silicon. In some embodiments, the storage film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0158] In some embodiments, such as Figure 8 As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although in Figure 8 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0159] Return to reference Figure 7 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 311. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 311.

[0160] Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 9 Some exemplary peripheral circuitry 302 is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line (BL) driver 506, a row decoder / word line (WL) driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 9 Additional peripheral circuitry not shown.

[0161] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page memory area 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0162] The line decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect the block memory area 304 of the memory cell array 301 and the word line 318 of the block memory area 304. The line decoder / word line driver 508 can also be configured to use the word line voltage (V) generated from the voltage generator 510.WL The line decoder / word line driver 508 can also select / deselect and drive SSG line 315 and DSG line 311. As described in detail below, the line decoder / word line driver 508 is configured to perform an erase operation on memory cell 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic unit 512 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0163] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0164] It should be emphasized that the peripheral circuit 302 is configured to perform the control method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0165] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0166] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0167] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0168] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0169] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0170] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for bad block management in a memory, characterized in that, The memory includes a die, which includes multiple storage surfaces. Each storage surface includes multiple block storage areas. A set of multiple block storage areas located at the same position in different storage surfaces within the die constitutes a virtual block group. The memory includes a hidden region, a storage region, and a reserved region. The reserved region includes virtual block groups n+1 to m, where n is less than m, and both n and m are natural numbers. The method includes: When a bad block is detected in the storage area, the target storage surface where the bad block is located is determined; When all the first replacement blocks in the hidden area of ​​the target storage surface are occupied, the (n+1)th virtual block group in the reserved area is determined as the current bad block replacement group, and the second replacement block in the (n+1)th virtual block group located in the target storage surface is used as the target replacement block to replace the current bad block; Release the second replacement block in the (n+1)th virtual block group, excluding the target replacement block; wherein the released second replacement block is used to store data.

2. The bad block management method according to claim 1, characterized in that, After replacing the current bad block with the target replacement block in the (n+1)th virtual block group, the method further includes: The (n+2)th virtual block group in the reserved area is determined as the next bad block replacement group; Releasing the second replacement block in the (n+1)th virtual block group, excluding the target replacement block, includes: An erasure operation is performed on the second replacement block in the (n+1)th virtual block group, excluding the target replacement block, and the erased second replacement block is used as a storage block; wherein the storage block is used to store the data.

3. The bad block management method according to claim 1, characterized in that, The method is applied to a memory comprising a plurality of said dies; wherein each of the virtual block groups comprises a plurality of block storage areas located at the same position in different storage planes within the plurality of said dies.

4. The bad block management method according to claim 1, characterized in that, When replacing the current bad block with the target replacement block in the (n+1)th virtual block group, the method further includes: Determine the address of the target replacement block; Generate a target replacement block address table based on the address of the target replacement block; Save the target replacement block address table to the bad block table.

5. The bad block management method according to claim 1, characterized in that, The method further includes: When there is a usable first replacement block in the hidden area of ​​the target storage surface, the current bad block is replaced by the first replacement block located in the target storage surface.

6. The bad block management method according to claim 5, characterized in that, When replacing the current bad block with a first replacement block located on the target storage surface, the method further includes: Determine the address of the first replacement block to replace the currently bad block; Generate a first replacement block address table based on the address of the first replacement block; Save the first replacement block address table to the bad block table.

7. The bad block management method according to claim 1, characterized in that, When a bad block is detected in the storage area, determining the target storage surface where the bad block is located includes: The memory is tested to obtain the test results; When the detection result indicates that a bad block has appeared in the storage area, the bad block address is determined, and the target storage surface is determined based on the bad block address.

8. A method for controlling a memory, characterized in that, When a bad block is detected in the storage area of ​​the memory, the bad block is managed by the management method as described in any one of claims 1 to 7, the control method comprising: Obtain the address of the target replacement block; Based on the address of the target replacement block, a control signal is applied to the target replacement block.

9. The control method according to claim 8, characterized in that, The control method includes at least one of the following: a programming method for performing programming operations on the memory; a reading method for performing reading operations on the memory; An erasure method for performing an erasure operation on the memory; Applying the control signal to the target replacement block includes: When performing a programming operation on the memory, a programming signal is applied to the target replacement block; When performing a read operation on the memory, a read signal is applied to the target replacement block; When performing an erase operation on the memory, an erase signal is applied to the target replacement block.

10. A memory system, characterized in that, include: The memory includes: a die, the die including multiple storage surfaces, each storage surface including multiple block storage areas, and a set of multiple block storage areas located at the same position in different storage surfaces within the die constituting a virtual block group; the memory includes a hidden region, a storage region, and a reserved region; wherein, the reserved region includes the (n+1)th virtual block group to the mth virtual block group; n is less than m, and n and m are both natural numbers; A memory controller includes: coupled to the memory and configured to perform the bad block management method as claimed in any one of claims 1 to 7, or configured to perform the control method as claimed in claim 8 or 9.

11. The memory system according to claim 10, characterized in that, The memory controller includes: The bad block management module is used to manage bad blocks generated in the memory.

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