Semiconductor device and method of manufacturing the same

Abstract

A semiconductor structure, a semiconductor device, and a method of manufacturing the same are disclosed. An exemplary method of manufacturing includes forming a stack of a first type epitaxial layer and a second type epitaxial layer on a front side of a semiconductor substrate; patterning the stack to form a fin structure; depositing a dielectric layer on sidewalls of the fin structure; and recessing the dielectric layer to expose a top portion of the fin structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary method of manufacturing further includes forming a gate structure above the top portion of the fin structure; etching the semiconductor substrate from a back side of the semiconductor substrate; and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through a trench.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (the number of interconnects per chip area) has generally increased, while its geometry (the smallest element (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down generally benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology has evolved towards smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices in which a gate structure (also called a gate stack) or a portion thereof is positioned above multiple sides of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. In a FinFET, the high-side channel is surrounded above multiple sides by a gate structure (e.g., the gate surrounds the top and sidewalls of a semiconductor material “fin” extending from the substrate). The gate structure of an MBC transistor may extend partially or entirely around the channel region to provide access to the channel regions on both sides or more. Because the gate structure of an MBC transistor surrounds the channel region, MBC transistors are also referred to as gate-all-around (SGT) transistors or gate-all-around (GAA) transistors.

[0004] MBC transistors in different regions or circuit sections of an IC chip have different functions, such as input / output (I / O) functions and core functions. These different functions require transistors with different structures. Simultaneously, it is advantageous to have similar processes and similar process windows to manufacture these different transistors to reduce costs and increase yield. For example, an IC chip may include high-power regions for high-performance computing (HPC) units or central processing units (CPUs), which require MBC transistors with strong current drive capabilities to achieve high operating speeds, and IC chips may include low-power regions for I / O or system-on-chip (SoC) units, which require MBC transistors with smaller current drive capabilities to achieve low capacitance and low leakage performance. Therefore, the required number of channel components for MBC transistors in different regions of an IC chip may differ. Generally, MBC transistors with more channel components provide stronger current drive capabilities, and vice versa. Therefore, in the evolution of ICs, how to achieve the appropriate number of different channel components for different applications on a single IC chip is a challenge facing the semiconductor industry. Simultaneously, it is advantageous to have similar processes and similar process windows to manufacture these different transistors to reduce costs and increase yield. Therefore, although existing semiconductor devices are generally sufficient to meet their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a stack of a first type epitaxial layer and a second type epitaxial layer on the front side of a semiconductor substrate, the first type epitaxial layer and the second type epitaxial layer having different material compositions, the first type epitaxial layer and the second type epitaxial layer being alternately disposed in a vertical direction; patterning the stack to form a fin structure; depositing a dielectric layer on the sidewalls of the fin structure; recessing the dielectric layer to expose a top portion of the fin structure, wherein the top surface of the recessed dielectric layer is located above the bottom surface of the stack; forming a gate structure above the top portion of the fin structure; etching the semiconductor substrate from the back side of the semiconductor substrate to form trenches between the dielectric layers, the trenches exposing the bottom surface of the stack; and etching at least the bottommost first type epitaxial layer and the bottommost second type epitaxial layer through the trenches.

[0006] According to another aspect of the present invention, a method of manufacturing a semiconductor device is provided, comprising: forming a first plurality of channel members over a first region of a substrate, the first plurality of channel members being vertically stacked; forming a second plurality of channel members over a second region of the substrate, the second plurality of channel members being vertically stacked; forming an isolation member in the first region and the second region, wherein the top surface of the isolation member is higher in the second region than in the first region, such that a portion of the second plurality of channel members is located below the top surface of the isolation member in the second region; forming a first gate structure bonded to the first plurality of channel members, thereby forming a first transistor in the first region; forming a second gate structure bonded to the second plurality of channel members, thereby forming a second transistor in the second region; and removing a portion of the second plurality of channel members from the second region, such that the number of the first plurality of channel members in the first transistor is greater than the number of the second plurality of channel members in the second transistor.

[0007] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first gate structure bonded to a first plurality of channel members; a second gate structure bonded to a second plurality of channel members; a first back dielectric member disposed directly below the first gate structure; and a second back dielectric member disposed directly below the second gate structure, wherein the number of the first plurality of channel members is greater than the number of the second plurality of channel members. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1A and Figure 1B A flowchart illustrating an example method for manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0010] Figure 2 A perspective view of a semiconductor device according to one or more aspects of the present invention is shown.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6A , Figure 6B , Figure 6C , Figure 6D、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 21E 、 Figure 21F 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 25E , Figure 25F , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 26E , Figure 26F , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C and Figure 28D This illustrates one or more aspects of the invention. Figure 1A and Figure 1B During each manufacturing stage of the method in Figure 2 A partial cross-sectional view of a semiconductor device. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, reference numerals and / or characters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, the formation of components on, connected to, and / or coupled to another component in subsequent embodiments of the invention may include embodiments in direct contact with the component, or embodiments formed as inserts into the component such that the components do not directly contact each other. Furthermore, for ease of description, spatially relative terms, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “below,” “upward,” “downward,” “below,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to describe the relationship between one component and another. Spatially relative terms are intended to cover different orientations of devices including components. Furthermore, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., the term is intended to cover numbers within a reasonable range, including the described number, such as the described number or other values ​​as understood by those skilled in the art, within + / -10%. For example, the term “about 5 nm” covers a size range from 4.5 nm to 5.5 nm.

[0014] This invention generally relates to semiconductor devices and their fabrication, and more specifically to integrated circuit (IC) chips having transistors with different numbers of channel elements in different regions to suit different applications on a single chip. In various embodiments, multi-bridge channel (MBC) transistors with different (variable) numbers of channel elements on the same substrate are respectively placed in a first region (e.g., a core region for high-power applications) and a second region (e.g., an I / O region for low-leakage applications) within an IC chip. According to various aspects of the invention, different numbers of channel elements can be implemented from the back side of the semiconductor structure. Although embodiments comprising stacked semiconductor channel layers in the form of nanowires or nanosheets are shown as channel elements in the figures, the invention is not limited thereto and is applicable to other multi-gate devices, such as other types of MBC transistors or FinFETs.

[0015] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1A and Figure 1B A flowchart of a method 100 for forming a semiconductor device is shown together. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after these methods, and some steps described may be replaced, eliminated, or moved for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 28D Description method 100, Figures 2 to 28DPartial perspective and cross-sectional views of workpiece 200 at different manufacturing stages according to an embodiment of method 100 are shown. Because a semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor device 200 or device 200 as the context requires.

[0016] In some embodiments, workpiece 200 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable elements, or combinations thereof. For clarity, simplification has been implemented. Figures 2 to 28D To better understand the inventive concept of the present invention, additional components may be added to workpiece 200, and certain components described below may be replaced, modified, or eliminated in other embodiments of workpiece 200. Workpiece 200 includes a first region (also referred to as Region I) for high-power and / or high-speed applications, such as a core region requiring strong current drive capability, and a second region (also referred to as Region II) for low-capacitance and / or low-leakage applications, such as an I / O region requiring weaker current drive capability. Region I may include high-performance computing (HPC) units, central processing unit (CPU) logic circuitry, memory circuitry, and other core circuitry. Region II may include I / O units, ESD units, and other circuitry.

[0017] Figure 2 A perspective view of workpiece 200 is shown, and Figures 3A to 28D Showing separately along Figure 2 The diagram shows cross-sectional views of workpiece 200 containing lines AA, BB, CC, DD, EE, and FF. Specifically, lines AA and BB are partial cross-sectional views (i.e., cross-sections in the YZ plane of the channel region along the length of the gate structure and perpendicular to the length of the channel member) of the transistor to be formed in regions I and II, respectively; lines CC and DD are partial cross-sectional views (i.e., cross-sections in the XZ plane along the length of the channel member and passing through the channel region and the adjacent source / drain region) of the transistor to be formed in regions I and II, respectively; lines EE and FF are partial cross-sectional views (i.e., cuts in the YZ plane of the source or drain region perpendicular to the longitudinal direction of the channel member) of the transistor to be formed in regions I and II, respectively. In this invention, the source and drain are interchangeable.

[0018] refer to Figure 2 and Figures 3A to 3D Method 100 includes a frame 102 for receiving workpiece 200. Figure 1A The workpiece 200 includes a substrate 202 and a stack 204 disposed on the substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). In various embodiments, the substrate 202 is a substrate that extends continuously from region I to region II.

[0019] The stack 204 may include alternating channel layers 208 and sacrificial layers 206 over a substrate 202, and a top sacrificial layer 206T over the sacrificial layers 206 and channel layers 208. Epitaxial processes can be used to deposit the sacrificial layers 206, channel layers 208, and top sacrificial layer 206T. Example epitaxial processes may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The channel layers 208 and sacrificial layers 206 may have different semiconductor compositions. In some implementations, the channel layer 208 is formed of silicon (Si) and the sacrificial layer 206 is formed of silicon germanium (SiGe). The additional germanium (Ge) content in the sacrificial layer 206 allows for selective removal or recessing of the sacrificial layer 206 without materially damaging the channel layer 208. The sacrificial layers 206 and channel layers 208 are alternately disposed such that the sacrificial layers 206 and channel layers 208 are staggered. Figure 2 The alternating and vertically arranged sacrificial layers 206 (three layers) and channel layers 208 (three layers) are shown for illustrative purposes only and are not intended to exceed the limitations set forth in the claims. The number of layers depends on the desired number of channel layers 208 of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 7.

[0020] Like sacrificial layer 206, top sacrificial layer 206T can be formed of silicon germanium (SiGe). In some examples, sacrificial layer 206 and top sacrificial layer 206T have essentially the same composition. Top sacrificial layer 206T can be thicker than sacrificial layer 206 and serves to protect stack 204 from damage during the manufacturing process. In some examples, the thickness of top sacrificial layer 206T can be between about 20 nm and about 40 nm, while the thickness of sacrificial layer 206 can be between about 4 nm and about 15 nm.

[0021] refer to Figures 4A to 4C Method 100 includes box 104 ( Figure 1A In this process, the stack 204 and substrate 202 are patterned to form fin-like structures 210 separated by fin trenches 212. To pattern the stack 204 and substrate 202, a hard mask layer 214 is deposited over the top sacrificial layer 206T. The hard mask layer 214 is then patterned to serve as an etch mask to pattern the top portions of the top sacrificial layer 206T, the stack 204, and the substrate 202. In some embodiments, the hard mask layer 214 may be deposited using CVD, plasma-enhanced CVD (PECVD, atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or a suitable deposition method). The hard mask layer 214 may be a single layer or multiple layers. When the hard mask layer 214 is multilayered, it may include pad oxide and pad nitride layers. In an alternative embodiment, the hard mask layer 214 may include silicon (Si). The fin structure 210 can be patterned using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, allowing the creation of patterns with pitches smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using photolithography. A self-alignment process is used to form spacers alongside the patterned material layer. The material layer is then removed, and the remaining spacers or mandrels can be used to pattern a hard mask layer 214, which can then be used as an etching mask to etch the stack 204 and the substrate 202 to form the fin structure 210. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0022] Still referencing Figures 4A to 4DEach of the fin structures 210 includes a base portion 210B formed by a portion of the substrate 202 and a top portion 210T formed by the stack 204. The top portion 210T is disposed above the base portion 210B. The fin structures 210 extend longitudinally along the X direction and vertically along the Z direction from the substrate 202. Along the Y direction, the fin structures 210 are separated by fin trenches 212. In some examples, the fin trenches 212 have a width in the range of about 20 nm to about 50 nm, thereby defining the spacing between adjacent fin structures 210.

[0023] refer to Figures 5A to 5D Method 100 includes box 106 ( Figure 1A In this process, an isolation member 216 is formed in the fin trench 212. The isolation member 216 may be referred to as a shallow trench isolation (STI) member 216. In an example process for forming the isolation member 216, a dielectric material is deposited over the workpiece 200 while the fin trench 212 is filled with the dielectric material. In some embodiments, the dielectric material may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In various examples, at block 106, the dielectric material may be deposited by flowable CVD (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process until the hard mask layer 214 is exposed.

[0024] After planarization, the deposited dielectric material is recessed in the etch-back process until some of the sacrificial layers 206 and channel layers 208 in the top portion of the fin structure 210 rise above the isolation member 216. In contrast, the base portion 210B remains completely covered by the isolation member 216 and the remaining portion of the sacrificial layers 206 and channel layers 208 in the bottom portion of the fin structure 210. As will be discussed in further detail below, although the number of channel layers 208 appears the same in zones I and II, the channel layers 208 in zone II that are completely or partially covered by the isolation member 216 will later be removed from the back side of the workpiece 200. Specifically, in the illustrated embodiment, the bottom sacrificial layer 206 is completely covered by the isolation member 216 and the bottom channel layer 208 is partially covered by the isolation member 216, and the bottom channel layer 208 will be removed, such that the number of channel layers 208 in zone II will be one less than the number of channel layers in zone I. In various embodiments, by not raising more of the bottom channel layers 208 completely above the isolation member 216, the number of channel layers 208 in region II will be further reduced, such as by one to four fewer layers than in region I. In other words, as shown below, the height of the isolation member 216 is used to control the number of channel layers 208 that will be removed from region II. The difference in the number of channel layers in regions I and II is determined by device performance requirements. The etch-back process at block 106 may include, for example, wet etching, dry etching, reactive ion etching, or other suitable etching methods. The hard mask layer 214 may also be removed in the etch-back process.

[0025] refer to Figures 6A to 6D Method 100 includes box 108 ( Figure 1A In this process, the isolation component 216 in region I is further recessed during the etch-back process until the stack 204 rises completely above the isolation component 216. As shown in the illustrated embodiment, the base portion 210B in region I may also be partially exposed. The etch-back process may include, for example, wet etching, dry etching, reactive ion etching, or other suitable etching methods. The distance ΔH of the further recess may range from about 5 nm to about 30 nm. To limit the etch-back process in region I, a mask layer 214 may first be deposited (e.g., by spin coating) to cover region II. In some embodiments, the mask layer 214 is a photoresist layer, such as a base antireflective coating (BARC) layer. After the isolation component 216 in region I is further recessed, the mask layer 214 may be removed during an etching process or other suitable processes such as ashing or resist stripping.

[0026] refer to Figures 7A to 7D , Figures 8A to 8D and Figures 9A to 9D Method 100 includes a frame 110 for forming dielectric fins 218. Figure 1AIn the illustrated embodiment, at frame 110, a dielectric fin 218 is formed in the fin trench 212. An example process for forming the dielectric fin 218 includes conformally depositing an overlay layer 220 (e.g., Figures 7A to 7D As shown), a first dielectric layer 222 is conformally deposited and a second dielectric layer 224 is deposited in the fin trench 212 (as shown). Figures 8A to 8D As shown), and a high-k dielectric layer 226 is deposited on top of the first dielectric layer 222 and the second dielectric layer 224 (as shown). Figures 9A to 9D (As shown).

[0027] A cladding layer 220 is deposited over workpiece 200, including over the sidewalls of the stack 204 and the top portion of the base portion 210B in region I, and partially over the sidewalls of the stack 204 in region II. In some embodiments, the cladding layer 220 may have a composition similar to that of the sacrificial layer 206 or the top sacrificial layer 206T. In one example, the cladding layer 220 may be formed of silicon germanium (SiGe). Their common composition allows for the selective simultaneous removal of the sacrificial layer 206 and the cladding layer 220 in a subsequent etching process. In some embodiments, the cladding layer 220 may be conformally and epitaxially grown using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Figures 7A to 7D As shown, the cladding layer 220 is selectively disposed on the exposed sidewall surface in the fin trench 212. Depending on the degree of selective growth of the cladding layer 220, an etch-back process can be performed to expose the isolation component 216.

[0028] An example process for forming the dielectric fin 218 further includes sequentially conformally depositing a first dielectric layer 222 and a second dielectric layer 224 over the workpiece 200. The second dielectric layer 224 is surrounded by the first dielectric layer 222. The first dielectric layer 222 can be conformally deposited using CVD, ALD, or a suitable method. The first dielectric layer 222 is reinforced with sidewalls and a bottom surface of the fin trench 212. The second dielectric layer 224 is then conformally deposited over the first dielectric layer 222 using CVD, high-density plasma CVD (HDPCVD), flowable CVD (FCVD), and / or other suitable processes. In some examples, the dielectric constant of the second dielectric layer 224 is less than that of the first dielectric layer 222. The first dielectric layer 222 may comprise silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, or a suitable dielectric material. In one embodiment, the first dielectric layer 222 comprises aluminum oxide. The second dielectric layer 224 may comprise silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or a suitable dielectric material. In one embodiment, the second dielectric layer 224 comprises silicon oxide. In some examples, such as Figures 8A to 8DAs shown, after depositing dielectric layers 222 and 224, a CMP process can be performed to remove excess material and planarize the top surface of workpiece 200, thereby exposing the top sacrificial layer 206T.

[0029] An example process for forming the dielectric fin 218 may further include depositing a high-k dielectric layer 226. In some examples, a recess process is performed to remove the top portions of dielectric layers 222 and 224. The recess process may include a dry etching process, a wet etching process, and / or a combination thereof. In some embodiments, the recess depth is controlled (e.g., by controlling the etching time) to produce a desired recess depth. After performing the recess process, a high-k dielectric layer 226 is deposited within the trench formed by the recess process. In some embodiments, the high-k dielectric layer 226 may include HfO2, ZrO2, or HfAlO2. x HfSiO x Y₂O₃, Al₂O₃, or another high-k material. The high-k dielectric layer 226 can be deposited using CVD, ALD, PVD, and / or other suitable processes. For example... Figures 9A to 9D As shown, after depositing the high-k dielectric layer 226, a CMP process is performed to remove excess material and planarize the top surface of the workpiece 200. At the end of frame 110, the dielectric fin 218 is defined as having a lower portion including recessed portions of dielectric layers 222, 224 and an upper portion including the high-k dielectric layer 226. The dielectric fin 218 is also referred to as a composite fin 218. The dielectric fins 218 in regions I and II have uneven bottom surfaces, such that the bottom surface in region I is ΔH lower than the bottom surface in region II. As described above, ΔH can range from about 5 nm to about 30 nm.

[0030] refer to Figures 10A to 10D Method 100 includes box 112 ( Figure 1A In this process, the top sacrificial layer 206T in the fin structure 210 is removed. At frame 112, the workpiece 200 is etched to selectively remove portions of the top sacrificial layer 206T and the cladding layer 220 to expose the topmost channel layer 208, without substantially damaging the dielectric fins 218. In some examples, because the top sacrificial layer 206T and the cladding layer 220 are formed of silicon germanium (SiGe), the etching process at frame 112 can be selective for silicon germanium (SiGe). For example, a selective wet etching process including ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof can be used to etch the cladding layer 220 and the top sacrificial layer 206T. After removing portions of the top sacrificial layer 206T and the cladding layer 220, the dielectric fins 218 rise above the topmost channel layer 208.

[0031] refer to Figures 11A to 11D Method 100 includes box 114 ( Figure 1AIn this embodiment, a dummy gate stack 240 is formed over the channel region of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 240 serves as a placeholder for the functional gate structure. Other processes and configurations are also possible. In the illustrated embodiment, the dummy gate stack 240 includes a dummy dielectric layer 242 and a dummy electrode 244 disposed over the dummy dielectric layer 242. For patterning purposes, a gate top hard mask 246 is deposited over the dummy gate stack 240. The gate top hard mask 246 may be multilayered and includes a silicon nitride mask layer 248 and a silicon oxide mask layer 250 above the silicon nitride mask layer 248. The region of the fin structure 210 located below the dummy gate stack 240 may be referred to as a channel region. Each channel region in the fin structure 210 is sandwiched between two source / drain regions to form a source / drain. In the example process, a dummy dielectric layer 242 is deposited over the workpiece 200 via CVD. A material layer for a dummy electrode 244 is then deposited over the dummy dielectric layer 242. A photolithography process is then used to pattern the material layers of the dummy dielectric layer 242 and the dummy electrode 244 to form a dummy gate stack 240. In some embodiments, the dummy dielectric layer 242 may comprise silicon oxide, and the dummy electrode 244 may comprise polysilicon.

[0032] Still referencing Figures 11A to 11D Method 100 includes box 116 ( Figure 1A In this process, gate spacers 252 are formed along the sidewalls of the dummy gate stack 240. Gate spacers 252 may include two or more gate spacer layers. The dielectric material used for gate spacers 252 may be selected to allow selective removal of the dummy gate stack 240. Suitable dielectric materials may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, and / or combinations thereof. In an example process, gate spacers 252 may be conformally deposited over workpiece 200 using CVD, subatmospheric CVD (SACVD), or ALD, and then anisotropically etched to remove horizontal portions, while vertical portions of gate spacers 252 remain on the sidewalls of the dummy gate stack 240.

[0033] refer to Figures 12A to 12D Method 100 includes box 118 ( Figure 1AIn this embodiment, the source / drain regions of the fin structure 210 are recessed to form source and drain grooves, which together serve as source / drain groove 254 (or source / drain trench 254). Using the dummy gate stack 240 and gate spacer 252 as etching masks, the workpiece 200 is anisotropically etched to form source / drain groove 254 above the source / drain regions of the fin structure 210. In the illustrated embodiment, the operation at block 118 removes the sacrificial layer 206 and channel layer 208 from the source / drain regions in regions I and II, thereby exposing the base portion 210B, and removes a portion of the cladding layer 220 and the isolation member 216 from region II, thereby exposing the isolation member 216. Figure 12B In comparison, because the covering layer 220 extends below the bottom sacrificial layer 206 in region I, the bottom portion of the covering layer 220 retains and covers the isolation member 216 in region I. Figure 12A Anisotropic etching at frame 118 may include a dry etching process. For example, a dry etching process may be implemented using hydrogen, oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. At the end of frame 118, the exposed top surface of the base portion 210B in zones I and II is horizontal, as... Figure 12A and Figure 12B As shown by the dashed line in the image.

[0034] refer to Figures 13A to 13D Method 100 includes frame 120, wherein a source / drain groove 254 in region I is further extended into the base portion 210B by an etching process to form a deeper source / drain groove 254D and the remaining portion of the cover layer 220 in region I is removed. To limit the etching process in region I, a mask layer 256 may first be deposited (e.g., by spin coating) to cover region II. In some embodiments, the mask layer 256 is a photoresist layer, such as a bottom antireflective coating (BARC) layer. After extending the deeper source / drain groove 254D in region I, the mask layer 256 may be removed in an etching process or other suitable processes such as ashing or resist stripping. The distance ΔH' of the further recess may be in the range of about 5 nm to about 10 nm.

[0035] refer to Figures 14A to 14DMethod 100 includes block 122, wherein an inner spacer component 258 is formed. In some embodiments, at block 122, a sacrificial layer 206 exposed in the source / drain trench 254 and deeper source / drain trench 254D is first selectively partially recessed to form an inner spacer trench, while the exposed channel layer 208 is substantially not etched. In embodiments where the channel layer 208 is substantially composed of silicon (Si) and the sacrificial layer 206 is substantially composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 may include a SiGe oxidation process followed by SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In other embodiments, the partial recessing may include a selective etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Selective wet etching processes may include ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof (e.g., APM etching including an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the inner spacer recess, CVD or ALD is then used to conformally deposit an inner spacer material layer over (and into) the workpiece 200. The inner spacer material may include silicon nitride, silicon carbonitride, silicon oxide, silicon carbide, silicon oxynitride, or silicon oxynitride. After depositing the inner spacer material layer, the inner spacer material layer is etched back to form the inner spacer component 258, as shown. Figures 14A to 14D As shown.

[0036] Still referencing Figures 14A to 14D Method 100 includes a frame 124 for forming a source / drain component 260. The source / drain component 260 is selectively and epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and the base portion 210B in the source / drain trench 254 and deeper source / drain trench 254D. The source / drain component 260 can be deposited using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some examples, the source / drain component 260 includes an undoped epitaxial layer 262 and a heavily doped epitaxial layer 264. The undoped epitaxial layer 262 is used to prevent leakage current between the heavily doped epitaxial layer 264 and the well region. In some examples, the undoped epitaxial layer 262 has a thickness of about 5 nm to about 15 nm. Due to the greater depth of the deeper source / drain trench 254D, the undoped epitaxial layer 262 is located in region I below the bottom channel layer 208. Figure 14C ) and in Zone II above the lowest channel layer 208 ( Figure 14DDepending on the desired transistor configuration, the heavily doped epitaxial layer 264 may be doped with p-type or n-type dopants. When the source / drain components 260 are n-type, the heavily doped epitaxial layer 264 may comprise silicon (Si) doped with n-type dopants such as phosphorus (P) or arsenic (As). When the source / drain components 260 are p-type, the heavily doped epitaxial layer 264 may comprise silicon germanium (SiGe) doped with p-type dopants such as boron (B) or gallium (Ga). Doping of the heavily doped epitaxial layer 264 can be performed in situ by deposition or ex-situ using implantation processes such as junction implantation. Similarly, as... Figure 14A and Figure 14B As shown, at the stepped regions of the sidewalls of the source / drain recess 254 and the deeper source / drain recess 254D, the facets of the source / drain component 260 can capture gaps 267 between the source / drain component 260 and dielectric components (such as dielectric fins 218 and isolation components 216). Subsequently, the high-k dielectric layer 226 of the dielectric fins 218 in the source / drain region is selectively removed in an etching process, such as... Figures 15A to 15D As shown. Etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0037] refer to Figures 16A to 16D Method 100 includes box 126 ( Figure 1A In this process, a contact etch stop layer (CESL) 270 and an interlayer dielectric (ILD) layer 272 are deposited on the front side of a workpiece 200. In the example process, the CESL 270 is first conformally deposited over the workpiece 200, and then the ILD layer 272 is deposited over the CESL 270. The CESL 270 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 270 may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 272 comprises tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), silicon phosphide glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 272 may be deposited by spin coating, FCVD processes, or other suitable deposition techniques. In some embodiments, after the ILD layer 272 is formed, the workpiece 200 may be annealed to improve the integrity of the ILD layer 272. In order to remove excess material (including the gate top hard mask 246) and expose the top surface of the dummy electrode 244 of the dummy gate stack 240, a planarization process (such as a CMP process) may be performed on the workpiece 200 to provide a flat top surface.

[0038] refer to Figures 17A to 17DMethod 100 includes box 128 ( Figure 1A In this process, dummy gate stack 240 is selectively removed. The dummy gate stack 240 exposed at the end of frame 126 is removed from workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 242 and the dummy electrode 244 without substantially damaging the channel layer 208 and the gate spacer 252. Removal of the dummy gate stack 240 creates a gate trench 266 over the channel region. After removal of the dummy gate stack 240, the channel layer 208, the sacrificial layer 206, and the cladding layer 220 in the channel region are exposed in the gate trench 266.

[0039] refer to Figures 18A to 18D Method 100 includes box 130 ( Figure 1A In this process, the sacrificial layer 206 and the cladding layer 220 are removed from the gate trench 266 to release the channel layer 208. It should be noted that although the sacrificial layer 206 in region I is removed, at least region II ( Figure 18B The bottom sacrificial layer 206 is retained because it is protected beneath the bottom channel layer 208 and the isolation member 216. The channel layer 208 released at the end of frame 130 is also referred to as channel member 208. In the depicted embodiment where the channel member 208 resembles a sheet or nanosheet, the channel member release process may also be referred to as a sheet formation process. The channel members 208 are stacked vertically along the Z-direction. All channel members 208 are laterally spaced from the dielectric fins 218 by a distance retained by the cladding layer 220. Selective removal of the sacrificial layer 206 and the cladding layer 220 may be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof (e.g., APM etching including a mixture of ammonium hydroxide-hydrogen peroxide-water). In some alternative embodiments, selective removal includes silicon germanium oxidation followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, and then silicon-germanium oxide can be removed by etchants such as NH4OH.

[0040] refer to Figures 19A to 19D Method 100 includes box 132 ( Figure 1AIn this configuration, a gate structure 274 (also referred to as a functional gate structure 274 or a metal gate structure 274) is formed in a gate trench 266 to engage with a channel member 208. In region I, each of the channel members 208 is surrounded by a corresponding gate structure 274. By comparison, in region II, the bottommost channel layer 208 has a top surface on which the gate structure 274 is deposited, but this top surface is not deposited on its bottom surface, which remains in contact with the bottommost sacrificial layer 206. Each of the gate structures 274 includes a gate dielectric layer 276 disposed on the channel member 208 and a gate electrode layer 278 disposed above the gate dielectric layer 276. In some embodiments, the gate dielectric layer 276 includes an interface layer and a high-k dielectric layer. The interface layer may include silicon oxide and is formed as a result of a pre-cleaning process. Example pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel component 208 to form an interface layer. A high-k dielectric layer is then deposited over the interface layer using ALD, CVD, and / or other suitable methods. The high-k dielectric layer comprises a high-k dielectric material. In one embodiment, the high-k dielectric layer may comprise hafnium oxide. Optionally, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming the gate dielectric layer 276, a gate electrode layer 278 is deposited over the gate dielectric layer 276. The gate electrode layer 278 may be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may comprise aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer 278 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes.Although not explicitly shown in the figures, gate structure 274 is deposited as a combined gate structure and then etched back until dielectric fins 218 separate the combined gate structure into individual gate structures 274. Dielectric fins 218 also provide electrical isolation between adjacent gate structures 274. The etch-back of gate structure 274 may include a selective wet etching process using nitric acid, hydrochloric acid, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or combinations thereof. Although in the illustrated embodiment the top surface of gate structure 274 after the etch-back process is flush with the bottom surface of high-k dielectric layer 226, in alternative embodiments the top surface process of gate structure 274 after etch-back may be located below the bottom surface of high-k dielectric layer 226. The etch-back of gate structure 274 may also include etching back the high-k dielectric layer 226 of dielectric fins 218 in the channel region.

[0041] refer to Figures 20A to 20D Method 100 includes box 134 ( Figure 1B The process involves forming a metal protective layer 280, a self-aligned protection (SAC) layer 282, and a gate dicing member 284 on the front side of workpiece 200. In some embodiments, the metal protective layer 280 may comprise titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), cobalt (Co), or nickel (Ni), and may be deposited using PVD, CVD, or metal-organic chemical vapor deposition (MOCVD). In one embodiment, the metal protective layer 280 comprises tungsten (W), such as fluorine-free tungsten (FFW), and is deposited via PVD. In some alternative embodiments where the metal protective layer 280 is deposited via MOCVD, the metal protective layer 280 may be selectively deposited on the gate structure 274. After depositing the metal protective layer 280, the SAC layer 282 is deposited over workpiece 200 via CVD, PECVD, or a suitable deposition process. The SAC layer 282 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, or a suitable dielectric material. A photolithography and etching process is then performed to etch the deposited SAC layer 282 to form a gate cleaving opening to expose the top surface of the dielectric fin 218. Subsequently, a dielectric material is deposited and planarized using a CMP process to form a gate cleaving member 284 in the gate cleaving opening. HDPCVD, CVD, ALD, or a suitable deposition technique may be used to deposit the dielectric material for the gate cleaving member 284. In some examples, the gate cleaving member 284 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, or a suitable dielectric material. In some embodiments, the gate dicing component 284 and the SAC layer 282 may have different compositions to introduce etch selectivity.

[0042] refer to Figures 21A to 21F Method 100 includes box 136 ( Figure 1B The process involves performing one or more front-side middle-end (MEOL) and front-side back-end (BEOL) processes to form one or more interconnect layers having contacts, vias, and metal lines (also referred to as metal wiring layers) embedded in dielectric layers. In some embodiments, the operation at block 136 includes forming source / drain contacts 286, gate contacts 288, an additional ILD layer 290, and a metal wiring layer 292. The workpiece 200 may also include a passivation layer and / or other layers formed on the front side of the workpiece 200. These layers and one or more interconnect layers connect the gates, sources, and drains of various transistors, as well as other circuitry in the workpiece 200, to partially or completely form an integrated circuit.

[0043] refer to Figures 22A to 22D Method 100 includes box 138 ( Figure 1B In this embodiment, a carrier 294 is attached to the front side of a workpiece 200. In some embodiments, the carrier 294 may be a silicon wafer. The operation at block 138 may use any suitable attachment process, such as direct bonding, composite bonding, adhesive bonding, or other bonding methods. In the illustrated embodiment, a bonding oxide layer 296 and an adhesive layer 298 are formed on the front side of the workpiece 200, and the carrier 294 is attached to the front side of the workpiece 200. The operation at block 138 may also include alignment, annealing, and / or other processes. The attachment of the carrier 294 allows the workpiece 200 to be flipped upside down, such as... Figures 23A to 23D As shown. This allows the workpiece 200 to be approached from its back side for further processing. It should be noted that the workpiece 200 is shown in the following figures (i.e., Figures 24A to 26D The text is also flipped up and down.

[0044] refer to Figures 24A to 24D Method 100 includes box 140 ( Figure 1B In this process, workpiece 200 is thinned from its back side. Example thinning processes may include removing substrate 202 in a selective etching process to form trench 300 over the back side of the workpiece. In some examples, gate structure 274 (particularly gate dielectric layer 276) is exposed in trench 300 in region I, and bottom sacrificial layer 206 is exposed in trench 300 in region II. Alternatively, in region II, as in the illustrated embodiment, a thin layer of substrate 202 may remain covering bottom sacrificial layer 206, such as in an etching process controlled by the duration of the etching process. Undoped epitaxial layer 262 is also exposed and partially recessed in regions I and II. In some embodiments, the recess depth of undoped epitaxial layer 262 is controlled (e.g., by controlling the etching time) to produce a desired recess depth. The exposed surfaces of undoped epitaxial layer 262 in regions I and II may even be formed at the end of frame 140, as... Figure 24C and Figure 24D As shown. In some embodiments, the first stage of the thinning process includes a mechanical polishing process to remove a large amount of substrate 202, with the isolation member 216 serving as a mechanical polishing stop layer. Subsequently, a chemical thinning process applies etch chemicals to the back side of the workpiece to remove substrate 202, with the bottom sacrificial layer 206 serving as an etch stop layer. Similarly, in some embodiments, the chemical thinning process may be timed so that a thin layer of substrate 202 remains on the bottom sacrificial layer 206.

[0045] refer to Figures 25A to 25F Method 100 includes box 142 ( Figure 1B In this embodiment, a sacrificial layer 206 and a channel layer 208 adjacent to the sacrificial layer 206 and not surrounded by the gate structure 274 are selectively etched from trench 300 in region II. To limit the etching process in region I, a mask layer 302 may first be deposited (e.g., by spin coating) to cover region I. In some embodiments, the mask layer 302 is a photoresist layer, such as a bottom antireflective coating (BARC) layer. In the illustrated embodiment, a sacrificial layer 206 (bottom layer) and a channel layer 208 (bottom layer) are etched to expose the gate structure 274 (especially the gate dielectric layer 276) in region II. In one example, the interface layer in the gate dielectric layer 276 is further etched, and the high-k dielectric layer in the gate dielectric layer 276 is exposed in trench 300. As described above... Figures 5A to 5D As discussed, the height of the isolation component 216 in region II is used to determine the number of channel layers 208 to be removed, such that only the channel layers 208 that rise completely above the isolation component 216 are retained. In other words, depending on device performance requirements, there may be multiple gate structures 274 with channel layers 208 that are not selectively etched, such as one to four layers of channel layers 208.

[0046] The operation at frame 142 employs one or more etching processes tuned to be selective for the semiconductor materials of the sacrificial layer 206 and channel layer 208, and to leave the dielectric materials of the inner spacer component 258 and gate dielectric layer 276 unetched (or minimally etched). Furthermore, the undoped epitaxial layer 262 may be recessed in trench 300 but not completely removed to protect the heavily doped epitaxial layer 264 from damage by the etching process. The selective etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching methods. Figure 25DAs shown, the removal of the sacrificial layer 206 and the recess of the undoped epitaxial layer 262 cause the inner spacer component 258 to protrude from the back side of the workpiece 200. The end of the channel layer 208 (denoted as end 208E) located directly below the inner spacer component 258 can be retained from the anisotropic etching process and also protrude from the back side of the workpiece 200. Depending on the recess depth, the exposed surface of the undoped epitaxial layer 262 may be completely located below the end 208E or the interface sidewall of the end 208E. In some examples, the exposed surface of the undoped epitaxial layer 262 is flush with the exposed surface of the gate dielectric layer 276. In some alternative examples, the exposed surface of the undoped epitaxial layer 262 is located below the exposed surface of the gate dielectric layer 276. However, in some examples, the recess of the undoped epitaxial layer 262 is optional and can be skipped, such that the undoped epitaxial layer 262 maintains its thickness and is located above the dielectric fin 218 in the YZ plane facing the back side of the workpiece 200. Following the selective etching process at frame 142, the mask layer 302 can be removed in an etching process or other suitable processes such as ashing or resist stripping. Furthermore, because the isolation member 216 in region I is protected from additional selective etching processes by the mask layer 302, the isolation member 216 in region I can have more shaped edges compared to the isolation member in region II, which may have rounded corners. Figure 25B and Figure 25F As shown by the dashed line in the image.

[0047] refer to Figures 26A to 26F Method 100 includes box 144 ( Figure 1B In this process, a back dielectric layer 304 is deposited over the back side of the workpiece 200, and this back dielectric layer fills the trench 300. The back dielectric layer 304 significantly reduces well isolation leakage and substrate leakage between the source and drain components. In some embodiments, the deposition material of the back dielectric layer 304 includes SiN, SiOCN, SiOC, SiCN, combinations thereof, or other suitable materials. The back dielectric layer 304 can be deposited by CVD, PVD, PE-CVD, F-CVD, coating processes, or other suitable deposition techniques. After the back dielectric layer 304 is deposited, the bottom inner spacer 258 and the end 208E protrude into the back dielectric layer 304, as shown below. Figure 26D As shown. The operation at box 144 also includes performing a planarization process, such as a CMP process, to remove excess dielectric material from the back side of workpiece 200 and expose the insulating component 216.

[0048] refer to Figures 27A to 27D Method 100 includes box 146 ( Figure 1BIn this process, a carrier 308 is attached to the back side of a workpiece 200. In some embodiments, the carrier 308 may be a silicon wafer. The operation at box 146 may use any suitable attachment process, such as direct bonding, composite bonding, adhesive bonding, or other bonding methods. In the illustrated embodiment, a bonding oxide layer 306 is formed on the back side of the workpiece 200 and the carrier 308 is abutted to the back side of the workpiece 200. The operation at box 146 may also include alignment, annealing, and / or other processes. The attachment of the carrier 308 allows the workpiece 200 to be flipped back. This makes the workpiece 200 accessible again from the front side for further processing. The operation at box 146 also includes performing a front-side thinning process, such as a CMP process, to remove the front-side carrier 294 and adhesive layer 298 from the front side of the workpiece 200 and expose the front-side bonding oxide layer 296.

[0049] refer to Figures 28A to 28D Method 100 includes box 148 ( Figure 1B In this embodiment, additional manufacturing processes are performed on workpiece 200. For example, it may perform other BEOL processes to form more interconnect layers, such as front power rails, on the front side of workpiece 200. In this embodiment, damascene processes, dual damascene processes, metal patterning processes, or other suitable processes may be used to form the front power rails. The front power rails may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. The operation at block 148 may also include forming a passivation layer on the front side of workpiece 200, performing other BEOL processes, and removing the back cover carrier 308.

[0050] Still referencing Figures 28A to 28DAt the end of method 100, multiple MBC transistors are formed in regions I and II, respectively. Each MBC transistor includes a gate structure 274 bonded to one or more channel members 208. Adjacent MBC transistors are electrically separated by dielectric fins 218 and gate cleaving members 284 resting on the dielectric fins 218. Specifically, the MBC transistors in region I have more stacked channel members 208 than the MBC transistors in region II, thereby providing stronger current drive capability. This is beneficial for meeting the different current drive capability requirements of different regions of an IC chip. In addition, a back dielectric layer 304 replaces the original semiconductor substrate and incorporates isolation members 216 to define a large dielectric layer below the gate structure and source / drain members. This implementation effectively reduces well isolation leakage and substrate leakage. Due to the space saved by fewer channel members 208 in region II, the back dielectric layer 304 has a greater thickness in region II than in region I. The thickness of the source / drain members 260 in region II is less than that in region I compared to the area below. Furthermore, the bottom inner spacer member 258 in zones I and II can be horizontal, while the spacer member in zone II protrudes downward into the back dielectric layer 304 and may have rounded edges due to the additional selective etching process received in zone II. In zone II, the end 208E of the partially removed bottommost channel member 208 also protrudes downward into the back dielectric layer 304.

[0051] In one exemplary aspect, the present invention relates to a method. The method includes: forming a stack of a first type epitaxial layer and a second type epitaxial layer on the front side of a semiconductor substrate, the first type epitaxial layer and the second type epitaxial layer having different material compositions, the first type epitaxial layer and the second type epitaxial layer being alternately disposed in a vertical direction; patterning the stack to form a fin structure; depositing a dielectric layer on the sidewalls of the fin structure; recessing the dielectric layer to expose a top portion of the fin structure, the top surface of the recessed dielectric layer being above the bottom surface of the stack; forming a gate structure above the top portion of the fin structure; etching the semiconductor substrate from the back side of the semiconductor substrate to form trenches between the dielectric layers, the trenches exposing the bottom surface of the stack; and etching at least the bottommost first type epitaxial layer and the bottommost second type epitaxial layer through the trenches. In some embodiments, the bottommost first type epitaxial layer is located below the bottommost second type epitaxial layer, and the top surface of the recessed dielectric layer is located above the top surface of the bottommost first type epitaxial layer. In some embodiments, the top surface of the recessed dielectric layer is located below the top surface of the bottommost second type epitaxial layer. In some embodiments, the gate structure is a metal gate structure, and etching of at least the bottommost first-type epitaxial layer and the bottommost second-type epitaxial layer occurs after the gate structure is formed. In some embodiments, the method further includes: removing the first-type epitaxial layer from a top portion of the fin structure before forming the gate structure, and after forming the gate structure, the gate structure surrounds the second-type epitaxial layer in the top portion of the fin structure. In some embodiments, after forming the gate structure, the bottommost second-type epitaxial layer has a top surface intersecting the gate structure and a bottom surface intersecting the bottommost first-type epitaxial layer. In some embodiments, etching of at least the bottommost first-type epitaxial layer and the bottommost second-type epitaxial layer includes completely removing the bottommost first-type epitaxial layer and partially removing the bottommost second-type epitaxial layer from the trench. In some embodiments, etching of at least the bottommost first-type epitaxial layer and the bottommost second-type epitaxial layer includes etching a plurality of second-type epitaxial layers. In some embodiments, the method further includes: depositing a dielectric material in the trench, and a portion of the bottommost second-type epitaxial layer protruding into the dielectric material.

[0052] In another exemplary aspect, the present invention relates to a method of manufacturing a multi-gate device. The method includes: forming a first plurality of channel members over a first region of a substrate, the first plurality of channel members being vertically stacked; forming a second plurality of channel members over a second region of the substrate, the second plurality of channel members being vertically stacked; forming an isolation member in the first and second regions, the top surface of the isolation member being higher in the second region than in the first region, such that a portion of the second plurality of channel members is located below the top surface of the isolation member in the second region; forming a first gate structure bonded to the first plurality of channel members, thereby forming a first transistor in the first region; forming a second gate structure bonded to the second plurality of channel members, thereby forming a second transistor in the second region; and removing a portion of the second plurality of channel members from the second region, such that the number of the first plurality of channel members in the first transistor is greater than the number of the second plurality of channel members in the second transistor. In some embodiments, forming the isolation member includes: depositing a dielectric material over the sidewalls of the first plurality of channel members and the second plurality of channel members; recessing the dielectric material in the first and second regions to expose top portions of the first plurality of channel members and the second plurality of channel members; and further recessing the dielectric material in the first region such that the first plurality of channel members are completely over the dielectric material. In some embodiments, the method further includes: etching a substrate in the first and second regions to form trenches in the first and second regions, and removing portions of the second plurality of channel members to expose a second gate structure in the trenches in the second region. In some embodiments, etching the substrate exposes a first gate structure in the trenches in the first region. In some embodiments, the method further includes: forming a first source / drain member adjacent to the first plurality of channel members; and forming a second source / drain member adjacent to the second plurality of channel members, wherein the thickness of the second source / drain member is less than the thickness of the first source / drain member. In some embodiments, the method further includes: forming a first inner spacer component between a first source / drain component and a first gate structure; forming a second inner spacer component between a second source / drain component and a second gate structure; and recessing the second source / drain component such that the lowest second inner spacer component is spaced apart from the second source / drain component. In some embodiments, the first gate structure surrounds each of a first plurality of channel members in a first region, and the second gate structure surrounds each of the top portions of a plurality of second channel members in a second region.

[0053] In another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a first gate structure bonded to a first plurality of channel members; a second gate structure bonded to a second plurality of channel members; a first back-side dielectric member disposed directly below the first gate structure; and a second back-side dielectric member disposed directly below the second gate structure. The number of the first plurality of channel members is greater than the number of the second plurality of channel members. In some embodiments, the height of the first gate structure is greater than the height of the second gate structure. In some embodiments, the thickness of the first back-side dielectric member is less than the thickness of the second back-side dielectric member. In some embodiments, the semiconductor device further includes: a first inner spacer member adjacent to the first gate structure; and a second inner spacer member adjacent to the second gate structure. The bottom of the second inner spacer member extends into the second back-side dielectric member.

[0054] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A stack of a first type epitaxial layer and a second type epitaxial layer is formed on the front side of a semiconductor substrate. The first type epitaxial layer and the second type epitaxial layer have different material compositions and are alternately arranged in the vertical direction. The stacked components are patterned to form a fin-like structure; A dielectric layer is deposited on the sidewall of the fin-like structure; The dielectric layer is recessed to expose the top portion of the fin structure, wherein the top surface of the recessed dielectric layer is located above the bottom surface of the stack. A gate structure is formed above the top portion of the fin-like structure; The semiconductor substrate is etched from its back side to form trenches between the dielectric layers, the trenches exposing the bottom surface of the stack; and At least the bottom first type epitaxial layer and the bottom second type epitaxial layer are etched through the trench.

2. The method according to claim 1, wherein, The bottom first type epitaxial layer is located below the bottom second type epitaxial layer, and the top surface of the recessed dielectric layer is located above the top surface of the bottom first type epitaxial layer.

3. The method according to claim 2, wherein, The top surface of the recessed dielectric layer is located below the top surface of the bottommost second type epitaxial layer.

4. The method according to claim 1, wherein, The gate structure is a metal gate structure, and the etching of at least the bottom first type epitaxial layer and the bottom second type epitaxial layer occurs after the formation of the gate structure.

5. The method according to claim 1, further comprising: Prior to forming the gate structure, the first type of epitaxial layer is removed from the top portion of the fin structure. Wherein, after the formation of the gate structure, the gate structure surrounds the second type of epitaxial layer in the top portion of the fin structure.

6. The method according to claim 1, wherein, After the gate structure is formed, the bottom second type epitaxial layer has a top surface that intersects with the gate structure and a bottom surface that intersects with the bottom first type epitaxial layer.

7. The method according to claim 1, wherein, The etching of at least the bottom first type epitaxial layer and the bottom second type epitaxial layer includes completely removing the bottom first type epitaxial layer from the trench and partially removing the bottom second type epitaxial layer.

8. The method according to claim 1, wherein, The etching of at least the bottom first type epitaxial layer and the bottom second type epitaxial layer includes etching a plurality of second type epitaxial layers.

9. The method according to claim 1, further comprising: A dielectric material is deposited in the trench, wherein a portion of the bottommost second-type epitaxial layer protrudes into the dielectric material.

10. A method for manufacturing a semiconductor device, comprising: A first plurality of channel components are formed above a first region of the substrate, and the first plurality of channel components are stacked vertically; A second plurality of channel components are formed above a second region of the substrate, and the second plurality of channel components are stacked vertically; An isolation member is formed in the first region and the second region, wherein the top surface of the isolation member is higher in the second region than in the first region, such that a portion of the second plurality of channel members is located below the top surface of the isolation member in the second region; A first gate structure is formed in conjunction with the first plurality of channel members, thereby forming a first transistor in the first region; A second gate structure is formed in conjunction with the second plurality of channel members, thereby forming a second transistor in the second region; and The portion of the second plurality of channel members is removed from the second region such that the number of the first plurality of channel members in the first transistor is greater than the number of the second plurality of channel members in the second transistor.

11. The method according to claim 10, wherein, The formation of the isolation component includes: Dielectric material is deposited above the sidewalls of the first plurality of channel components and the second plurality of channel components; The dielectric material is recessed in the first and second regions, thereby exposing the top portions of the first plurality of channel members and the second plurality of channel members; and The dielectric material is further recessed in the first region, so that the first plurality of channel members are completely located above the dielectric material.

12. The method of claim 10, further comprising: The substrate is etched in the first region and the second region to form trenches in the first region and the second region, wherein the portion of the second plurality of channel members removed exposes the second gate structure in the trench in the second region.

13. The method according to claim 12, wherein, The etching of the substrate exposes the first gate structure in the trench in the first region.

14. The method of claim 10, further comprising: Form a first source / drain component adjacent to the first plurality of channel components; as well as A second source / drain component is formed adjacent to the second plurality of channel components, wherein the thickness of the second source / drain component is less than the thickness of the first source / drain component.

15. The method of claim 14, further comprising: A first inner spacer component is formed between the first source / drain component and the first gate structure; A second inner spacer component is formed between the second source / drain component and the second gate structure; as well as The second source / drain component is recessed, such that the bottom second inner spacer component is spaced apart from the second source / drain component.

16. The method of claim 10, wherein, The first gate structure surrounds each of the first plurality of channel members in the first region, and the second gate structure surrounds each of the top portions of the second plurality of channel members in the second region.

17. A semiconductor device, comprising: A first gate structure is coupled to a first plurality of channel components; A second gate structure is coupled to a second plurality of channel components; The first back dielectric component is disposed directly below the first gate structure; as well as The second back-side dielectric component is disposed directly below the second gate structure. Wherein, the number of the first plurality of channel components is greater than the number of the second plurality of channel components, and the thickness of the first back dielectric component below the first plurality of channel components is less than the thickness of the second back dielectric component below the second plurality of channel components.

18. The semiconductor device according to claim 17, wherein, The height of the first gate structure is greater than the height of the second gate structure.

19. The semiconductor device according to claim 17, wherein, The bottom surface of the first gate structure is lower than the bottom surface of the second gate structure.

20. The semiconductor device of claim 17, further comprising: The first inner spacer component is adjacent to the first gate structure; as well as The second inner spacer component is adjacent to the second gate structure, wherein the bottom of the second inner spacer component extends into the second back dielectric component.

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