Semiconductor device, semiconductor structure and method of forming the same

Abstract

Semiconductor devices, semiconductor structures, and methods of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source / drain components and a first number of nanostructures that are vertically stacked with respect to each other and extend longitudinally between the two first source / drain components. The second transistor includes two second source / drain components and a second number of nanostructures that are vertically stacked with respect to each other and extend longitudinally between the two second source / drain components.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, semiconductor structures, and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of handling and manufacturing ICs.

[0004] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having gate structures or portions thereof disposed above more than one side of the channel region. The multi-bridge channel (MBC) transistor is an example of a multi-gate device. An MBC transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, an MBC transistor can also be called a gate-all-around (SGT) transistor or a gate-all-around (GAA) transistor.

[0005] Due to their different performance characteristics, MBC transistors with different configurations can be used for different circuit functions. While existing MBC transistors and the methods used to form MBC transistors are generally sufficient for their intended purposes, they are not satisfactory in all aspects. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device comprising: a first transistor including: two first source / drain components and a first number of nanostructures, the first number of nanostructures being stacked perpendicularly to each other and extending longitudinally between the two first source / drain components; and a second transistor including: two second source / drain components and a second number of nanostructures, the second number of nanostructures being stacked perpendicularly to each other and extending longitudinally between the two second source / drain components, wherein the first number is less than the second number.

[0007] Another embodiment of the present invention provides a semiconductor structure, comprising: a first number of channel members disposed above a first fin structure; a first gate structure enclosing each of the first number of channel members; a second number of channel members disposed above a second fin structure, the second number being greater than the first number; a second gate structure enclosing each of the second number of channel members; a dielectric fin disposed along a first direction between the first gate structure and the second gate structure; and an isolation member disposed along the first direction between the first fin structure and the second fin structure, wherein the dielectric fin includes a first bottom surface and a second bottom surface lower than the first bottom surface.

[0008] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate including a first region and a second region; selectively forming a first punch-through (APT) layer over the first region; selectively forming a second punch-through layer over the second region; depositing a first stack of semiconductor layers over the first region and the second region; selectively removing the first stack of semiconductor layers from the second region; after the selective removal, selectively depositing a second stack of semiconductor layers over the second region; patterning the first stack of semiconductor layers and the second stack of semiconductor layers to form a first fin structure over the first region and a second fin structure over the second region; after the patterning, depositing an isolation member over the substrate; and selectively etching back the isolation member over the second region such that the isolation member over the first region has a first thickness and the isolation member over the second region has a second thickness less than the first thickness. Attached Figure Description

[0009] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0010] Figure 1A and Figure 1B A flowchart of a method for forming a semiconductor device according to one or more aspects of the present invention is shown.

[0011] Figures 2 to 30 It is shown that, according to one or more aspects of the present invention, Figure 1A and Figure 1B Partial cross-sectional views of the workpiece during each manufacturing stage in the method.

[0012] Figures 31 to 36Interface regions of different MBC transistors according to one or more aspects of the present invention are shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0015] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with that value, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Further, the invention may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0016] MBC transistors may include multiple channel components serving as channels and a gate structure enclosing each channel component. Channel components may appear in the form of nanowires, nanosheets, nanorods, or other nanostructures. MBC transistors with different numbers of channel components have different properties. For example, an MBC transistor with two channel components can be compared to an MBC transistor with three channel components. The additional channel components in a 3-channel MBC transistor can help increase the on-state current, but the increased overlap between the gate structure and the drain may lead to increased parasitic capacitance and slower speed. A 2-channel MBC transistor has a smaller on-state current but smaller parasitic capacitance. It can be seen that 3-channel MBC transistors are more suitable for high-current applications, while 2-channel MBC transistors are more suitable for high-speed AC applications. This invention provides a method for forming hybrid devices comprising MBC transistors with different numbers of channel components. The method of this invention addresses various process challenges in forming different MBC transistors in different regions of a substrate.

[0017] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1A and Figure 1B A flowchart of a method 100 for forming a semiconductor device is shown together. Method 100 is merely an example and is not intended to limit the invention to what is explicitly described in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 30 Description method 100, Figures 2 to 30 Partial cross-sectional views of workpiece 200 at different stages of manufacturing according to an embodiment of method 100 are shown. Because a semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor device 200 or semiconductor structure 200, depending on the context. Figures 2 to 30 In this invention, the X, Y, and Z directions are perpendicular to each other and are used consistently. Furthermore, throughout the invention, the same reference numerals are used to denote the same components.

[0018] refer to Figure 1A and Figure 2 Method 100 may optionally include block 102, wherein a first punch-through (APT) layer 204 is formed over a first region 202A of substrate 202. Figure 2As shown, the operation of method 100 is performed on a workpiece 200 including a substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Example group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer (such as a silicon oxide layer) to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure. The substrate 202 includes a first region 202A and a second region 202B for forming MBC transistors of different configurations.

[0019] At frame 102, a first patterned mask 203 is formed over workpiece 200 to cover second region 202B and expose first region 202A. The first patterned mask 203 serves as an ion implantation mask and may include photoresist, a metal layer, a bottom anti-reflective coating (BARC) layer, or a carbon-containing layer. To form a first APT layer 204 over first region 202A, a first ion implantation process 300 is performed on workpiece 200, while second region 202B is protected by the first patterned mask 203. The first ion implantation process 300 is configured to form the first APT layer 204 near the top surface of first region 202A. In some embodiments, the first ion implantation process 300 includes a first ion energy between approximately 2 keV and approximately 100 keV, and a first ion energy at approximately 1 x 10⁻⁶ keV. 13 ions / cm 2 1x10 15 ions / cm 2 The first ion dose and the first temperature between approximately 600°C and approximately 1100°C. The thickness of the first APT layer 204 is determined by a 1x10⁻⁶ ion layer. 18 ions / cm 3The depth region defined above is the minimum activation concentration. In some cases, the thickness of the first APT layer 204 is between about 10 nm and about 30 nm and can be detected using energy-dispersive X-ray spectroscopy (EDS, EDX, EDXS, or XEDS). Depending on the conductivity type of the MBC transistor to be fabricated over the first region 202A and the second region 202B, the first ion implantation process 300 can implant different dopant materials, and the first APT layer 204 can include different dopant materials. For example, when the MBC transistor to be fabricated is n-type, the first APT layer 204 includes p-type dopant, such as boron (B) or boron difluoride (BF2). When the MBC transistor to be fabricated is p-type, the first APT layer 204 includes n-type dopant, such as phosphorus (P) or arsenic (As). After the first ion implantation process 300, the first patterned mask 203 is removed by ashing or selective etching.

[0020] refer to Figure 1A and Figure 3 Method 100 may optionally include block 104, wherein a second punch-through (APT) layer 206 is formed in a second region 202B of substrate 202. To selectively form the second APT layer 206 in the second region 202B, a second patterned mask 205 is formed over workpiece 200 to cover the first region 202A and expose the second region 202B. Like the first patterned mask 203, the second patterned mask 205 serves as an ion implantation mask and may include photoresist, a metal layer, or a carbon-containing layer. A second ion implantation process 302 is then performed on workpiece 200 while the first region 202A is protected by the second patterned mask 205. The second ion implantation process 302 is configured to form the second APT layer 206 at a depth d from the top surface of the second region 202B. In some embodiments, the second ion implantation process 302 includes a second ion energy between about 5 keV and about 150 keV, at about 1 x 10⁻⁶ ions. 13 ions / cm 2 1x10 15 ions / cm 2 The second ion dose is between approximately 600°C and approximately 1100°C, and the second ion energy is greater than the first ion energy, and the second ion dose is greater than the first ion dose. The thickness of the second APT layer 206 is determined by a thickness of 1×10⁻⁶. 18 ions / cm 3The depth region defined above is the minimum activation concentration. In some cases, the thickness of the second APT layer 206 is between about 10 nm and about 30 nm and can be detected using energy-dispersive X-ray spectroscopy (EDS, EDX, EDXS, or XEDS). Depending on the conductivity type of the MBC transistor to be fabricated over the first region 202A and the second region 202B, the second ion implantation process 302 can implant different dopant materials, and the second APT layer 206 can include different dopant materials. For example, when the MBC transistor to be fabricated is n-type, the second APT layer 206 includes p-type dopant, such as boron (B) or boron difluoride (BF2). When the MBC transistor to be fabricated is p-type, the second APT layer 206 includes n-type dopant, such as phosphorus (P) or arsenic (As). After the first ion implantation process 300, the second patterned mask 205 is removed by ashing or selective etching. Figure 3 As shown, at depth d, the portion of the substrate 202 in the second region 202B above the second APT layer 206 can be identified as the capping layer 2020. The capping layer 2020 contains the same dopant material as the second APT layer 206, but the dopant concentration in the capping layer 2020 is less than 1 x 10⁻⁶. 18 ions / cm 3 .

[0021] refer to Figure 1A and Figure 4Method 100 includes frame 106, wherein a first stack 210A is formed over a first region 202A and a second region 202B of a substrate 202. The first stack 210A includes a first number (N1) of channel layers 208 interleaved with sacrificial layers 207. In the depicted embodiment, the first stack 210A includes two (2) channel layers interleaved with two (2) sacrificial layers and a top sacrificial layer 207T. The top sacrificial layer 207T is thicker than the other sacrificial layers 207 to protect the underlying channel layers 208 in subsequent process steps. In some embodiments, the channel layers 208 are formed of silicon (Si), and the sacrificial layers 207 (including the top sacrificial layer 207T) are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 207 (or the top sacrificial layer 207T) allows for selective removal or recessing of the sacrificial layers 207 without materially damaging the first number of channel layers 208. A sacrificial layer 207, a top sacrificial layer 207T, and a first number of channel layers 208 can be deposited using epitaxial processes. In some embodiments, a first stack 210A can be epitaxially deposited using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes). The sacrificial layer 207 (or top sacrificial layer 207T) and the channel layers 208 are deposited alternately, one after the other, to form the first stack 210A. Note that, as Figure 4 As shown, two (2) sacrificial layers 207 and two (2) channel layers 208 are arranged alternately vertically. This is for illustrative purposes only and is not intended to limit the specific enumerations in the claims. The first number (N1) of channel layers 208 can be between 2 and 7. Reference Figure 4 The first stack 210A is directly deposited on the first APT layer 204 above the first region 202A and directly deposited on the cover layer 2020 above the second region 202B.

[0022] refer to Figure 1A and Figure 5 Method 100 includes frame 108, wherein a first stack 210A above a second region 202B is selectively removed. Figure 5In some embodiments shown, a third patterned mask 209 is formed over workpiece 200 to cover the first stack 210A over the first region 202A and expose the first stack 210A over the second region 202B. The third patterned mask 209 may be a patterned photoresist layer, a patterned BARC layer, a silicon oxide layer, a silicon nitride layer, or a combination thereof. With the third patterned mask 209 in place, workpiece 200 undergoes a dry etching process employing hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, NF3, BF3, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. Figure 5 In the embodiment shown, the dry etching process at frame 108 not only removes the first stack 210A in the second region 202B but also removes the cover layer 2020, thereby exposing the second APT layer 206.

[0023] refer to Figure 1A and Figure 6Method 100 includes frame 110, in which a second stack 210B is formed over a second region 202B. While a third patterned mask 209 is still in place, the second stack 210B is deposited on a second APT layer 206 over the second region 202B. The second stack 210B includes a second number (N2) of channel layers 208 interleaved with sacrificial layers 207. In the depicted embodiment, the second stack 210B includes three (3) channel layers interleaved with three (3) sacrificial layers and a top sacrificial layer 207T. The top sacrificial layer 207T is thicker than the other sacrificial layers 207 in the second stack 210B to protect the underlying channel layers 208 in subsequent process steps. In some embodiments, the channel layers 208 are formed of silicon (Si), and the sacrificial layers 207 (including the top sacrificial layer 207T) are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 207 (or top sacrificial layer 207T) allows for selective removal or recessing of the sacrificial layer 207 without materially damaging the second number of channel layers 208. The sacrificial layer 207, the top sacrificial layer 207T, and the second number of channel layers 208 can be deposited using epitaxial processes. In some embodiments, the second stack 210B can be epitaxially deposited using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes). Due to the epitaxial nature, layers in the second stack 210B may not be deposited on the third patterned mask 209. The sacrificial layer 207 (or top sacrificial layer 207T) and the channel layers 208 are deposited alternately, one after the other, to form the second stack 210B. Note that, as Figure 6 As shown, three (3) sacrificial layers 207, three (3) channel layers 208, and a top sacrificial layer 207T are arranged alternately vertically. This is for illustrative purposes only and is not intended to limit the scope beyond what is specifically stated in the claims. The second number (N2) is greater than the first number (N1). In some embodiments, the second stack 210B includes an additional channel layer 208 compared to the first stack 210A. The second number (N2) of channel layers 208 can be between 1 and 6. Reference Figure 6 The second stack 210B is deposited directly on the second APT layer 206 above the second region 202B. After the second stack 210B is deposited, the third patterned mask 209 is removed by ashing or selective etching.

[0024] refer to Figure 1A and Figure 7Method 100 includes block 112, wherein a first stack 210A and a second stack 210B are patterned to form a first fin structure 214A over a first region 202A and a second fin structure 214B over a second region 202B. To pattern the first stack 210A, the second stack 210B, and portions of the substrate 202, a fourth patterning mask 212 is formed over a workpiece 200. The fourth patterning mask 212 is then used as an etching mask to etch the workpiece 200 to form the first fin structure 214A over the first region 202A and the second fin structure 214B over the second region 202B. The fourth patterning mask 212 may be a single layer or multiple layers. When the fourth patterning mask 212 is multiple layers, the fourth patterning mask 212 includes a first layer and a second layer disposed over the first layer. In one embodiment, the first layer may be a pad oxide layer, and the second layer may be a pad nitride layer. Figure 7 As shown, the first fin structure 214A includes a first fin structure 214AF, a first APT layer 204, and layers in the first stack 210A, and the second fin structure 214B includes a second fin structure 214BF, a second APT layer 206, and layers in the second stack 210B. The first fin structure 214AF is formed from a substrate 202 in the first region 202A and may also be referred to as the first base portion 214AF. The second fin structure 214BF is formed from a substrate 202 in the second region 202B and may also be referred to as the second base portion 214BF. Because the patterning at frame 112 removes most of the first APT layer 204 or the second APT layer 206, the first APT layer 204 in the first fin structure 214A and the second APT layer 206 in the second fin structure 214B may also be referred to as the first APT component 204 and the second APT component 206, respectively. The top sacrificial layer 207T in the first fin structure 214A and the second fin structure 214B has the same thickness and is not identified using different reference numerals.

[0025] refer to Figure 7The first fin structure 214A and the second fin structure 214B extend longitudinally along the Y direction and perpendicularly along the Z direction from the substrate 202. The first fin structure 214A and the second fin structure 214B can be patterned using suitable processes including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern a fourth patterning mask 212. The fourth patterning mask 212 is then used as an etching mask to etch the first stack 210A, the second stack 210B, and the substrate 202 to form the first fin structure 214A and the second fin structure 214B. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The dry etching process for forming the first fin structure 214A and the second fin structure 214B may include the use of hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, NF3, BF3, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof.

[0026] refer to Figure 1A and Figure 8 Method 100 includes a frame 114 in which an isolation member 216 is formed. After forming the first fin structure 214A and the second fin structure 214B, an isolation member 216 is formed between adjacent first fin structures 214A or adjacent second fin structures 214B. Figure 8 The isolation component 216 shown (e.g., in) Figures 10 to 36(As shown in the diagram). Isolation component 216 may also be referred to as shallow trench isolation (STI) component 216. In the example process, dielectric material for isolation component 216 is first deposited over workpiece 200, filling the trench between adjacent first fin structures 214A or adjacent second fin structures 214B with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric material can be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD (FCVD) processes, ALD processes, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric material is further recessed by a dry etching process to form isolation component 216. Figure 8 As shown, after recessing, the first fin structure 214A and the second fin structure 214B rise above the isolation member, while the first base portion 214AF and the second base portion 214BF are surrounded by the isolation member 216. The fourth patterned mask 212 is removed by CMP and / or recessing processes.

[0027] refer to Figure 1A and Figure 9Method 100 includes frame 116, wherein an isolation member 216 in a second region 202B is selectively recessed to form a recessed isolation member 2160 in the second region 202B. To selectively recess the isolation member 216 in the second region 202B, a fifth patterned mask 217 is formed over a workpiece 200 to cover the first region 202A and expose the second region 202B. In some embodiments, the fifth patterned mask 217 may be a photoresist layer or a BARC layer. The selective recess at frame 116 is selective for the composition of the isolation member 216 and may include fluorinated gases (e.g., CF4, SF6, CH2F2, NF3, BF3, CHF3, and / or C2F6), suitable gaseous substances, or combinations thereof. In some embodiments, the selective recess at frame 116 reduces the thickness of the isolation member 216 in the second region 202B by a difference D. In some cases, the difference D may be between about 10 nm and about 30 nm. The difference D is a multiple of the sum of the thickness of the channel layer 208 and the thickness of the sacrificial layer 207. For example, in the depicted embodiment, when the difference between the first quantity (N1) and the second quantity (N2) is 1, the difference D is equal to the sum of the thickness of the channel layer 208 and the thickness of the sacrificial layer 207. When the difference between the first quantity (N1) and the second quantity (N2) is 2, the difference D is equal to twice the sum of the thickness of the channel layer 208 and the thickness of the sacrificial layer 207. After the selective recess at frame 116, the recessed isolation member 2160 is formed in the second region 202B, while the isolation member 216 in the first region 202A remains protected by the fifth patterned mask 217. After the recessed isolation member 2160 is formed, the fifth patterned mask 217 is removed.

[0028] refer to Figure 1A and Figure 10 Method 100 includes block 118, wherein a cladding layer 218 is formed over a first fin structure 214A and a second fin structure 214B. In some embodiments, the cladding layer 218 may have a composition similar to that of the sacrificial layer 207. In one example, the cladding layer 218 may be formed of silicon germanium (SiGe). This common composition allows for the selective removal of both the sacrificial layer 207 and the cladding layer 218 in subsequent processes. In some embodiments, the cladding layer 218 may be conformally and epitaxially grown using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Figure 10 As shown, the covering layer 218 is selectively disposed on the exposed surfaces of the first fin structure 214A and the second fin structure 214B, but not on the surface of the isolation member 216 or the recessed isolation member 2160.

[0029] refer to Figure 1A , Figure 11 and Figure 12Method 100 includes a frame 120 in which dielectric fins are formed. At frame 120, a first dielectric fin 2220 is formed in a first trench 2191, and a second dielectric fin 2222 is formed in a second trench 2192. In the depicted embodiment, each of the first dielectric fin 2220 and the second dielectric fin 2222 comprises multiple layers. In an example process, a pad 220 is conformally deposited over a workpiece 200, including in the first trench 2191 and the second trench 2192, as... Figure 11 As shown. The pad 220 can be deposited using PECVD, ALD, or a suitable method. The pad 220 is lining the sidewalls and bottom of the first trench 2191 and the second trench 2192. A filler layer 222 is then deposited over the pad 220 on the workpiece 200 using CVD, SACVD, FCVD, ALD, spin coating, and / or other suitable processes. In some cases, the dielectric constant of the pad 220 is greater than that of the filler layer 222. The pad 220 may comprise silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. The filler layer 222 may comprise silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or a suitable dielectric material. After depositing the pad 220 and filler layer 222, the workpiece 200 is planarized using a planarization process (such as chemical mechanical polishing (CMP)) until a portion of the pad 220 and filler layer 222 above the overlay layer 218 is removed, such as... Figure 11 As shown. Reference Figure 12 After planarization, the filler layer 222 and the pad 220 are selectively and partially recessed to form a groove defined by the adjacent cladding layer 218. A cap layer 224 is then deposited over the workpiece 200. The cap layer 224 may include silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, or a suitable dielectric material. The workpiece 200 is then planarized using a CMP process to remove excess cap layer 224 from the cladding layer 218. At this point, a first dielectric fin 2220 and a second dielectric fin 2222 are substantially formed. Each of the first dielectric fin 2220 and the second dielectric fin 2222 includes a cap layer 224 disposed over the pad 220 and the filler layer 222. In one embodiment, the liner 220 comprises silicon nitride, the filler layer 222 comprises silicon oxide, and the cap layer 224 comprises aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, or hafnium oxide. The vertical height of the first dielectric fin 2220 and the second dielectric fin 2222 is determined by the height of the insulating member 216 or the recessed insulating member 2160. Because the recessed insulating member 2160 is lower than the insulating member 216 by a difference D, the height of the second dielectric fin 2222 exceeds the height difference D of the first dielectric fin 2220.

[0030] refer to Figure 1A and Figure 13 Method 100 includes box 122, wherein the top sacrificial layer 207T above the first region 202A and the second region 202B is removed. Figure 13 As shown, a portion of the cladding layer 218 is removed together with the top sacrificial layer 207T. Because both the cladding layer 218 and the top sacrificial layer 207T are formed of silicon-germanium (SiGe), a silicon-germanium selective etching process can be used to remove the top sacrificial layer 207T at frame 122. In one embodiment, the etching process at frame 122 may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In another embodiment, the etching process at frame 122 may include a selective dry etching process, which may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Figure 13 As shown, the removal of the top sacrificial layer 207T exposes the topmost channel layer 208 in the first region 202A and the second region 202B.

[0031] refer to Figure 1A and Figure 14Method 100 includes block 124, wherein a first dummy gate stack 231A is formed over a channel region of a first fin structure 214A, and a second dummy gate stack 231B is formed over a channel region of a second fin structure 214B. In some embodiments, a gate replacement process (or a post-gate process) is employed, wherein the first dummy gate stack 231A and the second dummy gate stack 231B serve as placeholders for a functional gate structure. Other processes and configurations are possible. Note that although the first dummy gate stack 231A and the second dummy gate stack 231B are separately labeled, they can be the same dummy gate stack spanning from the first region 202A to the second region 202B. Each of the first dummy gate stack 231A and the second dummy gate stack 231B includes a dummy dielectric layer 225 on the surface of the corresponding dielectric fin (first dielectric fin 2220 and second dielectric fin 2222) and the exposed surfaces of the cladding layer 218 and the topmost channel layer 208, and a dummy electrode 226 disposed above the dummy dielectric layer 225. For patterning purposes, a silicon nitride mask layer 228 and a silicon oxide mask layer 230 are formed above the silicon nitride mask layer 228. The regions of the first fin structure 214A and the second fin structure 214B located below the first dummy gate stack 231A and the second dummy gate stack 231B may be referred to as channel regions. For ease of reference, the channel regions in the first region 202A are labeled as first channel regions 202A-C, and the channel regions in the second region 202B are labeled as second channel regions 202B-C. In the example process, a dummy dielectric layer 225 is deposited over workpiece 200 via CVD blanket deposition. Then, a material layer for dummy electrodes 226 is deposited blanket-deposited over the dummy dielectric layer 225. The dummy dielectric layer 225 and the material layer of the dummy electrode 226 are then patterned using a photolithography process to form a first dummy gate stack 231A and a second dummy gate stack 231B. In some embodiments, the dummy dielectric layer 225 may comprise silicon oxide, and the dummy electrode 226 may comprise polycrystalline silicon.

[0032] Although Figure 14 Not explicitly shown, but block 124 also includes deposited first gate spacer 246 and second gate spacer 248. Figure 25The operation is shown in the diagram. The first gate spacer 246 and the second gate spacer 248 are formed of a dielectric material to allow selective removal of the first dummy gate stack 231A and the second dummy gate stack 231B. Suitable dielectric materials for the first gate spacer 246 and the second gate spacer 248 may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, and / or combinations thereof. In the example process, the first gate spacer 246 and the second gate spacer 248 may be conformally deposited over the workpiece 200 using CVD, subatmospheric pressure CVD (SACVD), or ALD.

[0033] refer to Figure 1A , Figure 15 and Figure 16 Method 100 includes block 126, wherein a first source / drain region 202A-SD of the first fin structure 214A is recessed to form a first source / drain groove 232, and a second source / drain region 202B-SD of the second fin structure 214B is recessed to form a second source / drain groove 234. Due to the different layer stacks, the first source / drain groove 232 and the second source / drain groove 234 are formed separately to prevent uneven source / drain grooves in different regions. In the example process, a patterned mask layer (not shown) is first formed over the second region 202B. A first dummy gate stack 231A and a first gate spacer 246 (such as...) are then... Figure 25 (as shown) and the second gate spacer 248 (as shown) Figure 25 As shown) is used as an etching mask to anisotropically etch the first region 202A of the workpiece 200 to form a first source / drain groove 232 above the first source / drain region 202A-SD, as Figure 15 As shown. Then, the patterned mask layer above the second region 202B is removed, and another patterned mask layer 233 is formed above the first region 202A to expose the second region. The second dummy gate stack 231B and the first gate spacer 246 (as shown) are then... Figure 25 (as shown) and the second gate spacer 248 (as shown) Figure 25 As shown, the second region 202B of the workpiece 200 is anisotropically etched using an etching mask to form a second source / drain groove 234 above the second source / drain region 202B-SD, as... Figure 16As shown. The anisotropic etching at box 126 can include a dry etching process or a suitable etching process. For example, a dry etching process can employ oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. Figure 15 and Figure 16 As shown, the anisotropic etching at frame 124 removes not only the first fin structure 214A in the first source / drain region 202A-SD and the second fin structure 214B in the second source / drain region 202B-SD, but also the first APT layer 204 and the second APT layer 206. Figure 25 and Figure 26 In the middle, the operation at frame 126 exposes the top surface of the first fin structure 214AF in the first source / drain groove 232 and the top surface of the second fin structure 214BF in the second source / drain groove 234.

[0034] Although not in Figure 15 and Figure 16The diagram explicitly shows that an internal spacer component 251 is formed to cover the end faces of the sacrificial layer 207 in the first channel regions 202A-C and the second channel regions 202B-C. Because the sidewall surfaces of the channel layer 208 and the sacrificial layer 207 in the first channel regions 202A-C expose the first source / drain recesses 232 and the second region 202B covered by the patterned mask layer, the sacrificial layer 207 is selectively and partially recessed to form the internal spacer recesses, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is substantially composed of silicon (Si), the sacrificial layer 207 is substantially composed of silicon germanium (SiGe), and the cladding layer 218 is substantially composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 207 and the cladding layer 218 may include a SiGe oxidation process and subsequent SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In some other embodiments, selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 207 and the overlay layer 218 is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recess, an internal spacer material layer is then conformally deposited over the workpiece 200 using CVD or ALD, including in and over the internal spacer recess and in and over the space left by the removal of the overlay layer 218. The internal spacer material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, or silicon oxynitride. After depositing the internal spacer material layer, the internal spacer material layer is etched back to form the internal spacer component 251, as... Figure 25 As shown. After forming the inner spacer component 251 in the first region, a similar process is then performed on the second region 202B to form the inner spacer component 251 in the second region 202B, as follows. Figure 25 As shown.

[0035] refer to Figure 1A and Figure 17 Method 100 optionally includes block 128, wherein a pseudo-epitaxial layer 236 is formed in a first source / drain trench 232 and a second source / drain trench 234. The pseudo-epitaxial layer 236 may include undoped silicon (Si). In other words, the pseudo-epitaxial layer 236 comprises undoped silicon (Si). The pseudo-epitaxial layer 236 can be deposited using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Figure 17As shown, a pseudo-epitaxial layer 236 is deposited on the top surfaces of the first fin structure 214AF and the second fin structure 214BF. The deposition of the pseudo-epitaxial layer 236 is selective for the semiconductor material, and it is possible that the pseudo-epitaxial layer 236 is hardly formed on the surfaces of the first dielectric fin 2220 and the second dielectric fin 2222. In embodiments excluding the pseudo-epitaxial layer 236, the operation at box 128 can be omitted. Because the pseudo-epitaxial layer 236 is undoped, it has high resistance and serves to prevent source / drain leakage to the bulk substrate 202. In embodiments where both the pseudo-epitaxial layer 236 and the APT layer are formed, they work together to prevent undesirable leakage to the substrate 202. Figure 17 As shown, due to the height difference D between the first fin structure 214AF and the second fin structure 214BF, the bottom surface of the pseudo-epitaxial layer 236 in the first region 202A is higher than the bottom surface of the pseudo-epitaxial layer 236 in the second region 202B by the difference D. In some cases, the difference D can be between approximately 10 nm and approximately 30 nm.

[0036] refer to Figure 1B , Figure 17 and Figure 18Method 100 includes block 130, wherein a first source / drain component 238 is formed in a first source / drain recess 232, and a second source / drain component 240 is formed in a second source / drain recess 234. In a first region 202A, the first source / drain component 238 is selectively and epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and the pseudo-epitaxial layer 236 in the first source / drain recess 232. In a second region 202B, the second source / drain component 240 is selectively and epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and the pseudo-epitaxial layer 236 in the second source / drain recess 234. The first source / drain component 238 or the second source / drain component 240 can be deposited using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The first source / drain component 238 or the second source / drain component 240 can be n-type or p-type. When the first source / drain component 238 and the second source / drain component 240 are n-type, they can comprise silicon (Si) and may be doped with n-type dopants such as phosphorus (P) or arsenic (As). When the first source / drain component 238 and the second source / drain component 240 are p-type, they can comprise silicon germanium (SiGe) or germanium (Ge) and may be doped with p-type dopants such as boron (B) or boron difluoride (BF2). The doping of the first source / drain component 238 and the second source / drain component 240 can be performed in situ during their deposition or off-site using an implantation process (such as a junction implantation process). Although not explicitly shown in the figures, each of the first source / drain component 238 and the second source / drain component 240 can comprise multiple layers with different dopant concentrations or even different dopant materials. Note that although the first source / drain component 238 and the second source / drain component 240 have different heights, they can be satisfactorily formed simultaneously because their formation includes a large lateral growth component from the sidewalls of the channel layer 208 (or the vertical sidewalls of the substrate 202). In some cases, during the formation of the first source / drain component 238 and the second source / drain component 240, portions of them grow laterally from the sidewalls of the channel layer 208 or the vertical sidewalls of the substrate 202 and merge near the vertical centerline of the first source / drain component 238 and the second source / drain component 240. Figure 18 As shown, due to the height difference D between the first fin structure 214AF and the second fin structure 214BF, the bottom surface of the first source / drain component 238 is higher than the bottom surface of the second source / drain component 240 by a height difference D. In some cases, the difference D can be between approximately 10 nm and approximately 30 nm.

[0037] refer to Figure 17When the pseudo-epitaxial layer 236 is deposited at frame 128, a first source / drain component 238 and a second source / drain component 240 are deposited on the pseudo-epitaxial layer 236. (Reference) Figure 18 When the pseudo epitaxial layer 236 is omitted, the first source / drain component 238 and the second source / drain component 240 are directly deposited on the top surface of the first fin structure 214AF and the second fin structure 214BF.

[0038] refer to Figure 1B and Figure 19 Method 100 includes block 132, wherein a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are deposited over a workpiece 200. In an example process, the CESL 242 is first conformally deposited over the workpiece 200, and then the ILD layer 244 is blanket-deposited over the CESL 242. The CESL 242 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 242 may be deposited using an ALD, plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 244 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)) and / or other suitable dielectric materials. The ILD layer 244 can be deposited by spin coating, FCVD, or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 244, the workpiece 200 can be annealed to improve the integrity of the ILD layer 244. To remove excess material, a planarization process (such as chemical mechanical polishing (CMP)) can be performed on the workpiece 200 to provide a flat top surface, such as... Figure 19 As shown. The top surfaces of the first dummy gate stack 231A and the second dummy gate stack 231B are exposed on a flat top surface.

[0039] refer to Figure 1B and Figure 20Method 100 includes block 134, in which a first dummy gate stack 231A and a second dummy gate stack 231B are removed, and a channel member 2080 is released. At block 134, the first dummy gate stack 231A and the second dummy gate stack 231B exposed at the end of block 132 are removed from workpiece 200 by a selective etching process. The selective etching process may be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 225 and the dummy electrode 226 without substantially damaging the first dielectric fin 2220 and the second dielectric fin 2222. The removal of the first dummy gate stack 231A and the second dummy gate stack 231B exposes the cladding layer 218, the channel layer 208, and the sacrificial layer 207 in the first channel regions 202A-C and the second channel regions 202B-C. Then, the covering layer 218 and sacrificial layer 207 in the first channel region 202A-C and the second channel region 202B-C are selectively removed to release the channel layer 208 to form the channel member 2080, as shown. Figure 20 As shown. The channel member 2080 is stacked vertically along the Z-direction. Selective removal of the sacrificial layer 207 and the cladding layer 218 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, selective removal includes silicon germanium oxidation followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, followed by removal of the silicon germanium oxide by an etchant (such as NH4OH). With the removal of the sacrificial layer 207 and the cladding layer 218 in the channel regions, the channel member 2080, the top surface of the first APT member 204, the top surface of the second APT member 206, the isolation member 216, and the recessed isolation member 2160 are exposed in the first gate trench 243 in the first channel regions 202A-C and the second gate trench 245 in the second channel regions 202B-C. Figure 20 As shown, two channel members 2080 are exposed in the first gate trench 243, while three channel members 2080 are exposed in the second gate trench 245. When the first APT layer 204 and the second APT layer 206 are not formed, the top surfaces of the first fin structure 214AF and the second fin structure 214BF are exposed in the first gate trench 243 and the second gate trench 245, respectively.

[0040] refer to Figure 1B , Figure 21 , Figure 22 and Figure 23Method 100 includes block 136, wherein a first gate structure 258 is formed over a first region 202A and a second gate structure 260 is formed over a second region 202B. Each of the first gate structure 258 and the second gate structure 260 may include an interface layer 252 over a channel member 2080, a gate dielectric layer 254 over the interface layer 252, and a gate electrode layer 256 over the gate dielectric layer 254. In some embodiments, the interface layer 252 may include silicon oxide and may be formed as a result of a pre-cleaning process. Example pre-cleaning processes may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel member 2080 to form the interface layer 252. The gate dielectric layer 254 is then deposited over the interface layer 252 using ALD, CVD, and / or other suitable methods. The gate dielectric layer 254 may include a high-k dielectric material. As used herein, high-k dielectric materials include dielectric materials with a high dielectric constant, such as a dielectric constant greater than that of thermally heated silicon oxide (~3.9). In one embodiment, the gate dielectric layer 254 may include hafnium oxide. Optionally, the gate dielectric layer 254 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming or depositing the interface layer 252 and the gate dielectric layer 254, a gate electrode layer 256 is deposited over the gate dielectric layer 254. The gate electrode layer 256 may be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may comprise aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or combinations thereof.In various embodiments, the gate electrode layer 256 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a planarization process such as CMP may be performed to remove excess material to provide a substantially flat top surface of the gate structure. Reference. Figure 22 Each channel member 2080 is enclosed by an interface layer 252, a gate dielectric layer 254, and a gate electrode layer 256 and is separated by a first dielectric fin 2220 and a second dielectric fin 2222.

[0041] Now for reference Figure 23 Then, the gate electrode layer 256 is etched back until the first dielectric fin 2220 and the second dielectric fin 2222 rise above the gate electrode layer 256 to define the first gate structure 258 above the first channel regions 202A-C and the second channel regions 202B-C. In the depicted embodiment, the gate electrode layer 256 is etched back until the cap layer 224 rises above the gate electrode layer 256. Figure 23 As shown, each first gate structure 258 encloses two vertically stacked channel members 2080 in the first channel regions 202A-C, while each second gate structure 260 encloses three vertically stacked channel members 2080 in the second channel regions 202B-C. In the depicted embodiment, the first gate structure 258 and the second gate structure 260 are respectively disposed directly on the first APT layer 204 and the second APT layer 206. In embodiments where the first APT layer 204 and the second APT layer 206 are not formed, the first gate structure 258 and the second gate structure are respectively disposed directly on the first fin structure 214AF and the second fin structure 214BF. In some alternative embodiments, the etch-back of the gate electrode layer 256 also etches back the cap layer 224.

[0042] refer to Figure 1B and Figures 24 to 26 Method 100 includes block 138, wherein a first gate top metal layer 262 is deposited on a first gate structure 258 and a second gate structure 260. At block 138, the first gate top metal layer 262 is deposited over a workpiece 200, including on exposed first gate structure 258, second gate structure 260, and cap layer 224. In some embodiments, the first gate top metal layer 262 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), aluminum (Al), cobalt (Co), nickel (Ni), or a suitable metal. The first gate top metal layer 262 may be deposited using CVD or metal-organic chemical vapor deposition (MOCVD). In one embodiment, the first gate top metal layer 262 may include fluorine-free tungsten (W) and may be deposited using MOCVD. After depositing the first gate top metal layer 262, the first dielectric fin 2220 and the second dielectric fin 2222 are etched back, as shown. Figure 24 As shown. When viewed along the X direction, the first gate top metal layer 262 is disposed between the first gate spacers 246, as... Figure 25 and Figure 26 As shown. In Figure 25 In the illustrated embodiment, a pseudo-epitaxy layer 236, a first APT layer 204, and a second APT layer 206 are all formed. Figure 25 In this configuration, the pseudo-epitaxy layer 236 is in direct contact with the first APT layer 204 and the second APT layer 206. Due to the presence of the pseudo-epitaxy layer 236, the first source / drain component 238 is spaced apart from the first APT layer 204. Similarly, the second source / drain component 240 is spaced apart from the second APT layer 206. Figure 26 In the embodiment shown, when the pseudo epitaxial layer 236 is not formed, the first source / drain component 238 is allowed to directly contact the first APT layer 204, and the second source / drain component 240 is allowed to directly contact the second APT layer 206.

[0043] In some alternative embodiments (not shown) where the cap layer 224 is etched back together with the gate electrode layer 256, the first gate top metal layer 262 may be blanket-deposited over the workpiece 200 and extend continuously over the first dielectric fin 2220 and the second dielectric fin 2222.

[0044] refer to Figure 1B and Figure 27 Method 100 includes block 140, in which a gate dicing portion 264 is formed. The gate dicing portion 264 may also be referred to as a diced metal gate (CMG) portion 264 because they are used to otherwise separate electrically connected gate segments. In some embodiments, a material layer is deposited over workpiece 200, and a gate dicing opening is formed in the material layer. Material for the gate dicing portion 264 is then deposited into the gate dicing opening. After a chemical mechanical polishing process to remove excess material over the material layer, the material layer is removed, leaving the gate dicing portion 264. The material layer may be a photoresist layer, a bottom antireflective coating (BARC) layer, a silicon oxide layer, or a silicon layer. In one embodiment, the material layer may be a silicon layer. The gate dicing portion 264 may include silicon nitride, silicon oxynitride, or a metal oxide. In one embodiment, the gate dicing portion 264 may be formed of silicon nitride. Figure 27 As shown, the gate dicing component 264 is formed directly above the first dielectric fin 2220 and the second dielectric fin 2222.

[0045] refer to Figure 1B and Figure 28Method 100 includes block 142, wherein a second gate top metal layer 266 and a third gate top metal layer 268 are formed over a first gate top metal layer 262. In some embodiments, the second gate top metal layer 266 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), aluminum (Al), cobalt (Co), or nickel (No), and the third gate top metal layer 268 is a fluorine-free tungsten (W) layer. In an example process, the second gate top metal layer 266 is first deposited over a workpiece 200 using PVD or CVD. The deposited second gate top metal layer 266 is then etched back to remove the second gate top metal layer 266 disposed over the top surface of a gate dicing member 264, thereby allowing the gate dicing member 264 to segment the second gate top metal layer 266. The second gate top metal layer 266 can be considered as a seed layer for the third gate top metal layer 268. Then, a third gate top metal layer 268 is selectively deposited over the second gate top metal layer 262 using MOCVD or CVD. At the end of the operation of block 142, a gate dicing member 264 segments the second gate top metal layer 266 and the third gate top metal layer 268. In regions where the gate dicing member 264 is not formed, the second gate top metal layer 266 and the third gate top metal layer 268 may span over dielectric fins (such as the first dielectric fin 2220 and the second dielectric fin 2222) to serve as local interconnects for coupling adjacent gate structures.

[0046] In embodiments where the cap layer 224 and gate electrode layer 256 are etched back together, the second gate top metal layer 266 and the third gate top metal layer 268 may not be formed. In those embodiments, a patterned silicon hard mask layer may be deposited over the first gate top metal layer 262, and the first gate top metal layer 262 may be etched using the patterned silicon hard mask layer to form a gate dicing opening. Dielectric material is then deposited into the gate dicing opening to form a gate dicing feature 264.

[0047] refer to Figure 1B and Figure 29 Method 100 includes block 144, wherein a self-aligned overlay (SAC) layer 270 is formed over a third gate top metal layer 268. In some embodiments, the SAC layer 270 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. The SAC layer 270 may be deposited using CVD, ALD, PEALD, or a suitable method. After depositing the SAC layer 270, chemical mechanical polishing (CMP) may be performed to remove excess SAC layer 270. Figure 29As shown, the SAC layer 270 is deposited on the third gate top metal layer 268 and remains separated by the gate dicing member 264.

[0048] like Figure 29 As shown, at the end of the operation at block 144, a first MBC transistor 400 is formed over a first region 202A (where first channel regions 202A-C are located within the first region 202A), and a second MBC transistor 500 is formed over a second region 202B (where second channel regions 202B-C are located within the second region 202B). In the depicted embodiment, the first MBC transistor 400 includes two vertically stacked channel members 2080 enclosed by a first gate structure 258. The MBC transistor 400 is isolated from adjacent first MBC transistors 400 by first dielectric fins 2220 and gate cleaving members 264. Along the Y direction, the two vertically stacked channel members 2080 of the first MBC transistor 400 extend between two first source / drain members 238 (e.g., ...). Figure 19 or Figure 29 (As shown). The second MBC transistor 500 includes three vertically stacked channel members 2080 enclosed by a second gate structure 260. The second MBC transistor 500 is isolated from adjacent second MBC transistors 500 by second dielectric fins 2222 and gate cleaving members 264. Along the Y direction, the three vertically stacked channel members 2080 of the second MBC transistor 500 extend between two second source / drain members 240 (as shown). Figure 19 or Figure 29 (As shown). Compared to the second MBC transistor 500, the first MBC transistor 400 has one less channel member 2080 and a smaller first gate structure 258, resulting in a smaller overlap area with the adjacent first source / drain member 238, and a smaller parasitic gate-drain capacitance (Cgd). The smaller parasitic gate-drain capacitance allows the first MBC transistor 400 to switch faster in AC applications. Compared to the first MBC transistor 400, the second MBC transistor 500 has an additional channel member 2080 to conduct the on-current, giving it a larger on-current. The larger on-current makes the second MBC transistor 500 more suitable for high-current (HC) or high-performance computing (HPC) applications. Note that the invention is not limited to embodiments including only 3-channel MBC transistors and 2-channel MBC transistors. The invention is contemplated to include semiconductor devices comprising at least two types of MBC transistors with different numbers of channel members.

[0049] refer to Figure 1B and Figure 30Method 100 includes block 146, in which a first source / drain contact 274 and a second source / drain contact 276 are formed. After forming the SAC layer 270, source / drain contact openings are formed through the ILD layer 244 and CESL 242 to expose the first source / drain component 238 and the second source / drain component 240. A silicide precursor layer is then deposited over the exposed first source / drain component 238 and the exposed second source / drain component 240. The silicide precursor layer may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The workpiece 200 is then annealed to induce a silicide reaction between the silicide precursor layer and the first source / drain component 238 and between the silicide precursor layer and the second source / drain component 240 to form a silicide component 272. The silicide component 272 may be formed of titanium silicide, tantalum silicide, nickel silicide, cobalt silicide, or tungsten silicide. A metal filler layer is then deposited into the source / drain openings and planarized to form a first source / drain contact 274 and a second source / drain contact 276. The metal filler layer may include aluminum (Al), copper (Cu), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W). The first source / drain contact 274 is electrically coupled to a first source / drain component 238 via a silicide component 272. The second source / drain contact 276 is electrically coupled to a second source / drain component 240 via a silicide component 272.

[0050] Figures 31 to 36 The boundary between the first MBC transistor 400 and the second MBC transistor 500 according to various embodiments of the present invention is shown. First, refer to... Figure 31 and Figure 32The first MBC transistor 400 may intersect with the second MBC transistor 500 at the first interface region 202IX along the X direction. The first interface region 202IX may include anomalies. For example, the edge of the fifth patterned mask 217 used in block 116 may be directly above the boundary isolation member 216B. The boundary isolation member 216B includes a transition from the isolation member 216 to the recessed isolation member 2160 and has a stepped top surface that undergoes a stepped change in hierarchy. In the depicted embodiment, the right half of the boundary isolation member 216B shares the same depth (or thickness) as the isolation member 216, and the left half of the boundary isolation member 216B shares the same depth (or thickness) as the recessed isolation member 2160. In other words, the top surface of the right half of the boundary isolation member 216B is coplanar with the top surface of the isolation member 216, while the top surface of the left half of the boundary isolation member 216B is coplanar with the top surface of the recessed isolation member 2160. Boundary dielectric fins 222B disposed on boundary isolation member 216B include a bottom profile to conform to the shape of boundary isolation member 216B. Like boundary isolation member 216B, boundary dielectric fins 222B include a stepped bottom surface that undergoes similar hierarchical stepped changes. Figure 31 and Figure 32 As shown, the bottom surface of the right side of the boundary dielectric fin 222B is directly disposed on the right side of the boundary isolation member 216B, and the bottom surface of the left side of the boundary dielectric fin 222B is directly disposed on the left side of the boundary isolation member 216B. In some embodiments, the first width W1 of the first dielectric fin 2220 or the second dielectric fin 2222 can be equal to or less than the second width W2 of the boundary dielectric fin 222B. In some embodiments, the second width W2 can be more than three times the first width W1. Figure 31 In the illustrated embodiment, the first MBC transistor 400 includes a first APT component 204 disposed below the first gate structure 258, and the second MBC transistor 500 includes a second APT component 206 disposed below the second gate structure 260. Figure 32 In the illustrated embodiment, the first APT component 204 and the second APT component 206 are not formed. The first gate structure 258 is disposed directly above the first fin structure 214AF, and the second gate structure 260 is disposed directly above the second fin structure 214BF.

[0051] First refer to Figures 33 to 36 The first MBC transistor 400 can intersect with the second MBC transistor 500 at the second interface region 202IY along the Y direction. The second interface region 202IY can be perpendicularly aligned with the boundary source / drain component 240B. Figures 33 to 36In this embodiment, the boundary source / drain component 240B can be similar to the deeper of the first source / drain component 238 and the second source / drain component 240. In the depicted embodiment, because the second source / drain component 240 extends further into the substrate 202 and is deeper, the boundary source / drain component 240B can be similar to the second source / drain component 240. The boundary source / drain component 240B is sandwiched between the channel members 2080 of the first MBC transistor 400 and the second MBC transistor 500. In other words, the boundary source / drain component 240B can be shared by the first MBC transistor 400 and the second MBC transistor 500. Figure 33 In the illustrated embodiment, the first MBC transistor 400 is disposed above the first APT component 204, the second MBC transistor 500 is disposed above the second APT component 206, and the source / drain components (first source / drain component 238, second source / drain component 240, and boundary source / drain component 240B) are disposed above the pseudo-epitaxial layer 236. Figure 34 In the illustrated embodiment, the first MBC transistor 400 is disposed above the first APT component 204, and the second MBC transistor 500 is disposed above the second APT component 206, but the pseudo epitaxial layer 236 is omitted. Figure 35 In the illustrated embodiment, the first MBC transistor 400 is disposed above the first fin structure 214AF, the second MBC transistor 500 is disposed above the second fin structure 214BF, and the source / drain components (first source / drain component 238, second source / drain component 240, and boundary source / drain component 240B) are disposed on the pseudo-epipolar layer 236. Figure 36 In the embodiment shown, the first MBC transistor 400 is disposed above the first fin structure 214AF, the second MBC transistor 500 is disposed above the second fin structure 214BF, and the source / drain components (first source / drain component 238, second source / drain component 240 and boundary source / drain component 240B) are disposed on the substrate 202.

[0052] Based on the above discussion, it can be seen that the present invention provides advantages over conventional processes. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and no specific advantage is required in all embodiments. For example, the process disclosed in this invention forms a first MBC transistor including a first number of channel components and a second MBC transistor including a second number of channel components. The second number is greater than the first number. The first MBC transistor is more suitable for high-speed applications, and the second MBC transistor is more suitable for high-current applications.

[0053] In one exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source / drain components and a first number of nanostructures stacked perpendicularly to each other and extending longitudinally between the two first source / drain components. The second transistor includes two second source / drain components and a second number of nanostructures stacked perpendicularly to each other and extending longitudinally between the two second source / drain components. The first number is less than the second number.

[0054] In some embodiments, the bottommost nanostructure of the second number of nanostructures is lower than the bottommost nanostructure of the first number of nanostructures. In some embodiments, the bottom surface of the second source / drain component is lower than the bottom surface of the first source / drain component. In some embodiments, the semiconductor device may further include a first pseudo-epipolar component disposed below each of the two first source / drain components and a second pseudo-epipolar component disposed below at least one of the two second source / drain components. In some cases, the two first source / drain components and the two second source / drain components include a first semiconductor material and a first type of dopant, and the first and second pseudo-epipolar components include a second semiconductor material and are substantially free of the first type of dopant. In some cases, the first transistor further includes a first punch-through (APT) component disposed below the first number of nanostructures, and the second transistor further includes a second APT component disposed below the second number of nanostructures. In some embodiments, the first APT component is in direct contact with the first pseudo-epipolar component, and the second APT component is in direct contact with the second pseudo-epipolar component. In some embodiments, the second APT component is lower than the first APT component. In some cases, the first APT component and the second APT component include a second type of dopant that is different from the first type of dopant.

[0055] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure may include: a first number of channel members disposed above a first fin structure; a first gate structure enclosing each of the first number of channel members; a second number of channel members disposed above a second fin structure, the second number being greater than the first number; a second gate structure enclosing each of the second number of channel members; a dielectric fin disposed along a first direction between the first gate structure and the second gate structure; and an isolation member disposed along the first direction between the first fin structure and the second fin structure. The dielectric fin includes a first bottom surface and a second bottom surface lower than the first bottom surface.

[0056] In some embodiments, the semiconductor structure may further include gate dicing members disposed on the dielectric fins. In some embodiments, the first bottom surface and the second bottom surface include a stepped change. In some embodiments, the top surface of the first fin structure is higher than the top surface of the second fin structure, the first bottom surface is coplanar with the top surface of the first fin structure, and the second bottom surface is coplanar with the top surface of the second fin structure. In some embodiments, the isolation member includes a first top surface and a second top surface lower than the first top surface. In some embodiments, the first top surface of the isolation member intersects with the first bottom surface of the dielectric fin, and the second top surface of the isolation member intersects with the second bottom surface of the dielectric fin.

[0057] In yet another exemplary aspect, the present invention relates to a method. The method includes providing a substrate including a first region and a second region; selectively forming a first punch-through (APT) layer over the first region; selectively forming a second APT layer over the second region; depositing a first stack of semiconductor layers over the first and second regions; selectively removing the first stack of semiconductor layers from the second region; after selective removal, selectively depositing a second stack of semiconductor layers over the second region; patterning the first and second stacks of semiconductor layers to form a first fin structure over the first region and a second fin structure over the second region; after patterning, depositing an isolation member over the substrate; and selectively etching back the isolation member over the second region such that the isolation member over the first region has a first thickness and the isolation member over the second region has a second thickness less than the first thickness.

[0058] In some embodiments, the first stack of semiconductor layers includes a first number of silicon layers interleaved with a first silicon-germanium layer, and the second stack of semiconductor layers includes a second number of silicon layers interleaved with a second silicon-germanium layer, wherein the second number is greater than the first number. In some embodiments, the method may further include, after selective etch-back, forming a semiconductor cladding layer over a first fin structure and a second fin over an isolation member over a first region, forming a second dielectric fin over an isolation member over a second region, forming a dummy gate stack over the channel regions of the first and second fin structures, selectively recessing the source / drain regions of the first fin structure to form a first source / drain groove when covering the second region, selectively recessing the source / drain regions of the second fin structure to form a second source / drain groove when covering the first region, forming a first source / drain member in the first source / drain groove, and forming a second source / drain member in the second source / drain groove. In some cases, selective recessing of the source / drain regions of the first fin structure removes the first APT layer in the first source / drain trench, and selective recessing of the source / drain regions of the second fin structure removes the second APT layer in the second source / drain trench. In some embodiments, the method may further include forming pseudo-epipolar components in the first source / drain trench and the second source / drain trench before forming the first source / drain component and the second source / drain component.

[0059] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: The first transistor includes: Two first source / drain components, and A first number of nanostructures, the first number of nanostructures being stacked perpendicularly to each other and extending longitudinally between the two first source / drain components; The second transistor includes: Two second source / drain components, and A second number of nanostructures, the second number of nanostructures being stacked perpendicularly to each other and extending longitudinally between the two second source / drain components; and A dielectric component is disposed between the first number of nanostructures and the second number of nanostructures. Wherein, the first quantity is less than the second quantity. The dielectric component includes a first bottom surface and a second bottom surface that is lower than the first bottom surface.

2. The semiconductor device according to claim 1, wherein, The bottommost nanostructure of the second number of nanostructures is lower than the bottommost nanostructure of the first number of nanostructures.

3. The semiconductor device according to claim 1, wherein, The bottom surface of the second source / drain component is lower than the bottom surface of the first source / drain component.

4. The semiconductor device according to claim 1, further comprising: A first pseudo-epitaxy component is disposed below each of the two first source / drain components; as well as The second pseudo-epitaxy component is disposed below at least one of the two second source / drain components.

5. The semiconductor device according to claim 4, in, The two first source / drain components and the two second source / drain components comprise a first semiconductor material and a first type of dopant. The first pseudo-epi ...

6. The semiconductor device according to claim 5, in, The first transistor further includes a first anti-penetration component disposed beneath the first number of nanostructures. The second transistor further includes a second anti-penetration component disposed below the second number of nanostructures.

7. The semiconductor device according to claim 6, in, The first anti-penetration component is in direct contact with the first pseudo-epicentric component. The second anti-penetration component is in direct contact with the second pseudo-epicentric component.

8. The semiconductor device according to claim 6, wherein, The second anti-penetration component is lower than the first anti-penetration component.

9. The semiconductor device according to claim 6, wherein, The first and second punch-through components include a second type of dopant that is different from the first type of dopant.

10. A semiconductor structure comprising: The first number of channel components are disposed above the first fin structure; A first gate structure encloses each of the first number of channel members; A second number of channel components are disposed above the second fin structure, and the second number is greater than the first number. A second gate structure encloses each of the second number of channel members; Dielectric fins are disposed between the first gate structure and the second gate structure along a first direction; and An isolation component is disposed between the first fin structure and the second fin structure along the first direction. The dielectric fin includes a first bottom surface and a second bottom surface that is lower than the first bottom surface.

11. The semiconductor structure according to claim 10, further comprising a gate dicing member disposed on the dielectric fin.

12. The semiconductor structure according to claim 10, wherein, The first bottom surface and the second bottom surface include stepped variations.

13. The semiconductor structure according to claim 10, in, The top surface of the first fin structure is higher than the top surface of the second fin structure. The first bottom surface and the top surface of the first fin structure are coplanar. The second bottom surface is coplanar with the top surface of the second fin structure.

14. The semiconductor structure according to claim 13, wherein, The isolation component includes a first top surface and a second top surface that is lower than the first top surface.

15. The semiconductor structure according to claim 14, in, The first top surface of the isolation component meets the first bottom surface of the dielectric fin. The second top surface of the isolation component intersects with the second bottom surface of the dielectric fin.

16. A method for forming a semiconductor structure, comprising: A substrate comprising a first region and a second region is provided; A first anti-penetration layer is selectively formed above the first region; A second anti-penetration layer is selectively formed in the second region; A first stack of semiconductor layers deposited over the first region and the second region; The first stack of the semiconductor layer is selectively removed from the second region; After the selective removal, a second stack of semiconductor layers is selectively deposited over the second region; The first stack of the semiconductor layer and the second stack of the semiconductor layer are patterned to form a first fin structure over the first region and a second fin structure over the second region; After the patterning, an isolation component is deposited over the substrate; as well as The isolation member above the second region is selectively etched back, such that the isolation member above the first region has a first thickness, and the isolation member above the second region has a second thickness less than the first thickness.

17. The method according to claim 16, in, The first stack of the semiconductor layers includes a first number of silicon layers interleaved with the first silicon-germanium layer. The second stack of the semiconductor layers includes a second number of silicon layers interleaved with the second silicon-germanium layer. The second quantity is greater than the first quantity.

18. The method of claim 16, further comprising: After the selective etch-back, a semiconductor cladding layer is formed over the first fin structure and the second fin structure; A first dielectric fin is formed above the isolation member above the first region, and a second dielectric fin is formed above the isolation member above the second region; A dummy gate stack is formed above the channel regions of the first fin structure and the second fin structure; When covering the second region, the source / drain regions of the first fin structure are selectively recessed to form a first source / drain groove; When covering the first region, the source / drain regions of the second fin structure are selectively recessed to form a second source / drain groove; as well as A first source / drain component is formed in the first source / drain groove, and a second source / drain component is formed in the second source / drain groove.

19. The method according to claim 18, in, The source / drain regions of the first fin structure are selectively recessed to remove the first anti-penetration layer in the first source / drain groove. In this process, the source / drain regions of the second fin structure are selectively recessed to remove the second anti-penetration layer in the second source / drain groove.

20. The method of claim 18, further comprising: Before forming the first source / drain component and the second source / drain component, a pseudo epitaxial component is formed in the first source / drain groove and the second source / drain groove.

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