Semiconductor device, manufacturing method, three-dimensional memory and storage system

Abstract

The present invention provides a semiconductor device, a manufacturing method, a three-dimensional memory and a storage system, wherein the semiconductor device comprises: a substrate, the substrate comprises a device region arranged along a first direction; an isolation structure, the isolation structure is used to isolate the device region; a gate structure located on the device region, the gate structure extending along a second direction perpendicular to the first direction; wherein the device region comprises a first doping region and a second doping region, the first doping region is arranged on both sides of the gate structure along the first direction, the second doping region is located outside the first doping region in the second direction, and the first doping region and the second doping region have different doping states. By having different doping states between the first doping region and the second doping region, the effective channel width of the gate structure in the second direction can be changed to improve the double hump phenomenon of the Id-Vg curve of the semiconductor device, so as to improve the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method, a three-dimensional memory and a storage system. Background Art

[0002] Shallow trench isolation (STI) is an important component in semiconductor devices. It can isolate adjacent devices laterally. During the preparation of semiconductor devices, due to the high temperature during subsequent thermal oxidation, annealing and other heat treatment processes, the boron loss at the junction of the gate and the shallow trench isolation and the electric field concentration at the junction will cause the device corner (the junction of the gate and the shallow trench isolation) to turn on first, and the middle of the device (i.e., the area directly below the gate) to turn on later, resulting in a double hump on the Id-Vg curve.

[0003] However, the double hump phenomenon appears in the Id-Vg curve, which has an extremely adverse effect on both process control and device modeling. Therefore, this problem needs to be solved through a reasonable process. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device, a manufacturing method, a three-dimensional memory and a storage system, which can effectively improve the double hump phenomenon of the Id-Vg curve of the semiconductor device to improve the performance of the semiconductor device.

[0005] In order to solve the above problems, the present invention provides a semiconductor device, comprising: a substrate, the substrate comprising a device region arranged along a first direction; an isolation structure, the isolation structure being used to isolate the device region; a gate structure located on the device region, the gate structure extending along a second direction perpendicular to the first direction; wherein the device region comprises a first doped region and a second doped region, the first doped region being arranged on both sides of the gate structure along the first direction, the second doped region being located on the outside of the first doped region in the second direction, and the doping states of the first doped region and the second doped region are different.

[0006] The first doped region and the second doped region at least partially overlap.

[0007] The first doped region has a first width in the second direction, the second doped region has a second width in the second direction, and the effective channel width of the gate structure formed in the device region in the second direction corresponds to the difference between the first width and the second width.

[0008] The doping type of the second doping region is opposite to the doping type of the first doping region.

[0009] The second doped region is adjacent to the first doped region and is located on two sides of the device region bordering the isolation structure along the second direction.

[0010] The second doping region is also located below the gate structure, and a projection of the gate structure on the second doping region along a first longitudinal direction perpendicular to the substrate is located within the second doping region.

[0011] Among them, one of the doping type of the first doping region and the doping type of the second doping region is N-type and the other is P-type.

[0012] The second width is no greater than 50 nm.

[0013] In order to solve the above problems, an embodiment of the present application also provides a method for manufacturing a semiconductor device, including: providing a substrate, the substrate including a device region arranged along a first direction, and an isolation region separating the device region, and forming an isolation groove in the isolation region; forming a gate structure above the device region, the gate structure extending along a second direction perpendicular to the first direction; forming a first doped region located on both sides of the gate structure in the device region along the first direction, and; forming a second doped region in the device region, the second doped region being located on the outside of the first doped region in the second direction; wherein the doping states of the first doped region and the second doped region are different.

[0014] The step of forming the second doping region in the device region includes at least partially overlapping the first doping region and the second doping region.

[0015] Among them, the step of forming a second doped region in the device area includes: the first doped region has a first width in the second direction, the second doped region has a second width in the second direction, and the effective channel width of the gate structure formed in the device area in the second direction corresponds to the difference between the first width and the second width.

[0016] The doping type of the second doping region is opposite to the doping type of the first doping region.

[0017] The step of forming the second doping region in the device region is before the step of forming the gate structure above the device region, so that the second doping region is formed before forming the gate structure.

[0018] Among them, one of the doping type of the first doping region and the doping type of the second doping region is N-type and the other is P-type.

[0019] In order to solve the above problems, an embodiment of the present application further provides a three-dimensional memory, including a memory cell array and a peripheral circuit, wherein the peripheral circuit includes a semiconductor device as described above.

[0020] In order to solve the above problems, an embodiment of the present application also provides a storage system, including a controller and a three-dimensional memory, the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes a semiconductor device as any one of the above items.

[0021] The beneficial effects of the present invention are as follows: Different from the prior art, the present invention provides a semiconductor device, a manufacturing method, a three-dimensional memory and a storage system, wherein the semiconductor device comprises: a substrate, the substrate comprises a device region arranged along a first direction; an isolation structure, the isolation structure is used to isolate the device region; a gate structure located on the device region, the gate structure extends along a second direction perpendicular to the first direction; wherein the device region comprises a first doping region and a second doping region, the first doping region is arranged on both sides of the gate structure along the first direction, the second doping region is located outside the first doping region in the second direction, and the first doping region and the second doping region have different doping states. By having different doping states between the first doping region and the second doping region, the effective channel width of the gate structure in the second direction can be changed to improve the double hump phenomenon of the Id-Vg curve of the semiconductor device, so as to improve the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0023] Figure 1 A schematic structural diagram of a semiconductor device provided in accordance with a first embodiment of the present invention.

[0024] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor device at C1-C1.

[0025] Figure 3 It is the Id-Vg curve diagram of the semiconductor device.

[0026] Figure 4 for Figure 1 Schematic diagram of the top view of the semiconductor device in the Z direction.

[0027] Figure 5 A schematic structural diagram of a semiconductor device provided in accordance with a second embodiment of the present invention.

[0028] Figure 6 for Figure 5 Schematic diagram of the top view of the semiconductor device in the Z direction.

[0029] Figure 7 A flow chart of a method for manufacturing a semiconductor device provided in accordance with the first embodiment of the present invention.

[0030] Figure 8A schematic structural diagram of a substrate is provided in the first embodiment of the present invention.

[0031] Fig. 9 FIG. 1 is a schematic diagram of a structure for forming a gate in the first embodiment of the present invention.

[0032] Fig.10 1 is a comparison diagram of Id-Vg curves obtained by the method of the first embodiment of the present application and the method of the prior art respectively.

[0033] Fig.11 A flow chart of a method for manufacturing a semiconductor device provided in accordance with a second embodiment of the present invention.

[0034] Fig.12 A schematic structural diagram of a substrate is provided in the second embodiment of the present invention.

[0035] Fig.13 FIG. 4 is a schematic diagram of a structure for forming a second doping region in a second embodiment of the present invention.

[0036] Fig.14 A schematic block diagram of a storage system in some embodiments of the present invention. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0038] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present invention.

[0039] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0040] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0041] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0042] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0043] See also Figure 1 , is a schematic diagram of the structure of a semiconductor device 100 provided in the first embodiment of the present invention. The semiconductor device 100 comprises: a substrate 110, the substrate 110 comprises a device region arranged along a first direction; an isolation structure 121, the isolation structure 121 is used to isolate the device region; a gate structure 130 located on the device region, the gate structure 130 extends along a second direction perpendicular to the first direction; wherein the device region comprises a first doping region 140 and a second doping region 150, the gate structure 130 is arranged on both sides of the gate structure 130 along the first direction, the second doping region 150 is located outside the first doping region 140 in the second direction, and the first doping region 140 and the second doping region 150 have different doping states.

[0044] It should be noted that if Figure 1 As shown, the first direction refers to the direction parallel to the X direction, and the second direction refers to the direction parallel to the Y direction. The same is true below and will not be repeated hereafter. Figure 1 As shown, the semiconductor device 100 includes a substrate 110, on which a device region (eg, Figure 1 A1 area as shown) and isolation area (as Figure 1 The device region is used to form a functional device, such as a PMOS device or an NMOS device, and the isolation region is used to separate the device region. One or more isolation structures 121 are formed in the isolation region (for ease of explanation, in Figure 1 Only one isolation structure 121 is shown in the isolation region, and the isolation structure 121 is also called shallow trench isolation (STI). The device region can be isolated by the isolation structure 121. In addition, after the gate structure 130 is formed, a source 160 and a drain 170 can be formed on both sides of the gate structure 130 by ion implantation.

[0045] Among them, one of the doping type of the first doping region 140 and the doping type of the second doping region 150 is N-type, and the other is P-type.

[0046] Specifically, in general, the doping type can be N-type or P-type, and the doping types of the first doping region 140 and the second doping region 150 are opposite. When the first doping region 140 is P-type, the second doping region 150 is N-type, and when the first doping region 140 is N-type, the second doping region 150 is P-type.

[0047] Specifically, the device area can be used to form functional devices, such as PMOS devices or NMOS devices, that is, P-type transistors or N-type transistors, and the P-type transistors or N-type transistors generally include a gate, a source 160 and a drain 170. The source 160 and the drain 170 are generally formed by ion implantation and have a certain doping type. The doping type of the transistor is consistent with the doping type of the source 160 and the drain 170. For example, the doping type of the source 160 and the drain 170 of the N-type transistor are both N-type, and the gate is generally made of conductive material and has no doping type. Generally, the gate is located above the substrate 110 and an oxide layer for acting as a dielectric is formed between the gate and the substrate. The gate and the oxide layer both belong to the gate structure 130. The gate is used to control the conduction or non-conduction between the source 160 and the drain 170 of the N-type transistor or the P-type transistor. For example, when a voltage (positive voltage) is applied to the gate of the N-type transistor, an electric field is formed between the gate and the substrate 110. The effect of the electric field causes the electrons in the active region of the substrate 110 to gather on the upper surface of the substrate 110. When the electrons accumulate to a certain number, the substrate 110 will be inverted into an N-type conductive channel on the upper surface of the active region, so that the source 160 and the drain 170 are conductive. The gate voltage that turns on the source 160 and the drain 170 is the threshold voltage (Vth) or the turn-on voltage.

[0048] As can be seen from the above, an isolation structure 121 is formed in the isolation region around the device region. During the preparation process of the semiconductor device 100, however, due to the high temperature effect of subsequent thermal oxidation, annealing and other heat treatment processes, the boron loss at the junction of the gate structure 130 and the isolation structure 121 and the electric field concentration at the junction will cause the device edge to turn on first and the device middle to turn on later, thereby causing the Id-Vg curve to have a double hump phenomenon. Among them, Figure 2 for Figure 1 The schematic cross-sectional structure diagram of the semiconductor device 100 at C1-C1 is shown in FIG. Figure 2 It can be seen that the device edge is the junction between the gate structure 130 and the isolation structure 121, that is, Figure 2 The A3 region shown in FIG. 1 is the region directly below the gate structure 130 in the middle of the device. Figure 2 The A4 area shown.

[0049] like Figure 3 As shown, it is an Id-Vg curve diagram of the semiconductor device 100, wherein the abscissa is the voltage applied to the gate (in V), and the ordinate is the output current of the drain 170 (in A). Figure 3 As shown in the figure, the two curves on the far left have obvious double hump shapes, that is, the Id-Vg curve has double hump phenomenon, while the other curves on the right do not have obvious double hump shapes, which are normal Id-Vg curves. The double hump phenomenon of the Id-Vg curve has extremely adverse effects on both process control and device modeling.

[0050] Based on this, in the first embodiment of the present application, a second doping region 150 is formed in the device area. The second doping region 150 is located on the outside of the first doping region 140 in the second direction. The doping states of the first doping region 140 and the second doping region 150 are different. By changing the doping states of the first doping region 140 and the second doping region 150, the effective channel width of the gate structure 130 in the second direction can be changed to improve the problem of different opening of the device edge area and the device middle area.

[0051] In addition, it should be noted that the difference in doping state between the first doping region 140 and the second doping region 150 may be a difference in any one or more of doping concentration, doping ion type, doping material, etc. For example, the ion types doped in the first doping region 140 and the second doping region 150 are opposite. In addition, the principle of the difference in doping state between the first doping region 140 and the second doping region 150 below is similar to this, and will not be repeated hereafter.

[0052] The first doping region 140 and the second doping region 150 at least partially overlap.

[0053] Specifically, the second doping region 150 can be formed outside the first doping region 140, and the doping states of the first doping region 140 and the second doping region 150 are opposite, and the second doping region 150 excludes part of the effective channel width of the first doping region 140 in the second direction, so as to improve the problem that the edge region of the device and the middle region of the device are opened differently. Among them, the second doping region 150 can occupy at least part of the edge region of the device to improve the problem that the edge region of the device and the middle region of the device are opened differently. Among them, the second doping region 150 can be located only in at least part of the edge region of the device, and does not overlap with the first doping region 140. For example, the second doping region 150 is only close to the first doping region 140. In addition, when the second doping region 150 occupies at least part of the edge region of the device, the second doping region 150 can be located in at least part of the edge region of the device, and the first doping region 140 and the second doping region 150 at least partially overlap.

[0054] The first doped region 140 has a first width L1 in the second direction, the second doped region 150 has a second width L2 in the second direction, and the effective channel width of the gate structure 130 formed in the device region in the second direction corresponds to the difference between the first width L1 and the second width L2.

[0055] Specifically, Figure 1As shown, the second doping region 150 is located outside the first doping region 140 in the second direction and has a second width in the second direction. The effective channel width of the gate structure 130 formed in the device region in the second direction corresponds to the difference between the first width L1 and the second width L2, that is, by changing the effective channel width of the gate structure 130 in the second direction, the problem of different opening of the device edge region and the device middle region is improved. Generally, the effective channel width of the gate structure 130 in the second direction of the semiconductor device 100 without the second doping region 150 is L1. At this time, due to the boron loss at the junction of the gate structure 130 and the isolation structure 121 and the electric field concentration at the junction, the device edge and the device middle are opened successively, so that the Id-Vg curve has a double hump phenomenon. On the basis of the existing device, a second doping region 150 is formed in the device region, and the effective channel width of the gate structure 130 formed in the device region in the second direction corresponds to the difference between the first width L1 and the second width L2. At this time, two second doping regions 150 are formed in the first doping region 140, that is, the effective channel width of the gate structure 130 of the semiconductor device 100 in the second direction is the difference between the first width L1 and the two second widths L2, that is, the effective channel width of the gate structure 130 in the second direction is L1-2L2. It can be seen that at this time, the effective width of the gate structure 130 used to control the semiconductor device 100 to be turned on or off is the middle area of ​​the gate structure 130, that is, the part that the first doping region 140 and the second doping region 150 do not overlap. By excluding the effective channel in the edge area of ​​the device and only retaining the effective channel in the middle area of ​​the device, the problem of the edge area of ​​the device and the middle area of ​​the device being turned on successively when the turn-on voltage is applied to the gate is avoided, and the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be effectively improved to improve the performance of the semiconductor device 100.

[0056] In addition, it should be noted that when the gate structure 130 and the isolation structure 121 have an interface only on one side, at this time, it is only necessary to perform ion implantation on the region corresponding to the side where the interface exists, so as to form the second doping region 150 in the corresponding region, thereby improving the double hump phenomenon of the Id-Vg curve of the semiconductor device 100. At this time, the effective channel width of the gate structure 130 in the second direction is L1-L2, that is, the effective channel width of the gate structure 130 in the second direction corresponds to the difference between the first width L1 and the second width L2. The correspondence here is related to the number of the second doping regions 150. For example, when the second doping regions 150 are formed on both sides of the gate structure 130, the corresponding effective channel width is L1-2L2, and when the second doping region 150 is formed on one side of the gate structure 130, the corresponding effective channel width is L1-L2. Similarly, it can be known that the position and number of the second doping regions 150 formed can be adjusted according to the number and position of the interface between the gate structure 130 and the isolation structure 121, and no further description will be given hereinafter.

[0057] The doping type of the second doping region 150 is opposite to the doping type of the first doping region 140 .

[0058] Specifically, it can be seen from the above that the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be improved by changing the effective channel width of the gate structure 130 in the second direction, and there is no special restriction on the method of eliminating the effective channel in the edge area of ​​the device. For example, when forming the first doping region 140, ion implantation can be performed only in the area directly below the gate structure 130, and no ion implantation is performed at the junction of the gate structure 130 and the isolation structure 121 to form the first doping region 140. At this time, the effective width of the gate structure 130 in the second direction is the width of the first doping region 140 in the second direction, that is, L1-2L2, so as to change the effective channel width of the gate structure 130 in the second direction. Preferably, the doping type of the second doping region 150 can be opposite to the doping type of the first doping region 140, so as to achieve the change of the effective channel width of the gate structure 130 in the second direction. For example, when the semiconductor device 100 is an NMOS device, at this time, the doping type of the first doping region 140 is N-type, and the electrons of the NMOS device can move in the effective channel formed by the first doping region 140 by forming the N-type first doping region 140, and the effective channel width of the gate structure 130 in the second direction is the width of the first doping region 140 in the second direction, that is, the first width L1. Since the doping type of the second doping region 150 is opposite to the doping type of the first doping region 140, that is, the doping type of the second doping region 150 is P-type, at this time, the electrons of the NMOS device cannot move freely in the P-type second doping region 150, that is, the effective channel width of the gate structure 130 in the second direction needs to remove the overlapping portion of the second doping region 150 and the first doping region 140, and the effective channel width of the gate structure 130 in the second direction is L1-2L2. By eliminating the effective channels in the edge area of ​​the gate structure 130 and retaining only the effective channels in the middle area of ​​the gate structure 130, the problem of the edge area of ​​the gate structure 130 and the middle area of ​​the gate structure 130 being turned on successively when the turn-on voltage is applied to the gate structure 130 can be avoided. The double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be effectively improved, thereby improving the performance of the semiconductor device 100.

[0059] In a variation, the doping type of the second doping region 150 may be the same as the doping type of the first doping region 140, but different or opposite voltages may be applied through the contacts so that the effective channel width of the gate structure 130 in the second direction is L1-2L2. This can avoid the problem of the edge region of the gate structure 130 and the middle region of the gate structure 130 being turned on successively when a turn-on voltage is applied to the gate structure 130, and can effectively improve the double hump phenomenon of the Id-Vg curve of the semiconductor device 100, thereby improving the performance of the semiconductor device 100.

[0060] In addition, the semiconductor device 100 can also be a PMOS device. When the semiconductor device 100 is a PMOS device, the doping type of the first doping region 140 is P-type. By forming the P-type first doping region 140, the holes of the PMOS device can move in the effective channel formed by the first doping region 140. The effective channel width of the gate structure 130 in the second direction is the width of the first doping region 140 in the second direction, that is, the first width L1. Since the doping type of the second doping region 150 is opposite to the doping type of the first doping region 140, that is, the doping type of the second doping region 150 is N-type, at this time, the holes of the PMOS device cannot move freely in the N-type second doping region 150, that is, the effective channel width of the gate structure 130 in the second direction needs to remove the overlapping portion of the second doping region 150 and the first doping region 140, and the effective channel width of the gate structure 130 in the second direction is L1-2L2. By eliminating the effective channels in the edge area of ​​the gate structure 130 and retaining only the effective channels in the middle area of ​​the gate structure 130, the problem of the edge area of ​​the gate structure 130 and the middle area of ​​the gate structure 130 being turned on successively when the turn-on voltage is applied to the gate structure 130 can be avoided. The double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be effectively improved, thereby improving the performance of the semiconductor device 100.

[0061] The second doping region 150 is adjacent to the first doping region 140 and is located on both sides of the device region bordering the isolation structure 121 along the second direction.

[0062] like Figure 4 Shown Figure 1 The schematic diagram of the top view of the semiconductor device in the Z direction is shown in FIG. Figure 4It can be seen that the second doping region 150 is distributed on both sides of the edge of the gate structure 130 along the second direction. As can be seen from the above, the second doping region 150 can be formed in the device region to improve the double hump phenomenon of the Id-Vg curve of the semiconductor device 100. Generally, the formation process of the semiconductor device 100 includes: first, providing a substrate 110, on which a device region and an isolation region separating the device region are formed, and a plurality of isolation structures 121 are formed in the isolation region; then, forming a gate structure 130 on the device region, and forming a source 160 and a drain 170 on both sides of the gate structure 130, and finally, light ion implantation is performed on the device region to form the first doping region 140. Based on the formation process of the semiconductor device 100, it can be known that the second doping region 150 can be formed in the device region by ion implantation before or after the gate structure 130 is formed. For example, when the second doping region 150 is formed after the gate structure 130 and the first doping region 140 are formed, ion implantation is only required after the first doping region 140 is formed, so as to form the second doping region 150 in the device region. At this time, since the gate structure 130 has been formed, when the ion implantation is continued, due to the shielding of the gate structure 130, there is no second doping region 150 directly below the gate structure 130, and the second doping region 150 is located on both sides of the junction of the device region and the isolation region along the second direction, that is, Figure 4 The second doping region 150 shown is distributed on both sides of the edge of the gate structure 130 along the second direction. In addition, it should be noted that, in order to form the second doping region 150 at the position corresponding to the device region, before ion implantation is performed to form the second doping region 150, a mask corresponding to the position and pattern of the second doping region 150 can be used to form a photoresist layer having an opening corresponding to the position and pattern of the second doping region 150 on the substrate 110 through a photolithography process, so as to realize the formation of the second doping region 150 in the device region through ion implantation.

[0063] The second doping region 250 is also located below the gate structure 230 , and a projection of the gate structure 230 on the second doping region 250 along a first longitudinal direction (Z direction) perpendicular to the substrate 210 is located within the second doping region 250 .

[0064] Specifically, as can be seen from the above, the second doping region 250 can be formed below the gate structure 230 by ion implantation before or after the gate structure 230 is formed. Different from the scheme of forming the second doping region 250 after the gate structure 230 is formed in the first embodiment, the scheme of the second embodiment can also be adopted. For example, the second doping region 250 is formed before the gate structure 230 is formed. At this time, there is no obstruction by the gate structure 230. In addition to the first doping region 240 formed on both sides of the gate structure 230, a second doping region 250 is also formed directly below the gate structure 230, that is, the projection of the gate structure 230 on the second doping region 250 along the first longitudinal direction (Z direction) perpendicular to the substrate 210 is located in the second doping region 250, that is, the second doping region 250 is located directly below the gate structure 250 in addition to being located on both sides of the gate structure 230. Similarly, before performing ion implantation to form the second doping region 250 , a mask corresponding to the position and pattern of the second doping region 250 may be used to form the second doping region 250 in the device region through ion implantation via photolithography.

[0065] like Figure 5 As shown, it is a schematic diagram of the structure of a semiconductor device 200 provided in the second embodiment of the present invention. The semiconductor device 200 provided in the second embodiment includes: a substrate 210, the substrate 210 includes a device region arranged along a first direction, and an isolation structure 221 separating the device region; a gate structure 230 located on the device region, the gate structure 230 extends to a portion of the isolation structure 221 on both sides of the device region along a second direction perpendicular to the first direction; a first doping region 240 arranged on both sides of the gate structure 230 along the first direction, the first doping region 240 has a first width L1 in the second direction; a second doping region 250 located in the device region, the second doping region 250 is located outside the first doping region 240 in the second direction, and has a second width in the second direction, the effective channel width of the gate structure 230 formed in the device region in the second direction is the difference between the first width L1 and the second width L2, that is, the effective channel width of the gate structure 230 is L1-2L2. Figure 6 Shown Figure 5 The schematic diagram of the top view of the semiconductor device 200 in the Z direction is shown in FIG. Figure 6 It can be seen that in addition to the first doped region 240 formed on both sides of the gate structure 230, a second doped region 250 is also formed directly below the gate structure 230. By forming the second doped region 250, the double hump phenomenon of the Id-Vg curve of the semiconductor device 200 can be effectively improved to improve the performance of the semiconductor device 200.

[0066] The second width is no greater than 50 nm.

[0067] Specifically, it can be seen from the above that the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be effectively improved by excluding the effective channel in the edge area of ​​the device and only retaining the effective channel in the middle area of ​​the device. When the second width of the second doping region 150 in the second direction is greater than the width of the boron loss at the junction of the gate structure 130 and the isolation structure 121, the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be completely eliminated. However, if the second width of the second doping region 150 is too large, the effective channel of the gate structure 130 in the second direction will become smaller, thereby causing a short channel effect. Preferably, the second width of the second doping region 150 in the second direction is not greater than 50nm. Specifically preferably, the second width of the second doping region 150 in the second direction can be 20nm or 30nm.

[0068] Based on the semiconductor device 100 described in the above embodiment, the present application embodiment further provides a method for manufacturing the semiconductor device 100, such as Figure 7 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. Taking the semiconductor device 100 as an example, the manufacturing process of the semiconductor device 100 includes the following steps:

[0069] Step S101: providing a substrate 110, the substrate 110 comprising a device region arranged along a first direction and an isolation region separating the device region, and forming an isolation trench 120 in the isolation region.

[0070] Figure 8 The structure formed in step S101 includes: a substrate 110, respectively located at Figure 8 The device regions and isolation regions in the A1 region and the A2 region, as well as the isolation trenches 120 located in the isolation regions are shown.

[0071] Specifically, the substrate 110 is used as a basis for forming the semiconductor device 100. The substrate 110 is a semiconductor material, which may be silicon (Si), germanium (Ge) or silicon germanium (GeSi), silicon carbide (SiC), etc., or other materials. One or more active devices or passive devices may be formed on the substrate 110. Figure 8 As shown, the semiconductor device 100 includes a substrate 110, on which a device region (eg, Figure 1 A1 area shown) and isolation area (such as Figure 1 A2 area as shown), wherein the device area is used to form a functional device, such as a PMOS device or an NMOS device, and the isolation area is used to separate the device area. A plurality of isolation grooves 120 are formed in the isolation area. Subsequently, an insulating material can be filled in the isolation grooves 120 to form an isolation structure 121, and the isolation structure 121 can be used to isolate the device area.

[0072] Step S102: forming a gate structure 130 above the device region, wherein the gate structure 130 extends along a second direction perpendicular to the first direction.

[0073] Fig. 9 The structure formed in step S102 is shown, including: a substrate 110, a device region and an isolation region located on the substrate 110, an isolation structure 121 located in the isolation region, and a gate structure 130 located on the substrate 110. The gate structure 130 can extend to the partial isolation trenches 120 on both sides of the device region along a second direction (Y direction) perpendicular to the first direction.

[0074] Specifically, the gate structure 130 generally includes an oxide layer and a gate located on the oxide layer. Since the gate is used to control whether the semiconductor device 100 is turned on, the gate is mostly made of conductive materials, such as polysilicon (Poly), tungsten (W) or aluminum (Al), etc., as long as it is a conductive material, there is no specific limitation. The oxide layer serves as a dielectric layer to maintain the insulation between the substrate 110 and the gate. The material of the oxide layer is generally an oxide, such as silicon oxide (SiO2). An oxide layer can be formed on the substrate 110 by thermal oxidation reaction (Thermal Oxidation), and then a gate made of polysilicon is formed on the oxide layer by a deposition process. The gate structure 130 can be extended to the partial isolation grooves 120 on both sides of the device area along the second direction by controlling the parameters in the thermal oxidation reaction and the deposition process, such as the time of the thermal oxidation reaction, the deposition depth, the thickness and the position, etc. After the gate structure 130 is formed, ion implantation can also be used to form on both sides of the gate structure 130. Figure 8 A source 160 and a drain 170 are shown.

[0075] Step S103: forming a first doped region 140 located at both sides of the gate structure 130 along a first direction in the device region.

[0076] Step S104: forming a second doping region 150 in the device region, wherein the second doping region 150 is located outside the first doping region 140 in the second direction; wherein the first doping region and the second doping region have different doping states.

[0077] Figure 1 The structure formed by steps S103 and S104 includes: a substrate 110, a device region and an isolation region located on the substrate 110, an isolation structure 121 located in the isolation region, a gate structure 130 located on the substrate 110, and a first doped region 140 and a second doped region 150 located below the gate structure 130.

[0078] Specifically, a second doping region 150 is formed in the device area, and the second doping region 150 is located on the outside of the first doping region 140 in the second direction. The doping states of the first doping region 140 and the second doping region 150 are different. Through the different doping states of the first doping region 140 and the second doping region 150, the effective channel width of the gate structure 130 in the second direction can be changed to improve the problem of different opening of the device edge area and the device middle area.

[0079] Wherein, step S104: the step of forming the second doping region 150 in the device region includes that the first doping region 140 and the second doping region 150 at least partially overlap.

[0080] Specifically, as can be seen from the above, the second doping region 150 can occupy at least part of the device edge region to improve the problem of different opening of the device edge region and the device middle region. Among them, the second doping region 150 can be only located in at least part of the device edge region without overlapping with the first doping region 140. For example, the second doping region 150 is only close to the first doping region 140. In addition, when the second doping region 150 occupies at least part of the device edge region, the first doping region 140 and the second doping region 150 at least partially overlap.

[0081] Among them, the step of forming a second doped region in the device area includes, the first doped region has a first width L1 in the second direction, the second doped region has a second width L2 in the second direction, and the effective channel width of the gate structure formed in the device area in the second direction corresponds to the difference between the first width L1 and the second width L2.

[0082] See also Figure 1 , the width of the first doped region 140 in the second direction (i.e., the first width) is L1, and the width of the second doped region 150 in the second direction (i.e., the second width) is L2, and the effective channel width of the gate structure 130 formed in the device region in the second direction corresponds to the difference between the first width L1 and the second width L2, that is, the effective channel width of the gate structure 130 in the second direction is L1-2L2.

[0083] like Fig.10 , which are comparison diagrams of Id-Vg curves obtained by the method of the first embodiment of the present application and the method of the prior art, respectively, wherein the abscissa is the voltage applied to the gate structure 130 (in V), the ordinate is the output current of the drain 170 (in A), the black curve is the Id-Vg curve obtained by the method of the prior art, and the gray curve is the Id-Vg curve obtained by the method of the first embodiment of the present application, Fig. 9It can be seen that the curve of the prior art has an obvious double hump shape, while the curve of the first embodiment does not have an obvious double hump shape and is a normal Id-Vg curve. It can be seen that after performing step S102 to form the gate structure 130, a first doping region 140 and a second doping region 150 can be formed under the gate structure 130 by multiple ion implantations. By forming the second doping region 150 in the device region, the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be improved by changing the effective channel width of the gate structure 130 in the second direction, thereby improving the performance of the device.

[0084] The doping type of the second doping region 150 is opposite to the doping type of the first doping region 140 .

[0085] Specifically, it can be seen from the above that the double hump phenomenon of the Id-Vg curve of the semiconductor device 100 can be improved by changing the effective channel width of the gate structure 130 in the second direction, and there is no special restriction on the direction of the effective channel excluding the edge area of ​​the device. When forming the first doping region 140, ion implantation can be performed only in the area directly below the gate structure 130 to change the effective channel width of the gate structure 130 in the second direction. Preferably, the doping type of the second doping region 150 can be opposite to the doping type of the first doping region 140, thereby achieving the change of the effective channel width of the gate structure 130 in the second direction.

[0086] Among them, one of the doping type of the first doping region 140 and the doping type of the second doping region 150 is N-type, and the other is P-type.

[0087] Specifically, as can be seen from the above, the doping type can be N-type or P-type, and the doping types of the first doping region 140 and the second doping region 150 are opposite. When the first doping region 140 is P-type, the second doping region 150 is N-type, and when the first doping region 140 is N-type, the second doping region 150 is P-type.

[0088] Different from Figure 7 The method of forming the semiconductor device 100 is shown as follows. Fig.11 As shown, it is a schematic flow chart of the method for manufacturing a semiconductor device 200 provided in the second embodiment of the present invention, wherein the step of forming a second doped region 250 in the device region (i.e., step S104) is performed before the step of forming a gate structure 230 above the device region (i.e., step S102), so as to form the second doped region 250 before forming the gate structure 230.

[0089] Taking the semiconductor device 200 as an example, the preparation of the semiconductor device 200 includes the following steps:

[0090] Step S101: providing a substrate 210, the substrate 210 comprising a device region arranged along a first direction, and an isolation region separating the device region, and forming an isolation trench 220 in the isolation region.

[0091] Fig.12 The structure formed in step S101 includes: a substrate 210, respectively located at Fig.11 The device region and isolation region of the A1 region and the A2 region are shown, and the isolation trench 220 is located in the isolation region. A plurality of isolation trenches 220 are formed in the isolation region, and then, an insulating material can be filled in the isolation trenches 220 to form an isolation structure 221, and the device region can be isolated by the isolation structure 221. Since the process steps and structural elements involved in step S101 have been described in detail above, they will not be repeated here.

[0092] Step S104: forming a second doped region 250 in the device region.

[0093] Fig.13 The structure formed in step S104 is shown, including: a substrate 210, a device region and an isolation region on the substrate 210, an isolation trench 220 located in the isolation region, and a second doping region 250 located in the device region. After step S101 is performed, step S104 is continued. At this time, since the second doping region 250 is formed before the gate structure 230 is formed, there is no shielding of the gate structure 230, and the device region can be formed by ion implantation. Fig.13 The first doped region 240 is shown.

[0094] Step S102: forming a gate structure 230 above the device region, wherein the gate structure 230 extends along a second direction perpendicular to the first direction.

[0095] Specifically, a gate structure 230 made of polysilicon can be formed on the substrate 210 by a deposition process, and the gate structure 230 can be extended to the partial isolation trenches 220 on both sides of the device region along the second direction by controlling the parameters in the deposition process, such as deposition depth, thickness, and position. After the gate structure 230 is formed, ion implantation can be performed to form the gate structure 230 on both sides of the gate structure 230. Fig.13 The source 260 and the drain 270 are shown. The gate structure 230 may extend along a second direction (Y direction) perpendicular to the first direction to a portion of the isolation trench 220 on both sides of the device region.

[0096] Step S103: forming a first doping region 240 located on both sides of the gate structure 230 along the first direction in the device region, and a second doping region 250 located outside the first doping region 240 in the second direction; wherein the first doping region and the second doping region have different doping states.

[0097] Wherein, step S104: the step of forming the second doping region 250 in the device region includes that the first doping region 240 and the second doping region 250 at least partially overlap.

[0098] Figure 5 The structure formed by steps S102 and S103 is shown, including: a substrate 210, the substrate 210 includes a device region arranged along a first direction, and an isolation structure 221 separating the device region; a gate structure 230 located on the device region, the gate structure 230 extending to a portion of the isolation structure 221 on both sides of the device region along a second direction perpendicular to the first direction; and a first doped region 240 arranged on both sides of the gate structure 230 along the first direction.

[0099] Specifically, a second doping region 250 is formed in the device area. The second doping region 250 is located on the outside of the first doping region 240 in the second direction and is also located directly below the gate structure 230. The doping states of the first doping region 140 and the second doping region 150 are different. By having the first doping region 140 and the second doping region 150 have different doping states, the effective channel width of the gate structure 130 in the second direction can be changed to improve the problem of different opening of the device edge region and the device middle region.

[0100] Specifically, as can be seen from the above, the second doping region 250 can occupy at least part of the device edge region to improve the problem of different opening of the device edge region and the device middle region. Among them, the second doping region 250 can be only located in at least part of the device edge region without overlapping with the first doping region 240. For example, the second doping region 250 is only close to the first doping region 240. In addition, when the second doping region 250 occupies at least part of the device edge region, the first doping region 240 and the second doping region 250 at least partially overlap.

[0101] The effective channel width of the gate structure 230 formed in the device region in the second direction corresponds to the difference between the first width L1 and the second width L2 .

[0102] See also Figure 5 , the first doped region 240 has a first width L1 in the second direction; the second doped region 250 is located in the device area, the second doped region 250 is located on the outside of the first doped region 240 in the second direction, and has a second width L2 in the second direction, and the effective channel width of the gate structure 230 formed in the device area in the second direction is the difference between the first width L1 and the second width L2, that is, the effective channel width of the gate structure 230 is L1-2L2.

[0103] like Figure 6 Shown Figure 5 The schematic diagram of the top view of the semiconductor device 200 in the Z direction is shown in FIG. Figure 5It can be seen that in addition to the first doped region 240 formed on both sides of the gate structure 230, a second doped region 250 is also formed directly below the gate structure 230, and the second doped region 250 and the gate structure 230 form an overlapping portion. By forming the second doped region 250, the double hump phenomenon of the Id-Vg curve of the semiconductor device 200 can be effectively improved to improve the performance of the semiconductor device 200.

[0104] Based on the method for manufacturing the semiconductor structure described in the above embodiments, the embodiments of the present application also provide a three-dimensional memory (not shown in the figure), which includes an array storage structure and a peripheral circuit, wherein any of the above semiconductor devices is located in the peripheral circuit.

[0105] Specifically, the three-dimensional memory (3D NAND Flash) includes an array storage structure (array) and a peripheral circuit (periphery circuit), and any of the above semiconductor structures is located in the peripheral circuit, wherein the array storage structure is used to store information, and the peripheral circuit can be located above or below the array storage structure, or can be located around the array storage structure, and the peripheral circuit is used to control the corresponding array storage structure. In addition, the semiconductor structure can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation.

[0106] Based on the semiconductor structure described in the above embodiments, an embodiment of the present application further provides a storage system, wherein a controller is coupled to a three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes any of the semiconductor devices described above.

[0107] Specifically, Fig.14 As shown, the storage system 400 includes a controller 410 and one or more three-dimensional memories 420, wherein the three-dimensional memories 420 include one or more array storage structures 421 and a peripheral circuit 422. The storage system 400 can communicate with the host 500 through the controller 410, wherein the controller 410 can be connected to the one or more three-dimensional memories 420 via channels in the one or more three-dimensional memories 420. Each three-dimensional memory 420 can be managed by the controller 410 via the channels in the three-dimensional memory 420.

[0108] According to the above, the semiconductor device, manufacturing method, three-dimensional memory and storage system in this embodiment, the semiconductor device includes: a substrate, the substrate includes a device area arranged along a first direction; an isolation structure, the isolation structure is used to isolate the device area; a gate structure located on the device area, the gate structure extends along a second direction perpendicular to the first direction; wherein the device area includes a first doping area and a second doping area, the first doping area is arranged on both sides of the gate structure along the first direction, the second doping area is located outside the first doping area in the second direction, and the doping states of the first doping area and the second doping area are different. By having different doping states between the first doping area and the second doping area, the effective channel width of the gate structure in the second direction can be changed to improve the double hump phenomenon of the Id-Vg curve of the semiconductor device, so as to improve the performance of the semiconductor device.

[0109] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a device region arranged along a first direction; An isolation structure, wherein the isolation structure is used to isolate the device area; a gate structure located on the device region, the gate structure extending along a second direction perpendicular to the first direction; The device region includes a first doping region and a second doping region, the first doping region is arranged on both sides of the gate structure along the first direction, the second doping region is located outside the first doping region in the second direction, and the first doping region and the second doping region have different doping states.

2. The semiconductor device according to claim 1, wherein The first doped region at least partially overlaps with the second doped region.

3. The semiconductor device according to claim 1, wherein The first doped region has a first width in the second direction, the second doped region has a second width in the second direction, and an effective channel width of the gate structure formed in the device region in the second direction corresponds to a difference between the first width and the second width.

4. The semiconductor device according to claim 1, wherein The doping type of the second doping region is opposite to the doping type of the first doping region.

5. The semiconductor device according to claim 1, wherein: The second doping region is adjacent to the first doping region and is located on two sides of the device region bordering the isolation structure along the second direction.

6. The semiconductor device according to claim 5, characterized in that The second doping region is also located below the gate structure, and a projection portion of the gate structure on the second doping region along a first longitudinal direction perpendicular to the substrate is located within the second doping region.

7. The semiconductor device according to claim 1, wherein: One of the doping type of the first doping region and the doping type of the second doping region is N-type and the other is P-type.

8. The semiconductor device according to claim 3, wherein: The second width is no greater than 50 nm.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a device region arranged along a first direction, and an isolation region separating the device region, and forming an isolation groove in the isolation region; forming a gate structure above the device region, wherein the gate structure extends along a second direction perpendicular to the first direction; forming a first doped region located at both sides of the gate structure in the device region along the first direction, and; forming a second doped region in the device region, wherein the second doped region is located outside the first doped region in a second direction; The first doping region and the second doping region have different doping states.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming a second doped region in the device region includes at least partially overlapping the first doped region and the second doped region.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming a second doped region in the device region includes: the first doped region has a first width in the second direction, the second doped region has a second width in the second direction, and the effective channel width of the gate structure formed in the device region in the second direction corresponds to the difference between the first width and the second width.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: The doping type of the second doping region is opposite to the doping type of the first doping region.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming a second doped region in the device region is performed before the step of forming a gate structure above the device region, so that the second doped region is formed before forming the gate structure.

14. The method for manufacturing a semiconductor device according to claim 9, wherein: One of the doping type of the first doping region and the doping type of the second doping region is N-type and the other is P-type.

15. A three-dimensional memory, characterized in that: The method comprises a memory cell array and a peripheral circuit, wherein the peripheral circuit comprises the semiconductor device according to any one of claims 1 to 8.

16. A storage system, characterized in that: The device comprises a controller and the three-dimensional memory according to claim 15, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

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