Display substrate, display device

Abstract

A display substrate comprises: a substrate (9), comprising a display area (91) and a peripheral area (92) surrounding the display area (91); a plurality of sub-pixels (1), located in the display area (91); a plurality of data lines (12), located at least in the display area (91) and extending along a first direction (991), the plurality of data lines (12) being electrically connected to the plurality of sub-pixels (1); a plurality of gate lines (13), located at least in the display area (91) and extending along a second direction (992), the plurality of gate lines (13) being electrically connected to the plurality of sub-pixels (1); the first direction (991) and the second direction (992) intersecting; a plurality of welding pads (8), located in the peripheral area (92); a plurality of data lead lines (73), located in the peripheral area (92), and connected to the plurality of data lines (12) and the plurality of welding pads. (8) electrically connected; the plurality of data leads (73) include a first group of data leads (738) and a second group of data leads (739); a gate drive circuit (A41) located in the peripheral area (92) and electrically connected to the plurality of gate lines (13); a plurality of gate drive lines (61) located in the peripheral area (92) and at least partially surrounding the display area (91), the plurality of gate drive lines (61) being electrically connected to the gate drive circuit (A41); a plurality of gate leads (71) located in the peripheral area (92) and extending along a first direction (991), the plurality of gate leads (71) being electrically connected to the plurality of gate drive lines (61) and a plurality of pads (8); the plurality of gate leads (71) being located between the first group of data leads (738) and the second group of data leads (739).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In order to simplify the structure of the driving chip, the detection device, etc., some units or circuits for driving the display may be directly disposed on the display substrate. Summary of the invention

[0003] The present disclosure provides a display substrate, which includes:

[0004] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] a plurality of data lines, at least located in the display area and extending along a first direction, the plurality of data lines being electrically connected to the plurality of sub-pixels;

[0007] A plurality of gate lines, at least located in the display area and extending along a second direction, the plurality of gate lines being electrically connected to the plurality of sub-pixels; the first direction intersects with the second direction;

[0008] A plurality of pads located in the peripheral area;

[0009] A plurality of data leads, located in the peripheral area, and electrically connected to the plurality of data lines and the plurality of pads; the plurality of data leads include a first group of data leads and a second group of data leads;

[0010] a gate driving circuit, located in the peripheral area and electrically connected to the plurality of gate lines;

[0011] a plurality of gate drive lines, located in the peripheral area and at least partially surrounding the display area, the plurality of gate drive lines being electrically connected to the gate drive circuit;

[0012] A plurality of gate leads are located in the peripheral area and extend along the first direction. The plurality of gate leads are electrically connected to the plurality of gate drive lines and the plurality of pads. The plurality of gate leads are located between the first group of data leads and the second group of data leads.

[0013] In some embodiments, the plurality of gate drive lines include a gate start signal line, a first gate clock signal line, a second gate clock signal line, a gate drive test line, a high level signal line, and a low level signal line.

[0014] In some embodiments, the display substrate further comprises:

[0015] A plurality of control electrode lines, at least located in the display area and extending along the second direction, the plurality of control electrode lines being electrically connected to the plurality of sub-pixels;

[0016] A control electrode driving circuit is located in the peripheral area and is electrically connected to the plurality of control electrode lines;

[0017] A plurality of control electrode drive lines are located in the peripheral area and at least partially surround the display area, and the plurality of control electrode drive lines are electrically connected to the control electrode drive circuit;

[0018] A plurality of control electrode leads are located in the peripheral area and extend along the first direction. The plurality of control electrode leads are electrically connected to the plurality of control electrode drive lines and the plurality of pads. The plurality of control electrode leads are located between the first group of data leads and the second group of data leads.

[0019] In some embodiments, the plurality of control electrode drive lines include a control electrode start signal line, a first control electrode clock signal line, a second control electrode clock signal line, a control electrode drive test line, a high level signal line, and a low level signal line.

[0020] In some embodiments, the gate driving circuit and the gate driving circuit are located at two opposite sides of the display area along the second direction.

[0021] In some embodiments, the display substrate further comprises:

[0022] a multiplexing circuit, located in the peripheral area and electrically connected to the plurality of data lines;

[0023] a plurality of data drive lines located in the peripheral area and at least partially surrounding the display area, the multiplexing circuit being electrically connected to the plurality of data drive lines and the plurality of data lead lines;

[0024] a plurality of multiplexing driving lines located in the peripheral area and at least partially surrounding the display area, the plurality of multiplexing driving lines being electrically connected to the multiplexing circuit;

[0025] A plurality of multiplexing leads are located in the peripheral area and extend along the first direction, the plurality of multiplexing leads are electrically connected to the plurality of multiplexing driving lines and the plurality of pads; the plurality of multiplexing leads are located between the first group of data leads and the second group of data leads.

[0026] In some embodiments, the plurality of gate driving lines, the plurality of multiplexing driving lines, and the plurality of data driving lines are located on a side of the gate driving circuit and the multiplexing circuit away from the display area.

[0027] In some embodiments, the plurality of multiplexing driving lines are located on a side of the plurality of gate driving lines away from the display area;

[0028] The plurality of data driving lines are located at a side of the plurality of multiplexing driving lines away from the display area.

[0029] In some embodiments, the display substrate further comprises:

[0030] a test circuit, located in the peripheral area and electrically connected to the plurality of data lines;

[0031] a plurality of test drive lines, located in the peripheral area and at least partially surrounding the display area, the plurality of test drive lines being electrically connected to the test circuit;

[0032] A plurality of test leads are located in the peripheral area and extend along the first direction, the plurality of test leads are electrically connected to the plurality of test drive lines and the plurality of pads; the plurality of test leads are located between the first group of data leads and the second group of data leads.

[0033] In some embodiments, the plurality of test driving lines include test data signal lines and test control signal lines.

[0034] In some embodiments, the display substrate further comprises:

[0035] a multiplexing circuit, located in the peripheral area and electrically connected to the plurality of data lines;

[0036] The test circuit and the multiplexing circuit are located at two opposite sides of the display area along the first direction;

[0037] The plurality of pads are located at a side of the multiplexing circuit away from the display area.

[0038] In some embodiments, the display substrate further comprises:

[0039] an electrostatic discharge circuit, located in the peripheral area;

[0040] an electrostatic discharge driving line, located in the peripheral area and at least partially surrounding the display area, the electrostatic discharge driving line being electrically connected to the electrostatic discharge circuit;

[0041] The electrostatic release lead is located in the peripheral area and extends along the first direction. The electrostatic release lead is electrically connected to the electrostatic release drive line and the pad. The electrostatic release lead is located between the first group of data leads and the second group of data leads.

[0042] In some embodiments, the display substrate further comprises:

[0043] an initialization driving line, located in the peripheral area and at least partially surrounding the display area, the initialization driving line being electrically connected to the plurality of sub-pixels;

[0044] An initialization lead is located in the peripheral area and extends along the first direction. The initialization lead is electrically connected to the initialization drive line and the pad. The initialization lead is located between the first group of data leads and the second group of data leads.

[0045] In some embodiments, the display substrate further comprises:

[0046] A first power driving line, located in the peripheral area and at least partially surrounding the display area, the first power driving line being electrically connected to the plurality of sub-pixels;

[0047] A first power lead is located in the peripheral area and extends along the first direction, the first power lead is electrically connected to the first power driving line and the pad; the first power lead is located between the first group of data leads and the second group of data leads;

[0048] A second power driving line, located in the peripheral area and at least partially surrounding the display area, the second power driving line being electrically connected to the plurality of sub-pixels;

[0049] A second power lead is located in the peripheral area and extends along the first direction, and the second power lead is electrically connected to the second power drive line and the pad; the second power lead is located on the side of the first group of data leads away from the second group of data leads, or is located on the side of the second group of data leads away from the first group of data leads.

[0050] In some embodiments, the plurality of pads are located in an access area and are arranged along the second direction; the access area is located on one side of the display area along the first direction;

[0051] The plurality of gate leads and the plurality of data leads are located in a lead-out area; the lead-out area is located between the access area and the display area along the first direction;

[0052] Along the second direction, the plurality of gate leads are located between the first group of data leads and the second group of data leads.

[0053] In some embodiments, along the second direction, the plurality of pads electrically connected to the plurality of gate leads are located between the plurality of pads electrically connected to the first group of data leads and the plurality of pads electrically connected to the second group of data leads.

[0054] In some embodiments, the display substrate further comprises:

[0055] A plurality of control electrode lines, at least located in the display area and extending along the second direction, the plurality of control electrode lines being electrically connected to the plurality of sub-pixels;

[0056] A control electrode driving circuit is located in the peripheral area and is electrically connected to the plurality of control electrode lines;

[0057] A plurality of control electrode drive lines are located in the peripheral area and at least partially surround the display area, and the plurality of control electrode drive lines are electrically connected to the control electrode drive circuit;

[0058] A plurality of control electrode leads are located in the peripheral area and extend along the first direction. The plurality of control electrode leads are electrically connected to the plurality of control electrode drive lines and the plurality of pads. The plurality of control electrode leads are located between the first group of data leads and the second group of data leads.

[0059] In some embodiments, the display substrate further comprises:

[0060] A first power driving line, located in the peripheral area and at least partially surrounding the display area, the first power driving line being electrically connected to the plurality of sub-pixels;

[0061] A first power lead is located in the peripheral area and extends along the first direction, the first power lead is electrically connected to the first power driving line and the pad; the first power lead is located between the first group of data leads and the second group of data leads;

[0062] A second power driving line, located in the peripheral area and at least partially surrounding the display area, the second power driving line being electrically connected to the plurality of sub-pixels;

[0063] a second power lead, located in the peripheral area and extending along the first direction, the second power lead being electrically connected to the second power drive line and the pad; the second power lead being located on a side of the first group of data leads away from the second group of data leads, or on a side of the second group of data leads away from the first group of data leads;

[0064] Along the second direction, the pad electrically connected to the first power lead is located on a side of the pad electrically connected to the first group of data leads away from the pad electrically connected to the second group of data leads, or is located on a side of the pad electrically connected to the second group of data leads away from the pad electrically connected to the first group of data leads;

[0065] Along the second direction, the pad electrically connected to the second power lead is located on a side of the pad electrically connected to the first group of data leads that is away from the pad electrically connected to the second group of data leads, or is located on a side of the pad electrically connected to the second group of data leads that is away from the pad electrically connected to the first group of data leads.

[0066] In some embodiments, the display area is substantially circular;

[0067] The display substrate is substantially circular.

[0068] In a second aspect, an embodiment of the present disclosure provides a display device, comprising:

[0069] Any of the above display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0071] Figure 1 A schematic diagram of a top view structure of a display substrate provided in an embodiment of the present disclosure;

[0072] Figure 2 A schematic diagram of a top view of the distribution of some leads in a display substrate provided by an embodiment of the present disclosure;

[0073] Figure 3 A schematic diagram of the partial structure of an access area and an extraction area in a display substrate provided in an embodiment of the present disclosure;

[0074] Figure 4 A schematic diagram of the partial structure of an access area and an extraction area in another display substrate provided in an embodiment of the present disclosure;

[0075] Figure 5 A schematic diagram showing the positions of some structures in a display substrate provided by an embodiment of the present disclosure;

[0076] Figure 6 A circuit diagram of a sub-pixel in a display substrate provided in an embodiment of the present disclosure;

[0077] Figure 7 A schematic diagram of a partial cross-sectional structure of a sub-pixel in a display substrate provided in an embodiment of the present disclosure;

[0078] Figure 8 A circuit diagram of a gate shift register in a display substrate provided by an embodiment of the present disclosure;

[0079] Fig. 9 for Figure 8 The driving timing diagram of the gate shift register;

[0080] Fig.10 A circuit diagram of a control gate shift register in a display substrate provided by an embodiment of the present disclosure;

[0081] Fig.11 for Fig.10 The driving timing diagram of the control electrode shift register;

[0082] Fig.12 A circuit diagram of a multiplexing unit in a display substrate provided in an embodiment of the present disclosure

[0083] Fig.13 A circuit diagram of a test unit in a display substrate provided by an embodiment of the present disclosure;

[0084] Fig.14 A circuit diagram of an electrostatic discharge unit in a display substrate provided in an embodiment of the present disclosure;

[0085] Fig.15 for Figure 3 A local enlarged structural design layout of position A of a display substrate;

[0086] Fig.16 for Figure 4 A local enlarged structural design layout of a position B of a display substrate;

[0087] Fig.17 for Figure 4 A local enlarged structural design layout of a C position of a display substrate;

[0088] Fig.18 for Figure 4 A local enlarged structural design layout of a D position of a display substrate;

[0089] Fig.19 A local enlarged structural design layout of a position in a peripheral area of ​​a display substrate provided in an embodiment of the present disclosure;

[0090] Fig. 20 A structural design layout of a gate shift register in a display substrate provided in an embodiment of the present disclosure;

[0091] Fig.21 A structural design layout of a control gate shift register in a display substrate provided in an embodiment of the present disclosure;

[0092] Fig. 22A structural design layout of a multiplexing unit in a display substrate provided in an embodiment of the present disclosure

[0093] Fig.23 A structural design layout of a test unit in a display substrate provided in an embodiment of the present disclosure

[0094] Fig.24 A structural design layout of an electrostatic release unit in a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0095] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the display substrate and the display device provided by the embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings.

[0096] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0097] The embodiments of the present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0098] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0099] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0100] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0101] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0102] In the embodiments of the present disclosure, in the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0103] In the embodiments of the present disclosure, ordinal numbers such as “first”, “second”, and “third” are provided to avoid confusion among constituent elements rather than to limit the number.

[0104] In the embodiments of the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0105] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0106] In the disclosed embodiment, "A is basically B" means that A meets feature B in terms of the overall scale, but A may not completely meet feature B in terms of a scale that is significantly smaller than A as a whole. For example, "A is basically circular" means that A may be a perfect circle or ellipse, or the shape of A may be circular or elliptical as a whole, but some of its detailed structures are not strictly circular: for example, a small portion of the boundary of A may be a straight line or a broken line; for another example, some positions of the boundary of A may have protrusions or depressions; for another example, a small portion of the boundary of A may be an arc that is similar to an arc but not a strict arc; for another example, the boundaries of A at different positions may be arcs with different diameters, etc.

[0107] In the disclosed embodiments, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0108] In the disclosed embodiments, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0109] In the embodiments of the present disclosure, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0110] In the disclosed embodiments, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0111] In the embodiments of the present disclosure, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0112] In the embodiments of the present disclosure, "about" means that the limits are not strictly defined and the numerical value is allowed to be within the range of process and measurement errors.

[0113] First, refer to Figures 1 to 24 , an embodiment of the present disclosure provides a display substrate.

[0114] In some drawings of the embodiments of the present disclosure, due to space limitations, in order to clearly show the main structure, some structures are not shown, and some structures of the same type are combined into one structure. Therefore, the number, specific position, specific size relationship, etc. of the structures shown in each drawing are only schematic, and not a limitation of the embodiments of the present disclosure.

[0115] For example, each of the driving lines, leads, and auxiliary leads corresponding to a circuit is referred to as "a group of lines", and "a group of lines" may actually include multiple lines. In some drawings, one or two lines may be used to represent multiple lines in the same group.

[0116] The display substrate of the embodiment of the present disclosure is a substrate used in a display device, for example, an array substrate provided with a thin film transistor (TFT) array, and may also be provided with a light emitting device (such as an organic light emitting diode) for display.

[0117] The display substrate of the embodiment of the present disclosure includes:

[0118] A substrate 9, comprising a display area 91 and a peripheral area 92 surrounding the display area 91;

[0119] A plurality of sub-pixels 1, located in a display area 91;

[0120] A plurality of data lines 12, at least located in the display area 91 and extending along the first direction 991, the plurality of data lines 12 being electrically connected to the plurality of sub-pixels 1;

[0121] A plurality of gate lines 13 are at least located in the display area 91 and extend along the second direction 992. The plurality of gate lines 13 are electrically connected to the plurality of sub-pixels 1. The first direction 991 and the second direction 992 intersect.

[0122] A plurality of pads 8 located in the peripheral area 92;

[0123] A plurality of data leads 73 are located in the peripheral area 92 and are electrically connected to the plurality of data lines 12 and the plurality of pads 8; the plurality of data leads 73 include a first group of data leads 738 and a second group of data leads 739;

[0124] The gate driving circuit A41 is located in the peripheral area 92 and is electrically connected to the plurality of gate lines 13;

[0125] A plurality of gate driving lines 61 are located in the peripheral area 92 and at least partially surround the display area 91 , and the plurality of gate driving lines 61 are electrically connected to the gate driving circuit A41 ;

[0126] The plurality of gate leads 71 ​​are located in the peripheral area 92 and extend along the first direction 991 . The plurality of gate leads 71 ​​are electrically connected to the plurality of gate driving lines 61 and the plurality of pads 8 . The plurality of gate leads 71 ​​are located between the first group of data leads 738 and the second group of data leads 739 .

[0127] Reference Figure 1 , Figure 7 , various structures in the display substrate of the embodiment of the present disclosure are arranged on the "base 9".

[0128] Among them, the base 9 is the basis for supporting other structures on the display substrate. It is a basically sheet-like structure composed of glass, silicon (such as single crystal silicon), polymer material (such as polyimide) and other materials. It can be rigid or flexible, and the thickness can be in the order of millimeters.

[0129] The substrate 9 includes a display area 91 located in the middle and a peripheral area 92 surrounding the display area 91 .

[0130] The display area 91 is provided with a plurality of sub-pixels 1 for display.

[0131] Each sub-pixel 1 refers to the smallest structure that can be used to independently display required content, that is, the smallest "dot" that can be independently controlled in the display device.

[0132] Different sub-pixels 1 may have different colors, so that color display can be achieved through the mixing of light from different sub-pixels 1. When color display is to be achieved, multiple sub-pixels 1 of different colors arranged together may form a "pixel (or pixel unit)", that is, the light emitted by these sub-pixels 1 is mixed together to form a visual "point"; for example, three sub-pixels 1 of red, green, and blue may form a pixel. Alternatively, there may be no clear pixel (or pixel unit), but color display may be achieved through "sharing" between adjacent sub-pixels 1.

[0133] Reference Figure 1 In the display area 91, there are also data lines 12 extending along the first direction 991 and gate lines 13 extending along the second direction 992, wherein the first direction 991 intersects with the second direction 992 (i.e., they are not parallel to each other), so that each intersection of the data line 12 and the gate line 13 can define a sub-pixel 1, and through the joint control of the gate line 13 and the data line 12, the sub-pixel 1 at the intersection of the two can be displayed; in addition, the display area 91 can also be provided with a control electrode line 14 extending along the second direction 992, which also plays a role in controlling the sub-pixel 1.

[0134] In some embodiments, the first direction 991 is perpendicular to the second direction 992, that is, the first direction 991 may be a column direction (longitudinal direction, or column direction in each figure), and the second direction 992 may be a row direction (lateral direction, or row direction in each figure) perpendicular to the column direction.

[0135] It should be understood that the first direction 991 and the second direction 992 are actually just two relative directions corresponding to the data line 12 and the gate line 13 (or the control electrode line 14). The two are not necessarily the column direction and the row direction, and have no necessary relationship with the shape, position, placement, etc. of the display substrate (or display device).

[0136] In some embodiments, the sub-pixels 1 in the display area 91 can be arranged in an array, that is, the sub-pixels 1 can be arranged in multiple rows and columns, wherein each row of sub-pixels 1 is connected to a gate line 13 and a control electrode line 14, and each column of sub-pixels 1 is connected to a data line 12.

[0137] It should be understood that the sub-pixels 1 are not necessarily arranged in an array, and each data line 12 , gate line 13 , and control electrode line 14 is not necessarily connected to the sub-pixels 1 in the same column or row.

[0138] Exemplarily, the sub-pixel 1 may include a pixel circuit, which may emit light of desired brightness under the control of the corresponding gate line 13, the data line 12, etc. For example, the pixel circuit may be a 7T1C structure (i.e., including 7 transistors and 1 capacitor), referring to Figure 6 The above pixel circuit 7T1C may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, an organic light emitting diode OLED, a first reset terminal Reset, a second reset terminal Reset', an initialization signal terminal Vinit, a gate line 13 terminal Gate, a data line 12 terminal Data, a control terminal EM, a first power signal terminal VDD, a second power signal terminal VSS and the like; wherein each transistor may be a P-type transistor (such as PMOS).

[0139] That is to say, in each sub-pixel 1 of the display substrate of the embodiment of the present disclosure, an organic light emitting diode OLED can be used as a light emitting device, which is specifically an organic light emitting diode display substrate and also an array substrate provided with a thin film transistor (TFT) array.

[0140] Reference Figure 7 In some embodiments, the third transistor T3 in each sub-pixel 1 is a driving transistor, wherein the specific structure and stacking relationship of some devices may be as follows:

[0141] The driving transistor (third transistor T3) includes:

[0142] A first active layer 111 located on one side of the substrate 9;

[0143] A gate insulating layer 190 located on a side of the first active layer 111 away from the substrate 9;

[0144] A first gate electrode 112 located on a side of the gate insulating layer 190 away from the substrate 9;

[0145] A first insulating layer 191 located at a side of the first gate 112 away from the substrate 9;

[0146] A second insulating layer 192 (interlayer insulating layer ILD) located on a side of the first insulating layer 191 away from the substrate 9;

[0147] Located at a side of the second insulating layer 192 away from the substrate 9 , the first source electrode 113 and the first drain electrode 114 electrically connected to the first active layer 111 ;

[0148] The storage capacitor Cst includes:

[0149] A first pole piece 121 is provided at the same layer as the first gate 112;

[0150] The second pole piece 122 is located between the first insulating layer 191 and the second insulating layer 192 .

[0151] Of course, the sub-pixel 1 may also include other structures.

[0152] Of course, the specific structure of the sub-pixel 1 and the pixel circuit is not limited to the above method.

[0153] Among them, the data line 12 end Data can be connected to the data line 12, the gate line 13 end Gate can be connected to the gate line 13, the control line 14 end EM can be connected to the control line 14, the first reset end Reset and the second reset end Reset' can be connected to the gate line 13 of the previous row at the same time, and the second reset end Reset' can also be connected to the gate line 13 of the current row, and other ends (such as the initialization signal end Vinit, the first power signal end VDD, and the second power signal end VSS) can also be connected to corresponding signal sources, and these signal sources can be "lines" or integrated conductive structures.

[0154] The above-mentioned data lines 12, gate lines 13, control lines 14, and signals of the signal source for supplying power to the initialization signal terminal Vinit, the first power signal terminal VDD, and the second power signal terminal VSS are essentially provided directly (such as the driving lines are directly connected to the lines or signal sources in the display area 91) or indirectly (such as the driving lines are connected to the lines or signal sources in the display area 91 through certain units) through a variety of driving lines arranged in the peripheral area 92, surrounding or partially surrounding the display area 91.

[0155] Various driving lines are connected to the "leads" located in the peripheral area 92 and extending along the first direction 991; each "lead" is then directly or indirectly (such as through an auxiliary lead) connected to the corresponding pad 8, that is, the signal driving the sub-pixel 1 essentially comes from the "pad 8".

[0156] The pad 8 (Pad or Pin) refers to a structure in the peripheral area 92 of the display substrate that can obtain other signals and ultimately introduce the signals into the sub-pixel 1 .

[0157] Specifically, the pad 8 can be used to bind (Bonding) with a flexible circuit board (FPC) or a driver chip to obtain a signal from the flexible circuit board or the driver chip; or, the pad 8 can also be used to contact a test probe of a test device to obtain a signal from the test probe (or feed back a signal to the test probe).

[0158] Among them, the data leads 73 that are ultimately electrically connected to the data lines 12 (through the data driving lines 63 located in the peripheral area 92) include two groups, namely a first group of data leads 738 and a second group of data leads 739, while the majority of other leads (at least including the gate leads 71 ​​that are ultimately electrically connected to the gate lines 13) are located "between" the first group of data leads 738 and the second group of data leads 739.

[0159] That is, in the embodiment of the present disclosure, the data lead 73 is located at the “outside” (eg, outside along the second direction 992 ) relative to the other test leads 75 .

[0160] Compared with other leads, the number of data leads 73 is usually the largest, so the area of ​​the fan-out line (Fanout) required to transform from extending along the first direction 991 (longitudinal direction) to extending around the display area 91 (ie, the data drive line 63) is also larger.

[0161] In the disclosed embodiment, the data lead 73 is arranged on both sides of the other leads (or closer to the sides), so as to be closer to both sides of the peripheral area 92, which is convenient for fan-out, can reduce the wiring area, compress the border width of the display device, and realize a narrow border design.

[0162] For example, refer to Figure 5 When the length of the data lead 73 along the first direction 991 is the same, it is equivalent to the starting point of the fan-out line (the connection line between the data lead 73 and the data driving line 63) being "towards the side", so that relative to the data lead 73 being arranged in the middle, the dimension d1 can be saved in the second direction 992, or the dimension h1 can be saved in the first direction 991, thereby reducing the size of the peripheral area 92 and realizing a narrow frame design.

[0163] In some embodiments, the display area 91 is substantially circular; the display substrate is substantially circular.

[0164] Reference Figure 1 , Figure 2As one mode of an embodiment of the present disclosure, the above display area 91 and the display substrate may be basically circular, so that the peripheral area 92 outside the display area 91 is basically "ring-shaped", and the display device corresponding to the display substrate is also basically circular as a whole, such as a circular "smart watch".

[0165] Of course, the above shapes are not limitations on the specific forms of the display substrate and the regions therein, and the display substrate and the regions therein may also be other shapes.

[0166] In some embodiments, the plurality of gate drive lines 61 include a gate start signal line 611 , a first gate clock signal line 612 , a second gate clock signal line 613 , a gate drive test line 614 , a high level signal line 615 , and a low level signal line 616 .

[0167] Reference Fig.18 The above gate drive line 61 may specifically include a gate start signal line 611 , a first gate clock signal line 612 , a second gate clock signal line 613 , a gate drive test line 614 , a high level signal line 615 , and a low level signal line 616 .

[0168] Among them, refer to Figure 1 The gate driving circuit A41 may be composed of a plurality of gate driving units 41, and each gate driving unit 41 provides a gate driving signal to a gate line 13; wherein the gate driving units 41 may be located on both sides of the display area 91 along the second direction 992 (the row direction in each of the accompanying drawings), respectively, so as to provide gate driving signals to the gate lines 13 of different rows, respectively, or provide gate driving signals to the gate lines 13 from both sides at the same time (double-sided driving).

[0169] Specifically, each gate driving unit 41 may be a gate shift register (GOA), and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers can provide driving signals to a plurality of gate lines 13 respectively.

[0170] The specific forms of the gate shift register are various. For example, the circuit structure and driving timing of the gate shift register can be referred to Figure 8 , Fig. 20 , Fig. 9 The low level of each of the following signals may be specifically equal to the low level signal VGL, and the high level of each of the following signals may be specifically equal to the high level signal VGH.

[0171] In the input stage t1, the first gate clock signal CK is at a low level, the second gate clock signal CB is at a high level, and the gate start signal GSTV is at a low level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the gate start signal GSTV is transmitted to the third gate node N3 via the second gate transistor K2. Since the second gate transistor K2 has a threshold loss, the level of the third gate node N3 is GSTV - Vth2, that is, VGL - Vth2, where Vth2 represents the threshold level of the second gate transistor K2. Since the gate of the sixth gate transistor K6 receives the low-level signal VGL, the sixth gate transistor K6 is in an on state. Thus, the level VGL - Vth2 is transmitted to the first gate node N1 via the sixth gate transistor K6. For example, the threshold level of the sixth gate transistor K6 is denoted as Vth6. Similarly, since the sixth gate transistor K6 has a threshold loss, the level of the first gate node N1 is VGL - VthN1, where VthN1 is the smaller one of Vth2 and Vth6. The level of the first gate node N1 can control the eighth gate transistor K8 to be turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8. That is, in the input stage t1, the gate output signal GOUT is the second gate clock signal CB at a high level, that is, equal to VGH.

[0172] In the input stage t1, since the first gate clock signal CK is at a low level, the first gate transistor K1 is turned on, and the low-level signal VGL is transmitted to the second gate node N2 via the first gate transistor K1. Since the level of the third gate node N3 is VGL - Vth2, the seventh gate transistor K7 is turned on, and the low-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7. For example, the threshold level of the seventh gate transistor K7 is denoted as Vth7, and the threshold level of the first gate transistor K1 is denoted as Vth1. When Vth1 < Vth7 + Vth2, the level of the second gate node N2 is VGL - Vth7 - Vth2; when Vth1 > Vth7 + Vth2, the level of the second gate node N2 is VGL - Vth1. At this time, both the third gate transistor K3 and the fourth gate transistor K4 are turned on. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.

[0173] In the output stage t2, the first gate clock signal CK is at a high level, the second gate clock signal CB is at a low level, and the gate start signal GSTV is at a high level. The eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8. In the input stage t1, the level of one end of the second gate capacitor C2 connected to the first gate node N1 is VGL-VthN1, and the level of the other end is high; and in the output stage t2, the level of one end of the second gate capacitor C2 connected to the output end GOUT becomes VGL, and due to the bootstrap effect of the second gate capacitor C2, the level of one end of the second gate capacitor C2 connected to the first gate node N1 becomes 2VGL-VthN1-VGH, that is, the level of the first gate node N1 becomes 2VGL-VthN1-VGH, at this time, the sixth gate transistor K6 is turned off, the eighth gate transistor K8 can be better turned on, and the gate output signal GOUT is a low level signal VGL.

[0174] In the output stage t2, the first gate clock signal CK is at a high level, so that the second gate transistor K2 and the first gate transistor K1 are both turned off. The level of the third gate node N3 is still VGL-VthN1, the seventh gate transistor K7 is turned on, and the high-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7, that is, the level of the second gate node N2 is VGH, thus, the third gate transistor K3 and the fourth gate transistor K4 are both turned off. Since the second gate clock signal CB is at a low level, the fifth gate transistor K5 is turned on.

[0175] In the buffering stage t3, the first gate clock signal CK and the second gate clock signal CB are both at high level, and the gate start signal GSTV is at high level. The eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8. At this time, the gate output signal GOUT is the second gate clock signal CB at a high level, that is, VGH. Due to the bootstrap effect of the second gate capacitor C2, the level of the first gate node N1 becomes VGL-VthN1.

[0176] In the buffering stage t3, the first gate clock signal CK is at a high level, so that the second gate transistor K2 and the first gate transistor K1 are both turned off. The level of the first gate node N1 becomes VGL-VthN1. At this time, the sixth gate transistor K6 is turned on, the level of the third gate node N3 is also VGL-VthN1, the seventh gate transistor K7 is turned on, and the high-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7, that is, the level of the second gate node N2 is VGH, thus, the third gate transistor K3 and the fourth gate transistor K4 are both turned off. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.

[0177] In the first sub-phase t41 of the stable phase t4, the first gate clock signal CK is at a low level, the second gate clock signal CB is at a high level, and the gate start signal GSTV is at a high level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the gate start signal GSTV is transmitted to the third gate node N3 via the second gate transistor K2. Since the second gate transistor K2 transmits a high level without threshold loss, the level of the third gate node N3 is VGH, and the seventh gate transistor K7 is turned off. Since the sixth gate transistor K6 is in an on state, the level of the first gate node N1 is the same as that of the third gate node N3, that is, the level of the first gate node N1 is VGH, and the eighth gate transistor K8 is turned off. Since the first gate clock signal CK is at a low level, the first gate transistor K1 is turned on, the level of the second gate node N2 is VGL-Vth1, the third gate transistor K3 and the fourth gate transistor K4 are both turned on, and the high level signal VGH is transmitted as the gate output signal GOUT via the third gate transistor K3, that is, the gate output signal is a high level signal VGH.

[0178] In the second sub-phase t42 of the stable phase t4, the first gate clock signal is at a high level, the second gate clock signal is at a low level, and the gate start signal GSTV is at a high level. The levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are both turned off. The first gate clock signal CK is at a high level, so that the second gate transistor K2 and the first gate transistor K1 are both turned off. Due to the holding effect of the first gate capacitor C1, the level of the second gate node N2 is still VGL-Vth1, the third gate transistor K3 and the fourth gate transistor K4 are both turned on, and the high-level signal VGH is used as the gate output signal GOUT via the third gate transistor K3, that is, the gate output signal is a high-level signal VGH.

[0179] In the second sub-phase t42, since the second gate clock signal CB is at a low level, the fifth gate transistor K5 is turned on, so that the high-level signal VGH is transmitted to the third gate node N3 and the first gate node N1 via the fourth gate transistor K4 and the fifth gate transistor K5, so that the levels of the first gate node N1 and the third gate node N3 are maintained at a high level.

[0180] In the third sub-phase t43 of the stable phase t4, the first gate clock signal CK and the second gate clock signal CB are both at high level, and the gate start signal GSTV is at high level. The levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are turned off. The first gate clock signal CK is at a high level, so that the second gate transistor K2 and the first gate transistor K1 are both turned off, the level of the second gate node N2 is still VGL-Vth1, and the third gate transistor K3 and the fourth gate transistor K4 are both turned on. The high-level signal VGH is used as the gate output signal GOUT via the third gate transistor K3, that is, the gate output signal is a high-level signal VGH.

[0181] Among them, the above first gate clock signal CK can be provided through the above first gate clock signal line 612, and the second gate clock signal CB can be provided through the above second gate clock signal line 613, and the high level signal VGH and the low level signal VGL are provided through the high level signal line 615 and the low level signal line 616 respectively.

[0182] The gate start signal GSTV is provided by the gate output signal GOUT of the previous gate shift register, and the gate start signal GSTV of the first gate shift register is provided through the gate start signal line 611. The gate output signal GOUT generated by the last gate shift register is also connected to the gate drive test line 614 to detect whether the gate drive circuit A41 is working normally.

[0183] In some embodiments, the display substrate further comprises:

[0184] A plurality of control electrode lines 14, at least located in the display area 91 and extending along the second direction 992, the plurality of control electrode lines 14 being electrically connected to the plurality of sub-pixels 1;

[0185] A gate driving circuit A42 is located in the peripheral area 92 and is electrically connected to the plurality of gate lines 14;

[0186] A plurality of control electrode drive lines 62 are located in the peripheral area 92 and at least partially surround the display area 91, and the plurality of control electrode drive lines 62 are electrically connected to the control electrode drive circuit A42;

[0187] The plurality of control electrode leads 72 are located in the peripheral area 92 and extend along the first direction 991 . The plurality of control electrode leads 72 are electrically connected to the plurality of control electrode driving lines 62 and the plurality of pads 8 . The plurality of control electrode leads 72 are located between the first group of data leads 738 and the second group of data leads 739 .

[0188] Reference Figure 1The signal of the above control line 14 can be provided by the control driving circuit A42, and the control driving circuit A42 is driven by the control driving line 62, and the control driving line 62 is connected to the control lead 72 extending along the first direction 991, and the control lead 72 is also located between the above first group of data leads 738 and the second group of data leads 739.

[0189] In some embodiments, reference Fig.18 The plurality of control electrode drive lines 62 include a control electrode start signal line 621 , a first control electrode clock signal line, a second control electrode clock signal line 623 , a control electrode drive test line 624 , a high level signal line 615 , and a low level signal line 616 .

[0190] Among them, refer to Figure 1 The gate drive circuit A42 may be composed of a plurality of gate drive units 42, and each gate drive unit 42 provides a gate drive signal to a gate line 14; wherein each gate drive unit 42 may be located on both sides of the display area 91 along the second direction 992 (the row direction in each drawing), so as to provide gate drive signals to the gate lines 14 of different rows, or provide gate drive signals to the gate lines 14 from both sides at the same time (double-sided drive).

[0191] Specifically, each gate driving unit 42 may be a gate shift register (EM GOA), and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers can provide driving signals to a plurality of gate lines 14 respectively.

[0192] The specific forms of the control gate shift register are various. For example, the circuit structure and driving timing of the control gate shift register can refer to Fig.10 , Fig.21 , Fig.11 The low level of each of the following signals may be specifically equal to the low level signal VGL, and the high level of each of the following signals may be specifically equal to the high level signal VGH.

[0193] Among them, in the first stage P1, the first control electrode clock signal CK' is at a low level, so the first control electrode transistor M1 and the third control electrode transistor M3 are turned on, and the turned-on first control electrode transistor M1 transmits the high-level control electrode start signal ESTV to the first control electrode node N1', so that the level of the first control electrode node N1' becomes high, so the second control electrode transistor M2, the eighth control electrode transistor M8 and the tenth control electrode transistor M10 are turned off. In addition, the turned-on third control electrode transistor M3 transmits the low-level low-level signal VGL to the second control electrode node N2', so that the level of the second control electrode node N2' becomes low, so the fifth control electrode transistor M5 and the sixth control electrode transistor M6 are turned on. Since the second control electrode clock signal CB' is at a high level, the seventh control electrode transistor M7 is turned off. In addition, due to the storage effect of the third control electrode capacitor C3', the level of the fourth control electrode node N4 can be kept at a high level, so that the ninth control electrode transistor M9 is turned off. In the first phase P1 , since the ninth control transistor M9 and the tenth control transistor M10 are both turned off, the control output signal EMOUT maintains the previous low level.

[0194] In the second stage P2, the second control electrode clock signal CB' is at a low level, so the fourth control electrode transistor M4 and the seventh control electrode transistor M7 are turned on. Since the first control electrode clock signal CK' is at a high level, the first control electrode transistor M1 and the third control electrode transistor M3 are turned off. Due to the storage function of the first control electrode capacitor C1', the second control electrode node N2' can continue to maintain the low level of the previous stage, so the fifth control electrode transistor M5 and the sixth control electrode transistor M6 are turned on. The high level signal VGH is transmitted to the first control electrode node N1' through the turned-on fifth control electrode transistor M5 and the fourth control electrode transistor M4, so that the level of the first control electrode node N1' continues to maintain the high level of the previous stage, so the second control electrode transistor M2, the eighth control electrode transistor M8 and the tenth control electrode transistor M10 are turned off. In addition, the low-level second control electrode clock signal CB' is transmitted to the fourth control electrode node N4' through the turned-on sixth control electrode transistor M6 and the seventh control electrode transistor M7, so that the level of the fourth control electrode node N4' becomes a low level, so the ninth control electrode transistor M9 is turned on, and the turned-on ninth control electrode transistor M9 outputs the high-level signal VGH, so the control electrode output signal EMOUT is a high level.

[0195] In the third stage P3, the first control electrode clock signal CK' is at a low level, so the first control electrode transistor M1 and the third control electrode transistor M3 are turned on. The second control electrode clock signal CB' is at a high level, so the fourth control electrode transistor M4 and the seventh control electrode transistor M7 are turned off. Due to the storage function of the third control electrode capacitor C3', the level of the fourth control electrode node N4' can maintain the low level of the previous stage, so that the ninth control electrode transistor M9 remains in the on state, and the turned-on ninth control electrode transistor M9 outputs the high level signal VGH, so the control electrode output signal EMOUT is still at a high level.

[0196] In the fourth stage P4, the first control electrode clock signal CK' is at a high level, so the first control electrode transistor M1 and the third control electrode transistor M3 are turned off. The second control electrode clock signal CB' is at a low level, so the fourth control electrode transistor M4 and the seventh control electrode transistor M7 are turned on. Due to the storage function of the second control electrode capacitor C2', the level of the first control electrode node N1' remains at a high level in the previous stage, so that the second control electrode transistor M2, the eighth control electrode transistor M8 and the tenth control electrode transistor M10 are turned off. Due to the storage function of the first control electrode capacitor C1', the second control electrode node N2 continues to maintain the low level of the previous stage, so that the fifth control electrode transistor M5 and the sixth control electrode transistor M6 are turned on. In addition, the low-level second control electrode clock signal CB' is transmitted to the fourth control electrode node N4' through the turned-on sixth control electrode transistor M6 and the seventh control electrode transistor M7, so that the level of the fourth control electrode node N4' becomes a low level, so the ninth control electrode transistor M9 is turned on, and the turned-on ninth control electrode transistor M9 outputs the high-level signal VGH, so the control electrode output signal EMOUT is still at a high level.

[0197] In the fifth stage P5, the first control electrode clock signal CK' is at a low level, so the first control electrode transistor M1 and the third control electrode transistor M3 are turned on. The second control electrode clock signal CB' is at a high level, so the fourth control electrode transistor M4 and the seventh control electrode transistor M7 are turned off. The turned-on first control electrode transistor M1 transmits the low-level control electrode start signal ESTV to the first control electrode node N1', so that the level of the first control electrode node N1' becomes low, so the second control electrode transistor M2, the eighth control electrode transistor M8 and the tenth control electrode transistor M10 are turned on. The turned-on second control electrode transistor M2 transmits the low-level first control electrode clock signal CK' to the second control electrode node N2', so that the level of the second control electrode node N2' can be further lowered, so the second control electrode node N2' continues to maintain the low level of the previous stage, so that the fifth control electrode transistor M5 and the sixth control electrode transistor M6 are turned on. In addition, the turned-on eighth control electrode transistor M8 transmits the high level signal VGH to the fourth control electrode node N4', so that the level of the fourth control electrode node N4 becomes high level, so the ninth control electrode transistor M9 is turned off. The turned-on tenth control electrode transistor M10 outputs the low level signal VGL, so the control electrode output signal EMOUT becomes low level.

[0198] Among them, the above first control electrode clock signal CK' can be provided through the above first control electrode clock signal line 622, and the second control electrode clock signal CB' can be provided through the above second control electrode clock signal line 623, and the high level signal VGH and the low level signal VGL are provided through the high level signal line 615 and the low level signal line 616 respectively.

[0199] The control start signal ESTV is provided by the control output signal EOUT of the previous control shift register. The control start signal ESTV of the first control shift register is provided through the control start signal line 621. The control output signal EOUT generated by the last control shift register is also connected to the control drive test line 624 to detect whether the control drive circuit A42 is working normally.

[0200] Among them, refer to Fig. 9 , Fig.11 Since the high level signal VGH and the low level signal VGL used in the above gate drive circuit A41 and the control electrode drive circuit A42 are the same, Fig.18 The high level signal line 615 in the gate driving line 61 and the control driving line 62 may actually be the same line, and the low level signal line 616 in the gate driving line 61 and the control driving line 62 may actually be the same line.

[0201] In some embodiments, the gate driving circuit A41 and the gate driving circuit A42 are located at two opposite sides of the display area 91 along the second direction 992 .

[0202] Reference Figure 1 Since the gate driving circuit A41 and the control electrode driving circuit A42 correspond to the gate line 13 and the control electrode line 14 respectively, and the gate line 13 and the control electrode line 14 both extend along the second direction 992, from the perspective of simple routing, the gate driving circuit A41 (multiple gate driving units 41) and the control electrode driving circuit A42 (multiple control electrode driving units 42) can be relatively arranged along the second direction 992.

[0203] In some embodiments, the display substrate further comprises:

[0204] A multiplexing circuit A2 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;

[0205] A plurality of data drive lines 63 are located in the peripheral area 92 and at least partially surround the display area 91, and a multiplexing circuit A2 is electrically connected to the plurality of data drive lines 63 and the plurality of data leads 73;

[0206] A plurality of multiplexing driving lines 64 are located in the peripheral area 92 and at least partially surround the display area 91, and the plurality of multiplexing driving lines 64 are electrically connected to the multiplexing circuit;

[0207] Multiple multiplexing leads 74 are located in the peripheral area 92 and extend along the first direction 991 . Multiple multiplexing leads 74 are electrically connected to multiple multiplexing driving lines 64 and multiple pads 8 . Multiple multiplexing leads 74 are located between the first group of data leads 738 and the second group of data leads 739 .

[0208] Reference Figure 1 In some embodiments, the display substrate may include a multiplexing circuit A2, which is used to enable each data driving line 63 to be connected to different data lines 12 in a time-division manner under the control of multiple multiplexing driving lines 64. Thus, each data driving line 63 (or each data lead line 73) may correspond to multiple data lines 12, thereby reducing the number of data driving lines 63, data leads 73 (and corresponding pads 8, chips), simplifying the product structure, and facilitating the narrow frame design of the display device.

[0209] Among them, refer to Figure 1 , Figure 2 The above multiplexed driving line 64 also needs to be connected to the pad 8 through the multiplexed lead 74 extending along the first direction 991, and the multiplexed lead 74 is also located between the above first group of data leads 738 and the second group of data leads 739.

[0210] The multiplexing circuit A2 may include a plurality of multiplexing units 2 (MUX).

[0211] Reference Fig.12 , Fig. 22 , in some embodiments, the multiplexing units 2 include m (m is at least 2) multiplexing transistors 21;

[0212] In the m multiplexing transistors 21 of each multiplexing unit 2, the gate of each multiplexing transistor 21 is electrically connected to one of the multiple multiplexing driving lines 64, the first electrode of each multiplexing transistor 21 is electrically connected to one of the multiple data lines 12, and the second electrodes of the m multiplexing transistors 21 are electrically connected to one of the multiple data driving lines 63.

[0213] It can be seen that during the display process, when a turn-on signal is provided to any gate line 13, a turn-on signal can be provided to each multiplexing drive line 64 in a time-sharing manner, so that each multiplexing transistor 21 in each multiplexing unit 2 is turned on in a time-sharing manner; and when any multiplexing transistor 21 is turned on, the data signal required by the data line 12 electrically connected to the multiplexing transistor 21 is provided through the corresponding data drive line 63, so that the data signal is written into the corresponding sub-pixel 1.

[0214] For example, refer to Fig.12 , Fig. 22 , m is 3, that is, each multiplexing unit 2 can control three data lines 12 (one to three).

[0215] Obviously, according to the above method, the number of data lines 12 can be equal to "m*the number of multiplexing units 2"; and the number of multiplexing drive lines 64 cannot be less than m, for example, referring to Fig.12 , Fig. 22 When every two multiplexing units 2 are electrically connected to one data driving line 63, the number of multiplexing driving lines 64 may be m (eg, ).

[0216] The distribution of the layers of the structures of the multiplexing unit 2 can be varied.

[0217] For example, the active layer of each multiplexing transistor 21 can be set in the same layer as the first active layer 111 and arranged at intervals, and covered by the gate insulating layer 190; and the gate of each multiplexing transistor 21 can be set in the same layer as the first gate 112, and at the same time, the layer is also provided with a structure for electrically connecting the first electrode of some multiplexing transistors 21 to the corresponding data line 12 (or a part of the data line 12); the first electrode and the second electrode of the multiplexing transistor 21 can be provided in the same layer as the first source 113 and the first drain 114, wherein one end of the second electrode of each multiplexing transistor 21 in the same multiplexing unit 2 is connected as a whole; and the electrical connection of the corresponding structure can be achieved through the via in the second insulating layer 192.

[0218] In some embodiments, the plurality of gate driving lines 61 , the plurality of multiplexing driving lines 64 , and the plurality of data driving lines 63 are located on a side of the gate driving circuit A41 and the multiplexing circuit A2 away from the display area 91 .

[0219] In some embodiments, the multiplexed driving lines 64 are located on a side of the multiple gate driving lines 61 away from the display area 91 ;

[0220] The plurality of data driving lines 63 are located on a side of the plurality of multiplexing driving lines 64 away from the display area 91 .

[0221] Reference Fig.19 The above gate drive line 61, multiplexing drive line 64, and data drive line 63 can be arranged "outside" the gate drive circuit A41 (there may also be a control electrode drive circuit A42) and the multiplexing circuit A2, so that these circuits are closer to the display area 91 and supply power to the data lines 12 and gate lines 13 in the display area 91.

[0222] Furthermore, among the above drive lines, the gate drive line 61 (and the control electrode drive line 62) can be the "innermost" because the driving of the shift register (gate shift register, control electrode shift register) is relatively important, so the corresponding line is best as close to the shift register as possible; and the data drive line 63 is the largest in number and occupies a larger area, so it can be on the outermost side.

[0223] The specific positions of the units in various driving circuits can be set as required.

[0224] For example, refer to Fig.19 In the lower left half of the peripheral area 92 , the gate driving units 41 of the gate driving circuit A41 can be “mixed” with the multiplexing units 2 of the multiplexing circuit A2 along the circumference of the peripheral area 92 .

[0225] In the lower right half of the peripheral area 92 , the gate driving units 42 of the gate driving circuit A42 may be “mixed” with the multiplexing units 2 of the multiplexing circuit A2 along the circumference of the peripheral area 92 .

[0226] In the upper left half of the peripheral area 92 , the gate driving units 41 of the gate driving circuit A41 may be “mixed” with the test units 3 of the test circuit A3 described later along the circumference of the peripheral area 92 .

[0227] In the upper right half of the peripheral area 92 , the gate driving units 41 of the gate driving circuit A42 may be “mixed” with the test units 3 of the test circuit A3 described later along the circumference of the peripheral area 92 .

[0228] The number of electrostatic discharge units 5 of the electrostatic discharge circuit A5 described later is relatively small, so they can be only disposed in the gaps of some other structures.

[0229] Among them, the specific positions of various other driving lines can be set according to needs.

[0230] For example, refer to Fig.18 , the first power driving line 68 and the initialization driving line 67 described later may be located on the "inside" of the gate driving unit 41, the multiplexing unit 2 and other units (the first power driving line 68 may be the innermost, and the initialization driving line 67 is on the outside).

[0231] For example, the second power driving line 69 described later is located at the “outside” of the data driving line 63 , and of course is also located at the “outside” of the gate driving unit 41 , the multiplexing unit 2 and other units.

[0232] For example, refer to Fig.18 The test drive line 65 described later can be arranged between different gate drive lines 61 (or control drive lines 62) with the above gate drive lines 61 (also including control drive lines 62) and multiplexing drive lines 64, wherein the specific arrangement order is diverse (the same type of drive lines are not necessarily arranged continuously).

[0233] In some embodiments, the display substrate further comprises:

[0234] The test circuit A3 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;

[0235] A plurality of test drive lines 65 are located in the peripheral area 92 and at least partially surround the display area 91 , and the plurality of test drive lines 65 are electrically connected to the test circuit A3 ;

[0236] The plurality of test leads 75 are located in the peripheral area 92 and extend along the first direction 991 . The plurality of test leads 75 are electrically connected to the plurality of test drive lines 65 and the plurality of pads 8 . The plurality of test leads 75 are located between the first group of data leads 738 and the second group of data leads 739 .

[0237] Reference Figure 1 There is also a test circuit A3 in the display substrate, and the test circuit A3 is also connected to each data line 12, so that each sub-pixel 1 can be tested under the control of multiple test drive lines 65, for example, a lighting test can be performed before the display substrate leaves the factory.

[0238] Among them, refer to Figure 1 , Figure 2 The test driving line 65 also needs to be connected to the corresponding pad 8 through the test lead 75 extending along the first direction 991, and the test lead 75 is also located between the first group of data leads 738 and the second group of data leads 739.

[0239] In some embodiments, the plurality of test driving lines 65 include a test data signal line 651 and a test control signal line 652 .

[0240] The test circuit A3 may include a plurality of test units 3 (CT).

[0241] Reference Fig.13 , Fig.23 Each test unit 3 is electrically connected to at least one test data signal line 651, at least one test control signal line 652, and at least one of the multiple data lines 12, and is configured to provide a signal provided by at least one test data signal line 651 to at least one data line 12 based on a signal provided by at least one test control signal line 652.

[0242] Reference Fig.13 As one embodiment of the present disclosure, the total number of at least one test data signal line 651 is n (at least 2, for example, 3), the total number of at least one test control signal line 652 is one, and n is an integer greater than or equal to 2;

[0243] At least one of the plurality of test units 3 includes n test transistors 31;

[0244] Among the n test transistors 31 of the same test unit 3, the gates 311 of the n test transistors 31 are electrically connected to a test control signal line 652, the first electrode 313 of each test transistor 31 is electrically connected to one of the multiple data lines 12, and the second electrode 314 of each test transistor 31 is electrically connected to one of the n test data signal lines 651.

[0245] As one form of an embodiment of the present disclosure, the number of test data signal lines 651 is n, while there is only one test control signal line 652; and each test unit 3 also includes n test transistors 31, the gates 311 of the n test transistors 31 are all electrically connected to the test control signal line 652, and the first electrodes 313 (such as drains) are respectively electrically connected to different data lines 12; the second electrodes 314 (such as sources) of the n test transistors 31 are respectively electrically connected to the n test data signal lines 651 (that is, the second electrodes of different test transistors 31 are electrically connected to different test data signal lines 651).

[0246] It can be seen that, through the test control signal line 652, it is possible to control whether the test transistor 31 in each test unit 3 is turned on, and the signal of each test data signal line 651 can be controlled to be written into different data lines 12, that is, to control "whether to perform a test"; when a test is to be performed, a conduction signal can be provided to the test control signal line 652, and the required signals can be provided to n test data signal lines 651 respectively, so that each data line 12 obtains the required signal to realize detection.

[0247] Therefore, in some embodiments, the number of data lines 12 may be equal to n*the number of test units 3 .

[0248] In some embodiments, n is 3.

[0249] In some embodiments, the sub-pixels 1 electrically connected to each data line 12 have the same color, for example, the sub-pixels 1 in the same column have the same color, for example, the columns of red, green, and blue sub-pixels are arranged along the second direction 992. Fig.13 In the figure, the red sub-pixel, the green sub-pixel, and the blue sub-pixel are represented by R, G, and B, respectively.

[0250] Therefore, when testing, the same signal can be provided to the data lines 12 corresponding to the sub-pixels 1 of the same color so that these sub-pixels 1 can perform the same display (such as lighting up or not lighting up), so as to determine whether there are any defective sub-pixels 1 and locate the defective sub-pixels 1 through the color of the displayed image.

[0251] Of course, the arrangement of the colors of the sub-pixels 1 and the specific form of the test unit 3 are not limited thereto.

[0252] In some embodiments, the display substrate further comprises:

[0253] A multiplexing circuit A2 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;

[0254] The test circuit A3 and the multiplexing circuit A2 are located at two opposite sides of the display area 91 along the first direction 991;

[0255] The plurality of pads 8 are located on a side of the multiplexing circuit A2 away from the display area 91 .

[0256] Reference Figure 1 Since both the test circuit A3 and the multiplexing circuit A2 need to be connected to the data line 12, and the data line 12 extends along the first direction 991, from the perspective of easy routing, the test circuit A3 (multiple test units 3) and the multiplexing circuit A2 (multiple multiplexing units 2) can be relatively arranged along the first direction 991; and since the multiplexing circuit A2 requires the largest number of data driving lines 63, the pad 8 can be arranged on the side where the multiplexing circuit A2 is located, so that the data driving line 63 can be "nearby" connected to the multiplexing circuit A2 without having to go around half a circle for connection.

[0257] In some embodiments, the display substrate further comprises:

[0258] The electrostatic discharge circuit A5 is located in the peripheral area 92;

[0259] The electrostatic discharge driving line 66 is located in the peripheral area 92 and at least partially surrounds the display area 91. The electrostatic discharge driving line 66 is electrically connected to the electrostatic discharge circuit A5.

[0260] The electrostatic release lead is located in the peripheral area 92 and extends along the first direction 991 . The electrostatic release lead is electrically connected to the electrostatic release driving line 66 and the pad 8 . The electrostatic release lead is located between the first group of data leads 738 and the second group of data leads 739 .

[0261] Reference Figure 1 In some embodiments, the display substrate also includes an electrostatic release circuit A5 for releasing static electricity accumulated in other lines (such as gate drive lines 61, control electrode drive lines 62, multiplexing drive lines 64, test drive lines 65, etc.) to avoid static electricity breakdown and other defects caused by excessive accumulation of static electricity in the lines; and the electrostatic release circuit A5 can operate under the control of the electrostatic release drive line 66, and the electrostatic release drive line 66 is connected to the electrostatic release lead, and the electrostatic release lead is also located between the first group of data leads 738 and the second group of data leads 739 above.

[0262] Specifically, the electrostatic discharge circuit A5 may include an electrostatic discharge unit 5 (ESD). Each electrostatic discharge unit 5 is used to discharge static electricity in the line to be protected (such as the gate drive line 61, the control electrode drive line 62, the multiplexing drive line 64, the test drive line 65, etc.) to the electrostatic discharge drive line 66.

[0263] Reference Fig.14 , Fig.24In some embodiments, the electrostatic release driving line 66 may include an electrostatic high level line 661 and an electrostatic low level line 662; each electrostatic release unit 5 includes a first release transistor 51 and a second release transistor 52: the gate and the first electrode of the first release transistor 51 are connected to the electrostatic high level line 661, and the second electrode is connected to the line to be protected by the electrostatic release unit 5 ( Fig.14 The gate and the first electrode of the second release transistor 52 are connected to the line that needs to be protected by the electrostatic release unit 5, and the second electrode is connected to the electrostatic low level line 662.

[0264] The electrostatic high level line 661 and the electrostatic low level line 662 are respectively continuously loaded with the high level signal VGH and the low level signal VGL.

[0265] Reference Fig.14 The above electrostatic release unit 5 includes a first release transistor 51 and a second release transistor 52, wherein one electrode of each release transistor is connected to its own gate, thereby forming an equivalent "diode". Therefore, when the line to be protected by the electrostatic release unit 5 has an instantaneous high voltage (such as 100V) due to the accumulation of positive charges, the "diode" of the first release transistor 51 is turned on to release the positive charges in the signal line; and when the signal line has an instantaneous low voltage (such as -100V) due to the accumulation of negative charges, the "diode" of the second release transistor 52 is turned on to release the negative charges in the signal line.

[0266] In some embodiments, the display substrate further comprises:

[0267] An initialization driving line 67 is located in the peripheral area 92 and at least partially surrounds the display area 91 , and the initialization driving line 67 is electrically connected to the plurality of sub-pixels 1 ;

[0268] The initialization lead 77 is located in the peripheral area 92 and extends along the first direction 991 . The initialization lead 77 is electrically connected to the initialization driving line 67 and the pad 8 . The initialization lead 77 is located between the first group of data leads 738 and the second group of data leads 739 .

[0269] Reference Figure 1 , Figure 2 , Fig.17 , Fig.18 As mentioned above, in order to provide an initialization signal to the initialization signal terminal Vinit of each sub-pixel 1 in the display area 91, an initialization drive line 67 may also be provided in the peripheral area 92, and the initialization drive line 67 is connected to the initialization lead 77, and the initialization lead 77 is also located between the first group of data leads 738 and the second group of data leads 739 mentioned above.

[0270] In some embodiments, the display substrate further comprises:

[0271] A first power driving line 68, located in the peripheral area 92 and at least partially surrounding the display area 91, the first power driving line 68 is electrically connected to the plurality of sub-pixels 1;

[0272] A first power lead 78 is located in the peripheral area 92 and extends along the first direction 991. The first power lead 78 is electrically connected to the first power driving line 68 and the pad 8. The first power lead 78 is located between the first group of data leads 738 and the second group of data leads 739.

[0273] A second power driving line 69, located in the peripheral area 92 and at least partially surrounding the display area 91, the second power driving line 69 is electrically connected to the plurality of sub-pixels 1;

[0274] The second power lead 79 is located in the peripheral area 92 and extends along the first direction 991. The second power lead 79 is electrically connected to the second power drive line 69 and the pad 8. The second power lead 79 is located on the side of the first group of data leads 738 away from the second group of data leads 739, or on the side of the second group of data leads 739 away from the first group of data leads 738.

[0275] Reference Figure 1 , Figure 2 , Fig.17 As mentioned above, in order to provide the first power signal (corresponding to the anode) and the second power signal (corresponding to the cathode) to the first power signal terminal VDD and the second power signal terminal VSS of each sub-pixel 1 in the display area 91, a first power driving line 68 and a second power driving line 69 may also be provided in the peripheral area 92, and the first power driving line 68 and the second power driving line 69 are respectively connected to the pad 8 through the first power lead 78 and the second power lead 79 extending along the first direction 991.

[0276] Among them, the first power lead 78 is also located between the first group of data leads 738 and the second group of data leads 739; while the second power lead 79 is different and is located "outside" the first group of data leads 738 and the second group of data leads 739.

[0277] Among them, under the condition of meeting the above position requirements, the specific position relationship of various leads can be varied.

[0278] For example, see Fig.17 , Fig.18 Among the other leads between the first group of data leads 738 and the second group of data leads 739, the first power lead 78 is in the middle, with the initialization lead 77 on both sides, and the two sides outside are also the test lead 75 and the multiplexing lead 74, and the two sides outside are the gate lead 71 and the control electrode lead 72 (the figure takes the gate lead 71 on the left and the control electrode lead 72 on the right as an example).

[0279] Among them, refer to Figure 2 , Fig.17 , Fig.18 The test drive line 65, the multiplexing drive line 64, the high-level signal line 615, the low-level signal line 616, etc. can form a closed ring, so there can be two leads corresponding to each of them, which are connected from both sides at the same time; and each of the gate drive line 61 and the control electrode drive line 62 only corresponds to the "half circle" of the peripheral area 92, so the other leads corresponding to them (except the leads corresponding to the high-level signal line 615 and the low-level signal line 616) can enter from one side separately.

[0280] In some embodiments, a plurality of pads 8 are located in the access area 921 and arranged along the second direction 992 ; the access area 921 is located on one side of the display area 91 along the first direction 991 ;

[0281] A plurality of gate leads 71 ​​and a plurality of data leads 73 are located in the lead-out area 922; the lead-out area 922 is located between the access area 921 and the display area 91 along the first direction 991;

[0282] Along the second direction 992 , the plurality of gate leads 71 ​​are located between the first group of data leads 738 and the second group of data leads 739 .

[0283] Reference Figure 2 The above multiple pads 8 can be arranged in a row along the second direction 992, and located in the access area 921 on one side of the display area 91 along the first direction 991; and between the access area 921 and the display area 91 is the lead-out area 922 for setting the above leads.

[0284] Therefore, refer to Figure 2 , the leads extend in the lead-out area 922 along the first direction 991, and different leads should be arranged along the second direction 992, that is, the other majority of leads (except the second power lead 79) should be located between the first group of data leads 738 and the second group of data leads 739 in the second direction 992, or the first group of data leads 738 and the second group of data leads 739 are located on both sides of the other majority of leads in the second direction 992.

[0285] In some embodiments, along the second direction 992 , the plurality of pads 8 electrically connected to the plurality of gate leads 71 ​​are located between the plurality of pads 8 electrically connected to the first group of data leads 738 and the plurality of pads 8 electrically connected to the second group of data leads 739 .

[0286] Reference Figure 3 , Fig.15 As a form of embodiment of the present disclosure, the pads 8 corresponding to the data leads 73 should also be divided into two groups, and are respectively located outside the pads 8 corresponding to the majority of other leads (except the first power lead 78 and the second power lead 79).

[0287] Thus, most of the pads 8 can be directly connected to their corresponding leads.

[0288] In some embodiments, the display substrate further comprises:

[0289] A plurality of control electrode lines 14, at least located in the display area 91 and extending along the second direction 992, the plurality of control electrode lines 14 being electrically connected to the plurality of sub-pixels 1;

[0290] A gate driving circuit A42 is located in the peripheral area 92 and is electrically connected to the plurality of gate lines 14;

[0291] A plurality of control electrode drive lines 62 are located in the peripheral area 92 and at least partially surround the display area 91, and the plurality of control electrode drive lines 62 are electrically connected to the control electrode drive circuit A42;

[0292] A plurality of control electrode leads 72 are located in the peripheral area 92 and extend along the first direction 991. The plurality of control electrode leads 72 are electrically connected to the plurality of control electrode driving lines 62 and the plurality of pads 8. The plurality of control electrode leads 72 are located between the first group of data leads 738 and the second group of data leads 739.

[0293] Along the second direction 992, the plurality of pads 8 electrically connected to the plurality of data leads 73 are located between the plurality of pads 8 electrically connected to the plurality of gate leads 71 ​​and the plurality of pads 8 electrically connected to the plurality of control electrode leads 72;

[0294] At least part of the data leads 73 are electrically connected to the multiple pads 8 through multiple data auxiliary leads 731, multiple gate leads 71 ​​are electrically connected to the multiple pads 8 through multiple gate auxiliary leads 711, and multiple control electrode leads 72 are electrically connected to the multiple pads 8 through multiple control electrode auxiliary leads 721.

[0295] Reference Figure 4 , Fig.16 , Fig.17 , Fig.18 As another form of the embodiment of the present disclosure, the gate lead 71 and the control electrode lead 72 (and also the multiplexing lead 74, the test lead 75, the initialization lead 77, and the first power lead 78) may still be located between the first group of data leads 738 and the second group of data leads 739 in the second direction 992; but the pad 8 corresponding to each data lead 73 is located in the middle of the pad 8 corresponding to the gate lead 71 and the control electrode lead 72 (and also the multiplexing lead 74, the test lead 75, the initialization lead 77, and the first power lead 78) in the second direction 992.

[0296] Therefore, the data lead 73 needs to be connected to the pad 8 through the data auxiliary lead 731 , that is, the data auxiliary lead 731 at least partially extends along the second direction 992 , so that in the second direction 992 , the signal from the pad 8 is led from the middle to both sides and enters the data lead 73 .

[0297] Similarly, the gate lead 71 and the control electrode lead 72 are connected to the corresponding pad 8 through the gate auxiliary lead 711 and the control electrode auxiliary lead 721 respectively (and the multiplexing lead 74, the test lead 75, the initialization lead 77, and the first power supply lead 78 are also connected to the corresponding pad 8 through the multiplexing auxiliary lead 741, the test auxiliary lead 751, the initialization auxiliary lead 771, and the first power supply auxiliary lead 781 respectively).

[0298] In some embodiments, the display substrate further comprises:

[0299] A first power driving line 68, located in the peripheral area 92 and at least partially surrounding the display area 91, the first power driving line 68 is electrically connected to the plurality of sub-pixels 1;

[0300] A first power lead 78 is located in the peripheral area 92 and extends along the first direction 991. The first power lead 78 is electrically connected to the first power driving line 68 and the pad 8. The first power lead 78 is located between the first group of data leads 738 and the second group of data leads 739.

[0301] A second power driving line 69, located in the peripheral area 92 and at least partially surrounding the display area 91, the second power driving line 69 is electrically connected to the plurality of sub-pixels 1;

[0302] A second power lead 79, which is located on a side of the first group of data leads 738 away from the second group of data leads 739, or on a side of the second group of data leads 739 away from the first group of data leads 738;

[0303] Along the second direction 992, the pad 8 electrically connected to the first power lead 78 is located at a side of the pad 8 electrically connected to the first group of data leads 738 away from the pad 8 electrically connected to the second group of data leads 739, or located at a side of the pad 8 electrically connected to the second group of data leads 739 away from the pad 8 electrically connected to the first group of data leads 738;

[0304] Along the second direction 992, the pad 8 electrically connected to the second power lead 79 is located at a side of the pad 8 electrically connected to the first group of data leads 738 away from the pad 8 electrically connected to the second group of data leads 739, or located at a side of the pad 8 electrically connected to the second group of data leads 739 away from the pad 8 electrically connected to the first group of data leads 738;

[0305] The first power lead 78 is electrically connected to the pad 8 via a first power auxiliary lead 781 .

[0306] Reference Figure 2 , Figure 4 , Figure 5 , Fig.16 In the second direction 992, the pads 8 corresponding to the first power lead 78 and the second power lead 79 are usually located on both sides of the other pads 8, or in other words, the other pads 8 are located between the two pads 8 connected to the first power lead 78, and also between the two pads 8 connected to the second power lead 79.

[0307] As before, since the first power lead 78 is located between the first group of data leads 738 and the second group of data leads 739 , the first power lead 78 needs to be connected to the corresponding pad 8 through the first power auxiliary lead 781 extending at least partially along the second direction 992 .

[0308] Since the second power lead 79 is located outside the first group of data leads 738 and the second group of data leads 739 , it can be directly connected to the corresponding pad 8 .

[0309] In a second aspect, an embodiment of the present disclosure provides a display device, comprising:

[0310] Any of the above display substrates.

[0311] The above display substrate can be combined with other components (such as a box cover, a flexible circuit board, a driving chip, a power supply component, etc.) to form a display device with a display function.

[0312] In some embodiments, the display device is a wearable display device.

[0313] Specifically, the above display device is particularly suitable for use as a wearable display device that can be worn on a human body. For example, the display device can be a smart watch worn on a person's wrist.

[0314] Of course, the wearable display device may also include devices such as watch straps for being worn on the human body.

[0315] Of course, the above display device is not limited to a wearable display device, and it can also be any product or component with a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0316] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display substrate, wherein: include: A substrate, comprising a display area and a peripheral area surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, at least located in the display area and extending along a first direction, the plurality of data lines being electrically connected to the plurality of sub-pixels; A plurality of gate lines, at least located in the display area and extending along a second direction, the plurality of gate lines being electrically connected to the plurality of sub-pixels; the first direction intersects with the second direction; A plurality of pads located in the peripheral area; A plurality of data leads, located in the peripheral area, and electrically connected to the plurality of data lines and the plurality of pads; the plurality of data leads include a first group of data leads and a second group of data leads; a gate driving circuit, located in the peripheral area and electrically connected to the plurality of gate lines; a plurality of gate drive lines, located in the peripheral area and at least partially surrounding the display area, the plurality of gate drive lines being electrically connected to the gate drive circuit; A plurality of gate leads, located in the peripheral area and extending along the first direction, the plurality of gate leads being electrically connected to the plurality of gate drive lines and the plurality of pads; the plurality of gate leads being located between the first group of data leads and the second group of data leads; A plurality of control electrode lines, at least located in the display area and extending along the second direction, the plurality of control electrode lines being electrically connected to the plurality of sub-pixels; A control electrode driving circuit is located in the peripheral area and is electrically connected to the plurality of control electrode lines; A plurality of control electrode drive lines are located in the peripheral area and at least partially surround the display area, and the plurality of control electrode drive lines are electrically connected to the control electrode drive circuit; A plurality of control electrode leads, located in the peripheral area and extending along the first direction, the plurality of control electrode leads being electrically connected to the plurality of control electrode drive lines and the plurality of pads; the plurality of control electrode leads being located between the first group of data leads and the second group of data leads; a multiplexing circuit, located in the peripheral area and electrically connected to the plurality of data lines; a plurality of data drive lines located in the peripheral area and at least partially surrounding the display area, the multiplexing circuit being electrically connected to the plurality of data drive lines and the plurality of data lead lines; a plurality of multiplexing driving lines located in the peripheral area and at least partially surrounding the display area, the plurality of multiplexing driving lines being electrically connected to the multiplexing circuit; A plurality of multiplexing leads, located in the peripheral area and extending along the first direction, the plurality of multiplexing leads being electrically connected to the plurality of multiplexing driving lines and the plurality of pads; The plurality of multiplexing leads are located between the first group of data leads and the second group of data leads; An electrostatic discharge circuit, located in the peripheral area; an electrostatic discharge driving line, located in the peripheral area and at least partially surrounding the display area, the electrostatic discharge driving line being electrically connected to the electrostatic discharge circuit; The electrostatic release lead is located in the peripheral area and extends along the first direction. The electrostatic release lead is electrically connected to the electrostatic release drive line and the pad. The electrostatic release lead is located between the first group of data leads and the second group of data leads.

2. The display substrate according to claim 1, wherein: The plurality of gate drive lines include a gate start signal line, a first gate clock signal line, a second gate clock signal line, a gate drive test line, a high level signal line, and a low level signal line.

3. The display substrate according to claim 1, wherein: The plurality of control electrode drive lines include a control electrode start signal line, a first control electrode clock signal line, a second control electrode clock signal line, a control electrode drive test line, a high level signal line, and a low level signal line.

4. The display substrate according to claim 1, wherein: The gate driving circuit and the gate driving circuit are located at two opposite sides of the display area along the second direction.

5. The display substrate according to claim 1, wherein: The plurality of gate driving lines, the plurality of multiplexing driving lines, and the plurality of data driving lines are located on a side of the gate driving circuit and the multiplexing circuit that is away from the display area.

6. The display substrate according to claim 5, wherein: The multiplexed driving lines are located at a side of the multiple gate driving lines away from the display area; The plurality of data driving lines are located at a side of the plurality of multiplexing driving lines away from the display area.

7. The display substrate according to claim 1, wherein: Also includes: a test circuit, located in the peripheral area and electrically connected to the plurality of data lines; a plurality of test drive lines, located in the peripheral area and at least partially surrounding the display area, the plurality of test drive lines being electrically connected to the test circuit; A plurality of test leads are located in the peripheral area and extend along the first direction, the plurality of test leads are electrically connected to the plurality of test drive lines and the plurality of pads; the plurality of test leads are located between the first group of data leads and the second group of data leads.

8. The display substrate according to claim 7, wherein: The plurality of test driving lines include test data signal lines and test control signal lines.

9. The display substrate according to claim 7, wherein: Also includes: a multiplexing circuit, located in the peripheral area and electrically connected to the plurality of data lines; The test circuit and the multiplexing circuit are located at two opposite sides of the display area along the first direction; The plurality of pads are located at a side of the multiplexing circuit away from the display area.

10. The display substrate according to claim 1, wherein: Also includes: an initialization driving line, located in the peripheral area and at least partially surrounding the display area, the initialization driving line being electrically connected to the plurality of sub-pixels; An initialization lead is located in the peripheral area and extends along the first direction. The initialization lead is electrically connected to the initialization drive line and the pad. The initialization lead is located between the first group of data leads and the second group of data leads.

11. The display substrate according to claim 1, wherein: Also includes: A first power driving line, located in the peripheral area and at least partially surrounding the display area, the first power driving line being electrically connected to the plurality of sub-pixels; A first power lead, located in the peripheral area and extending along the first direction, the first power lead being electrically connected to the first power drive line and the pad; The first power lead is located between the first group of data leads and the second group of data leads; A second power driving line, located in the peripheral area and at least partially surrounding the display area, the second power driving line being electrically connected to the plurality of sub-pixels; A second power lead is located in the peripheral area and extends along the first direction, and the second power lead is electrically connected to the second power drive line and the pad; the second power lead is located on the side of the first group of data leads away from the second group of data leads, or is located on the side of the second group of data leads away from the first group of data leads.

12. The display substrate according to claim 1, wherein: The peripheral area includes an access area and a lead-out area, the access area is located on one side of the display area along the first direction, and the lead-out area is located between the access area and the display area along the first direction; the multiple pads are located in the access area and arranged along the second direction; the multiple gate leads and the multiple data leads are located in the lead-out area; along the second direction, the multiple gate leads are located between the first group of data leads and the second group of data leads.

13. The display substrate according to claim 12, wherein: Along the second direction, the plurality of pads electrically connected to the plurality of gate leads are located between the plurality of pads electrically connected to the first group of data leads and the plurality of pads electrically connected to the second group of data leads.

14. The display substrate according to claim 12, wherein: Also includes: A plurality of control electrode lines, at least located in the display area and extending along the second direction, the plurality of control electrode lines being electrically connected to the plurality of sub-pixels; A control electrode driving circuit is located in the peripheral area and is electrically connected to the plurality of control electrode lines; A plurality of control electrode drive lines are located in the peripheral area and at least partially surround the display area, and the plurality of control electrode drive lines are electrically connected to the control electrode drive circuit; A plurality of control electrode leads, located in the peripheral area and extending along the first direction, the plurality of control electrode leads being electrically connected to the plurality of control electrode drive lines and the plurality of pads; the plurality of control electrode leads being located between the first group of data leads and the second group of data leads; Along the second direction, the plurality of pads electrically connected to the plurality of data leads are located between the plurality of pads electrically connected to the plurality of gate leads and the plurality of pads electrically connected to the plurality of control leads.

15. The display substrate according to claim 12, wherein: Also includes: A first power driving line, located in the peripheral area and at least partially surrounding the display area, the first power driving line being electrically connected to the plurality of sub-pixels; A first power lead, located in the peripheral area and extending along the first direction, the first power lead being electrically connected to the first power drive line and the pad; The first power lead is located between the first group of data leads and the second group of data leads; A second power driving line, located in the peripheral area and at least partially surrounding the display area, the second power driving line being electrically connected to the plurality of sub-pixels; a second power lead, located in the peripheral area and extending along the first direction, the second power lead being electrically connected to the second power drive line and the pad; the second power lead being located on a side of the first group of data leads away from the second group of data leads, or on a side of the second group of data leads away from the first group of data leads; Along the second direction, the pad electrically connected to the first power lead is located on a side of the pad electrically connected to the first group of data leads away from the pad electrically connected to the second group of data leads, or is located on a side of the pad electrically connected to the second group of data leads away from the pad electrically connected to the first group of data leads; Along the second direction, the pad electrically connected to the second power lead is located on a side of the pad electrically connected to the first group of data leads that is away from the pad electrically connected to the second group of data leads, or is located on a side of the pad electrically connected to the second group of data leads that is away from the pad electrically connected to the first group of data leads.

16. The display substrate according to any one of claims 1 to 15, wherein: The display area is substantially circular; The display substrate is substantially circular.

17. A display device comprising: A display substrate as claimed in any one of claims 1 to 16.

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