Solid-state imaging device and electronic apparatus

Abstract

A solid-state imaging device includes a light-receiving surface, a plurality of pixels each including a photoelectric conversion section that photoelectrically converts light incident through the light-receiving surface, and a separation section that electrically and optically separates the photoelectric conversion sections. Each of the pixels includes a charge holding section that holds a charge transferred from the photoelectric conversion section, a transfer transistor that includes a vertical gate electrode reaching the photoelectric conversion section and transfers the charge from the photoelectric conversion section to the charge holding section, and a light-shielding section provided in a layer between the photoelectric conversion section and the charge holding section. In a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of vertical gate electrodes are electrically connected together.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a solid-state imaging device and an electronic apparatus. BACKGROUND

[0002] In a solid-state imaging device, a global shutter method using a CMOS image sensor is known (see, for example, Patent Literature 1). In the invention described in Patent Literature 1 above, by providing a charge holding portion (to which the charge accumulated in a photoelectric conversion portion is transferred) at a depth different from that of the photoelectric conversion portion, it is possible to ensure the saturated number of electrons while ensuring the area of the photoelectric conversion portion.

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2010-114273 SUMMARY

[0006] However, in the invention described in Patent Literature 1 above, there is a possibility that noise is generated due to light incident to the charge holding portion. In order to reduce the noise, it is conceivable to provide a light shielding layer. In the case where the light shielding layer is provided, it is difficult to transfer the charge from the photoelectric conversion portion to the charge holding portion. In order to facilitate the charge transfer, it is conceivable to provide a vertical gate electrode reaching the photoelectric conversion portion from an opening provided in the light shielding layer. In the case where the vertical gate electrode is provided, the pixel size increases, and the noise caused by the light incident to the charge holding portion from the opening provided in the light shielding layer increases. Therefore, it is desirable to provide a solid-state imaging device capable of avoiding the deterioration of the charge transfer while suppressing the increase in the noise and the pixel size, and an electronic apparatus including the same.

[0007] A first solid-state imaging device according to an embodiment of the present disclosure includes: a light receiving surface; a plurality of pixels each including a photoelectric conversion portion that photoelectrically converts light incident through the light receiving surface; and a separation portion that electrically and optically separates the photoelectric conversion portions. Each of the pixels includes: a charge holding portion that holds a charge transferred from the photoelectric conversion portion; a transfer transistor including a vertical gate electrode reaching the photoelectric conversion portion, and transferring the charge from the photoelectric conversion portion to the charge holding portion; and a light shielding portion provided in a layer between the photoelectric conversion portion and the charge holding portion. In a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together.

[0008] A first electronic device according to an embodiment of the present disclosure includes a solid-state imaging device that outputs a pixel signal corresponding to incident light, and a signal processing circuit that processes the pixel signal. The solid-state imaging device provided in the first electronic device has the same configuration as the configuration of the above-described first solid-state imaging device.

[0009] In the first solid-state imaging device and the first electronic device according to the embodiments of the present disclosure, the vertical gate electrode reaches the photoelectric conversion section. Therefore, it is possible to avoid degradation of charge transfer from the photoelectric conversion section to the charge holding section due to the provision of the light shielding section. In addition, in the present disclosure, in a plurality of first pixels that are adjacent to each other among the plurality of pixels, the plurality of vertical gate electrodes are electrically connected together. As compared with a case where a transfer transistor is provided for each pixel, it is possible to reduce the size of the transfer transistor; therefore, it is possible to reduce the size of the opening through which the vertical gate electrode of the light shielding section penetrates. As a result, it is possible to suppress an increase in noise and pixel size.

[0010] A second solid-state imaging device according to an embodiment of the present disclosure includes a light receiving surface, a plurality of pixels each including a photoelectric conversion section that photoelectrically converts light incident through the light receiving surface, and a separation section that electrically and optically separates the photoelectric conversion sections. Each of the pixels includes a charge holding section that holds charge transferred from the photoelectric conversion section, a transfer transistor that includes a first vertical gate electrode that reaches the photoelectric conversion section and transfers charge from the photoelectric conversion section to the charge holding section, a discharge transistor that includes a second vertical gate electrode that reaches the photoelectric conversion section and is provided adjacent to the transfer transistor, the discharge transistor discharging charge from the photoelectric conversion section, and a light shielding section provided in a layer between the photoelectric conversion section and the charge holding section. In a plurality of first pixels that are adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together.

[0011] A second electronic device according to an embodiment of the present disclosure includes a solid-state imaging device that outputs a pixel signal corresponding to incident light, and a signal processing circuit that processes the pixel signal. The solid-state imaging device provided in the second electronic device has the same configuration as the configuration of the above-described second solid-state imaging device.

[0012] In the second solid-state imaging device and the second electronic apparatus according to the embodiments of the present disclosure, the first and second vertical gate electrodes reaching the photoelectric conversion section are provided. Therefore, it is possible to avoid degradation of charge transfer from the photoelectric conversion section to the charge holding section due to the provision of the light shielding section. Further, in the present disclosure, in a plurality of first pixels adjacent to each other among the plurality of pixels, the plurality of first vertical gate electrodes are electrically connected together, and the plurality of second vertical gate electrodes are electrically connected together. Therefore, compared to a case where the first and second transfer transistors are respectively provided for each pixel, it is possible to reduce the size of the first and second transfer transistors; therefore, it is possible to reduce the size of the opening through which the first and second vertical gate electrodes of the light shielding section pass. As a result, it is possible to suppress an increase in noise and pixel size. BRIEF DESCRIPTION OF DRAWINGS

[0013] [ Figure 1 ] Figure 1 An example of a schematic configuration of a solid-state imaging device according to an embodiment of the present disclosure is shown.

[0014] [ Figure 2 ] Figure 2 An example of a circuit configuration of a pixel array section in Figure 1 is shown.

[0015] [ Figure 3 ] Figure 3 An example of a cross-sectional configuration of a pixel array section in Figure 1 is shown.

[0016] [ Figure 4 ] Figure 4 An example of a planar configuration of a logic circuit side of a pixel array section in Figure 3 is shown.

[0017] [ Figure 5 ] Figure 5 An example of a planar configuration of a light-receiving surface side of a pixel array section in Figure 3 is shown.

[0018] [ Figure 6 ] Figure 6 A modification example of a planar configuration of a logic circuit side of a pixel array section in Figure 3 is shown.

[0019] [ Figure 7 ] Figure 7 A modification example of a planar configuration of a light-receiving surface side of a pixel array section in Figure 3 is shown.

[0020] [ Figure 8 ] Figure 8 A modification example of a planar configuration of a logic circuit side of a pixel array section in Figure 3 is shown.

[0021] [ Figure 9 ] Figure 9 A modification example of the planar configuration of the light-receiving surface side of the pixel array section in Figure 3 is shown.

[0022] [ Figure 10 ] Figure 10 A modification example of the circuit configuration of the pixel array section in Figure 1 is shown.

[0023] [ Figure 11 ] Figure 11 An example of the planar configuration of the logic circuit side of the pixel array section having the circuit configuration of Figure 10 is shown.

[0024] [ Figure 12 ] Figure 12 A modification example of the planar configuration of the light-receiving surface side of the pixel array section having the circuit configuration of Figure 10 is shown.

[0025] [ Figure 13 ] Figure 13 A modification example of the planar configuration of the logic circuit side of the pixel array section is shown.

[0026] [ Figure 14 ] Figure 14 A modification example of the planar configuration of the light-receiving surface side of the pixel array section is shown.

[0027] [ Figure 15 ] Figure 15 A modification example of the circuit configuration of the pixel array section in Figure 1 is shown.

[0028] [ Figure 16 ] Figure 16 A modification example of the cross-sectional configuration of the pixel array section in Figure 1 is shown.

[0029] [ Figure 17 ] Figure 17 An example of the planar configuration of the logic circuit side of the pixel array section in Figure 16 is shown.

[0030] [ Figure 18 ] Figure 18 An example of the planar configuration of the light-receiving surface side of the pixel array section in Figure 16 is shown.

[0031] [ Figure 19 ] Figure 19 A modification example of the planar configuration of the logic circuit side of the pixel array section in Figure 16 is shown.

[0032] [Figure 20 ] Figure 20 A modification example of the planar configuration of the light-receiving surface side of the pixel array section in Figure 16 is shown.

[0033] [ Figure 21 ] Figure 21 A modification example of the planar configuration of the logic circuit side of the pixel array section in Figure 16 is shown.

[0034] [ Figure 22 ] Figure 22 A modification example of the planar configuration of the light-receiving surface side of the pixel array section in Figure 16 is shown.

[0035] [ Figure 23 ] Figure 23 A modification example of the cross-sectional configuration of the pixel array section in Figure 3 is shown.

[0036] [ Figure 24 ] Figure 24 A modification example of the cross-sectional configuration of the pixel array section in Figure 16 is shown.

[0037] [ Figure 25 ] Figure 25 A modification example of the cross-sectional configuration of the pixel array section in Figure 3 is shown.

[0038] [ Figure 26 ] Figure 26 A modification example of the cross-sectional configuration of the pixel array section in Figure 16 is shown.

[0039] [ Figure 27 ] Figure 27 A modification example of the cross-sectional configuration of the pixel array section in Figure 3 is shown.

[0040] [ Figure 28 ] Figure 28 A modification example of the cross-sectional configuration of the pixel array section in Figure 16 is shown.

[0041] [ Figure 29 ] Figure 29 A modification example of the cross-sectional configuration of a portion of the pixel array section in any one of Figure 3 , Figure 16 and Figures 23-28 is shown.

[0042] [ Figure 30 ] Figure 30 is an illustrative diagram of a backbond in a crystal plane of an Si substrate of the present disclosure.

[0043] [ Figure 31 ] Figure 31 is an illustrative diagram of an angle of departure at a front surface of a Si substrate of the present disclosure.

[0044] [ Figure 32 ] Figure 33 An example of a schematic configuration of an imaging system including the solid-state imaging device according to the foregoing embodiment is shown.

[0045] [ Figure 33 ] Figure 33 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0046] [ Figure 34 ] Figure 34 is a diagram that assists in explaining an example of a mounting position of an outside information detection section and an imaging section. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the drawings. Note that the explanation is given in the following order.

[0048] 1. Embodiment (Solid-state imaging device)… Figures 1-4

[0049] 2. Modified example (Solid-state imaging device)… Figures 5-31

[0050] 3. Application example (Imaging system)… Figure 32

[0051] 4. Application example of mobile body… Figure 33 、 Figure 34

[0052] <1. Embodiment>

[0053] [Configuration]

[0054] A solid-state imaging device 1 according to an embodiment of the present disclosure is explained. The solid-state imaging device 1 is, for example, a backside illumination type image sensor or the like of a global shutter method including a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The solid-state imaging device 1 receives light from a subject and performs photoelectric conversion to generate an image signal, thereby capturing an image. The solid-state imaging device 1 outputs a pixel signal corresponding to incident light.

[0055] The global shutter method is a method of performing global exposure in which all pixels start exposure at substantially the same time and all pixels end exposure at the same time. Here, the term "all pixels" refers to all pixels present in a portion appearing in an image, and excludes dummy pixels and the like. In addition, the global shutter method also includes a method in which, when global exposure is performed in units of multiple rows (e.g., tens of rows) instead of all pixels at the same time, the region in which global exposure is performed is moved. In addition, the global shutter method also includes a method in which, instead of performing global exposure on all pixels present in a portion appearing in an image, global exposure is performed on pixels of a predetermined region.

[0056] A back-illuminated image sensor is an image sensor having a configuration in which a photoreception surface on which light from a subject is incident and a wiring layer in which a wiring for driving a transistor or the like of each pixel is provided are provided with a photoelectric conversion section (e.g., a photodiode) that receives light from a subject and converts light into an electric signal. Note that the present disclosure is not limited to application to a CMOS image sensor.

[0057] Figure 1 An example of a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present disclosure is shown. The solid-state imaging device 1 includes a pixel array section 10 in which a plurality of sensor pixels 11 that perform photoelectric conversion are arranged in a matrix. The sensor pixels 11 correspond to a specific example of the "pixel" of the present disclosure. Figure 2 An example of a circuit configuration of the pixel array section 10 is shown. Figure 3 An example of a cross-sectional configuration of the pixel array section 10 is shown. The solid-state imaging device 1 is configured, for example, by bonding two substrates (a first substrate 30 and a second substrate 40) together.

[0058] The first substrate 30 includes a plurality of sensor pixels 11 on a semiconductor substrate 31. The plurality of sensor pixels 11 are provided in a position opposite to a back surface (a light-receiving surface 31A) of the semiconductor substrate 31 in a matrix. The first substrate 30 also includes a plurality of readout circuits 12 on the semiconductor substrate 31. Each readout circuit 12 outputs a pixel signal based on charge output from the sensor pixel 11. The plurality of readout circuits 12 are provided, for example, one for each sensor pixel 11. The readout circuit 12 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP.

[0059] The first substrate 30 includes a plurality of pixel drive lines extending in the row direction and a plurality of data output lines VSL extending in the column direction. The pixel drive line is a wiring to which a control signal for controlling the output of the electric charge accumulated in the sensor pixel 11 is applied, and extends, for example, in the row direction. The data output line VSL is a wiring through which the pixel signal output from each readout circuit 12 is output to the logic circuit 20, and extends, for example, in the column direction.

[0060] The second substrate 40 includes the logic circuit 20 that processes the pixel signal on the semiconductor substrate 41. The logic circuit 20 includes, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, and a system control circuit 24. The logic circuit 20 (specifically, the horizontal drive circuit 23) outputs the output voltage of each sensor pixel 11 to the outside.

[0061] The vertical drive circuit 21 selects, for example, a plurality of sensor pixels 11 in order for each predetermined unit pixel row. The term “predetermined unit pixel row” refers to a pixel row in which pixels having the same address can be selected.

[0062] The column signal processing circuit 22 performs, for example, Correlated Double Sampling (CDS) processing on the pixel signal output from each sensor pixel 11 of the row selected by the vertical drive circuit 21. The column signal processing circuit 22 performs the CDS processing, for example, to extract the signal level of the pixel signal and hold the pixel data corresponding to the light-receiving amount of each sensor pixel 11. The column signal processing circuit 22 includes, for example, a column signal processing section for each data output line VSL. The column signal processing section includes, for example, a single slope A / D converter. The single slope A / D converter includes, for example, a comparator and a counter circuit. The horizontal drive circuit 23 outputs the pixel data held in the column signal processing circuit 22 to the outside in order. The system control circuit 24 controls the drive of each block (the vertical drive circuit 21, the column signal processing circuit 22, and the horizontal drive circuit 23) in the logic circuit 20.

[0063] Each sensor pixel 11 includes components common to each other. Each sensor pixel 11 includes, for example, a photodiode PD, a transfer transistor TRG, and a floating diffusion section FD. The transfer transistor TRG is an NMOS (Metal Oxide Semiconductor) transistor, for example. The photodiode PD corresponds to a specific example of the “photoelectric conversion section” of the present disclosure. The transfer transistor TRG corresponds to a specific example of the “transfer transistor” of the present disclosure. The floating diffusion section FD corresponds to a specific example of the “charge holding section” of the present disclosure.

[0064] The photodiode PD photoelectrically converts light L incident through the light-receiving surface 31A. The photodiode PD photoelectrically converts, thereby generating electric charges corresponding to the amount of light reception. The photodiode PD is, for example, a PN junction photoelectric conversion element including an N-type semiconductor region 32A and a P-type semiconductor region 32B provided in the semiconductor substrate 31. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TRG, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground GND). The transfer transistor TRG is formed in a layer different from the photodiode PD, and at a position opposite to the photodiode PD in the normal line direction of the semiconductor substrate 31.

[0065] The transfer transistor TRG is connected between the photodiode PD and the floating diffusion FD, and in response to a control signal applied to the gate electrode, the transfer transistor TRG transfers the electric charges accumulated in the photodiode PD from the photodiode PD to the floating diffusion FD. The transfer transistor TRG transfers the electric charges from the photodiode PD to the floating diffusion FD. The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD1, and the gate of the transfer transistor TRG is electrically connected to a pixel drive line.

[0066] The transfer transistor TRG includes two vertical gate electrodes VG as gate electrodes and a connection portion CN. In the transfer transistor TRG, one vertical gate electrode VG is provided in one of the two sensor pixels 11 adjacent to each other, and the other vertical gate electrode VG is provided in the other of the two sensor pixels 11 adjacent to each other. In the transfer transistor TRG, the connection portion CN is in contact with the two vertical gate electrodes VG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the connection portion CN (a part of the gate electrode). Here, the term "share" means that the outputs of the two sensor pixels 11 adjacent to each other are controlled by the common connection portion CN.

[0067] The floating diffusion FD is a floating diffusion that temporarily holds the electric charges output from the photodiode PD via the transfer transistor TRG. For example, the reset transistor RST is connected to the floating diffusion FD, and in addition, the vertical signal line VSL is connected to the floating diffusion FD via the amplification transistor AMP and the selection transistor SEL.

[0068] In the reset transistor RST, the drain is connected to the power supply line VDD, and the source is connected to the floating diffusion FD. The reset transistor RST initializes (resets) the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential level of the power supply line VDD. That is, the floating diffusion FD is initialized.

[0069] The amplification transistor AMP has a gate electrode connected to the floating diffusion FD and a drain electrode connected to the power supply line VDD, and functions as an input portion of a source follower circuit that reads a charge obtained by photoelectric conversion at the photodiode PD. That is, the source of the amplification transistor AMP is connected to the vertical signal line VSL via the selection transistor SEL, and thus the amplification transistor AMP constitutes a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL.

[0070] The selection transistor SEL is connected between the source of the amplification transistor AMP and the vertical signal line VSL, and a control signal is supplied as a selection signal to the gate electrode of the selection transistor SEL. When the control signal is on, the selection transistor SEL becomes in an on state, and the sensor pixel 11 connected to the selection transistor SEL becomes in a selection state. When the sensor pixel 11 is in the selection state, a pixel signal output from the amplification transistor AMP is read by the column signal processing circuit 22 via the vertical signal line VSL.

[0071] Next, the configuration of the sensor pixel 11 will be described in detail with reference to Figure 3 , Figure 4 and Figure 5 . Figure 4 An example of the planar configuration of the logic circuit 20 side of the pixel array section 10 is shown. Figure 5 An example of the planar configuration of the light-receiving surface 31A side of the pixel array section 10 is shown. Note that in Figure 4 , the layout of the various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration of the logic circuit 20 side of the semiconductor substrate 31. Also in Figure 5 , the layout of the vertical gate electrode VG overlaps on the planar configuration of the light-receiving surface 31A side of the semiconductor substrate 31.

[0072] The first substrate 30 is configured by sequentially stacking the semiconductor layer 33 and the insulating layer 32 on the semiconductor substrate 31. That is, the insulating layer 32 is formed in contact with the upper surface of the semiconductor layer 33. The transfer transistor TRG and the floating diffusion portion FD are formed on the upper surface of the semiconductor layer 33. Thus, the upper surface of the semiconductor layer 33 is the formation surface 31B of the transfer transistor TRG and the like. Note that the stack including the semiconductor substrate 31 and the semiconductor layer 33 can also be considered as a semiconductor substrate. In this case, the upper surface of the stack (semiconductor substrate) including the semiconductor substrate 31 and the semiconductor layer 33 is the formation surface 31B, and the back surface of the stack (semiconductor substrate) including the semiconductor substrate 31 and the semiconductor layer 33 is the light-receiving surface 31A. At this time, each sensor pixel 11 is formed in the stack (semiconductor substrate) including the semiconductor substrate 31 and the semiconductor layer 33.

[0073] The gate of the transfer transistor TRG and the wiring connected to the gate of the transfer transistor TRG are provided in the insulating layer 32. For example, the gate of the transfer transistor TRG and the wiring connected to the gate of the transfer transistor TRG are formed of a metal material. Note that the gate of the transfer transistor TRG can be formed of polysilicon. The readout circuit 12 is provided in the insulating layer 32. Note that the readout circuit 12 can also be formed on the formation surface 31B of the semiconductor substrate 31.

[0074] For example, the semiconductor substrates 31 and 41 are each configured of a silicon substrate. For example, the semiconductor layer 33 is configured of a silicon layer formed by epitaxial crystal growth. The semiconductor substrate 31 includes, in a portion of the upper surface and in the vicinity thereof, a P-type semiconductor region 32B and an N-type semiconductor region 32A whose conduction type is different from that of the P-type semiconductor region 32B in a region deeper than the P-type semiconductor region 32B. The P-type semiconductor region 32B is provided on the side of the surface of the semiconductor substrate 31 opposite to the light-receiving surface 31A. The conduction type of the P-type semiconductor region 32B is P-type. The conduction type of the N-type semiconductor region 32A is N-type, which is a conduction type different from that of the P-type semiconductor region 32B. The semiconductor layer 33 has a P-type conduction type which is the same as that of the P-type semiconductor region 32B. The semiconductor layer 33 includes the floating diffusion portion FD whose conduction type is different from that of the semiconductor layer 33. A portion (two vertical gate electrodes VG) of the gate of the transfer transistor TRG is formed so as to extend from the upper surface (formation surface 31B) of the semiconductor layer 33 in the thickness direction (normal direction) of the semiconductor substrate 31. This portion (two vertical gate electrodes VG) of the gate of the transfer transistor TRG extends from the formation surface 31B to a depth reaching the N-type semiconductor region 32A. For example, this portion (two vertical gate electrodes VG) of the gate of the transfer transistor TRG has a rod-like shape extending in the thickness direction (normal direction) of the semiconductor substrate 31.

[0075] For example, the first substrate 30 further includes a fixed charge film 36 in contact with the back surface (light-receiving surface 31A) of the semiconductor substrate 31. The fixed charge film 36 has a negative fixed charge so as to suppress generation of dark current caused by an interface state on the light-receiving surface 31A side of the semiconductor substrate 31. For example, the fixed charge film 36 is formed of an insulating film having a negative fixed charge. Examples of a material of such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. An electric field caused by the fixed charge film 36 forms a hole accumulation layer at the interface on the light-receiving surface 31A side of the semiconductor substrate 31. This hole accumulation layer suppresses generation of electrons from the interface. For example, the first substrate 30 further includes a color filter 37. The color filter 37 is provided on the light-receiving surface 31A side of the semiconductor substrate 31. For example, the color filter 37 is provided in contact with the fixed charge film 36 and at a position opposite to the sensor pixel 11 with the fixed charge film 36 interposed therebetween.

[0076] Each sensor pixel 11 includes a light-receiving lens 50 on the back surface (light-receiving surface 31A) side of the semiconductor substrate 31. That is, the solid-state imaging device 1 includes a plurality of light-receiving lenses 50 provided one for each sensor pixel 11. The plurality of light-receiving lenses 50 are provided one for each photodiode PD and are arranged at positions opposite to the photodiodes PD. That is, the solid-state imaging device 1 is a back-illuminated type imaging device. For example, the light-receiving lens 50 is provided in contact with the color filter 37 and at a position opposite to the sensor pixel 11 with the color filter 37 and the fixed charge film 36 interposed therebetween.

[0077] The first substrate 30 includes separation portions 51, 52, and 54 that electrically and optically separate two adjacent sensor pixels 11 from each other. The separation portions 51, 52, and 54 correspond to specific examples of the “separation portion” of the present disclosure. The separation portions 51 and 52 are formed so as to extend in the normal direction (thickness direction) of the semiconductor substrate 31 within the semiconductor substrate 31 and the semiconductor layer 33. In other words, the separation portions 51 and 52 are connected to each other. The structure including the separation portions 51 and 52 is formed so as to extend from the light-receiving surface 31A to the formation surface 31B. That is, the structure including the separation portions 51 and 52 penetrates the semiconductor substrate 31 and the semiconductor layer 33. Likewise, the separation portion 54 is formed so as to extend in the normal direction (thickness direction) of the semiconductor substrate 31 within the semiconductor substrate 31 and the semiconductor layer 33. The separation portion 54 is formed so as to extend from the light-receiving surface 31A to the formation surface 31B. That is, the separation portion 54 penetrates the semiconductor substrate 31 and the semiconductor layer 33.

[0078] The separation portions 51 and 54 are formed integrally, and are formed, for example, in a manner so as to surround the sensor pixels 11 (particularly, the photodiodes PD) in the horizontal plane direction, and are further formed so as to extend in the normal line direction (thickness direction) of the semiconductor substrate 31. The separation portion 52 and 54 are formed, for example, in a manner so as to surround the sensor pixels 11 (particularly, the transfer transistors TRG and the floating diffusion portion FD) in the horizontal plane direction, and are further formed so as to extend in the normal line direction (thickness direction) of the semiconductor substrate 31.

[0079] The separation portions 51 and 54 are, for example, high-resistance regions formed by implanting impurities into the semiconductor substrate 31. The separation portion 52 includes, for example, a DTI (Deep Trench Isolation) structure. In the separation portion 52, the DTI includes an insulating film 52B in contact with an inner wall of a trench provided in the semiconductor substrate 31 and a metal-embedded portion 52A provided inside the insulating film 52B. The metal-embedded portion 52A is formed so as to extend from the formation surface 31B to a predetermined depth. The insulating film 52B is, for example, an oxide film formed by heat-oxidizing the semiconductor substrate 31, and is formed of, for example, silicon oxide. The metal-embedded portion 52A is a ring-shaped metal layer that surrounds the sensor pixels 11 (specifically, the transfer transistors TRG and the floating diffusion portion FD) in the horizontal plane direction. The metal-embedded portion 52A is formed, for example, using CVD (Chemical Vapor Deposition), and is formed of, for example, aluminum or an aluminum alloy.

[0080] The first substrate 30 further includes, for each sensor pixel 11, a light-blocking portion 53 provided in a layer between the photodiode PD and the floating diffusion portion FD. The light-blocking portion 53 has an opening 53H through which the vertical gate electrode VG penetrates. In two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are arranged so as to face each other with the separation portion 54 interposed therebetween, and are in contact with the separation portion 54. The connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged so as to face each other. The light-blocking portion 53 has the opening 53H at a position in contact with the separation portion 54 and through which the vertical gate electrode VG penetrates. That is, the light-blocking portion 53 has the opening 53H at a position opposite the gate of the transfer transistor TRG. The light-blocking portion 53 blocks light L incident through the light-receiving surface 31A from being incident on the floating diffusion portion FD at a position other than the opening 53H.

[0081] The light-blocking portion 53 includes, for example, an insulating film 53B in contact with an inner wall of a hollow portion 58 provided in the first substrate 30 and a metal-embedded portion 53A provided inside the insulating film 53B. The metal-embedded portion 53A corresponds to a specific example of the "light-blocking portion" of the present disclosure.

[0082] The hollow portion 58 extends in the laminated in-plane direction in the semiconductor layer 33. The hollow portion 58 is formed at a predetermined position in the semiconductor layer 33 by wet etching using a predetermined chemical solution, for example. An etching stopper layer can be provided at a position of the hollow portion 58 opposite the vertical gate electrode VG, for example. The etching stopper layer is composed of a material having a relatively slow etching rate with respect to the chemical solution described above, compared to the semiconductor layer 33.

[0083] The insulating film 53B is formed using CVD, for example. The insulating film 53B is formed of a dielectric material such as SiO2, for example. The insulating film 53B has a laminated structure including a SiO2 film (silicon oxide film), an SCF film, and a SiO2 film (silicon oxide film), for example. Note that the insulating film 53B can be a single-layer film including SiO2 (silicon oxide). The metal-embedded portion 53A is formed using CVD, for example. The metal-embedded portion 53A can be uniformly formed using CVD, for example. The metal-embedded portion 53A is formed of aluminum or an aluminum alloy, for example.

[0084] The metal-embedded portion 53A is formed in contact with a lower portion of the metal-embedded portion 52A of the separation portion 52. The metal-embedded portion 53A blocks the incidence of light incident through the back surface (light-receiving surface 31A) of the semiconductor substrate 31 toward the floating diffusion FD. The metal-embedded portion 53A is provided in a layer between the photodiode PD and the floating diffusion FD. The metal-embedded portion 53A is a sheet-shaped metal layer extending in a direction orthogonal to the normal direction (thickness direction) of the semiconductor substrate 31. The metal-embedded portion 53A has an opening through which the vertical gate electrode VG penetrates. The insulating film 53B covers the metal-embedded portion 53A and insulates and separates the metal-embedded portion 53A and the vertical gate electrode VG from each other. The metal-embedded portion 53A and the vertical gate electrode VG are arranged apart from each other with the insulating film 53B and a portion of the semiconductor layer 33 (hereinafter referred to as “semiconductor portion 33A”), for example.

[0085] [Effects]

[0086] Next, the effects of the solid-state imaging device 1 according to the present embodiment will be described.

[0087] In a solid-state imaging device, a global shutter method using a CMOS image sensor is known (see Patent Literature 1, for example). In the invention described in the above Patent Literature 1, by providing a charge holding portion (to which the electric charges accumulated in the photoelectric conversion portion are transferred) at a depth different from that of the photoelectric conversion portion, it is possible to secure the saturated number of electrons while securing the area of the photoelectric conversion portion.

[0088] However, in the invention described in Patent Document 1 described above, there is a possibility that noise is generated due to light incident to the charge holding portion. In order to reduce the noise, it is conceivable to provide a light shielding layer. In the case where the light shielding layer is provided, it is difficult to transfer the charge from the photoelectric conversion portion to the charge holding portion. In order to facilitate the charge transfer, it is conceivable to provide a vertical gate electrode reaching the photoelectric conversion portion from an opening provided in the light shielding layer. In the case where the vertical gate electrode is provided, the pixel size increases, and the noise caused by the light incident to the charge holding portion from the opening provided in the light shielding layer increases.

[0089] Meanwhile, in the present embodiment, the vertical gate electrode VG reaching the photodiode PD is provided. Therefore, it is possible to avoid the degradation of the charge transfer from the photodiode PD to the floating diffusion portion FD caused by the provision of the light shielding portion 53. Further, in the present embodiment, the two vertical gate electrodes VG are electrically connected together in the two sensor pixels 11 adjacent to each other. Therefore, compared to the case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; therefore, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light shielding portion 53 penetrates. As a result, it is possible to suppress the increase in the noise and the pixel size. Therefore, it is possible to avoid the degradation of the charge transfer while suppressing the increase in the noise and the pixel size.

[0090] In the present embodiment, the connection portion CN is provided in the two sensor pixels 11 adjacent to each other, the connection portion CN being in contact with and electrically connecting together the two vertical gate electrodes VG. Therefore, compared to the case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; therefore, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light shielding portion 53 penetrates. As a result, it is possible to suppress the increase in the noise and the pixel size. Therefore, it is possible to avoid the degradation of the charge transfer while suppressing the increase in the noise and the pixel size.

[0091] In the present embodiment, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 therebetween, and are in contact with the separation portion 54. Further, the connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. Therefore, compared to the case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; therefore, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light shielding portion 53 penetrates. As a result, it is possible to suppress the increase in the noise and the pixel size. Therefore, it is possible to avoid the degradation of the charge transfer while suppressing the increase in the noise and the pixel size.

[0092] In the present embodiment, the opening 53H is provided at a position in contact with the separation portion 54 and through which the vertical gate electrode VG penetrates. Therefore, compared to a case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; therefore, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light shielding portion 53 penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0093] <2. Modification>

[0094] Hereinafter, a modification of the solid-state imaging device 1 according to the foregoing embodiment will be described.

[0095] [Modification A]

[0096] In the foregoing embodiment, each of the sensor pixels 11 can have a plurality of transfer transistors TRG. For example, as shown in Figs. 17A and 17B, each of the sensor pixels 11 can have two transfer transistors TRG. Figure 6 and Figure 7 Figure 6 A modification of the planar configuration on the logic circuit 20 side of the pixel array portion 10 is shown. Figure 7 A modification of the planar configuration on the light-receiving surface 31A side of the pixel array portion 10 is shown. Note that in Figure 6 , the layout of various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration on the logic circuit 20 side of the semiconductor substrate 31. In addition, in Figure 7 , the layout of the vertical gate electrode VG overlaps on the planar configuration on the light-receiving surface 31A side of the semiconductor substrate 31.

[0097] ​For example, the discharge transistor OFG is an NMOS transistor. The discharge transistor OFG discharges the charge from the photoelectric conversion section in response to a control signal applied to the gate electrode. The discharge transistor OFG has a common configuration with the transfer transistor TRG, and includes two vertical gate electrodes VG and a connection portion CN as the gate electrode. In each transfer transistor TRG, one vertical gate electrode VG is provided in one sensor pixel 11 of the two sensor pixels 11 adjacent to each other, and the other vertical gate electrode VG is provided in the other sensor pixel 11 of the two sensor pixels 11 adjacent to each other. In each transfer transistor TRG, the connection portion CN is in contact with the two vertical gate electrodes VG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the connection portion CN (a part of the gate electrode). Here, the term "share" means that the discharge of the charge in the two sensor pixels 11 adjacent to each other is controlled by the common connection portion CN.

[0098] In the present modification, the transfer transistor TRG corresponds to a specific example of the "transfer transistor" of the present disclosure. In addition, in the present modification, the vertical gate electrode VG of one transfer transistor TRG corresponds to a specific example of the "first vertical gate electrode" of the present disclosure, and the vertical gate electrode VG of the other transfer transistor TRG corresponds to a specific example of the "second vertical gate electrode" of the present disclosure.

[0099] In the present modification, the connection portion CN is in contact with the two vertical gate electrodes VG in the transfer transistor TRG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the transfer transistor TRG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the above-described connection portion CN (a part of the gate electrode). In the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the transfer transistor TRG are arranged to face each other with the separation portion 54 therebetween, and are in contact with the separation portion 54. In the transfer transistor TRG, the above-described connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other.

[0100] In the present modification, the light shielding portion 53 has an opening 53H at a position in contact with the separation portion 54 and through which the vertical gate electrode VG included in the transfer transistor TRG passes. The two transfer transistors TRG provided in each sensor pixel 11 are arranged adjacent to each other, and the floating diffusion portion FD is arranged adjacent to the gap between the two vertical gate electrodes VG.

[0101] In the present modification example, two transfer transistors TRG are provided in each sensor pixel 11. Therefore, compared to a case where one transfer transistor TRG is provided in each sensor pixel 11, the charge transfer from the photodiode PD to the floating diffusion FD is improved.

[0102] In the present modification example, the two transfer transistors TRG provided in each sensor pixel 11 are arranged adjacent to each other. Further, in each sensor pixel 11, the floating diffusion FD is arranged adjacent to the gap between the two vertical gate electrodes VG. Therefore, compared to a case where the floating diffusion FD is provided away from the gap between the two vertical gate electrodes VG, the charge transfer from the photodiode PD to the floating diffusion FD is improved.

[0103] In the present modification example, in the transfer transistor TRG, a connection portion CN that contacts the two vertical gate electrodes VG and electrically connects the two vertical gate electrodes VG together is provided. Therefore, compared to a case where the transfer transistor TRG is provided for each sensor pixel 11, the size of the transfer transistor TRG can be reduced; therefore, the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 can be reduced. As a result, an increase in noise and pixel size can be suppressed. Therefore, the degradation of the charge transfer can be avoided while suppressing an increase in noise and pixel size.

[0104] In the present modification example, in the transfer transistor TRG, the two vertical gate electrodes VG are arranged opposite to each other with the separation portion 54 interposed therebetween and contact the separation portion 54. Further, the connection portion CN contacts the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged opposite to each other. Therefore, compared to a case where the transfer transistor TRG is provided for each sensor pixel 11, the size of the transfer transistor TRG can be reduced; therefore, the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 can be reduced. As a result, an increase in noise and pixel size can be suppressed. Therefore, the degradation of the charge transfer can be avoided while suppressing an increase in noise and pixel size.

[0105] In the present modification example, the opening 53H is provided at a position where the separation portion 54 is contacted and the two vertical gate electrodes VG are penetrated. Therefore, compared to a case where the transfer transistor TRG is provided for each sensor pixel 11, the size of the transfer transistor TRG can be reduced; therefore, the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 can be reduced. As a result, an increase in noise and pixel size can be suppressed. Therefore, the degradation of the charge transfer can be avoided while suppressing an increase in noise and pixel size.

[0106] [Modification Example B]

[0107] In the foregoing embodiment, for example, asFigure 8 and Figure 9 As shown in FIG. 12, the transfer transistor TRG of each sensor pixel 11 can further include a vertical gate electrode VG that is not connected to the connection portion CN. Figure 8 A modification example of the planar configuration on the logic circuit 20 side of the pixel array section 10 is shown. Figure 9 A modification example of the planar configuration on the light-receiving surface 31A side of the pixel array section 10 is shown. Note that, in Figure 8 In the modification example, the layout of the various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration on the logic circuit 20 side of the semiconductor substrate 31. In addition, in Figure 9 In the modification example, the layout of the vertical gate electrodes VG overlaps on the planar configuration on the light-receiving surface 31A side of the semiconductor substrate 31.

[0108] In the present modification example, each sensor pixel 11 includes a floating diffusion portion FD at a position adjacent to a gap between the vertical gate electrode VG connected to the connection portion CN and the vertical gate electrode VG not connected to the connection portion CN. Thus, compared to a case where the floating diffusion portion FD is disposed away from the gap between the two vertical gate electrodes VG, the transfer of charges from the photodiode PD to the floating diffusion portion FD is improved.

[0109] [Modification Example C]

[0110] In the foregoing embodiment and the modification examples thereof, the transfer transistor TRG can include four vertical gate electrodes VG as gate electrodes and the connection portion CN. In this case, as shown in Figure 10 , Figure 11 and Figure 12 In the transfer transistor TRG, the four vertical gate electrodes VG are provided one by one with respect to the four sensor pixels 11 adjacent to each other, as shown in

[0111] Figure 10 An example of the circuit configuration of the pixel array section 10 according to the present modification example is shown. Figure 11 An example of the planar configuration on the logic circuit 20 side of the pixel array section 10 according to the present modification example is shown. Figure 12 An example of the planar configuration on the light-receiving surface 31A side of the pixel array section 10 according to the present modification example is shown. Note that, in Figure 11 In the modification example, the layout of the various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration on the logic circuit 20 side of the semiconductor substrate 31. In addition, in Figure 12 In the modification example, the layout of the vertical gate electrodes VG overlaps on the planar configuration on the light-receiving surface 31A side of the semiconductor substrate 31.

[0112] In the present modification example, the connection portion CN is in contact with the four vertical gate electrodes VG in the transfer transistor TRG. That is, in the four sensor pixels 11 adjacent to each other, the four vertical gate electrodes VG are electrically connected to each other via the connection portion CN, and the four sensor pixels 11 adjacent to each other share the connection portion CN (a part of the gate electrode).

[0113] In the present modification example, in the four sensor pixels 11 adjacent to each other, the four vertical gate electrodes VG are arranged to face each other with the separation portion 54 therebetween, and are in contact with the separation portion 54. The connection portion CN is in contact with the top of the separation portion 54 and the top of each of the four vertical gate electrodes VG arranged to face each other. The light shielding portion 53 includes the opening 53H at a position in contact with the separation portion 54 and through which the vertical gate electrode VG passes.

[0114] In this way, in the present modification example, in the transfer transistor TRG, the four vertical gate electrodes VG as the gate electrode and the connection portion CN are provided. Therefore, compared to a case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; therefore, it is possible to reduce the size of the opening 53H of the light shielding portion 53 through which the vertical gate electrode VG passes. As a result, it is possible to suppress an increase in noise and pixel size. Therefore, it is possible to avoid degradation of charge transfer while suppressing an increase in noise and pixel size.

[0115] [Modification Example D]

[0116] In the foregoing embodiment and its modification examples, for example, as shown in Figure 13 and Figure 14 , each of the sensor pixels 11 can include the transfer transistor TRG and the discharge transistor OFG. Figure 13 A modification example of the planar configuration on the logic circuit 20 side of the pixel array portion 10 is shown. Figure 14 A modification example of the planar configuration on the light-receiving surface 31A side of the pixel array portion 10 is shown. Note that, in Figure 13 , the layout of the various transistors (the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration on the logic circuit 20 side of the semiconductor substrate 31. Also, in Figure 14 , the layout of the vertical gate electrode VG overlaps on the planar configuration on the light-receiving surface 31A side of the semiconductor substrate 31.

[0117] For example, the discharge transistor OFG is an NMOS transistor. The discharge transistor OFG discharges the electric charge from the photoelectric conversion section in response to a control signal applied to the gate electrode. The discharge transistor OFG has a common configuration with the transfer transistor TRG, and includes two vertical gate electrodes VG and a connection portion CN as the gate electrode. In the discharge transistor OFG, one vertical gate electrode VG is provided in one of the two sensor pixels 11 adjacent to each other, and the other vertical gate electrode VG is provided in the other of the two sensor pixels 11 adjacent to each other. In the discharge transistor OFG, the connection portion CN is in contact with the two vertical gate electrodes VG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the connection portion CN (a part of the gate electrode). Here, the term "share" means that the discharge of the electric charge in the two sensor pixels 11 adjacent to each other is controlled by the common connection portion CN.

[0118] In the present modification, the transfer transistor TRG corresponds to a specific example of the "transfer transistor" of the present disclosure, and the discharge transistor OFG corresponds to a specific example of the "discharge transistor" of the present disclosure. In addition, in the present modification, the vertical gate electrode VG of the transfer transistor TRG corresponds to a specific example of the "first vertical gate electrode" of the present disclosure, and the vertical gate electrode VG of the discharge transistor OFG corresponds to a specific example of the "second vertical gate electrode" of the present disclosure.

[0119] In the present modification, the connection portion CN is in contact with the two vertical gate electrodes VG in the transfer transistor TRG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the transfer transistor TRG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the above-described connection portion CN (a part of the gate electrode). In the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the transfer transistor TRG are arranged so as to face each other with the separation portion 54 therebetween, and are in contact with the separation portion 54. In the transfer transistor TRG, the above-described connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged so as to face each other.

[0120] Further, in the present modification example, the connection portion CN is in contact with two vertical gate electrodes VG in the discharge transistor OFG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the discharge transistor OFG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the above-described connection portion CN (a part of the gate electrode). In the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG included in the discharge transistor OFG are arranged so as to face each other with the separation portion 54 therebetween, and are in contact with the separation portion 54. In the discharge transistor OFG, the above-described connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged so as to face each other.

[0121] In the present modification example, the light shielding portion 53 has an opening 53H at a position where the vertical gate electrode VG included in the transfer transistor TRG and the vertical gate electrode VG included in the discharge transistor OFG pass through in contact with the separation portion 54. The transfer transistor TRG and the discharge transistor OFG provided in each sensor pixel 11 are arranged adjacent to each other, and the floating diffusion portion FD is arranged adjacent to the gap between the two vertical gate electrodes VG.

[0122] In the present modification example, the transfer transistor TRG and the discharge transistor OFG are provided in each sensor pixel 11. Compared to a case where one transfer transistor TRG is provided in each sensor pixel 11, charge transfer from the photodiode PD to the floating diffusion portion FD is improved.

[0123] In the present modification example, the transfer transistor TRG and the discharge transistor OFG provided in each sensor pixel 11 are arranged adjacent to each other. Further, in each sensor pixel 11, the floating diffusion portion FD is arranged adjacent to the gap between the two vertical gate electrodes VG. Compared to a case where the floating diffusion portion FD is provided away from the gap between the two vertical gate electrodes VG, charge transfer from the photodiode PD to the floating diffusion portion FD is improved.

[0124] In the present modification example, in the transfer transistor TRG, a connection portion CN that contacts the two vertical gate electrodes VG and electrically connects the two vertical gate electrodes VG together is provided. Further, in the present modification example, in the discharge transistor OFG, a connection portion CN that contacts the two vertical gate electrodes VG and electrically connects the two vertical gate electrodes VG together is provided. Therefore, compared to a case where the transfer transistor TRG and the discharge transistor OFG are respectively provided for each sensor pixel 11, it is possible to reduce the size of the transfer transistor TRG and the discharge transistor OFG; therefore, it is possible to reduce the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 through which the vertical gate electrode VG penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0125] In the present modification example, in the transfer transistor TRG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and contact the separation portion 54. Further, the connection portion CN contacts the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. Further, in the present modification example, in the discharge transistor OFG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and contact the separation portion 54. Further, the connection portion CN contacts the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. This can reduce the size of the transfer transistor TRG and the discharge transistor OFG compared to a case where the transfer transistor TRG and the discharge transistor OFG are respectively provided for each sensor pixel 11; therefore, it is possible to reduce the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 through which the vertical gate electrode VG penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0126] In the present modification example, the opening 53H is provided at a position where the separation portion 54 is contacted and the two vertical gate electrodes VG penetrate. This can reduce the size of the transfer transistor TRG compared to a case where the transfer transistor TRG is respectively provided for each sensor pixel 11; therefore, it is possible to reduce the size of the opening 53H of the vertical gate electrode VG of the light-shielding portion 53 through which the vertical gate electrode VG penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0127] [Modification Example E]

[0128] In the foregoing embodiment and its modification examples, as Figure 15 , Figure 16 , Figure 17 and Figure 18As illustrated, each sensor pixel 11 can include, for example, a photodiode PD, a transfer transistor TRG, a transfer transistor TRM, a charge holding portion MEM, a transfer transistor TRX, a floating diffusion portion FD, a discharge transistor OFG, and a discharge floating diffusion portion OFD.

[0129] Figure 15 An example of a circuit configuration of the pixel array section 10 according to the present modification is illustrated. Figure 16 An example of a cross-sectional configuration of the pixel array section 10 according to the present modification is illustrated. Figure 17 An example of a planar configuration of the logic circuit 20 side of the pixel array section 10 according to the present modification is illustrated. Figure 18 An example of a planar configuration of the light-receiving surface 31A side of the pixel array section 10 according to the present modification is illustrated. Note that, in the present modification, the layout of the vertical gate electrode VG overlaps on the planar configuration of the light-receiving surface 31A side of the semiconductor substrate 31. Figure 17 In the present modification, the layout of the various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration of the logic circuit 20 side of the semiconductor substrate 31. In addition, in the present modification, the layout of the vertical gate electrode VG overlaps on the planar configuration of the light-receiving surface 31A side of the semiconductor substrate 31. Figure 18 In the present modification, the layout of the vertical gate electrode VG overlaps on the planar configuration of the light-receiving surface 31A side of the semiconductor substrate 31.

[0130] For example, the transfer transistors TRG, TRM, TRX, and OFG are NMOS transistors, respectively. Figure 15 A case where a part of the gate of the transfer transistor TRG is shared by two sensor pixels 11 adjacent to each other is illustrated. Note that, in the present modification, a part of the gate of the transfer transistor TRG can be shared by four sensor pixels 11 adjacent to each other.

[0131] In the present modification, the transfer transistor TRG is connected between the photodiode PD and the transfer transistor TRM, and the transfer transistor TRG transfers the charge accumulated in the photodiode PD to the transfer transistor TRM in response to a control signal applied to the gate. The transfer transistor TRG transfers the charge from the photodiode PD to the charge holding portion MEM. For example, when the discharge transistor OFG is off and the transfer transistor TRG is on, the charge held in the photodiode PD is transferred to the floating diffusion portion FD via the transfer transistor TRG. The drain of the transfer transistor TRG is electrically connected to the source of the transfer transistor TRM, and the gate of the transfer transistor TRG is connected to the pixel drive line.

[0132] The transfer transistor TRM is connected between the transfer transistor TRG and the transfer transistor TRX, and controls the potential of the charge holding portion MEM in response to a control signal applied to the gate. For example, when the transfer transistor TRM is turned on, the potential of the charge holding portion MEM becomes deep, and when the transfer transistor TRM is turned off, the potential of the charge holding portion MEM becomes shallow. Further, for example, when the transfer transistor TRG and the transfer transistor TRM are turned on, the charge accumulated in the photodiode PD is transferred to the charge holding portion MEM via the transfer transistor TRG and the transfer transistor TRM. The drain of the transfer transistor TRM is electrically connected to the source of the transfer transistor TRX, and the gate of the transfer transistor TRM is connected to the pixel drive line.

[0133] The charge holding portion MEM is a region that temporarily holds the charge accumulated in the photodiode PD in order to realize a global shutter function. The charge holding portion MEM holds the charge transferred from the photodiode PD.

[0134] The transfer transistor TRX is connected between the transfer transistor TRM and the floating diffusion portion FD, and transfers the charge held by the charge holding portion MEM to the floating diffusion portion FD in response to a control signal applied to the gate. For example, when the transfer transistor TRM is turned off and the transfer transistor TRX is turned on, the charge held by the charge holding portion MEM is transferred to the floating diffusion portion FD via the transfer transistor TRM and the transfer transistor TRX. The drain of the transfer transistor TRX is electrically connected to the floating diffusion portion FD, and the gate of the transfer transistor TRX is connected to the pixel drive line.

[0135] The floating diffusion portion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor TRX. For example, the reset transistor RST is connected to the floating diffusion portion FD, and further, the vertical signal line VSL is connected to the floating diffusion portion FD via the amplification transistor AMP and the selection transistor SEL.

[0136] In the discharge transistor OFG, the drain is connected to the power supply line VDD, and the source is connected between the transfer transistor TRG and the transfer transistor TRM. The discharge transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to the gate. For example, when the transfer transistor TRG and the discharge transistor OFG are turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. That is, the photodiode PD is initialized. Further, the discharge transistor OFG forms an overflow path between the transfer transistor TRG and the power supply line VDD, for example, and discharges the charge overflowing from the photodiode PD to the power supply line VDD.

[0137] The transfer transistors TRG, TRM, and TRX, the charge holding portion MEM, the floating diffusion portion FD, and the discharge transistor OFG are formed on the upper surface (formation surface 31B) of the semiconductor layer 33. The gates of the transfer transistors TRG, TRM, and TRX, the gate electrode of the discharge transistor OFG, and the wiring connected to these gate electrodes are provided in the insulating layer 32.

[0138] In the present modification example, like the foregoing embodiment and its modification examples, the vertical gate electrode VG reaching the photodiode PD is provided. Thus, it is possible to avoid the degradation of the charge transfer from the photodiode PD to the floating diffusion portion FD caused by the provision of the light shielding portion 53. Further, in the present modification example, a plurality of (for example, two or four) vertical gate electrodes VG are electrically connected together in a plurality of (for example, two or four) sensor pixels 11 adjacent to each other. Thus, compared to the case where the transfer transistor TRG is provided for each of the sensor pixels 11, it is possible to reduce the size of the transfer transistor TRG; thus, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light shielding portion 53 penetrates. As a result, it is possible to suppress the increase in noise and the pixel size. Thus, it is possible to avoid the degradation of the charge transfer while suppressing the increase in noise and the pixel size.

[0139] In the present modification example, each sensor pixel 11 can include a buffer region between the vertical gate electrode VG and the charge holding portion MEM. For example, the buffer region is an N-type semiconductor region having the same conductivity type as that of the charge holding portion MEM. For example, in the case where the accumulated charge overflows due to the irradiation of the photodiode PD with a large amount of light, by providing the buffer region in this way, it is possible to prevent the overflowing charge from directly entering the charge holding portion MEM.

[0140] In the present modification example, the readout circuit 12 can be provided in the insulating layer 32, instead of being provided on the formation surface 31B of the semiconductor substrate 31. That is, the readout circuit 12 can be provided in a layer different from the layer of each transistor (for example, the transfer transistors TRG, TRM, and TRX, or the discharge transistor OFG) included in the sensor pixel 11. In this case, it is possible to form the charge holding portion MEM larger, thereby making it possible to secure a larger number of saturated electrons.

[0141] [Modification Example F]

[0142] In the foregoing modification example E, for example, as Figure 19 and Figure 20As shown, the discharge transistor OFG can include two vertical gate electrodes VG and a connection portion CN as a gate electrode. In the discharge transistor OFG, one vertical gate electrode VG is provided in one of the two sensor pixels 11 adjacent to each other, and the other vertical gate electrode VG is provided in the other of the two sensor pixels 11 adjacent to each other. In the discharge transistor OFG, the connection portion CN is in contact with the two vertical gate electrodes VG. That is, in the two sensor pixels 11 adjacent to each other, the two vertical gate electrodes VG are electrically connected together via the connection portion CN, and the two sensor pixels 11 adjacent to each other share the connection portion CN (a part of the gate electrode). Here, the term "share" means that the outputs of the two sensor pixels 11 adjacent to each other are controlled by the common connection portion CN.

[0143] In the present modification, the light shielding portion 53 has an opening 53H at a position through which the vertical gate electrode VG included in the transfer transistor TRG and the vertical gate electrode VG included in the discharge transistor OFG in contact with the separation portion 54. The transfer transistor TRG and the discharge transistor OFG provided in each sensor pixel 11 are arranged adjacent to each other, and the floating diffusion portion FD is arranged adjacent to the gap between the two vertical gate electrodes VG.

[0144] In the present modification, the transfer transistor TRG and the discharge transistor OFG are provided in each sensor pixel 11. Compared to the case where one transfer transistor TRG is provided in each sensor pixel 11, the charge transfer from the photodiode PD to the floating diffusion portion FD is improved.

[0145] In the present modification, the transfer transistor TRG and the discharge transistor OFG provided in each sensor pixel 11 are arranged adjacent to each other. Further, in each sensor pixel 11, the floating diffusion portion FD is arranged adjacent to the gap between the two vertical gate electrodes VG. Compared to the case where the floating diffusion portion FD is provided away from the gap between the two vertical gate electrodes VG, the charge transfer from the photodiode PD to the floating diffusion portion FD is improved.

[0146] In the present modification example, in the transfer transistor TRG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and are in contact with the separation portion 54. Further, the connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. Further, in the present modification example, in the discharge transistor OFG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and are in contact with the separation portion 54. Further, the connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. This can reduce the size of the transfer transistor TRG and the discharge transistor OFG as compared with the case where the transfer transistor TRG and the discharge transistor OFG are provided for each of the sensor pixels 11; thus, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light-shielding portion 53 penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Thus, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0147] In the present modification example, in the transfer transistor TRG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and are in contact with the separation portion 54. Further, the connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. Further, in the present modification example, in the discharge transistor OFG, the two vertical gate electrodes VG are arranged to face each other with the separation portion 54 interposed therebetween and are in contact with the separation portion 54. Further, the connection portion CN is in contact with the top of the separation portion 54 and the top of each of the two vertical gate electrodes VG arranged to face each other. This can reduce the size of the transfer transistor TRG and the discharge transistor OFG as compared with the case where the transfer transistor TRG and the discharge transistor OFG are provided for each of the sensor pixels 11; thus, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light-shielding portion 53 penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Thus, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0148] In the present modification example, the opening 53H is provided at a position in contact with the separation portion 54 and penetrated by the two vertical gate electrodes VG. This can reduce the size of the transfer transistor TRG as compared with the case where the transfer transistor TRG is provided for each of the sensor pixels 11; thus, it is possible to reduce the size of the opening 53H through which the vertical gate electrode VG of the light-shielding portion 53 penetrates. As a result, it is possible to suppress an increase in noise and pixel size. Thus, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0149] [Modification Example G]

[0150] In the foregoing Modification Example E, for example, as shown in FIGS. 17A and 17B, the transfer transistor TRG of each of the sensor pixels 11 can further include one vertical gate electrode VG that is not connected to the connection portion CN. Figure 21 and Figure 22 The transfer transistor TRG of each of the sensor pixels 11 can further include one vertical gate electrode VG that is not connected to the connection portion CN. Figure 21A modification of the planar configuration of the logic circuit 20 side of the pixel array section 10 is shown. Figure 22 A modification of the planar configuration of the light-receiving surface 31A side of the pixel array section 10 is shown. Note that, in Figure 21 , the layout of the various transistors (reset transistor RST, amplification transistor AMP, and selection transistor SEL) included in the readout circuit 12 overlaps on the planar configuration of the logic circuit 20 side of the semiconductor substrate 31. Also, in Figure 22 , the layout of the vertical gate electrodes VG overlaps on the planar configuration of the light-receiving surface 31A side of the semiconductor substrate 31.

[0151] In the present modification, each sensor pixel 11 includes a floating diffusion portion FD at a position adjacent to a gap between a vertical gate electrode VG connected to the connection portion CN and a vertical gate electrode VG not connected to the connection portion CN. Thus, compared to a case where the floating diffusion portion FD is disposed away from the gap between the two vertical gate electrodes VG, charge transport from the photodiode PD to the floating diffusion portion FD is improved.

[0152] [Modification H]

[0153] In the foregoing embodiment and its modifications, at least a position of the separation portions 51 and 54 adjacent to the plurality of vertical gate electrodes VG can be formed of an oxide film. For example, as shown in Figure 23 and Figure 24 , a position of the separation portions 51 and 54 adjacent to the plurality of vertical gate electrodes VG can be formed of an oxide film 54A. Also, for example, as shown in Figure 25 and Figure 26 , the entire separation portion 54 can be formed of an oxide film 54A. Also, for example, as shown in Figure 27 and Figure 28 , in the separation portion 54, an oxide film 54A extending from the light-receiving surface 31A to a position adjacent to the plurality of vertical gate electrodes VG can be formed.

[0154] The oxide film 54A is formed, for example, by embedding SiO2 (silicon oxide) into a trench formed in the semiconductor substrate 31 using CVD. In this case, when the gate of the transfer transistor TRG is turned on, charge leakage between two sensor pixels 11 adjacent to each other due to a change in potential of the separation portions 51 and 54 can be prevented. Thus, noise caused by charge leakage can be reduced.

[0155] [Modification I]

[0156] In the foregoing embodiment and its modifications, for example, as shown in Figure 29As shown, the vertical gate electrode VG can be formed to span two sensor pixels 11 adjacent to each other. Even in this case, an effect similar to that of the foregoing embodiment and its modified examples can be obtained.

[0157] [Modified Example J]

[0158] In the foregoing modified examples E, F, G, H, and I, a shape in a laminated surface of a region of the semiconductor substrate 31 formed by the separation portions 51 and 54 that surround the photodiode PD (hereinafter referred to as "first shape") and a shape in a laminated surface of a region of the semiconductor substrate 31 formed by the separation portions 52 and 54 that surround the floating diffusion portion FD or the charge holding portion MEM (hereinafter referred to as "second shape") can be different from each other. For example, the first shape can be a rectangular shape, and the second shape can be a shape closer to a square shape than the first shape.

[0159] [Modified Example K]

[0160] In the foregoing embodiment and its modified examples, for example, the semiconductor substrate 31 can include a Si{111} substrate. The Si{111} substrate is a single-crystal silicon substrate or a single-crystal silicon wafer that has a crystal plane represented by the Miller index symbol {111}. In the single-crystal silicon substrate or the single-crystal silicon wafer, the crystal plane represented by {111} (a crystal plane represented by the plane index {111}) extends along a plane (a horizontal plane) orthogonal to the thickness direction. In the present modified example, the Si{111} substrate also includes a substrate or a wafer whose crystal orientation deviates by several degrees, for example, a substrate or a wafer that deviates by several degrees from the {111} plane toward the nearest

[110] direction. In the present modified example, the Si{111} substrate also includes a silicon single crystal grown on a part or the entire surface of a substrate or a wafer by an epitaxial method or the like.

[0161] In addition, in the present modified example, the {111} plane is a general term for the (111) plane, the (-111) plane, the (1-11) plane, the (11-1) plane, the (-1-11) plane, the (-11-1) plane, the (1-1-1) plane, and the (-1-1-1) plane, which are crystal planes equivalent to each other in symmetry. Therefore, in the present modified example, for example, the description of the Si{111} substrate can be replaced with a Si(1-11) substrate. Here, a bar-shaped symbol used to represent an index in the negative direction is replaced with a minus sign.

[0162] In addition, in the present modification example, the <110> direction is a general term of the

[110] direction, the

[101] direction, the

[011] direction, the [-110] direction, the [1-10] direction, the [-101] direction, the [10-1] direction, the [0-11] direction, the [01-1] direction, the [-1-10] direction, the [-10-1] direction, and the [0-1-1] direction, which are crystal plane directions equivalent to each other in symmetry, and can be understood as any of the above. However, in the present modification example, etching is performed in a direction orthogonal to the element formation surface and a direction further orthogonal to the direction orthogonal to the element formation surface (i.e., a direction parallel to the element formation surface).

[0163] Table 1 shows specific combinations of planes and orientations in which etching is established in the <110> direction in the {111} plane, which is a crystal plane of the Si {111} substrate in the present modification example.

[0164] [Table 1]

[0165]

[0166] As shown in Table 1, there are 96 (= 8 x 12) combinations of the {111} plane and the <110> direction. However, in the present modification example, the <110> direction is defined as a direction orthogonal to the {111} plane, which is the element formation surface, and a direction parallel to the element formation surface. That is, in the present modification example, the combination of the element formation surface in the Si {111} substrate and the orientation in which etching is performed on the Si {111} substrate is selected from one of the combinations indicated by O in Table 1.

[0167] In the present modification example, by performing wet etching using the Si {111} substrate, etching can be easily performed in the lateral direction (X-axis direction) in Figure 3 Figure 16 and Figures 23-28 , and not easily performed in at least the depth direction (Y-axis direction) and the Z-axis direction of the vertical direction (Z-axis direction) in Figure 3 Figure 16 and Figures 23-28 , so that the hollow portion 58 can be formed.

[0168] The hollow portion 58 can be formed, for example, by performing wet etching using a predetermined aqueous alkali solution on the Si {111} substrate. As the aqueous alkali solution, KOH, NaOH, or CsOH or the like is suitable for inorganic solutions, and EDP (ethylenediamine pyrocatechol aqueous solution), N2H4 (hydrazine), NH4OH (ammonium hydroxide), or TMAH (tetramethylammonium hydroxide) or the like is suitable for organic solutions. Depending on the plane orientation of the Si {111}, crystalline anisotropic etching is performed using the characteristics of different etching rates, so that the hollow portion 58 can be formed.

[0169] ​​Specifically, in the Si{111} substrate, <110> The etching rate in the direction (i.e., the direction with one or two Si reverse bonds) is higher than <111> The etching rate in the direction (i.e., the direction with three Si reverse bonds) is sufficiently high. Therefore, in this variant, the etching rate is... <110> The direction (i.e., the direction with one or two Si reverse bonds) is set as the X-axis direction, and the direction is... <111> The direction (i.e., the direction with the three Si reverse bonds) is set to the Z-axis direction, thereby allowing etching to be performed in the X-axis direction, while almost no etching is performed in the Z-axis direction, at least in the Y-axis direction and the Z-axis direction. Therefore, a hollow portion 58 including a pair of first planes, a pair of second planes, and a third plane is formed within the semiconductor substrate 31, which is a Si{111} substrate. Therefore, the light-shielding portion 53 formed in the hollow portion 58 also includes a pair of first planes, a pair of second planes, and a third plane.

[0170] use Figure 30 The schematic diagram is used for illustration. For example, when the Si dangling bond (or dangling bond) side is defined as the positive direction of the normal to the Si{111} plane, the Si reverse bond refers to an atomic bond that extends in the negative direction opposite to the positive direction. Figure 30 An example is given of three reverse bonds at an angle of -19.47° to +19.47° to the {111} plane. Specifically, when a photodiode PD, a hollow portion 58, a light-shielding portion 53, and a charge-retaining portion MEM are provided in a Si{111} substrate, the hollow portion 58 and the light-shielding portion 53 include: a first plane along a first crystal plane of the Si{111} substrate, the first crystal plane being orthogonal to a first direction and represented by the plane index {111}; and a second plane along a second crystal plane of the Si{111} substrate, the second crystal plane being inclined relative to the first direction and represented by the plane index {111}.

[0171] A pair of first planes are planes along the first crystal plane of the semiconductor substrate 31 and are opposite to each other in the Z-axis direction. It should be noted that the first crystal plane in the semiconductor substrate 31 is denoted by the plane index {111}. A pair of second planes are planes along the second crystal plane of the semiconductor substrate 31 and are opposite to each other in the Y-axis direction. It should be noted that the second crystal plane in the semiconductor substrate 31 is denoted by the plane index {111} and is tilted approximately 19.5° relative to the Z-axis direction. That is, the tilt angle of the second crystal plane relative to the horizontal plane (XY plane) is approximately 70.5°. Furthermore, the second crystal plane is tilted relative to the X-axis and Y-axis in the horizontal plane (XY plane), and forms an angle of approximately 30° relative to the Y-axis, for example. A third plane is a plane along the third crystal plane of the semiconductor substrate 31. Similar to the second crystal plane, the third crystal plane of the semiconductor substrate 31 is tilted approximately 19.5° relative to the Z-axis direction. That is, the tilt angle of the third crystal plane relative to the horizontal plane (XY plane) is approximately 70.5°.

[0172] It should be noted, for example, such as Figure 31 As shown, the Si{111} substrate also includes a substrate surface that has been processed relative to... <112> The case of a substrate with an angular deviation. When the deviation angle is less than or equal to 19.47°, the substrate maintains its orientation even with the angular deviation. <110> The etching rate in the direction (i.e., the direction with one Si reverse bond) is higher than <111> The etching rate in the direction (i.e., with three Si reverse bonds) is sufficiently high. As the offset angle increases, the number of steps increases, thus increasing the density of microsteps; therefore, the offset angle is preferably less than or equal to 5°. Incidentally, Figure 31 Examples illustrate the substrate surface in <112> In cases where there is an angular deviation in direction; however, it is also possible to use a substrate surface with... <110> In cases where there is an angular deviation in the orientation, the direction of the deviation is irrelevant. Additionally, X-ray diffraction, electron beam diffraction, or electron beam backscattering diffraction can be used to analyze the planar orientation of Si. Since the number of antibonds in Si is determined by the Si crystal structure, the number of antibonds can also be analyzed by examining the planar orientation of Si.

[0173] In this modified example, a hollow portion 58 and a light-shielding portion 53 are provided within a semiconductor substrate 31, which serves as a Si{111} substrate. The hollow portion 58 and the light-shielding portion 53 each include a first plane along a first crystal plane and a second plane along a second crystal plane inclined relative to the first plane. Here, the first and second crystal planes are each represented by the plane index {111}. Therefore, the hollow portion 58 can be easily formed by anisotropic etching of the crystal using an etching solution such as an alkaline aqueous solution, and exhibits high dimensional accuracy.

[0174] <3. Application Examples>

[0175] Figure 32 An example of a schematic construction of a camera system 2 including a solid-state camera device 1 according to any of the foregoing embodiments and their variations is shown. The camera system 2 corresponds to a specific example of the "electronic device" of this disclosure. The camera system 2 includes, for example, an optical system 210, a solid-state camera device 1, a signal processing circuit 220, and a display unit 230.

[0176] The optical system 210 forms an image of the image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. The solid-state imaging device 1 receives the image light (incident light) incident from the solid-state imaging device 1 and outputs a pixel signal corresponding to the received image light (incident light) to the signal processing circuit 220. The signal processing circuit 220 processes the image signal input from the solid-state imaging device 1 and generates image data. The signal processing circuit 220 also generates an image signal corresponding to the generated image data and outputs the generated image signal to the display unit 230. The display unit 230 displays a screen based on the image signal input from the signal processing circuit 220.

[0177] In this applicable example, the solid-state imaging device 1 according to any one of the foregoing embodiments and their variations is suitable for the imaging system 2. Therefore, it is possible to provide an imaging system 2 with high image quality and low noise.

[0178] <4. Examples of applications of moving bodies>

[0179] The technology according to embodiments of this disclosure (the technology) is applicable to a variety of products. For example, the technology according to embodiments of this disclosure can be implemented as a device mounted on any type of mobile body. Non-limiting examples of such mobile bodies may include: automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, any personal mobile device, airplanes, unmanned aerial vehicles (drones), ships, and robots.

[0180] Figure 33 This is a block diagram illustrating a schematic example of the construction of a vehicle control system, which is an example of a mobile body control system to which the technology according to an embodiment of the present disclosure is applicable.

[0181] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 33 In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0182] The drive system control unit 12010 controls the operations of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generation device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a brake device for generating the braking force of the vehicle.

[0183] The body system control unit 12020 controls the operations of various devices mounted on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, an intelligent key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, or fog lamps. In this case, radio waves transmitted from a mobile device that substitutes for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, the power window device, or the lamps of the vehicle.

[0184] The outside -vehicle information detecting unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 causes the imaging section 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside-vehicle information detecting unit 12030 can perform a detection process or a distance detection process on an object such as a pedestrian, a vehicle, an obstacle, a sign, or a letter on a road surface.

[0185] The imaging section 12031 is an optical sensor for receiving light and outputting an electric signal corresponding to the amount of received light. The imaging section 12031 can output the electric signal as an image or can output the electric signal as ranging information. Further, the light received by the imaging section 12031 can be visible light or can be non-visible light such as infrared rays.

[0186] The in-vehicle information detecting unit 12040 detects information inside the vehicle. For example, the in-vehicle information detecting unit 12040 is connected with a driver state detecting section 12041 for detecting the state of a driver. For example, the driver state detecting section 12041 includes a camera for imaging the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver or can determine whether the driver is dozing off.

[0187] Based on information outside or inside the vehicle acquired by the outside information detecting unit 12030 or the inside information detecting unit 12040, the microcomputer 12051 can calculate a control target value of a driving force generating device, a steering mechanism, or a braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing an advanced driver assistance system (ADAS) function including collision avoidance or impact mitigation of the vehicle, follow-up travel based on a following distance, vehicle speed maintenance travel, vehicle collision warning, or lane deviation warning of the vehicle, or the like.

[0188] Further, the microcomputer 12051 can control a driving force generating device, a steering mechanism, or a braking device, or the like, based on information outside or inside the vehicle acquired by the outside information detecting unit 12030 or the inside information detecting unit 12040, thereby performing cooperative control for realizing autonomous driving of the vehicle independently of the operation of the driver, or the like.

[0189] In addition, based on information outside the vehicle acquired by the outside information detecting unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 controls a headlamp and switches a high beam to a low beam for preventing glare, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detecting unit 12030, thereby performing cooperative control for preventing glare.

[0190] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device that can visually or aurally notify a passenger on the vehicle or outside the vehicle of information. In Figure 33 In an example, as the output device, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are shown. The display section 12062 can include at least one of a vehicle-mounted display and a head-up display, for example.

[0191] Figure 34 FIG. 12 is a diagram showing an example of a mounting position of the imaging section 12031.

[0192] In Figure 34 The imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0193] For example, the imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at positions of a front nose, a rearview mirror, a rear bumper, and a rear door of the vehicle 12100 and a position of an upper portion of a windshield inside the vehicle. The imaging section 12101 provided at the front nose and the imaging section 12105 provided at the upper portion of the windshield inside the vehicle mainly acquire images of a front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the rearview mirror mainly acquire images of sides of the vehicle 12100. The imaging section 12104 provided at the rear bumper or the rear door mainly acquires an image of a rear of the vehicle 12100. The imaging section 12105 provided at the upper portion of the windshield inside the vehicle is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal lamp, a traffic sign, or a lane.

[0194] Incidentally, Figure 34 Examples of imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 indicates an imaging range of the imaging section 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate imaging ranges of the imaging sections 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates an imaging range of the imaging section 12104 provided at the rear bumper or the rear door. For example, a bird's-eye image of the vehicle 12100 when viewed from above is obtained by superimposing image data acquired by the imaging sections 12101 to 12104.

[0195] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera composed of a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0196] For example, the microcomputer 12051 can determine distances to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in the distances over time (relative speeds with respect to the vehicle 12100) on the basis of distance information obtained from the imaging sections 12101 to 12104, and thereby extract a three-dimensional object closest to the vehicle and traveling in almost the same direction as the vehicle 12100 at a predetermined speed (for example, greater than or equal to 0 km / h) on a road on which the vehicle 12100 travels as a preceding vehicle. In addition, the microcomputer 12051 can set a following distance to be maintained in front of the preceding vehicle in advance, and can perform automatic brake control (including follow-up stop control) or automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control aimed at autonomous driving of the vehicle without depending on an operation of a driver or the like can be performed.

[0197] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data on a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to be visually recognized by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk for indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or higher than a set value and thus a collision is likely to occur, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid a collision.

[0198] At least one of the imaging sections 12101 to 12104 can be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in an image captured by the imaging sections 12101 to 12104. For example, recognition of such a pedestrian is performed by extracting feature points in an image captured by the imaging sections 12101 to 12104 as an infrared camera, and determining whether an object represented by a series of the feature points is a pedestrian by pattern matching processing. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging sections 12101 to 12104 and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a rectangular outline line for emphasis is superimposed and displayed on the recognized pedestrian. The sound / image output section 12052 can also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0199] One example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied has been described above. The technology according to the embodiment of the present disclosure can be applied to the imaging section 12031 in the above-described configuration. Specifically, the solid-state imaging device 1 according to any one of the foregoing embodiments and modifications thereof is suitable for the imaging section 12031. By applying the technology according to the embodiment of the present disclosure to the imaging section 12031, a high-quality captured image with less noise can be obtained, and thus high-precision control using the captured image can be performed in the mobile body control system.

[0200] The above, although the present disclosure is described with reference to the embodiments and modifications, applications, and application examples thereof, the present disclosure is not limited to the foregoing embodiments, etc., but can also be modified in various ways. It should be noted that the effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure can have other effects than those described herein.

[0201] The first solid-state imaging device and the first electronic apparatus according to the embodiments of the present disclosure provide a vertical gate electrode reaching a photoelectric conversion section, and in a plurality of first pixels adjacent to each other among a plurality of pixels, a plurality of vertical gate electrodes are electrically connected together. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0202] The second solid-state imaging device and the second electronic apparatus according to the embodiments of the present disclosure provide first and second vertical gate electrodes reaching a photoelectric conversion section, and in a plurality of first pixels adjacent to each other among a plurality of pixels, a plurality of first vertical gate electrodes are electrically connected together, and a plurality of second vertical gate electrodes are electrically connected together. Therefore, it is possible to avoid deterioration of charge transfer while suppressing an increase in noise and pixel size.

[0203] In addition, the present disclosure can also have the following configuration. (1)

[0205] A solid-state imaging device includes:

[0206] a light-receiving surface;

[0207] a plurality of pixels each including a photoelectric conversion section that photoelectrically converts light incident through the light-receiving surface; and

[0208] a separation section that electrically and optically separates each photoelectric conversion section,

[0209] Each of the pixels includes:

[0210] a charge holding section that holds a charge transferred from the photoelectric conversion section;

[0211] a transfer transistor including a vertical gate electrode reaching the photoelectric conversion section, and the transfer transistor transfers a charge from the photoelectric conversion section to the charge holding section; and

[0212] a light-shielding section provided in a layer between the photoelectric conversion section and the charge holding section, wherein

[0213] In a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together. (2)

[0215] The solid-state imaging device according to (1), wherein the first pixel shares a connection portion that contacts the plurality of vertical gate electrodes and electrically connects the plurality of vertical gate electrodes together. (3)

[0217] The solid-state imaging device according to (2), wherein, in the plurality of first pixels,

[0218] The plurality of vertical gate electrodes are arranged to face each other across the separation portion and contact the separation portion, and

[0219] The connection portion contacts a top of the separation portion and a top of each of the plurality of vertical gate electrodes arranged to face each other. (4)

[0221] The solid-state imaging device according to (3), wherein the light-shielding portion has an opening at a position that contacts the separation portion and through which the vertical gate electrode penetrates. (5)

[0223] The solid-state imaging device according to any one of (1) to (4), further comprising a semiconductor substrate in which the light-shielding portion is included, wherein

[0224] The semiconductor substrate includes a Si{111} substrate that includes a first crystal plane represented by a plane index {111} extending along a plane orthogonal to a thickness direction, and

[0225] The light-shielding portion includes:

[0226] a first plane along the first crystal plane; and

[0227] a second plane that is inclined with respect to the thickness direction and along a second crystal plane of the Si{111} substrate. (6)

[0229] A solid-state imaging device comprising:

[0230] a light-receiving surface;

[0231] a plurality of pixels each including a photoelectric conversion portion that photoelectrically converts light incident through the light-receiving surface; and

[0232] a separation portion that electrically and optically separates each photoelectric conversion portion,

[0233] Each of the pixels includes:

[0234] a charge holding portion that holds a charge transferred from the photoelectric conversion portion;

[0235] a transfer transistor including a first vertical gate electrode reaching the photoelectric conversion section, and transferring a charge from the photoelectric conversion section to the charge holding section;

[0236] a discharge transistor including a second vertical gate electrode reaching the photoelectric conversion section, and being disposed adjacent to the transfer transistor, the discharge transistor discharging a charge from the photoelectric conversion section; and

[0237] a light shielding section disposed in a layer between the light receiving surface and the charge holding section, wherein

[0238] in a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the first vertical gate electrodes are electrically connected together, and a plurality of the second vertical gate electrodes are electrically connected together. (7)

[0240] The solid-state imaging device according to (6), wherein, in the plurality of first pixels,

[0241] the plurality of first vertical gate electrodes are arranged to face each other across the separation section and to be in contact with the separation section,

[0242] the plurality of second vertical gate electrodes are arranged to face each other across the separation section and to be in contact with the separation section, and

[0243] the first pixel shares a first connection section and a second connection section,

[0244] the first connection section is in contact with the plurality of first vertical gate electrodes and electrically connects the plurality of first vertical gate electrodes together,

[0245] the second connection section is in contact with the plurality of second vertical gate electrodes and electrically connects the plurality of second vertical gate electrodes together. (8)

[0247] The solid-state imaging device according to (7), wherein

[0248] in the plurality of first pixels, the plurality of first vertical gate electrodes are arranged to face each other across the separation section and to be in contact with the separation section, and

[0249] the first connection section is in contact with a top of the separation section and a top of each of the plurality of first vertical gate electrodes arranged to face each other, and

[0250] in the plurality of first pixels, the plurality of second vertical gate electrodes are arranged to face each other across the separation section and to be in contact with the separation section, and

[0251] The second connection portion contacts the top of the separation portion and the top of each of the plurality of second vertical gate electrodes arranged opposite to each other. (9)

[0253] The solid-state imaging device according to (8), wherein the light-blocking portion has an opening at a position in contact with the separation portion and through which the first vertical gate electrode and the second vertical gate electrode pass. (10)

[0255] The solid-state imaging device according to any one of (6) to (9), wherein the charge holding portion is arranged adjacent to a gap between the first vertical gate electrode and the second vertical gate electrode. (11)

[0257] The solid-state imaging device according to any one of (6) to (10), further comprising a semiconductor substrate in which the light-blocking portion is included, wherein

[0258] The semiconductor substrate includes a Si{111} substrate including a first crystal plane represented by a plane index {111} extending along a plane orthogonal to a thickness direction, and

[0259] The light-blocking portion includes:

[0260] a first plane along the first crystal plane; and

[0261] a second plane inclined with respect to the thickness direction and along a second crystal plane of the Si{111} substrate. (12)

[0263] An electronic apparatus including:

[0264] a solid-state imaging device that outputs a pixel signal corresponding to incident light; and

[0265] a signal processing circuit that processes the pixel signal,

[0266] The solid-state imaging device includes:

[0267] a light-receiving surface;

[0268] a plurality of pixels each including a photoelectric conversion portion that photoelectrically converts light incident through the light-receiving surface; and

[0269] a separation portion that electrically and optically separates each photoelectric conversion portion,

[0270] Each of the pixels includes:

[0271] a charge holding portion that holds a charge transferred from the photoelectric conversion portion;

[0272] a transfer transistor including a vertical gate electrode reaching the photoelectric conversion section and transferring a charge from the photoelectric conversion section to the charge holding section; and

[0273] a light shielding section provided in a layer between the photoelectric conversion section and the charge holding section, wherein

[0274] in a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together. (13)

[0276] An electronic apparatus including:

[0277] a solid-state imaging device that outputs a pixel signal corresponding to incident light; and

[0278] a signal processing circuit that processes the pixel signal,

[0279] the solid-state imaging device includes:

[0280] a light receiving surface;

[0281] a plurality of pixels each including a photoelectric conversion section that photoelectrically converts light incident through the light receiving surface; and

[0282] a separation section that electrically and optically separates each photoelectric conversion section,

[0283] each of the pixels includes:

[0284] a charge holding section that holds a charge transferred from the photoelectric conversion section;

[0285] a transfer transistor including a first vertical gate electrode reaching the photoelectric conversion section and transferring a charge from the photoelectric conversion section to the charge holding section;

[0286] a discharge transistor including a second vertical gate electrode reaching the photoelectric conversion section, the discharge transistor being provided adjacent to the transfer transistor, the discharge transistor discharging a charge from the photoelectric conversion section; and

[0287] a light shielding section provided in a layer between the light receiving surface and the charge holding section, wherein

[0288] in a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together.

[0289] This application claims the benefit of Japanese Priority Patent Application JP 2019-207923 filed November 18, 2019 with the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0290] Those skilled in the art will understand that various modifications, combinations, sub-combinations, and alterations can occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A solid-state imaging device comprising: a light-receiving surface; a plurality of pixels each including a photoelectric conversion section that photoelectrically converts light incident through the light-receiving surface; and a separation section that electrically and optically separates each of the photoelectric conversion sections, each of the pixels includes: a charge holding section that holds a charge transferred from the photoelectric conversion section; a transfer transistor including a vertical gate electrode reaching the photoelectric conversion section, and that transfers a charge from the photoelectric conversion section to the charge holding section; and a light-shielding section provided in a layer between the photoelectric conversion section and the charge holding section, wherein in a plurality of first pixels adjacent to each other among the plurality of pixels, a plurality of the vertical gate electrodes are electrically connected together, wherein the solid-state imaging device further has a semiconductor substrate including the light-shielding section therein, wherein the semiconductor substrate includes a Si{111} substrate including a first crystal plane represented by a plane index {111} extending along a plane orthogonal to a thickness direction, and the light-shielding section includes: a first plane along the first crystal plane; and a second plane inclined with respect to the thickness direction and along a second crystal plane of the Si{111} substrate. The first pixels share a connection section that is in contact with the plurality of vertical gate electrodes and electrically connects the plurality of vertical gate electrodes to each other.

2. The solid-state image pickup device according to claim 1, wherein In the plurality of first pixels, 3.The solid-state camera according to claim 2, wherein the plurality of vertical gate electrodes are arranged to face each other across the separation section and are in contact with the separation section, and the connection section is in contact with a top of the separation section and a top of each of the plurality of vertical gate electrodes arranged to face each other. The light-shielding section has an opening at a position in contact with the separation section and through which the vertical gate electrode penetrates.

4. The solid-state camera of claim 3, wherein, 5. An electronic apparatus comprising: the solid-state imaging device according to any one of claims 1 to 4 that outputs a pixel signal corresponding to incident light; and a signal processing circuit that processes the pixel signal. ​

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