LED Array and Method of Forming the Same

Abstract

Provided is a light-emitting diode (LED) array precursor. The LED array precursor includes a substrate having a substrate surface, a first LED stack, a p++ layer, an n++ layer, and a second LED stack. The first LED stack is disposed on a first portion of the substrate surface. The first LED stack includes a plurality of first group-III nitride layers that define a first semiconductor junction configured to output light having a first wavelength, wherein the n-type side of the first semiconductor junction is oriented toward the substrate surface. The p++ layer is disposed on the first LED stack and includes a group-III nitride. The n++ layer has a first portion covering the p++ layer of the first LED stack and a second portion covering a second portion of the substrate surface, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, and the n++ layer includes a group-III nitride. The second LED stack is disposed on the second portion of the n++ layer covering the second portion of the substrate surface. The second LED stack includes a plurality of second group-III nitride layers that define a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein the n-type side of the semiconductor junction is disposed toward the n++ layer. Also provided is a method of manufacturing an LED array precursor.

Description

Technical Field

[0001] The present disclosure relates to LED arrays and methods of forming LED arrays. In particular, the present disclosure relates to LED arrays including group III nitrides. Background Art

[0002] Monolithic micro-LED arrays are well-suited for producing high-resolution displays with small pitch, where pick-and-place manufacturing methods are undesirable due to yield and throughput limitations. Techniques for manufacturing efficient monochromatic (blue) GaN monolithic micro-LED arrays are known in the art. To produce full-color micro-LED-based displays, red and green subpixels need to be integrated into the display.

[0003] One way to form a full-color display is to provide an LED array including a plurality of different LEDs, each LED configured to output one or, for example, red, green, and blue light. Such an LED array is typically referred to as a "native" LED array if the full-color spectrum is directly generated by electroluminescence rather than by using color conversion materials such as phosphors or quantum dots.

[0004] A native multicolor LED array can be formed by a multiple selective-area-growth (SAG) deposition step. This method is challenging because the growth conditions of the subpixels formed in the SAG step are severely affected by the local surroundings (i.e., the deposition parameters are highly geometry-dependent). Therefore, the growth parameters for forming multiple native LEDs by SAG need to be adjusted according to the specific mask layout. Thus, minor changes in the display / LED geometry may require re-calibration of all SAGs. For example, a SAG process is disclosed in GB 1811109.6, as shown in FIG. 1a, where a first LED having a blue light active region is selectively formed on a first region of a GaN substrate. Then, the first LED having the blue light active region is coated with a SiO2 mask layer. Subsequently, as shown in FIG. 1b, a second LED having a green light active region is selectively formed on a second region of the GaN substrate by a subsequent SAG deposition step.

[0005] The SAG preparation of LEDs may result in compositional non-uniformity on a single subpixel for medium to large pixel sizes. This, in turn, leads to a broad emission wavelength, which reduces the color purity of the display. In addition, the mask material used in the SAG process may cause the active region to be contaminated with unwanted impurities, as described in US 2004 / 0129929 A1. Thus, the SiO2 mask layer in FIG. 1 may cause contamination of the second LED.

[0006] Finally, it has been observed that the p-type GaN surface in the mask region of the LED array may decompose during the subsequent high-temperature deposition following the LED junction, thus damaging the anode contact to the junction deposited in an earlier step. This limits the process window for depositing the LED junction following.

[0007] The object of the present invention is to provide an improved method for forming an LED array, which solves at least one problem associated with prior art methods, or at least provides a commercially useful alternative. Summary of the Invention

[0008] The present inventors have realized that when forming an LED array, it is preferably to use a deposition process independent of geometry. For example, a deposition process in which a layer is deposited on a substrate and then patterned (e.g., by etching) can be considered independent of geometry. However, the present inventors have realized a problem associated with patterning a group III nitride LED array is that an etching process terminated on a p-type semiconductor group III nitride will damage the conductivity of the p-type material, as documented in Journal of The Electrochemical Society, 150(9) G513 - G519(2003).

[0009] Therefore, according to a first aspect of the present disclosure, there is provided a method for forming an LED array. The method includes:

[0010] (a) forming a first LED stack on a substrate surface of a substrate, the first LED stack including a plurality of first group III nitride layers, the plurality of first group III nitride layers defining a first semiconductor junction configured to output light having a first wavelength, wherein the n-type side of the semiconductor junction is oriented towards the substrate surface;

[0011] (b) forming a p++ layer on the first LED stack, the p++ layer including group III nitride;

[0012] (c) forming an n++ layer above the substrate to cover the p++ layer, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, and the n++ layer includes group III nitride;

[0013] (d) forming a second LED stack on the n++ layer, the second LED stack including a plurality of second group III nitride layers, the plurality of second group III nitride layers defining a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein the n-type side of the second semiconductor junction is set closest to the n++ layer,

[0014] wherein the method further includes the steps of:

[0015] Selectively remove portions of a first LED stack and a second LED stack on a substrate surface to define:

[0016] A first portion of an LED array, wherein the second LED stack is selectively removed, and the first portion of the LED array includes:

[0017] A first portion of the first LED stack;

[0018] A first portion of the p++ layer; and

[0019] A first portion of the n++ layer such that a tunnel junction is disposed on the first portion of the first LED stack; and

[0020] A second portion of the LED array, including:

[0021] A second portion of the n++ layer; and

[0022] A first portion of the second LED stack disposed on the second portion of the n++ layer.

[0023] The method according to the first aspect provides a method of forming two different native LEDs on a substrate. Compared with the prior art methods, the method of the first aspect allows each of the first LED stack and the second LED stack to be formed on the substrate and then a selective removal step. Thus, the first LED stack and the second LED stack can be grown on the substrate independently of the geometry of the LED to be formed. Therefore, the method according to the first aspect can be used for a series of different device geometries without calibrating the processing methods for forming the first LED stack and the second LED stack when the device geometry changes.

[0024] As described above, one problem with selectively removing portions of the LED stack is that the selective removal process may not terminate on the p-type semiconductor layer. In the method of the first aspect, a tunnel junction is disposed on top of the first LED stack such that the first LED stack does not terminate with a p-type semiconductor group III nitride.

[0025] Thus, subsequent deposition and removal of the second LED stack on top of the first LED stack does not impair the conductivity of the first p-type layer of the first LED stack. Therefore, the method according to the first aspect allows different native LEDs (the first LED stack and the second LED stack) to be monolithically formed on the same substrate using a geometry-independent process.

[0026] Importantly, the method according to the first aspect does not involve forming any layer of the first LED stack and the second LED stack on a mask layer. Thus, the method according to the first aspect reduces or eliminates problems associated with mask layer contamination (e.g., Si or O contamination of the LED stack layers).

[0027] Thus, the method according to the first aspect may include:

[0028] (a) Forming a first LED stack on a substrate surface of a substrate, the first LED stack including a plurality of first group-III nitride layers that define a first semiconductor junction configured to output light having a first wavelength, wherein an n-type side of the semiconductor junction is oriented toward the substrate surface;

[0029] (b) Forming a p++ layer on the first LED stack, the p++ layer including a group-III nitride;

[0030] (c) Forming an n++ layer over the substrate to cover the p++ layer, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, and the n++ layer includes a group-III nitride;

[0031] (d) Forming a second LED stack on the n++ layer, the second LED stack including a plurality of second group-III nitride layers that define a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein the n-type side of the semiconductor junction is disposed closest to the n++ layer;

[0032] (e) Selectively removing a portion of the second LED stack on the substrate surface;

[0033] wherein the method further includes the step of:

[0034] Before forming the n++ layer, or after forming the second LED stack, selectively removing a portion of the first LED stack to define:

[0035] A first portion of the LED array, wherein the second LED stack is selectively removed, and the first portion of the LED array includes:

[0036] A first portion of the first LED stack;

[0037] A first portion of the p++ layer; and

[0038] A first portion of the n++ layer such that the tunnel junction is disposed on the first portion of the first LED stack; and

[0039] A second portion of the LED array, including:

[0040] A second portion of the n++ layer; and

[0041] A first portion of the second LED stack disposed on the second portion of the n++ layer.

[0042] In some embodiments, one or more surface treatment processes may be performed on the p++ layer before the formation of the n++ layer. For example, an annealing step may be performed on the p++ layer before the formation of the n++ layer. The annealing step may be set to enhance the activation of acceptor ions (such as Mg ions) in the p++ layer. A surface treatment process may be performed on the p++ layer, in which the p++ layer is exposed to BHF. The BHF treatment may counteract the concentration of acceptor ions formed near the surface of the p++ layer, on which the n++ layer will be formed. By applying one or more surface treatment processes to the p++ layer, the resistance of the tunnel junction formed between the n++ layer and the p++ layer can be reduced. In this way, the deposition of the p++ layer and the n++ layer may be performed in two different deposition steps separated by an in-situ surface treatment step. This method may reduce or prevent the diffusion of acceptor ions (such as Mg) from the p++ layer to the n++ layer.

[0043] In some embodiments, the first LED stack includes: a first n-type layer disposed on a substrate surface; a first active layer configured to be disposed on the first n-type layer to generate light having a first wavelength; and a first p-type layer disposed on the first active layer. Each layer of the first LED stack may include a group III nitride. Each layer may be formed as a substantially continuous layer.

[0044] In some embodiments, the second LED stack includes: a second n-type layer disposed on the n++ layer; a second active layer configured to be disposed on the second n-type layer to generate light having a second wavelength, wherein the second wavelength is different from the first wavelength; and a second p-type layer disposed on the second active layer. Each layer of the second LED stack may include a group III nitride. Each layer of the second LED stack may be formed as a substantially continuous layer.

[0045] In some embodiments, the first active layer of the first LED stack includes a first multiple quantum well stack configured to output light having a first wavelength, and the second active layer of the second LED stack includes a second multiple quantum well stack configured to output light having a second wavelength. In this way, the first active layer and the second active layer of the LED array may be configured to provide two different native LEDs that output light having the first wavelength and the second wavelength, respectively. The same concept may be extended to further include a third active region having a third emission wavelength.

[0046] In some embodiments, the first LED stack includes a first strain relaxation stack disposed between the first n-type layer and the first active layer. In some embodiments, the second LED stack includes a second strain relaxation stack disposed between the second n-type layer and the second active layer. The first strain relaxation stack and the second strain relaxation stack may be provided to accommodate the lattice constant difference between the lattice constant of the substrate and the lattice constant of the first active layer or the second active layer.

[0047] In some embodiments, the first multi - quantum well stack includes alternating layers of GaN and In X Ga 1-X N, where 0 < X ≤ 1. In some embodiments, the second multi - quantum well stack includes alternating layers of GaN and In Y Ga 1-Y N, where 0 < Y ≤ 1. In some embodiments, each of the first strain relaxation stack and the second strain relaxation stack includes alternating layers of GaN and In Z Ga 1-Z N, where 0 < Z ≤ 1. That is, in some embodiments, only the first strain relaxation stack or the second strain relaxation stack may be provided. In some embodiments, the first strain relaxation stack and the second strain relaxation stack may be provided, where the first strain relaxation stack and the second strain relaxation stack may be the same or they may be different.

[0048] In some embodiments, the first LED stack includes a first electron blocking layer disposed between the first active layer and the first p - type layer. In some embodiments, the second LED stack includes a second electron blocking layer disposed between the second active layer and the second p - type layer. The first electron blocking layer and the second electron blocking layer may include group - III nitrides, such as AlGaN. The first electron blocking layer and the second electron blocking layer may be configured to increase charge carrier confinement in the corresponding first active region or second active region.

[0049] In some embodiments, the n++ layer may include an etch - stop sub - layer. The etch - stop sub - layer includes a group - III nitride containing Al. Thus, the etch - stop sub - layer may be configured to provide a sub - layer of the n++ layer that is more resistant to etching than other materials of the n++ layer 40. Thus, the etch - stop layer may provide a surface that can terminate a selective removal process.

[0050] In some embodiments, the first wavelength may be at least 380 nm and not greater than 480 nm. In some embodiments, the second wavelength may be at least 500 nm and not greater than 580 nm. Thus, the LED array may provide native LEDs configured to output substantially blue visible light and substantially green visible light.

[0051] In some embodiments, each portion of the LED array has a surface size of less than 100 μm × 100 μm on the substrate. Thus, the method according to the first aspect may provide a micro - LED array. The micro - LED array is an array of micro - LEDs.

[0052] In some embodiments, the n++ layer has a charge carrier density of at least 10 19 cm -3 . In some embodiments, the p++ layer has a charge carrier density of at least 1019 cm -3 The charge carrier density of. For example, in some embodiments, the n++ layer may include an electron donor having an electron donor density (ND) of at least 10 19 cm -3 In some embodiments, the p++ layer may include an electron acceptor having an electron acceptor density (NA) of at least 10 20 cm -3 of electron acceptors.

[0053] In some embodiments, the method may further include forming a first contact layer on a second n-type layer covering the first LED stack, and / or forming a second contact layer on a second p-type layer of the second LED stack. For example, in some embodiments, the first contact layer includes one or more metal layers adapted to form an ohmic contact with an n-type semiconductor (e.g., n-type GaN). Thus, the first contact layer may include Ti, Al, or Mo (e.g., a stack based on Ti or Mo). In some embodiments, the second contact layer includes one or more metal layers adapted to form an ohmic contact with a p-type semiconductor (e.g., p-type GaN). Thus, the second contact layer may include Ni, Pd, or Pt (e.g., a stack based on Ni or based on Pt or based on Pd).

[0054] In some embodiments of the first aspect, the step of selectively removing a portion of at least one of the first LED stack or the second LED stack includes selectively depositing a mask layer on a portion of the first LED stack covering a first portion of the substrate surface or on a portion of the second LED stack covering a second portion of the substrate surface, and etching the exposed portion of the first LED stack or the second LED stack to expose the underlying layer. Advantageously, the etching step according to the first aspect does not terminate on the p-type semiconductor layer.

[0055] According to some embodiments of the present disclosure, the method includes performing the step of selectively removing a portion of the first LED stack before forming the second LED stack.

[0056] Thus, in some embodiments, a second portion of the first LED stack may be selectively removed to expose a second portion of the substrate surface before forming the n++ layer, wherein the n++ layer is formed over the substrate surface such that the n++ layer covers the first portion of the first LED stack and the second portion of the substrate surface, and such that the second portion of the second LED stack is disposed on the second portion of the substrate surface.

[0057] In some embodiments, a second portion of the p++ layer and a second portion of the first LED stack are selectively removed together to expose a second portion of the substrate surface. That is, before the formation of the n++ layer (i.e., between the formation of the p++ layer and the formation of the n++ layer), a second portion of the first LED stack and a second portion of the p++ layer are selectively removed.

[0058] That is, according to some embodiments of the first aspect, the method includes:

[0059] (a) forming a first LED stack on a substrate surface of a substrate, the first LED stack including a plurality of group III nitride layers, the plurality of group III nitride layers defining a semiconductor junction configured to output light having a first wavelength, wherein an n-type side of the semiconductor junction is oriented toward the substrate surface;

[0060] (b) forming a p++ layer on the first LED stack, the p++ layer including a group III nitride;

[0061] (c) selectively removing a portion of the first LED stack and a portion of the p++ layer to define a first portion and a second portion of an LED array, providing a first portion of the first LED stack and a first portion of the p++ layer in the first portion of the LED array, and selectively removing the first LED stack and the p++ layer in the second portion of the LED array;

[0062] (d) forming an n++ layer over the first and second portions of the LED array to cover the p++ layer, wherein a tunnel junction is formed at an interface between the n++ and p++ layers, and the n++ layer includes a group III nitride;

[0063] (e) forming a second LED stack on the n++ layer, the second LED stack including a plurality of group III nitride layers, the plurality of group III nitride layers defining a semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein an n-type side of the semiconductor junction is disposed closest to the n++ layer; and

[0064] (f) selectively removing a portion of the second LED stack from the first portion of the LED array to define:

[0065] a first portion of the LED array, wherein the second LED stack is selectively removed, and the first portion of the LED array includes:

[0066] a first portion of the first LED stack;

[0067] a first portion of the p++ layer; and

[0068] a first portion of the n++ layer such that the tunnel junction is disposed on the first portion of the first LED stack; and

[0069] The second part of the LED array, comprising:

[0070] The second part of the n++ layer; and

[0071] The first part of the second LED structure, disposed on the second part of the n++ layer.

[0072] In some embodiments, the method may further include selectively removing portions of the first LED stack and portions of the second LED stack in the LED array region between the first part and the second part of the LED array. For example, the method may include:

[0073] (f) Selectively removing portions of the first LED stack and portions of the second LED stack to expose the sidewall surfaces of the first LED stack and the sidewall surfaces of the second LED stack, so as to define a trench between the first part and the second part of the LED array; and

[0074] (g) Depositing a passivation layer in the trench to cover the sidewall surfaces of the first LED stack and the sidewall surfaces of the second LED stack.

[0075] Thus, embodiments of the present disclosure can provide a method for forming an LED array having different native LEDs.

[0076] In some embodiments, a plurality of first LED stacks are formed on the substrate surface on a corresponding first part of the substrate (i.e., a plurality of first parts of the LED array, in which the second LED stacks are selectively removed). In some embodiments, a plurality of trenches are formed between the first LED stacks and the second LED stacks covering the plurality of second parts of the substrate surface. That is, in some embodiments, the method according to the first aspect can provide an LED array, which includes a plurality of LEDs configured to output light having a first wavelength, and a plurality of LEDs configured to output light having a second wavelength.

[0077] In some embodiments, the first LED stack is formed by a process at a first temperature, and the second LED stack is formed by a process at a second temperature lower than the first temperature. Thus, the method according to the first aspect can take into account the difference in processing temperatures for forming the first LED stack and the second LED stack. In this way, once the first LED stack is formed, it is subjected to the lower processing temperature for forming the second LED stack, thereby reducing or eliminating any heat-induced effects associated with the processing temperature. For example, the step of forming the first LED stack may include one or more steps of forming a quantum well layer (forming a part of the active layer). Thus, the first temperature for forming the first LED stack may be the first temperature for forming the active layer (or the quantum well layer of the active layer). The second temperature for forming the second LED stack may be the second temperature for forming the second active layer (or the quantum well layer of the second active layer). The second temperature will be a temperature lower than the first temperature.

[0078] In some embodiments, the second wavelength is longer than the first wavelength. That is, according to the method of the present disclosure, LEDs with shorter wavelengths can be formed first, and then LEDs with longer wavelengths can be formed. The LEDs with shorter wavelengths may have a higher processing temperature than the LEDs with longer wavelengths (i.e., the processing temperature of the first LED stack may be higher than the processing temperature of the second LED stack).

[0079] According to some embodiments of the present disclosure, the method includes forming the first LED stack and the second LED stack before performing any selective removal steps. Importantly, the first LED stack and the second LED stack can be formed as continuous layers on a substrate before any patterning (selective removal) steps. Thus, the formation of the first LED stack and the second LED stack can be independent of the geometry of the LED array.

[0080] Therefore, in some embodiments of the first aspect, the second part of the LED array further includes: a second part of the p++ layer, with a second part of the n++ layer provided on the second part of the p++ layer; and a second part of the first LED stack, with a second part of the p++ layer provided on the second part of the first LED stack.

[0081] Thus, the step of selectively removing some of the first LED stacks and some of the second LED stacks includes:

[0082] A first selective removal step, including:

[0083] Selectively masking the second part of the second LED stack; and

[0084] Selectively removing the unmasked part of the second LED stack, wherein the selective removal step terminates at the n++ layer;

[0085] And

[0086] A second selective removal step, comprising:

[0087] selectively masking a first portion and a second portion of the LED array; and

[0088] selectively removing the unmasked portion of the LED array.

[0089] For example, the method according to the first aspect may include:

[0090] (a) forming a first LED stack on a substrate surface of a substrate, the first LED stack including a plurality of group III nitride layers, the plurality of group III nitride layers defining a semiconductor junction configured to output light having a first wavelength, wherein an n-type side of the semiconductor junction is oriented towards the substrate surface;

[0091] (b) forming a p++ layer on the first LED stack, the p++ layer including a group III nitride;

[0092] (c) forming an n++ layer over the substrate to cover the p++ layer, wherein a tunnel junction is formed at an interface between the n++ and p++ layers, the n++ layer including a group III nitride;

[0093] (d) forming a second LED stack on the n++ layer, the second LED stack including a plurality of group III nitride layers, the plurality of group III nitride layers defining a semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein the n-type side of the semiconductor junction is disposed closest to the n++ layer,

[0094] (e) selectively removing portions of the first LED stack and portions of the second LED stack on the substrate surface to define:

[0095] a first portion of the LED array, wherein the second LED stack is selectively removed, and the first portion of the LED array includes:

[0096] a first portion of the first LED stack;

[0097] a first portion of the p++ layer; and

[0098] a first portion of the n++ layer such that the tunnel junction is disposed on the first portion of the first LED stack; and

[0099] a second portion of the LED array, including:

[0100] a second portion of the first LED stack;

[0101] a second portion of the p++ layer;

[0102] a second portion of the n++ layer; and

[0103] The first part of the second LED structure is disposed on the second part of the n++ layer.

[0104] In some embodiments, the first part and the second part of the LED array can be separated from each other by selectively removing portions of the second LED stack, portions of the p++ layer, portions of the n++ layer, and portions of the first LED stack that surround the first part and the second part of the LED array.

[0105] According to a second aspect of the present disclosure, there is provided a light emitting diode (LED) array precursor. The LED array precursor includes a substrate, a first LED stack, a p++ layer, an n++ layer, and a second LED stack. The substrate has a substrate surface. The first LED stack is disposed on a first part of the substrate surface. The first LED stack includes a plurality of first group III nitride layers that define a first semiconductor junction configured to output light having a first wavelength, wherein the n-type side of the first semiconductor junction is oriented towards the substrate surface. The p++ layer is disposed on the first LED stack and includes a group III nitride. The n++ layer has: a first part that covers the p++ layer of the first LED stack (e.g., a first part of the p++ layer of the first LED stack); and a second part that covers a second part of the substrate surface. A tunnel junction is formed at an interface between the n++ layer and the p++ layer. The n++ layer includes a group III nitride. The second LED stack is disposed on the second part of the n++ layer that covers the second part of the substrate surface. The second LED stack includes a plurality of second group III nitride layers that define a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein the n-type side of the semiconductor junction is disposed towards the n++ layer.

[0106] In some embodiments, the second part of the n++ layer is disposed on the second part of the p++ layer, and the second part of the p++ layer is disposed on the second part of the first LED stack, and the first LED stack is disposed on the substrate surface.

[0107] It should be understood that the LED array precursor of the second aspect can be provided by the method according to the first aspect of the present disclosure. Thus, the optional features shown in the first aspect can also be applied to the LED array precursor of the second aspect.

[0108] Regarding the term "precursor" in the LED array precursor, it should be noted that the described LED array precursor does not necessarily include electrical contacts for each LED, such as to allow light emission, nor does it necessarily include associated circuitry. Of course, the LED array precursors of the first and second aspects and the methods of forming them do not exclude the addition of further electrical contacts and associated circuitry. The use of the term precursor in the present disclosure is intended to include the final product (i.e., an LED array, etc.). BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The present disclosure is now described with reference to the following non - limiting drawings. Other advantages of the present disclosure will be apparent from the detailed description when considered in conjunction with the drawings, in which:

[0110] - Figures 1a and 1b show schematic diagrams of a method for forming an LED array precursor by SAG known in the prior art;

[0111] - Figure 2 shows a schematic diagram of an intermediate step of a method according to a first embodiment of the present disclosure;

[0112] - Figure 3 shows a schematic diagram of an intermediate step of a method according to a first embodiment of the present disclosure in a tunnel junction, and a second LED stack is formed on the intermediate structure; Figure 2 above;

[0113] - Figure 4 shows a schematic diagram of an LED array precursor according to an embodiment of the present disclosure;

[0114] - Figure 5 shows a schematic diagram of an LED array according to an embodiment of the present disclosure;

[0115] - Figure 6 shows a schematic diagram of an intermediate step of a method according to a second embodiment of the present disclosure;

[0116] - Figure 7 shows a schematic diagram of an intermediate step of a method according to a second embodiment, in which a first LED stack, a tunnel junction, and a second LED stack are formed on a substrate;

[0117] - Figure 8 shows a schematic diagram of an intermediate step of a method according to a second embodiment, in which the second LED stack is patterned;

[0118] - Figure 9 shows a schematic diagram of an LED array precursor according to an embodiment of the present disclosure;

[0119] - Figure 10 shows a schematic diagram of an LED array precursor including a passivation layer;

[0120] - Figure 11 shows a schematic diagram of an LED array precursor including a passivation layer and a plurality of contact vias;

[0121] - Figure 12 shows a schematic diagram of an LED array precursor including gap - filled contacts;

[0122] - Figure 13Shows a schematic diagram of an LED array precursor including gap-fill contacts and insulating spacers

[0123] - Figure 14 Shows a schematic diagram of an LED array according to an embodiment of the present disclosure;

[0124] - Figure 15 Shows a schematic diagram of an intermediate step of a method in which a strain relaxation layer is provided;

[0125] - Figure 16 Shows a schematic diagram of a further intermediate step of a method in which a strain relaxation layer is provided. Detailed Description

[0126] According to a first embodiment of the present disclosure, a method of forming an LED array precursor is provided. The method of the first embodiment is described below with reference to Figures 2 - 4 to describe the method of the first embodiment.

[0127] As Figure 2 shown, a substrate 10 is provided. The substrate 10 includes a group III nitride. For example, in the embodiment of FIG. 1, the substrate 10 includes a GaN layer. The substrate 10 may be an n-type doped group III nitride. In the embodiment of FIG. 1, the substrate 10 includes n-type doped GaN. The n-type dopant may be any suitable n-type dopant for group III nitrides, such as Si or Ge. The substrate 10 may be n-type doped with a donor density of about 10 17 -10 19 cm -3 .

[0128] In some embodiments, the substrate 10 may be a single layer of GaN. In other embodiments, the substrate 10 may include a layer that includes a group III nitride disposed on a support wafer. For example, in some embodiments, the substrate 10 may include one or more group III nitride layers disposed on a Si, SiC, or sapphire wafer.

[0129] Next, a first LED stack 20 is formed on the surface of the substrate 10. The first LED stack 20 may be formed on most (e.g., the entire surface) of the substrate surface 11. The first LED stack 20 includes a plurality of layers. Each layer of the first LED stack 20 may be formed as a substantially continuous layer. Thus, the first LED stack 20 may be formed as a substantially continuous stack on the substrate surface 11.

[0130] The first LED stack 20 includes a plurality of group III nitride layers such that the first LED stack forms a semiconductor junction configured to output light having a first wavelength. As is known in the art, a semiconductor junction may be a diode having a p-type side and an n-type side. Thus, the plurality of layers of the first LED stack are arranged on top of each other to define the semiconductor junction.

[0131] In Figure 2 the embodiment of Figure 2 , the first LED stack 20 includes a first active layer 21 and a first p-type semiconductor layer 22.

[0132] In some embodiments, the first LED stack may further include one or more of a first n-type semiconductor layer 23 and a first electron blocking layer 24.

[0133] As Figure 2 shown, the first active layer 21 may be formed on the substrate surface 11. The first active layer 21 is configured to generate light of a first wavelength as part of the first LED stack.

[0134] In Figure 2 the embodiment of Figure 2 , the first active layer 21 may include one or more quantum well layers (not shown). Thus, the first active layer 21 may be a multiple quantum well layer. The quantum well layers in the first active layer 21 may include: group III nitride semiconductors, preferably group III nitride alloys containing In. For example, in the embodiment of FIG. 1, the first active layer 21 may include alternating layers of GaN and In X Ga 1-X N, where 0 < X ≤ 1. In particular, in some embodiments, the first active layer 21 may include In X Ga 1-X N layers, where 0 < X ≤ 0.2. Thus, in some embodiments, the first active layer 21 of the LED may be configured to output light having a wavelength of at least 380 nm and not greater than 490 nm. The thickness and In content (X) of the quantum well layers can be controlled to control the wavelength of the light generated by the first active layer 21. The first active layer 21 may be formed as a continuous layer that covers most (e.g., all) of the substrate surface 11. Any suitable process for preparing group III nitride thin films can be used to deposit the first active layer 21, for example, Metal Organic Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

[0135] In some embodiments, the first LED stack 20 may include a first strain relaxation layer 25 disposed between the first active layer 21 and the substrate 10. The strain relaxation layer will be discussed in more detail below with reference to Figure 15 and Figure 16 FIGS. Figure 15 and Figure 16 .

[0136] In some embodiments, before the formation of the first active layer 21, a first n-type semiconductor layer 23 may be deposited on the substrate surface 11. The first n-type semiconductor layer 23 may include group-III nitrides. The first n-type semiconductor layer 23 may be doped with a suitable electron donor, such as Si or Ge. The first n-type semiconductor layer 23 may be formed as a continuous layer that covers most (e.g., all) of the substrate surface 11. The first n-type semiconductor layer 23 may enhance the injection of charge carriers into the first active layer 21 of the first LED.

[0137] Then, on the side of the first active layer 21 opposite to the substrate surface 11, the other layers of the first LED stack 20 may be deposited on the first active layer 21.

[0138] In some embodiments, a first electron blocking layer 24 is disposed on the active layer 21. The first electron blocking layer 24 is disposed on a side of the first active layer 21 that is opposite to the side of the first active layer 21 on which the substrate 10 is disposed. The first electron blocking layer 24 may include group-III nitrides. The first electron blocking layer 24 may be formed as a continuous layer that covers most (e.g., all) of the exposed surface of the active layer 21. The first electron blocking layer 24 is configured to reduce the flow of electrons from the first active layer 21 into the first p-type semiconductor layer 22 of the first LED stack. For example, in some embodiments, the first electron blocking layer 24 may include Al X Ga 1-X N. More details of suitable electron blocking layers can be found at least in APPLIED PHYSICS LETTERS 103, 061104 (2013).

[0139] As Figure 2 shown, a first p-type semiconductor layer 22 is disposed above the first active layer 21. The first p-type semiconductor layer 21 is disposed on a side of the first active layer 21 that is opposite to the side of the first active layer 21 on which the substrate 10 is disposed. The first p-type semiconductor layer 22 includes group-III nitrides. The first p-type semiconductor layer 22 is doped with a suitable electron acceptor, such as Mg. The first p-type semiconductor layer 22 may have an acceptor density (N 19 -10 21 cm -3 ) of about 10 A . The first p-type semiconductor layer 22 may be formed as a continuous layer that covers most (e.g., all) of the exposed surface of the first active layer 22 (or the first electron blocking layer 24, if present).

[0140] In some embodiments, any suitable process for fabricating III-nitride thin films can be used to deposit each layer of the first LED stack 20. For example, Metal Organic Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

[0141] The formation of the first LED stack 20 on the substrate 10 provides a first portion (A) of the LED array in which the first LED will be formed. The first LED can output light having a first wavelength.

[0142] After the formation of the first LED stack 20, a p++ layer 30 is formed on the first LED stack 20. The p++ layer 30 comprises a III-nitride. The p++ layer 30 is a III-nitride layer which, in some embodiments, can be a substantially degenerate p-type semiconductor. For example, the p++ layer 30 can be doped with an acceptor density N A of at least 10 20 cm -3 with any suitable acceptor. For example, in Figure 2 embodiments, the p++ layer comprises GaN doped with Mg having an acceptor density of about 3×10 20 cm -3 . Thus, the p++ layer 30 can have a charge carrier density of at least 10 19 cm -3 . The p++ layer 30 is provided to form a part of the tunnel junction. By forming the tunnel junction over the first LED stack, the Mg-doped layers (i.e., the p-type semiconductor layer 22 and the p++ layer 30) can be substantially protected from the etchant, which can in turn affect the conductivity of the Mg-doped layers.

[0143] As Figure 2 shown, after the formation of the p++ layer 30, a part of the p++ layer and the first LED stack 20 are selectively removed.

[0144] For example, in Figure 2 , the selective removal step is provided by an etching process. In the etching process, a first mask layer (not shown) can be deposited on the exposed surface of the p++ layer 30. The first mask layer is configured to cover a part of the first LED stack 20 and the p++ layer which is intended to form the first portion (A) of the LED array precursor. The first mask layer can define one or more holes which are intended to define at least a second portion (B) of the LED array. Then, the part of the first LED stack 20 and the part of the p++ layer 30 exposed through the holes in the mask layer can be selectively removed using an etchant. As Figure 2As shown, the etchant can etch away portions of the p++ layer 30 and portions of the first LED stack 20 down to the substrate 10. As shown in FIG. 1, the etchant can be etched partially into the thickness of the substrate 10 to ensure removal of the layers of the first LED stack 20. The first mask layer can then be removed from the p++ layer 30.

[0145] Any known method in the art can be used to provide the mask layer. For example, a mask layer can be provided using a photolithography method.

[0146] As Figure 2 shown, the selective removal step can expose the substrate 10 at the second portion B of the LED array. The exposed surface of the substrate 10 in the second portion B of the LED array can be substantially parallel to the substrate surface 11 and each layer of the first LED stack 20.

[0147] A selective removal step is provided to form the second portion B of the LED array, in which the second LED B1 will be provided. The second LED B1 is formed from the second LED stack 50. The second LED B1 can have output light of a (second) wavelength different from that of the first LED stack 20.

[0148] Although in Figure 2 , only a portion of the first LED stack 20 and the p++ layer 30 is shown being removed, it should be understood that in other embodiments, multiple portions can be selectively removed. Thus, the LED array precursor can include multiple second portions B that will provide the second LEDs.

[0149] After the selective removal step, multiple layers are formed over the first portion A and the second portion B of the LED array. Figure 3 An example of an intermediate structure formed after forming the multiple layers over the structure of Figure 2 is shown.

[0150] Thus, as Figure 3 shown, an n++ layer 40 and a second LED stack 50 are formed over the intermediate structure of Figure 2 .

[0151] The n++ layer 40 is first formed on the surface of the p++ layer 30. The n++ layer 40 includes a group III nitride. For example, the n++ layer can be doped with a donor density N D of at least 10 19 cm -3 with any suitable electron donor. For example, in Figure 3 embodiments, the n++ layer 40 includes GaN, and GaN is doped with Si having a donor density of about 3×10 19 cm -3 . Thus, the n++ layer 40 can have a donor density of at least 10 19 cm-3 The charge carrier density. The n++ layer 40 is arranged to combine with the p++ layer 30 to form a tunnel junction, and the n++ layer 40 is disposed on the p++ layer 30. By forming a tunnel junction above the first LED stack, the Mg-doped layer (i.e., the p-type semiconductor layer 22 and the p++ layer 30) is protected from any subsequent etching steps. By forming the tunnel junction, electrical contact with the active layer 21 of the first LED stack 20 can still be made through the tunnel junction. Thus, providing a tunnel junction on the first LED stack 20 enables other LED stacks (i.e., the second LED stack 50) to be formed and patterned on the substrate 10 without damaging the electrical properties of the first LED stack 20.

[0152] As Figure 3 shown, the tunnel junction is formed above the first part A of the LED array. The tunnel junction is not formed on the second part B of the LED array because there is no p++ layer 30 present due to a previous selective removal step.

[0153] As Figure 3 shown, the n++ layer 40 is formed as a substantially continuous layer across the substrate surface 11. At the transition part C between the first part A and the second part B of the LED array, the n++ layer 40 can be inclined with respect to the surface. These transition parts C of the LED array can be removed in subsequent processing steps.

[0154] In some embodiments, the n++ layer 40 may include an etch stop sublayer (not shown). The etch stop sublayer includes a group III nitride. The etch stop sublayer is configured to provide a sublayer of the n++ layer 40 that is more resistant to etching than other materials of the n++ layer 40. Thus, the etch stop layer can provide a surface at which a selective removal process can be terminated. In some embodiments, the etch stop sublayer may include Al Z Ga 1-Z N, where 0 < Z ≤ 1. More details of suitable etch stop sublayers can be found at least in Jpn. J. Appl. Phys. Vol. 42 (2003) pp. L 1139 - L 1141.

[0155] For example, in some embodiments, the n++ layer 40 may include an etch stop sublayer disposed between n++ sublayers. The n++ sublayers may have substantially the same composition as the n++ layer 40 described above.

[0156] In some embodiments, one or more surface treatment processes may be performed on the p++ layer before the formation of the n++ layer. For example, an annealing step may be performed on the p++ layer before the formation of the n++ layer. The annealing step may be set to enhance the activation of acceptor ions (such as Mg ions) in the p++ layer. A surface treatment process may be performed on the p++ layer, in which the p++ layer is exposed to BHF. The BHF treatment may counteract the concentration of acceptor ions formed near the surface of the p++ layer, on which the n++ layer will be formed. By applying one or more surface treatment processes to the p++ layer, the resistance of the tunnel junction formed between the n++ layer and the p++ layer can be reduced. Thus, the deposition of the p++ layer and the n++ layer may be performed in two different deposition steps separated by an in-situ surface treatment step. This method may reduce or prevent the diffusion of acceptor ions (such as Mg) from the p++ layer to the n++ layer. More details of suitable surface treatment processes can be found at least in SeungGeun Lee et al 2018 Appl. Phys. Express 11 062703.

[0157] After the n++ layer 40 is formed, a second LED stack 50 may be disposed on the n++ layer 40. In Figure 3 it, the second LED stack 50 is disposed on such a side of the n++ layer 40 that is opposite to the side of the n++ layer 40 on which the p++ layer 30 is disposed. The second LED stack 50 may be formed on most (such as all) of the n++ layer 40. The second LED stack 50 includes multiple layers. Each layer of the second LED stack 50 may be formed as a substantially continuous layer. Thus, the second LED stack 50 may be formed as a substantially continuous stack.

[0158] The second LED stack 50 includes multiple group III nitride layers such that the second LED stack 50 forms a semiconductor junction configured to output light having a second wavelength. As is known in the art, a semiconductor junction may be a diode having a p-type side and an n-type side. Thus, the multiple layers of the second LED stack 50 are arranged on top of each other to define the semiconductor junction. The n-type side of the second LED stack 50 is disposed toward the substrate 10, and the p-type side of the second LED stack 50 is disposed on the opposite side. Thus, the second LED stack defines the semiconductor junction in the same direction as the semiconductor junction of the first LED stack 20.

[0159] In Figure 3 embodiments, the second LED stack 50 includes a second active layer 51 and a second p-type semiconductor layer 52.

[0160] In some embodiments, the second LED stack 50 may further include one or more of a second n-type semiconductor layer 53 and a second electron blocking layer 54. Thus, the second LED stack may have a structure similar to that of the first LED stack 10.

[0161] As shown Figure 3 in FIG. 4, a second active layer 51 can be formed on the exposed surface of the n++ layer 40. The second active layer 51 is configured to generate light of a second wavelength as part of a second LED stack.

[0162] In Figure 3 an embodiment, the second active layer 51 can include one or more quantum well layers (not shown). Thus, the second active layer 51 can be a multiple quantum well layer. The quantum well layers within the second active layer 51 can include: group III nitride semiconductors, preferably group III nitride alloys containing In. Thus, the second active layer 51 can have a general structure similar to that of the first active layer 21 of the first LED stack 20. For example, in Figure 3 an embodiment, the second active layer 21 can include alternating layers of GaN and In X2 Ga 1-X2 GaN, where 0 < X2 ≤ 1. In particular, in some embodiments, a second active layer can be provided such that the second wavelength is longer than the first wavelength. Thus, in some embodiments, the second active layer can include In X2 Ga 1-X2 GaN layers, where the In content (X2) of the layers is greater than the In content (X1) of the corresponding layers of the first active layer 21. For example, in some embodiments, the second active layer can include In X2 Ga 1-X2 GaN layers, where 0 < X2 ≤ 0.5 or 0.2 ≤ X2 ≤ 0.5.

[0163] Thus, the second active layer 51 can be configured to output light having a wavelength of at least 490 nm. In some embodiments, the second active layer 51 can be configured to output substantially green light having a wavelength in the range of 510 nm to 580 nm. The thickness and In content (X2) of the quantum well layers can be controlled to control the wavelength of the light generated by the second active layer 51. The second active layer 51 can be formed as a continuous layer that covers most (e.g., all) of the n++ layer 40. Any suitable process for preparing group III nitride thin films can be used to deposit the second active layer 51, for example, Metal Organic Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

[0164] In some embodiments, the second LED stack 50 can include a second strain relaxation layer 55. Further discussion of the first and second strain relaxation layers 25, 55 is provided below with reference to Figure 15 and Figure 16 FIGS. 5 and 6.

[0165] In some embodiments, before the formation of the second active layer 51, a second n-type semiconductor layer 53 may be deposited on the n++ layer 40. The second n-type semiconductor layer 53 may include a Group III nitride. The second n-type semiconductor layer 53 may be doped with a suitable electron donor, such as Si or Ge. The second n-type semiconductor layer 53 may be formed as a continuous layer that covers most (e.g., all) of the n+ layer 40. The second n-type semiconductor layer 53 may enhance the injection of charge carriers into the second active layer 51 of the LED precursor.

[0166] Then, on the side of the second active layer 51 opposite to the n++ layer 40, the other layers of the second LED stack 50 may be deposited on the second active layer 51.

[0167] Similar to the first LED stack, in some embodiments, a second electron blocking layer 54 may be provided on the second active layer 51. The electron blocking layer 54 may be provided on the side of the second active layer 51 that is opposite to the side of the second active layer 51 where the n++ layer 40 is provided. The second electron blocking layer 54 may be provided in a manner similar to the first electron blocking layer 24.

[0168] As Figure 3 shown, a second p-type semiconductor layer 52 is provided on the second active layer 51. The second p-type semiconductor layer 51 is provided on the side of the second active layer 51 that is opposite to the side of the active layer 51 where the n++ layer 40 is provided. The second p-type semiconductor layer 52 may be provided in a manner similar to the first p-type semiconductor layer 22 discussed above.

[0169] In some embodiments, any suitable process for fabricating Group III nitride thin films may be used to deposit each layer of the second LED stack 50, for example, Metal Organic Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

[0170] After the second LED stack 50 is formed, the second LED stack 50 may be patterned to define a first portion A and a second portion B of the LED array.

[0171] According to a first embodiment of the present disclosure, a first portion of the second LED stack 50 formed on the first portion A of the LED array can be selectively removed, while a second portion of the second LED stack 50 formed on the second portion B of the LED array is retained (i.e., not selectively removed). The first portion of the second LED stack 50 can be selectively removed by an etching process similar to the process used to pattern the first LED stack 20 described above. Importantly, the process of selectively removing the second LED stack can terminate on the n++ layer 40 disposed below the second LED stack. Thus, selective removal of the second LED stack 50 can be performed, for example, by etching, without compromising the electrical performance of the first LED stack 20, particularly the electrical performance of any Mg-doped (i.e., p-type) layer in the first LED stack 20.

[0172] Figure 4 An example of an LED array precursor formed by the above method is shown. As Figure 4 shown, the LED array precursor includes a first portion A of the LED array in which the second LED stack 50 has been selectively removed. The first portion A of the LED array includes a first portion 20a of the first LED stack, a first portion 30a of the p++ layer, and a first portion 40a of the n++ layer, such that a tunnel junction is disposed on the first portion of the first LED stack. The LED array precursor further includes a second portion B, which includes a second portion 40b of the n++ layer and a first portion 50b of the second LED stack disposed on the second portion 40b of the n++ layer.

[0173] Thus, the method of forming the LED array precursor can provide an array having different regions (for forming LEDs having different wavelengths). In this way, the LED array precursor formed by the method of the first embodiment has a first portion in which one or more LEDs of a first wavelength (e.g., blue light) can be formed. The LED array precursor also has one or more second portions in which LEDs of a second wavelength (e.g., green or red) can be formed.

[0174] As Figure 4 shown, the LED array precursor can be further processed to separate the first LED array portion and the second LED array portion from each other. Thus, the method can further include forming a trench between the first portion of the LED array and the second portion of the LED array by selectively removing layers of the first LED stack and layers of the second LED stack to expose sidewall surfaces of the first LED stack and sidewall surfaces of the second LED stack. In this way, the transition portion C between the first portion A and the second portion B of the LED array can be removed by a selective removal process, such as an etching process.

[0175] Further processing steps can be performed on the LED array 1 to provide an LED array.Figure 5 It shows from Figure 4 An example of an LED array formed by an LED precursor.

[0176] exist Figure 5 In the embodiment of FIG. 4 , a first portion A of the LED array precursor has been processed to provide a first LED A1 , and a second portion of the LED array precursor has been processed to provide a second LED B1 .

[0177] The LED array has been formed by depositing a passivation layer 60 over the first portion A and the second portion B. Figure 5 The first LED and the second LED. The passivation layer 60 may be an electrical insulator. The passivation layer 60 may, for example, include SiO2.

[0178] Contact vias 71, 72, 73, 74, 75, 76 comprising metal have been formed through the passivation layer 60 to provide suitable electrical contacts with the respective p-side and n-side of each LED. Each of the first contact vias 71, 72, 73, 74 can be configured to make contact with the n-type side of the semiconductor junction. For example, each of the first contact vias 71, 72, 73, 74 is a cathode contact and can include Ti, Al, or a Ti and Al metal stack Ti / Al. A second contact via 75 is provided to make electrical contact with the p-side of the first LED A1. Due to the presence of the tunnel junction in the first LED A1, the second contact via is in direct electrical contact with the n++ layer 40, and the second contact via is an anode contact for the LED A1. Thus, the second contact via 75 can include Ti, Al, or a Ti and Al metal stack. In some embodiments, the second contact via 75 can be formed in the same deposition step as the first contact vias 71, 72, 73, 74. The third contact via 76 is provided to make electrical contact with the p-side of the second LED B1. Since there is no tunnel junction in the second LED B1, the third contact via 76 is in direct electrical contact with the second p-type semiconductor layer 52. Thus, the third contact via may include a suitable metal to form an ohmic contact with p-type GaN (e.g., Ni / Ag).

[0179] like Figure 5 As shown, Figure 4 The LED array precursor may then be bonded to the backplane electronic substrate 100. The backplane electronic substrate 100 may include contact surfaces and control electronics configured to provide power to the first LED A1 and the second LED B1. A gap-filling contact layer 110 may be deposited over the LED array precursor to provide electrical contact between the contact vias 71, 72, 73, 74, 75, 76 and the backplane electronic substrate 100.

[0180] like Figure 5As shown, a further selective removal step may be performed on the substrate 10 to pattern the light-emitting surfaces 12a, 12b of the substrate 10. The light-emitting surfaces 12a, 12b may be disposed on a side of the substrate 10 opposite to the respective active layers 21, 51 of the first LED A1 and the second LED B1. One or more convex lens structures 13a, 13b may be formed in the light-emitting surfaces 12a, 12b of the substrate by selective removal. As shown in FIG. g, each of the first LED A1 and the second LED B1 has three convex lens structures 13a, 13b formed therein. The convex lens structures may increase the light extraction efficiency of the LED. In other embodiments, the light-emitting surface may be shaped such that the randomness of the direction of photons emitted from the light-emitting surfaces 12a, 12b is increased. For example, in some embodiments, the surface roughness of the light-emitting surface may be increased. Thus, an LED array may be provided according to the above method.

[0181] Next, a method of forming the LED array precursor 1 will be described according to a second embodiment of the present disclosure. Refer to Figures 6 - 9 to describe the method of the second embodiment.

[0182] As Figure 6 shown, a first LED stack 20 is formed on the substrate surface of the substrate 10. The substrate 10 and the first LED stack 20 may be formed substantially as described above according to the method of the first embodiment.

[0183] Next, a p++ layer 30 is formed on the first LED stack. The p++ layer is formed on a side of the first LED stack 20 opposite to the side on which the substrate 10 is disposed. The p++ layer 30 may be formed substantially as described above according to the method of the first embodiment. Thus, an intermediate structure as Figure 6 shown may be formed according to the method of the second embodiment. In Figure 6 , each of the substrate 10, the first LED stack 20, and the p++ layer 30 is provided as a continuous layer, which are formed monolithically with each other.

[0184] Next, as Figure 7 shown, an n++ layer 40 is formed on the p++ layer 30. The n++ layer 40 is formed on the p++ layer 30 such that a tunnel junction is formed at the interface between the two layers. The n++ layer 40 may be similar to the n++ layer 40 of the first embodiment. Compared with the method of the first embodiment, in the method of the second embodiment, the n++ layer 40 is formed on the p++ layer 30 before the selective removal step. That is, the n++ layer 40 is formed on substantially the entire p++ layer 30, including the first portion 30a of the p++ layer and the second portion 30b of the p++ layer that form the respective first part A and second part B of the LED array.

[0185] AsFigure 7 As shown, a second LED stack 50 is then formed on the n++ layer 40. The second LED stack 50 can be formed in a manner similar to that of the second LED stack 50 of the first embodiment. Compared with the method of the first embodiment, in the method of the second embodiment, the second LED stack 50 is formed on the n++ layer 40 before the selective removal step. Thus, an intermediate structure can be formed. Figure 7 As Figure 7 shown, each layer forming the intermediate structure is provided as a continuous layer, which is formed monolithically with each other.

[0186] According to the method of the second embodiment, all layers of the first LED stack 20 and the second LED stack 50 can be formed on the substrate 10 without any intervening patterning steps. In this way, the method of the second embodiment allows the layers of the first LED stack 20 and the second LED stack 50 to be formed independently of the geometry or layout of the LED array. Importantly, the layers of the second LED stack 50 can be formed on a surface on which a selective removal step (such as etching) may not have been performed yet. Such a selective removal step may introduce surface damage to the surface on which the second LED stack is formed, which in turn can affect the electrical and / or mechanical properties of the second LED stack 50. Thus, compared with a process in which a selective removal step is performed before forming the second LED stack 50, the resulting layers of the second LED stack 50 in the second embodiment can be formed to have improved electrical properties.

[0187] Next, a selective removal process is used to pattern the Figure 7 intermediate structure. In the second embodiment of the method, the selective removal process initially removes a portion of the second LED stack 50, which includes a first portion of the second LED stack, while a second portion 50b of the second LED stack is not selectively removed. The selective removal step can be performed using an etching process as described above. As Figure 8 shown, the etching process can terminate on the n++ layer 40 of the tunnel junction. Thus, the provision of the tunnel junction allows the etching process to be performed and the etching process not to terminate on a layer including Mg doping (such as the p++ layer 30), while also allowing electrical contact with the first LED stack through the tunnel junction. Terminating the selective removal process on the n++ layer 40 also allows electrical contact with the n-side of the second portion 50b of the second LED stack.

[0188] The selective removal step provides a second portion B of the LED array, where the second portion 50b of the second LED stack is disposed on the tunnel junction (n++ layer 40 and p++ layer 30), the first LED stack 20, and the substrate 10. The second portion 50b of the second LED stack forms a mesa structure relative to the surface of the tunnel junction surrounding the second LED stack 50b. That is, the second portion 50b of the second LED stack extends from the surface formed by the n++ layer 40.

[0189] Figure 9 shows a LED array precursor formed by the method of the second embodiment. After the formation of the intermediate structure in Figure 8 , the structure undergoes a further selective removal step to define the first LED A and the second LED B of the LED array precursor.

[0190] As Figure 9 shown, a further selective removal step is performed, in which parts of the first LED stack 20 and parts of the tunnel junction (n++ layer 40 and p++ layer 30) are selectively removed. For example, as Figure 9 shown, parts of the first LED stack 20 and parts of the tunnel junction are selectively removed around the first part of the first LED stack 20 and the first part of the tunnel junction (n++ layer 40 and p++ layer 30) to form the first LED A. Thus, the method according to the second embodiment provides the first part A of the LED array, in which the second LED stack is selectively removed in the first part A of the LED array. The first part A of the LED array includes the first part 20a of the first LED stack, the first part 30a of the p++ layer, and the first part 40a of the n++ layer, such that a tunnel junction is disposed on the first part 20a of the first LED stack.

[0191] Parts of the first LED stack 20 and parts of the tunnel junction are selectively removed around the second part 50b of the second LED stack to form the second LED B. Thus, the method of the second embodiment provides the second part B of the LED array. The second part B of the LED array includes the second part 40b of the n++ layer and the second part 50b of the second LED structure disposed on the second part 40b of the n++ layer. As Figure 9 shown, the second part 40b of the n++ layer and the second part 50b of the second LED stack are disposed on the second part 30b of the p++ layer and the second part 20b of the first LED stack, and the second part 30b of the p++ layer is disposed on the second part 20b of the first LED stack.

[0192] As Figure 9As shown, the selective removal process can retain the contact portions 30c, 40c of the tunnel junction adjacent to the second portion (second LED) B of the LED array and the contact portion 20c of the first LED stack. The n++ layer, p++ layer, and the contact portions 20c, 30c, 40c of the first LED stack can surround the second portion B of the LED array. The contact portions 20c, 30c, 40c provide such a surface 20c of the n++ layer that is in direct electrical contact with the second portion 40b of the n++ layer. Thus, the n++ layers 40b, 40c allow electrical contact with the n-side of the semiconductor junction of the second LED stack 50b. The second portion of the second p-type semiconductor layer can be used for electrical contact with the p-side of the semiconductor junction of the second LED stack 50b.

[0193] Figure 10 and Figure 11 shows further processing steps of the LED array precursor 1 that can be performed in some embodiments of the present disclosure to form one or more contact vias to the LEDs A, B of the array.

[0194] Similar to Figure 5 the LEDs, the LED array precursor in Figure 10 is further processed by forming a passivation layer 60 on the first portion A and the second portion B of the LED array. As Figure 10 shown, the passivation layer 60 also covers the contact portion C of the LED array. The passivation layer 60 can be an electrical insulator. The passivation layer 60 can include, for example, SiO2.

[0195] Contact vias 71, 72, 73, 74, 75, 76 including metal have been formed through the passivation layer 60 to provide suitable electrical contact with the respective p- and n-sides of each LED. For example, as Figure 10As shown, first contact vias 73, 74 are provided to contact the n-side of the first LED A1 through the substrate 10. Each of the first contact vias 73, 74 may be configured to contact the n-type side of the semiconductor junction. For example, each of the first contact vias 73, 74 may include: aluminum (Al), or a double-layer electrical contact including a Ti layer and an Al layer. A second contact via 75 is provided for electrical contact with the p-side of the first LED A1. Due to the presence of the tunnel junction in the first LED A1, the second contact via 75 is in direct electrical contact with the n++ layer 40. Thus, the second contact via may include a suitable metal configured to form an ohmic contact with the n++ layer 40, such as the second contact via 75 including a Ti and / or Al layer. A third contact via 76 is provided for electrical contact with the p-side of the second LED B1. Since there is no tunnel junction in the second LED B1, the third contact via 76 is in direct electrical contact with the second p-type semiconductor layer 52. Thus, the third contact via 76 may be configured to form an ohmic contact with the p-type layer. For example, the third contact via 76 may be a double-layer electrical contact including: a Ni layer and an Au layer; a Ni layer and an Ag layer. In some embodiments, the third contact 76 may include an indium tin oxide layer. Fourth contact vias 71, 72 are provided to contact the n-side of the second LED B1 through the n++ layer 40 of the tunnel junction. Each of the fourth contact vias 71, 72 may be configured to contact the n-type side of the semiconductor junction. For example, each of the first contact vias 71, 72 may include: Al, or a double-layer electrical contact including a Ti layer and an Al layer.

[0196] In some embodiments, after the formation of the contact vias, the LED array precursor may be bonded to the backplane electronic substrate 100. Figures 12 - 14 A schematic diagram showing the formation of an LED array incorporated with a backplane electronic substrate 100 is shown.

[0197] In Figure 12 a gap-fill contact layer 110 is formed on the LED array precursor. For example, in Figure 12 the gap-fill contact layer is disposed above the LED array precursor including the Figure 11 contact vias. The gap-fill contact layer includes Al, Cu, or Au. The gap-fill contact layer may be deposited by thermal or electron beam evaporation. Subsequently, the upper surface may be planarized (smoothed) by a chemical mechanical polishing process. Alternatively, the Cu gap-fill contacts may also be electroplated directly in a pillar form.

[0198] In Figure 13In this case, a portion of the gap-fill contact layer is selectively removed and replaced with an insulating spacer 120. The insulating spacer 120 is configured to electrically isolate the p-side electrical contacts and the n-side electrical contacts to each of the LEDs A1, B1 from each other. In this way, an insulating spacer can be provided to surround the p-side contacts (i.e., the second and third contact vias 75, 76) of each LED. The n-side contacts (i.e., the first and fourth contact vias 71, 72, 73, 74) can be provided with a common contact (common cathode contact). The insulating spacer may include an electrically insulating material. For example, the insulating spacer may include the same material as the passivation layer 60. In Figure 13 the embodiment, the insulating spacer includes SiO2.

[0199] In Figure 14 this case, Figure 13 the LED array can be bonded to a backplane electronic substrate 100. The backplane electronic substrate 100 may include a contact surface and control electronics, which are configured to supply power to the first and second LEDs A1, B1. The gap-fill contact layer 110 provides electrical contact between the contact vias 71, 72, 73, 74, 75, 76 and the backplane electronic substrate 100.

[0200] As Figure 14 shown, a further selective removal step can also be performed on the substrate 10 in order to pattern the light-emitting surfaces 12a, 12b of the substrate 10. The light-emitting surfaces 12a, 12b can be provided on a side of the substrate 10 opposite to the respective active layers 21, 51 of the first LED A1 and the second LED B1. The light-emitting surfaces 12a, 12b of the substrate can be formed with one or more convex lens structures 13a, 13b therein by selective removal. As Figure 14 shown, each of the first LED A1 and the second LED B1 has three convex lens structures 13a, 13b formed therein. The convex lens structures can increase the light extraction efficiency of the LEDs.

[0201] In Figure 14 the embodiment, the substrate 10 can also undergo a selective removal step to separate the portion of the substrate 10a provided with the first LED A1 from the portion of the substrate 10b provided with the second LED B1.

[0202] In some embodiments of the present disclosure, the first active layer 22 and / or the second active layer 52 may be formed on a corresponding first strain relaxation layer 25 or second strain relaxation layer 55. In this way, the first strain relaxation layer may be disposed between the first active layer 22 and the substrate 10. The second strain relaxation layer 55 may be disposed between the second active layer 52 and the n++ layer 40. The first strain relaxation layer 25 may be formed as part of the first LED stack 20. The second strain relaxation layer may be formed as part of the second LED stack 50. The strain relaxation layers 22, 52 may be provided to reduce the lattice mismatch between the in-plane lattice constant of the active layers 22, 52 and the in-plane lattice constant of the structure on which the corresponding LED stacks 20, 50 are formed. In particular, the strain relaxation layers 22, 52 may be provided in the case where the active layer is configured to generate light having a relatively long wavelength (e.g., a wavelength exceeding 490 nm).

[0203] As Figure 15 shown, the first strain relaxation layer 25 may be formed on the substrate surface 11. The first strain relaxation layer 25 may include a group III nitride. The first strain relaxation layer 25 includes a first strain relaxation surface 26 on a side of the first strain relaxation layer 25 opposite to the substrate 10.

[0204] Thus, an LED array precursor may be provided according to the embodiments discussed above. The LED array precursor provides a plurality of native LEDs formed monolithically on a substrate. In this way, the method of the present disclosure provides a method of forming a plurality of native LEDs of different colors monolithically on a substrate 10.

Claims

1. A method of forming a precursor of an LED array, comprising: forming a first LED stack on a substrate surface of a substrate, the first LED stack including a plurality of first group III nitride layers, the plurality of first group III nitride layers defining a first semiconductor junction configured to output light having a first wavelength, wherein an n-type side of the semiconductor junction is oriented toward the substrate surface; forming a p++ layer on the first LED stack, the p++ layer including a group III nitride; selectively removing a portion of the first LED stack; forming an n++ layer over the substrate to cover the p++ layer, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, the n++ layer including a group III nitride; wherein the n++ layer is formed over the substrate surface such that a first portion of the n++ layer covers a first portion of the first LED stack disposed on a first portion of the substrate surface, and a second portion of the n++ layer covers a second portion of the substrate, wherein the first LED stack on the second portion of the substrate is selectively removed; forming a second LED stack on the n++ layer, the second LED stack including a plurality of second group III nitride layers, the plurality of second group III nitride layers defining a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein an n-type side of the semiconductor junction is disposed closest to the n++ layer; wherein the method further comprises the step of: selectively removing a portion of the second LED stack on the substrate surface to define: a first portion of the LED array, wherein the second LED stack is selectively removed, the first portion of the LED array comprising: a first portion of the first LED stack; a first portion of the p++ layer; and a first portion of the n++ layer such that the tunnel junction is disposed on the first portion of the first LED stack; and a second portion of the LED array, comprising: a second portion of the n++ layer; and a first portion of the second LED stack disposed on the second portion of the n++ layer.

2. The method according to claim 1, wherein the plurality of first group III nitride layers of the first LED stack includes: a first n-type layer disposed on the substrate surface; a first active layer configured to be disposed on the first n-type layer to generate light having the first wavelength; and a first p-type layer disposed on the first active layer, and / or the plurality of group III nitride layers of the second LED stack includes: a second n-type layer disposed on the n++ layer; a second active layer configured to be disposed on the second n-type layer to generate light having a second wavelength, wherein the second wavelength is different from the first wavelength; and a second p-type layer disposed on the second active layer.

3. The method according to claim 2, wherein the first active layer of the first LED stack includes a first multi-quantum well stack configured to output light having the first wavelength; and The second active layer of the second LED stack includes a second multi-quantum well stack configured to output light of the second wavelength.

4. The method according to claim 3, wherein The first multi-quantum well stack includes alternating layers of GaN and In X Ga 1-X N, where 0 < X ≤ 1; The second multi-quantum well stack includes alternating layers of GaN and In Y Ga 1-Y N, where 0 < Y ≤ 1.

5. The method according to any one of claims 2 to 4, wherein the first LED stack includes a first electron blocking layer between the first active layer and the first p-type layer; and / or the second LED stack includes a second electron blocking layer between the second active layer and the second p-type layer.

6. The method according to any one of claims 1 to 4, further comprising selectively removing portions of the first LED stack and portions of the second LED stack to expose sidewall surfaces of the first LED stack and sidewall surfaces of the second LED stack, so as to define a trench between a first portion of the LED array and a second portion of the LED array; and depositing a passivation layer in the trench to cover the sidewall surfaces of the first LED stack and the sidewall surfaces of the second LED stack.

7. The method according to any one of claims 1 to 4, wherein the first LED stack is formed by a process at a first temperature; and the second LED stack is formed by a process at a second temperature lower than the first temperature.

8. The method according to any one of claims 1 to 4, wherein, The second wavelength is longer than the first wavelength.

9. The method according to any one of claims 1 to 4, wherein The step of selectively removing portions of the first LED stack includes: selectively depositing a mask layer on portions of the first LED stack covering a second portion of the substrate surface; and etching the exposed portions of the first LED stack to expose a second portion of the underlying substrate surface.

10. The method according to any one of claims 1 to 4, wherein the first wavelength is at least 380 nm and not greater than 480 nm; and / or the second wavelength is at least 500 nm and not greater than 580 nm.

11. The method according to any one of claims 1 to 4, wherein Each portion of the LED array has a surface size of less than 100 μm × 100 μm on the substrate.

12. The method according to any one of claims 1 to 4, wherein The n++ layer has a charge carrier density of at least 10 19 cm -3 ; and / or The p++ layer has a charge carrier density of at least 10 19 cm -3 .

13. The method according to any one of claims 1 to 4, wherein Forming the n++ layer over the substrate to cover the p++ layer includes: forming an etch stop sub-layer within the n++ layer, the etch stop sub-layer including a group III nitride containing Al.

14. The method according to any one of claims 1 to 4, further comprising: forming a first contact layer for a first portion of the LED array on a first portion of the n++ layer covering the first LED stack, and / or forming a second contact layer for a second portion of the LED array on a first portion of the second LED stack.

15. The method according to claim 14, wherein the first contact layer includes one or more of Ti, Al, and Mo; and the second contact layer includes one or more of Ni, Pt, Au, and indium tin oxide (ITO).

16. The method according to any one of claims 1 to 4, wherein selectively removing a second portion of the p++ layer together with a second portion of the first LED stack to expose a second portion of the substrate surface.

17. The method according to any one of claims 1 to 4, wherein before forming the p++ layer, a second part of the first LED stack is selectively removed to expose a second part of the substrate surface.

18. A light-emitting diode (LED) array precursor, comprising: a substrate having a substrate surface; a first LED stack disposed on a first part of the substrate surface, the first LED stack including a plurality of first group III nitride layers that define a first semiconductor junction configured to output light having a first wavelength, wherein an n-type side of the first semiconductor junction is oriented towards the substrate surface; a p++ layer disposed on the first LED stack, the p++ layer including a group III nitride; an n++ layer having: a first part that covers the p++ layer on the first LED stack; and a second part that covers a second part of the substrate surface, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, and the n++ layer includes a group III nitride; and a second LED stack disposed on the second part of the n++ layer that covers the second part of the substrate surface, the second LED stack including a plurality of second group III nitride layers that define a second semiconductor junction configured to output light having a second wavelength different from the first wavelength, wherein an n-type side of the semiconductor junction is disposed towards the n++ layer; wherein the first part of the n++ layer is disposed on the first part of the substrate surface, and the second part of the n++ layer is directly disposed on a part of the substrate surface.

19. The light-emitting diode (LED) array precursor according to claim 18, wherein the plurality of first group III nitride layers of the first LED stack include: a first n-type layer disposed on the substrate surface; a first active layer configured to be disposed on the first n-type layer to generate light having a first wavelength; and a first p-type layer disposed on the first active layer; a second n-type layer disposed on the n++ layer; the plurality of second group III nitride layers of the second LED stack include: a second n-type layer disposed on the n++ layer; a second active layer configured to be disposed on the second n-type layer to generate light having the second wavelength; and a second p-type layer disposed on the second active layer.

20. The light-emitting diode (LED) array precursor according to claim 18 or 19, wherein a trench is provided between the first LED stack covering the first part of the substrate surface and the second LED stack covering the second part of the substrate, the trench being defined by sidewall surfaces of the first LED stack and sidewall surfaces of the second LED stack; and a passivation layer is provided in the trench to cover the sidewall surfaces of the first LED stack and the sidewall surfaces of the second LED stack.

21. The light-emitting diode (LED) array precursor according to claim 18 or 19, further comprising A first contact layer disposed on a first portion of the n++ layer covering the first LED stack; and / or a second contact layer disposed on the second LED stack.

22. The light-emitting diode (LED) array precursor according to claim 21, wherein the first contact layer comprises one or more of Ti, Al, and Mo; and the second contact layer comprises one or more of Ni, Pt, Au, and indium tin oxide (ITO).

23. The light-emitting diode (LED) array precursor according to claim 21, wherein a first adhesion layer is disposed between a second n-type layer covering the first LED stack and the first contact layer, and / or a second adhesion layer is disposed between the second contact layer disposed and a second p-type layer of the second LED stack.

24. The light emitting diode (LED) array precursor according to claim 18 or 19, wherein, An etch stop sublayer is formed within the n++ layer, the etch stop sublayer comprising a group III nitride containing Al.

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