Parallel CRC Implementation on Image Processing Unit

Abstract

Devices, systems and techniques for calculating cyclic redundancy checks use a graphics processing unit (GPU) to calculate cyclic redundancy checks. For example, in at least one embodiment, according to various new techniques described herein, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value of the input data sequence.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 16 / 559,424, filed on September 3, 2019, entitled “PERFORMING CYCLIC REDUNDANCY CHECKS USING PARALLEL COMPUTING ARCHITECTURES,” the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to at least one embodiment for computing cyclic redundancy checks, and more particularly, at least one embodiment relates to computing cyclic redundancy check values ​​using a parallel computing architecture for wireless communications and processing. Background Art

[0004] A cyclic redundancy check is performed to make bit errors detectable and to detect bit errors. In many communications applications, checking, detecting and / or correcting errors requires a significant amount of time, especially for current and future applications that rely on improving communications speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 illustrates data reception at a physical layer (PHY) of a mobile device network in accordance with one or more embodiments;

[0006] Figure 2 Elements of a GPU-based CRC processing unit that may be used in a GPU-based cyclic redundancy checker are shown according to one or more embodiments;

[0007] Figure 3 illustrates the operation of a CRC thread according to one or more embodiments;

[0008] Figure 4 illustrates block-level operations for combining and reducing thread outputs in parallel according to one or more embodiments;

[0009] Figure 5 illustrates block-level operations for combining and reducing thread block outputs in parallel according to one or more embodiments;

[0010] Figure 6 A process of checking a CRC value according to one or more embodiments is shown;

[0011] Fig. 7A Inference and / or training logic according to at least one embodiment is shown;

[0012] Figure 7B Inference and / or training logic according to at least one embodiment is shown;

[0013] Figure 8 An example data center system is shown in accordance with at least one embodiment;

[0014] Fig. 9A An example of an autonomous vehicle according to at least one embodiment is shown;

[0015] Fig. 9B A method for Fig. 9A Examples of camera positions and fields of view for autonomous vehicles;

[0016] Fig. 9C is a diagram showing a method for Fig. 9A A block diagram of an example system architecture for an autonomous vehicle;

[0017] Fig.9D is a diagram illustrating a method for performing a multi-threaded operation on a cloud-based server and a Fig. 9A A diagram of a system for communicating between autonomous vehicles;

[0018] Fig.10 is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Fig.11 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Fig.12 A computer system according to at least one embodiment is shown;

[0021] Fig.13 A computer system according to at least one embodiment is shown;

[0022] Fig.14 An exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to at least one embodiment are shown;

[0023] Fig.15A A computer system according to at least one embodiment is shown;

[0024] Fig. 15B A computer system according to at least one embodiment is shown;

[0025] Fig. 15C A computer system according to at least one embodiment is shown;

[0026] Fig.15D A computer system according to at least one embodiment is shown;

[0027] Fig.15E A computer system according to at least one embodiment is shown;

[0028] Fig.15F A computer system according to at least one embodiment is shown;

[0029] Fig.16A and 16B An exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to at least one embodiment are shown;

[0030] Fig.17A and 17B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Fig.18 A computer system according to at least one embodiment is shown;

[0032] Fig.19A illustrates a parallel processor according to at least one embodiment;

[0033] Fig.19B shows a partition unit according to at least one embodiment;

[0034] Fig.19C illustrates a processing cluster according to at least one embodiment;

[0035] Fig.19D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Fig. 20 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Fig.21 A graphics processor according to at least one embodiment is shown;

[0038] Fig. 22 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Fig.23 A deep learning application processor according to at least one embodiment is shown;

[0040] Fig.24 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Fig.25 and 26 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0042] Fig. 27is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0043] Fig.28A and 28B illustrates thread execution logic according to at least one embodiment;

[0044] Fig.29 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0045] Fig.30 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0046] Fig.31 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment; and

[0047] Fig.32 A streaming multiprocessor in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0048] In at least one embodiment, error correction and detection are useful in communications where errors may occur in the data being transmitted. In at least one embodiment, adding a cyclic redundancy check (CRC) value to the data being transmitted can allow a receiver to verify whether the data was received correctly, and if not, to recover from such errors in some cases. For example, in at least one embodiment, CRC is used for Internet Protocol data packets transmitted over the Internet and for transport blocks and code blocks in communications conforming to various protocols, such as those used with mobile device networks known as "LTE" or "5G". In at least one embodiment, in communications on mobile device networks including voice and streaming media, it is important to detect and correct errors soon after the signal is received.

[0049] In at least one embodiment, a particular CRC has an associated generator polynomial P(x), and the CRC value of the protected data is a function of the data and the generator polynomial. In at least one embodiment, if the input data is a binary sequence, it can represent a binary polynomial with coefficients in a Galois Field of characteristic 2 ("GF2"), and the CRC value of the input data will be the remainder of the binary polynomial divided by its generator polynomial P(x). In at least one embodiment, the CRC value can be calculated in a serial process, which may be slow. In at least one embodiment, an example representation of an input binary sequence is shown in Equation 1, and an example representation of a CRC value of the input binary sequence is shown in Equation 2, where f is the order of P(x), and therefore the size of the CRC value, and the sum is the bits of the input data sequence. In at least one embodiment, f=24, f=16, f=8, or some other value.

[0050] I(x)=∑ i (x i b i ) (Equation 1)

[0051] CRC f =(x f ∑ i (x i b i ))mod P(x) (Equation 2)

[0052] In at least one embodiment, a CRC value is calculated for data on an uplink from a mobile device to a cellular infrastructure serving multiple mobile devices. In at least one embodiment, a CRC value is calculated for data on a downlink. In at least one embodiment, a CRC value is calculated from an input data sequence to compare it with a received CRC value received with the input data sequence, or a CRC value is generated for the input data sequence. In at least one embodiment, a generating polynomial such as in Equation 3 is used and / or a generating polynomial such as in Equation 4 is used.

[0053] P(x) CRC24A =x 24 +x 23 +x 18 +x 17 +x 14 +x 11 +x 10 +x 7 +x 6 +x 5 +x 4 +x 3 +x+1 (Equation 3)

[0054] P(x) CRC24B =x24 +x 23 +x 6 +x 5 +x+1 (Equation 4)

[0055] In at least one embodiment, the input data sequence has a size of K bytes (8*K bits), where K is a positive integer from 1 to the maximum size allowed by the protocol. In at least one embodiment, K may be 1,056 bytes or 13,728 bytes, or some other value, depending on the specific protocol. In at least one embodiment, a multi-level sequence with its own CRC value is provided. In at least one embodiment, for example, a code block may have a size of 1,056 bytes (8,448 bits), and a transport block may consist of 13 code blocks or some other number of code blocks. In at least one embodiment, a transport block may be made into a larger block. In at least one embodiment in which a transport block consists of a plurality of code blocks, there may be a CRC value for each code block and a CRC value for a transport block representing a series connection of those plurality of code blocks. In at least one embodiment, a transport block has a size of N=L*K bytes, where L is the number of code blocks in the transport block N and K is the number of bytes in each of those code blocks.

[0056] In at least one embodiment, the input data sequence can be viewed as a binary polynomial and divided into smaller data segments, such as bytes, where the data segments are processed in parallel using the parallel capabilities of a graphics processing unit (GPU). In at least one embodiment, the data segments are processed using an XOR step or otherwise in conjunction with a generator segment associated with a generator polynomial for a CRC process being used. In at least one embodiment, the generator segment is pre-calculated based on the position of the corresponding data segment in the larger input data sequence. In at least one embodiment, the output of the data segment processing is combined in a reduction process, resulting in a remainder of a modulo operation using the generator polynomial. In at least one embodiment, the data segments and the generator segment are processed in parallel, possibly each of a first plurality of threads of the GPU is assigned a data segment and a generator segment, and a second plurality of threads performs the reduction process on the output of the first plurality of threads.

[0057] In at least one embodiment, as shown in Equation 5, the generation segments are pre-computed, where the i-th generation segment GSi is one byte wide and has as many bytes in the generation segment as there are input data segments, or can be input data segments, pre-computed and stored as stored generation segments.

[0058] GS i =x f+8i mod P(x) (Equation 5)

[0059] In at least one embodiment, the stored generated segments may be stored in the global memory of the GPU. In at least one embodiment, the intermediate segments IS representing the results of the input data segments and the generated segments i , whether precomputed or otherwise, can be expressed as shown in Equation 6.

[0060] IS i =x f+8i b i mod P(x)=GS i (b i mod P(x))modP(x) (Equation 6)

[0061] In at least one embodiment, multiple bytes, such as four bytes, may be processed at a time. In at least one embodiment, modular polynomial multiplication and addition may be implemented by a combination of shift and XOR operations. In at least one embodiment, multiple GPU threads each process a data segment, where a GPU thread processes four bytes, given a thread input TIi (which represents four bytes of the data segment), the operation may arrive at a thread output TO of thread i located at thread position i among the multiple threads as shown in Equation 7. i .

[0062]

[0063] In at least one embodiment, the outputs of multiple GPU threads TO i XORs may be performed using an XOR reduction tree implemented at the thread block level with an atomic XOR in shared memory followed by an atomic XOR in global memory. In at least one embodiment, in addition to the pre-computed generation segments, a pre-computed table, possibly in global GPU memory, may be used to store possible values ​​of components of thread outputs for a given thread input. In at least one embodiment, a GPU thread receives an input byte of an input data sequence and outputs a byte corresponding to the input byte multiplied by a certain power of x modulo P(x). In at least one embodiment, where the input is a byte, a 256-byte table pre-computed from the generation segment is sufficient to handle all possible input byte values. In at least one embodiment, when a lookup table is used, the operation of outputting a thread output to be XORed with other thread outputs can be reduced to a lookup and some XORs.

[0064] In at least one embodiment, decomposing an input data sequence represented by a binary polynomial into data segments of bytes or other widths can reduce the computational effort of certain pre-computation and storage costs, with the end result being lower latency, which may be desirable in certain protocols. In at least one embodiment, where the generator polynomial does not change or changes infrequently, the pre-computation and storage costs can be distributed over many operations. In at least one embodiment, CRC processing is performed on CRC generator polynomials used in 5G software defined radio access network (RAN) equipment, and the number of such CRC generator polynomials is small and is not expected to change frequently.

[0065] In at least one embodiment, another data width is used, such as 1, 2, 4, 16 or some other data width, which can be varied and / or adjusted based on optimization factors, GPU architecture or some constants. In at least one embodiment, processing four bits at a time may increase the overall CRC processing speed.

[0066] Figure 1 Data reception at the physical layer (PHY) of a mobile device network according to one or more embodiments is shown. In at least one embodiment, the network system 100 can provide multiple mobile devices 102 (1)-(4) to connect to base stations 104 (1)-(4), where received signals are demodulated by demodulators 106 (1)-(4) and processed by various other signal processing elements 108, such as channel estimation and multiple-input multiple-output signal processing. In at least one embodiment, the output of the signal processing element 108 can resolve the signal into multiple paths and provide these signals to other elements 110 (1)-(4), which may include transform decoders, constellation mappers, descramblers, rate matchers, low-density parity check (LDPC) decoders, etc. In at least one embodiment, the output of the elements 110 (1)-(4) may be to a GPU-based cyclic redundancy checker 112 (1)-(4). In at least one embodiment, where the network system 100 provides real-time data transmission or otherwise requires fast processing, the use of a GPU to perform CRC processing and the parallelization available with the GPU can provide fast processing of the CRC.

[0067] Figure 2 A method for using the device according to one or more embodiments is shown. Figure 11 . The GPU-based CRC processing unit 202(1)-(N) of the GPU-based cyclic redundancy checker 112(1)-(4) in FIG. 1 . In at least one embodiment, N is the number of threads used for CRC processing. In at least one embodiment, the GPU-based CRC processing unit 202(1), similar to the other GPU-based CRC processing units shown, includes a load / store unit 204, an execution core 206, a register file 208, an instruction cache 210, and access to a shared memory 212 and a global memory 214. In at least one embodiment, the GPU-based CRC processing unit 202(1) processes multiple different CRC processes, and indicates a selection of which generator polynomial to use at a select input of the GPU-based CRC processing unit 202(1). In at least one embodiment, in the operations described herein, the GPU-based CRC processing unit 202(1) can read in multiple bytes of a data segment, load the data into the register file 208, access those bytes using the execution core 206, and return thread outputs to the register file 208. In at least one embodiment, thread outputs are stored in shared memory 212 and processed by other threads in a parallel XOR reduction tree.

[0068] Figure 3 Operation of a CRC thread 302 according to one or more embodiments is shown. In at least one embodiment, the CRC thread is one of a plurality of threads and may be one of K threads processing a CRC for input data having 4*K bytes. In at least one embodiment, the CRC thread 302 is for thread T, where T=0, 1, ..., K-1. In at least one embodiment, the CRC thread 302 has storage 304 for four bytes of a data segment in a local memory such as a thread register. In at least one embodiment, the CRC thread 302 accesses storage 306 for polynomial factors modulo a generator polynomial and multiplies a byte value by the polynomial factors or performs an equivalent lookup. In at least one embodiment, a parallel XOR reduction tree may reduce four values ​​to one value to form a thread output 310, which represents a portion of a CRC on a 4*K byte input data sequence.

[0069] In at least one embodiment, the GPU-based CRC processing unit can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In at least one embodiment, a single instruction multiple data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads without having to provide multiple independent instruction units. In at least one embodiment, a single instruction multiple thread (SIMT) technique is used to support the parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster.

[0070] In at least one embodiment, a first plurality of threads of a GPU-based CRC processing unit operates on different segments of an input data sequence to process the segments, wherein corresponding generator polynomial segments perform common operations among threads in the plurality of threads, even though each thread has different data. In at least one embodiment, a GPU-based CRC processing unit distributes the input data sequence among threads in the plurality of threads by parsing the input data sequence into a plurality of input data segments, wherein the plurality of input data segments are sized to fit the data width of the thread's local memory. In at least one embodiment, the threads in the first plurality of threads perform operations such as Figure 3 Those operations shown, while threads in the second plurality of threads perform reduction operations such as XOR operations on the outputs of the threads and reducing the outputs by modulo a generator polynomial.

[0071] In at least one embodiment, the thread of the GPU-based CRC processing unit can calculate the multiplication of the data segment of the input data sequence with the polynomial factor on the Galois field GF2. In at least one embodiment, the thread of the GPU-based CRC processing unit can calculate the multiplication of the data segment of the input data sequence with the pre-calculated multiplication of the polynomial factor and the generator polynomial segment on the Galois field GF2. In at least one embodiment, the thread of the GPU-based CRC processing unit can perform a lookup of the multiplication value of the data segment of the input data sequence on the Galois field GF2 with the polynomial factor and the generator polynomial segment in a pre-calculated table. In at least one embodiment, the polynomial factor is a monomial with a single non-zero coefficient and an order equal to the order of the corresponding generator polynomial.

[0072] Figure 4 Block-level operations for parallel combination and reduction of thread outputs according to one or more embodiments are shown. In at least one embodiment, a block-level parallel CRC module 402 processes the outputs of threads 404(0)-(K-1) multiplied by corresponding polynomial factors 406(0)-(K-1). In at least one embodiment, the result of the multiplication is provided to a parallel XOR reduction tree 408 to form an output 410 of a CRC value having an input data sequence of 4*K bytes, which has been reduced to an f-bit value, where f is the size of the corresponding CRC. In at least one embodiment, the threads operate on 32 bits at a time, so the powers of x in each polynomial factor 406(0)-(K-1) are increased by 32, but other sizes may be used instead and adjusted accordingly.

[0073] In at least one embodiment, a more general lookup table approach may be used, such as where a lookup table is provided, the powers of the polynomial factors are pre-computed and stored at index i (e.g., x 8i ,x 16i,...,x 1016i ) in the first lookup table, and some larger powers 、x 2048i is stored in the second lookup table. In at least one embodiment, this allows combinations to be pre-computed using a smaller total number of lookup table entries. In at least one embodiment, for example, x (2048+64)*5 The value of can be determined using the index value i=5 to provide x 64*5 The first table of precomputed values ​​and the provided x 2048*5 The second table of pre-computed values ​​may then be multiplied by the modulus of the generator polynomial. In at least one embodiment, the powers of the polynomial factors to be pre-computed may be in the table used to hold the pre-computed values ​​x. 41 , x 8i , x 12i , x 16i And so on, another value, for example 4, is added to the lookup table at index i.

[0074] Figure 5 Block-level operations for combining and reducing thread block outputs in parallel are shown in accordance with one or more embodiments. In at least one embodiment, a thread block-level parallel CRC module 502 processes the outputs of multiplying thread blocks 504(0)-(M-1) by corresponding polynomial factors 506(0)-(M-1). In at least one embodiment, the results of the multiplications are provided to a parallel XOR reduction tree 508 to form an output 510 of a CRC value for the input data sequence. In at least one embodiment, the thread block-level parallel CRC module 502 processes a larger input data set than a block-level parallel CRC module.

[0075] Figure 6 The process of checking CRC value according to one or more embodiments is shown. In at least one embodiment, input data block 602 is provided to parallel CRC module 606 based on GPU that can be implemented as described herein, and uses selected CRC output CRC value. In at least one embodiment, output CRC value is stored in storage 608. In at least one embodiment, the output CRC value stored in storage 608 can be compared by using comparator 610 with the CRC value 604 received by input data block 602, and comparator 610 outputs verification or fails according to whether CRC matches. In at least one embodiment, the content of storage 608 can be used as CRC value to create CRC value for known good data block. In at least one embodiment, the difference between output CRC value and CRC value 604 stored in storage 608 can be used for detecting and / or correcting errors in input data block 602.

[0076] Fig. 7AInference and / or training logic 715 is shown for performing reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or 7B provide details regarding the reasoning and / or training logic 715 .

[0077] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 701 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0078] In at least one embodiment, any portion of data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, data storage 701 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether data storage 701 is internal or external to a processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0079] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 705 to store the reverse and / or output weights and / or input / output data corresponding to the neurons or layers of the neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 705 stores the weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during the back propagation of the input / output data and / or weight parameters. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequence, wherein the weights and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads the weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0080] In at least one embodiment, data store 701 and data store 705 may be separate storage structures. In at least one embodiment, data store 701 and data store 705 may be the same storage structure. In at least one embodiment, data store 701 and data store 705 may be partially the same storage structure and partially independent storage structures. In at least one embodiment, any portion of data store 701 and data store 705 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory.

[0081] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALU(s)”) 710, including integer and / or floating point units, that perform logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​of a layer or neuron in a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data memory 701 and / or code and / or data storage 705. In at least one embodiment, the activations stored in activation storage 720 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 710 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 705 and / or data 701 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705 or code and / or data storage 701 or in another storage on or off-chip.

[0082] In at least one embodiment, ALU(s) 710 are included within one or more processors or other hardware logic devices or circuits, or ALU(s) 710 may be external to a processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALU 710 may be included within an execution unit of a processor or otherwise included within an ALU bank accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, data store 701, data store 705, and activation store 720 may be on the same processor or other hardware logic device or circuit, or they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 720 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry, and fetched and / or processed using fetch, decode, schedule, execute, exit, and / or other logic circuitry of the processor.

[0083] In at least one embodiment, activation storage 720 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation storage 720 may be completely or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 720 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or some combination of these factors. In at least one embodiment, Fig. 7A The inference and / or training logic 715 shown may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Fig. 7A The illustrated inference and / or training logic 715 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware, such as a field programmable gate array (“FPGA”).

[0084] Figure 7B Inference and / or training logic 715 is shown in accordance with at least one embodiment. In at least one embodiment, the reasoning and / or training logic 715 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B The inference and / or training logic 715 shown in FIG. 7 may be used in conjunction with an application specific integrated circuit (ASIC), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7BThe inference and / or training logic 715 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 7B In at least one embodiment shown in , each of code and / or data storage 701 and code and / or data storage 705 is associated with a dedicated computing resource (e.g., computing hardware 702 and computing hardware 706), respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, and the results of performing the functions are stored in activation storage 720.

[0085] In at least one embodiment, each of the data stores 701 and 705 and the corresponding computing hardware 702 and 706 corresponds to a different layer of the neural network, such that activations obtained from one "storage / compute pair 701 / 702" of the data store 701 and computing hardware 702 are provided as inputs to the next "storage / compute pair 705 / 706" of the data store 705 and computing hardware 706, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 715 after or in parallel with the storage / compute pairs 701 / 702 and 705 / 706.

[0086] Data Center

[0087] Figure 8 An example data center 800 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0088] In at least one embodiment, Figure 8As shown, the data center infrastructure layer 810 may include a resource coordinator 812, group computing resources 814, and node computing resources ("node CR") 816 (1)-816 (N), where "N" represents any integer, a positive integer. In at least one embodiment, the node CR 816 (1)-816 (N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 816 (1)-816 (N) may be a server having one or more of the above computing resources.

[0089] In at least one embodiment, the grouped computing resources 814 may include a separate grouping (not shown) of node CRs housed in one or more racks, or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 814 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0090] In at least one embodiment, resource coordinator 822 may configure or otherwise control one or more node CRs 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 822 may include a software design infrastructure ("SDI") management entity for data center 800. In at least one embodiment, resource coordinator 108 may include hardware, software, or some combination thereof.

[0091] In at least one embodiment, Figure 8As shown, the framework layer 820 includes a job scheduler 832, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, the framework layer 820 may include a framework that supports the software 832 of the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 832 or the application 842 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which can utilize the distributed file system 838 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 832 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 800. In at least one embodiment, the configuration manager 834 may be able to configure different layers, such as the software layer 830 and the framework layer 820 including Spark and a distributed file system 838 for supporting large-scale data processing. In at least one embodiment, the resource manager 836 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 838 and the job scheduler 832. In at least one embodiment, the cluster or group computing resources may include group computing resources 814 on the data center infrastructure layer 810. In at least one embodiment, the resource manager 836 can coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0092] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0093] In at least one embodiment, the one or more applications 842 included in the application layer 840 may include one or more types of applications used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 838 of the framework layer 820. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[0094] In at least one embodiment, any of the configuration manager 834, the resource manager 836, and the resource coordinator 812 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 800 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0095] In at least one embodiment, the data center 800 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 800. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to the data center 800.

[0096] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In at least one embodiment, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0097] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A7B and / or 7C provide details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Figure 8 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0098] Autonomous Vehicles

[0099] Fig. 9A An example of an autonomous vehicle 900 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 900 (alternatively referred to herein as "vehicle 900") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that may accommodate one or more passengers. In at least one embodiment, vehicle 900 may be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 900 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0100] An autonomous vehicle may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) of the U.S. Department of Transportation and the Society of Automotive Engineers (“SAE”) in the “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, the vehicle 900 may be capable of functioning according to one or more of the levels 1 to 5 of the autonomous driving levels. For example, in at least one embodiment, depending on the embodiment, the vehicle 900 may be capable of conditional automation (level 3), high automation (level 4), and / or full automation (level 5).

[0101] In at least one embodiment, the vehicle 900 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 900 may include, but is not limited to, a propulsion system 950, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 950 may be connected to a drive train of the vehicle 900, which may include, but is not limited to, a transmission, so that the vehicle 900 can be propelled. In at least one embodiment, the propulsion system 950 may be controlled in response to receiving a signal from one or more throttles / accelerators 952.

[0102] In at least one embodiment, when propulsion system 950 is operating (e.g., when vehicle 900 is traveling), steering system 954 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 900 (e.g., along a desired path or route). In at least one embodiment, steering system 954 may receive signals from steering actuator 956. In at least one embodiment, a steering wheel is not required for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 946 may be used to operate vehicle brakes in response to signals received from brake actuator 948 and / or brake sensors.

[0103] In at least one embodiment, the controller 936 may include, but is not limited to, one or more system on a chip (“SoC”) ( Fig. 9A) and / or a graphics processing unit (“GPU”) provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 900. For example, in at least one embodiment, the controller 936 may send signals to operate vehicle brakes through a brake actuator 948, operate a steering system 954 through one or more steering actuators 956, and operate a propulsion system 950 through one or more throttles / accelerators 952. In at least one embodiment, the one or more controllers 936 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to achieve autonomous driving and / or assist the driver in driving the vehicle 900. In at least one embodiment, the one or more controllers 936 may include a first controller 936 for autonomous driving functions, a second controller 936 for functional safety functions, a third controller 936 for artificial intelligence functions (e.g., computer vision), a fourth controller 936 for infotainment functions, a fifth controller 936 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 936 may handle two or more of the above functions, two or more controllers 936 may handle a single function, and / or any combination thereof.

[0104] In at least one embodiment, the one or more controllers 936 provide signals for controlling one or more components and / or systems of the vehicle 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 958 (e.g., one or more global positioning system sensors), one or more RADAR sensors 960, one or more ultrasonic sensors 962, one or more LIDAR sensors 964, one or more inertial measurement unit (IMU) sensors 966 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 996, one or more stereo cameras 968, one or more wide angle cameras 970 (e.g., fisheye cameras), one or more infrared cameras 972, one or more surround cameras 974 (e.g., 360 degree cameras), telephoto cameras (e.g., infrared cameras), and / or a plurality of other sensors. Fig. 9A Not shown), mid-range camera ( Fig. 9A900), one or more speed sensors 944 (e.g., for measuring the speed of the vehicle 900), one or more vibration sensors 942, one or more steering sensors 940, one or more brake sensors (e.g., as part of a brake sensor system 946), and / or other sensor types are received.

[0105] In at least one embodiment, one or more controllers 936 may receive input (e.g., represented by input data) from a dashboard 932 of the vehicle 900 and provide output (e.g., represented by output data, display data, etc.) through a human machine interface ("HMI") display 934, an audible annunciator, a speaker, and / or through other components of the vehicle 900. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Fig. 9A 900, such as on a map), directions, locations of other vehicles (e.g., an occupancy grid), information about objects and states of objects sensed by controller 936, and the like. For example, in at least one embodiment, HMI display 934 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.), and / or information about driving maneuvers that the vehicle has taken, is taking, or will take (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0106] In at least one embodiment, the vehicle 900 further includes a network interface 924, which can use one or more wireless antennas 926 and / or one or more modems to communicate through one or more networks. For example, in at least one embodiment, the network interface 924 may be able to communicate through Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. In at least one embodiment, one or more wireless antennas 926 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., LoRaWAN, SigFox, etc.) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0107] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BProvides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Fig. 9A for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0108] In at least one embodiment, the Fig. 9A A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0109] Fig. 9B According to at least one embodiment, Fig. 9A 900. In at least one embodiment, the cameras and corresponding fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different locations on the vehicle 900.

[0110] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be applicable to components and / or systems of the vehicle 900. One or more cameras may operate at automotive safety integrity level ("ASIL") B and / or other ASILs. In at least one embodiment, depending on the embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220fps, 240fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent ("RCCC") filter array, a red transparent transparent blue ("RCCB") filter array, a red blue green transparent ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or another type of filter array. In at least one embodiment, a transparent pixel camera, such as a camera with an RCCC, RCCB, and / or RBGC filter array, may be used in an effort to increase light sensitivity.

[0111] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0112] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the vehicle (e.g., reflections of the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated within four pillars at each corner of the cabin.

[0113] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 900 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 936 and / or control SoCs, thereby providing information critical to generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, a forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, a forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0114] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("complementary metal oxide semiconductor") color imager. In at least one embodiment, a wide-angle camera 970 can be used to sense objects entering from the periphery (e.g., pedestrians, road crossings, or bicycles). Although in Fig. 9B Only one wide-angle camera 970 is shown, however, in at least one embodiment, there may be any number (including zero) of wide-angle cameras 970 on the vehicle 900. In at least one embodiment, any number of remote cameras 998 (e.g., a remote stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 998 may also be used for object detection and classification and basic object tracking.

[0115] In at least one embodiment, any number of stereo cameras 968 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 968 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 900, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 968 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 900 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 968 may be used in addition to those described herein.

[0116] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 900 (e.g., a side view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 974 (e.g., a side view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. Fig. 9B Four surround cameras 974 (shown) can be positioned on the vehicle 900. The one or more surround cameras 974 can include, but are not limited to, any number and combination of wide-angle cameras 970, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located at the front, rear, and sides of the vehicle 900. In at least one embodiment, the vehicle 900 can use three surround cameras 974 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0117] In at least one embodiment, a camera 900 having a field of view including a portion of the environment behind the vehicle (e.g., a rear view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 998 and / or one or more mid-range cameras 976, one or more stereo cameras 968, one or more infrared cameras 972, etc.), as described herein.

[0118] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B , details about the reasoning and / or training logic 715 are provided herein. In at least one embodiment, the reasoning and / or training logic 715 may be Fig. 9B for use in a system for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0119] In at least one embodiment, the Fig. 9B A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0120] Fig. 9C According to at least one embodiment, Fig. 9A A block diagram of an example system architecture of an autonomous vehicle 900 is shown. In at least one embodiment, Fig. 9C Each of one or more components, one or more features, and one or more systems of the vehicle 900 in FIG. 902 is shown as being connected via a bus 902. In at least one embodiment, the bus 902 may include, but is not limited to, a CAN data interface (referred to herein alternatively as a "CAN bus"). In at least one embodiment, the CAN may be a network inside the vehicle 900 that helps control various features and functions of the vehicle 900, such as actuation, acceleration, braking, steering, wipers, etc. of the brakes. In one embodiment, the bus 902 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 902 may be read to find steering wheel angles, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, the bus 902 may be a CAN bus that complies with ASIL B.

[0121] In at least one embodiment, in addition to or from CAN, FlexRay and / or Ethernet can be used. In at least one embodiment, there can be any number of buses 902, which can include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses can be used to perform different functions, and / or can be used for redundancy. For example, in at least one embodiment, the first bus 902 can be used for collision avoidance functions, and the second bus 902 can be used for actuation control. In at least one embodiment, each bus 902 can communicate with any component of the vehicle 900, and two or more buses 902 can communicate with the same component. In at least one embodiment, each of any number of systems on a chip ("SoC") 904, each of one or more controllers 936, and / or each computer in the vehicle can access the same input data (e.g., input from sensors of the vehicle 900) and can be connected to a common bus, such as a CAN bus.

[0122] In at least one embodiment, the vehicle 900 may include one or more controllers 936, such as those described herein with respect to Fig. 9A Those described. In at least one embodiment, the controller 936 can be used for a variety of functions. In at least one embodiment, the controller 936 can be coupled to any of the various other components and systems of the vehicle 900 and can be used to control the vehicle 900, the artificial intelligence of the vehicle 900, the infotainment of the vehicle 900, and / or the like.

[0123] In at least one embodiment, the vehicle 900 may include any number of SoCs 904. In at least one embodiment, each of the SoCs 904 may include, but is not limited to, a central processing unit ("CPU(s)") 906, a graphics processing unit ("GPU(s")) 908, one or more processors 910, one or more caches 912, one or more accelerators 914, one or more data stores 916, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 904 may be used to control the vehicle 900 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 904 may be combined with a high-definition ("HD") map 922 in a system (e.g., a system of the vehicle 900), which may be downloaded from one or more servers (e.g., a system of the vehicle 900) via a network interface 924. Fig. 9C ) to obtain map refreshes and / or updates.

[0124] In at least one embodiment, one or more CPUs 906 may include a CPU cluster or CPU complex (referred to herein alternatively as "CCPLEX"). In at least one embodiment, one or more CPUs 906 may include multiple cores and / or a secondary ("L2") cache. For example, in at least one embodiment, one or more CPUs 906 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 906 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 906 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 906 may be active at any given time.

[0125] In at least one embodiment, one or more CPUs 906 may implement power management functions, including but not limited to one or more of the following features: each hardware module may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently powered; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 906 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0126] In at least one embodiment, one or more GPUs 908 may include an integrated GPU (or referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 908 may be programmable and may be effective for parallel workloads. In at least one embodiment, one or more GPUs 908 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 908 may include one or more streaming microprocessors, each of which may include a level 1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512KB). In at least one embodiment, one or more GPUs 908 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 908 may use a computing application programming interface (API). In at least one embodiment, one or more GPUs 908 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0127] In at least one embodiment, one or more GPUs 908 may be optimized for power consumption to achieve optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 908 may be manufactured on fin field effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor may include multiple mixed precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, a zero-level (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file may be allocated to each processing block. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to achieve finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0128] In at least one embodiment, one or more GPUs 908 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900GB / sec in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0129] In at least one embodiment, one or more GPUs 908 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 908 to directly access one or more CPU 906 page tables. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 908 experiences a miss, an address translation request may be sent to one or more CPUs 906. In response, in at least one embodiment, 2CPUs in one or more CPUs 906 may look up the virtual-physical mapping of the address in its page table and transmit the translation back to one or more GPUs 908. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 906 and one or more GPUs 908, thereby simplifying the programming of one or more GPUs 908 and porting applications to one or more GPUs 908.

[0130] In at least one embodiment, one or more GPUs 908 may include any number of access counters that may track the frequency of accesses to other processors' memory by one or more GPUs 908. In at least one embodiment, the one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0131] In at least one embodiment, one or more SoCs 904 may include any number of caches 912, including those described herein. For example, in at least one embodiment, one or more caches 912 may include a level 3 ("L3") cache available for one or more CPUs 906 and one or more GPUs 908 (e.g., connected to both CPUs 906 and GPUs 908). In at least one embodiment, one or more caches 912 may include a write-back cache that may, for example, track the state of a line by using a cache coherent protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although smaller cache sizes may be used, the L3 cache may include 4MB or more, depending on the embodiment.

[0132] In at least one embodiment, one or more SoCs 904 may include one or more accelerators 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 904 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to supplement one or more GPUs 908 and unload some tasks of one or more GPUs 908 (e.g., freeing up more cycles of one or more GPUs 908 to perform other tasks). In at least one embodiment, one or more accelerators 914 may be used for target workloads that are sufficiently stable to withstand acceleration tests (e.g., perception, convolutional neural networks ("CNN"), recursive neural networks ("RNN"), etc.). In at least one embodiment, CNNs may include regional or regional convolutional neural networks ("RCNN") and fast RCNNs (e.g., such as for object detection) or other types of CNNs.

[0133] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include a deep learning accelerator ("DLA"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally greatly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single instance convolution functions for features and weights and post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from microphone 996; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0134] In at least one embodiment, a DLA can perform any function of one or more GPUs 908, and by using an inference accelerator, for example, a designer can target one or more DLAs or one or more GPUs 908 for any function. For example, in at least one embodiment, a designer can focus the processing and floating point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 908 and / or other one or more accelerators 914.

[0135] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 938, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0136] In at least one embodiment, the RISC core can be coupled to an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and / or the like. In at least one embodiment, each RISC core can include any number of memories. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or storage devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or a tightly coupled RAM.

[0137] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of one or more CPUs 906. In at least one embodiment, the DMA may support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0138] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may be used as the main processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may increase throughput and speed.

[0139] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even different algorithms on sequence images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

[0140] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 914. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuits, controllers, and multiplexers. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0141] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communications for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0142] In at least one embodiment, one or more SoCs 904 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of an object (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other purposes.

[0143] In at least one embodiment, one or more accelerators 914 (e.g., a hardware accelerator cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power consumption and low latency are well matched to algorithmic domains that require predictable processing. In other words, the PVA excels in semi-intensive or intensive conventional computations, even on small data sets, which require predictable runtimes with low latency and low power consumption. In at least one embodiment, an autonomous vehicle, such as in vehicle 900, the PVA is designed to run classic computer vision algorithms because they are efficient at object detection and integer math operations.

[0144] For example, in at least one embodiment, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching based algorithm may be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0145] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0146] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network, which outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. For example, in at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score, and only detects that exceed the threshold are considered true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 966 associated with vehicle 900 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 964 or one or more RADAR sensors 960), and the like.

[0147] In at least one embodiment, one or more SoCs 904 may include one or more data stores 916 (e.g., memory). In at least one embodiment, one or more data stores 916 may be on-chip memory of one or more SoCs 904 that may store neural networks to be executed on one or more GPUs 908 and / or DLAs. In at least one embodiment, one or more data stores 916 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 912 may include an L2 or L3 cache.

[0148] In at least one embodiment, one or more SoCs 904 may include any number of processors 910 (e.g., embedded processors). In at least one embodiment, one or more processors 910 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 904 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist system low power state transitions, one or more SoCs 904 thermal and temperature sensor management, and / or one or more SoCs 904 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and one or more SoCs 904 may use the ring oscillator to detect the temperature of one or more CPUs 906, one or more GPUs 908, and / or one or more accelerators 914. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 904 into a lower power consumption state and / or place the vehicle 900 into a driver's safe parking pattern (e.g., bringing the vehicle 900 to a safe stop).

[0149] In at least one embodiment, one or more processors 910 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0150] In at least one embodiment, one or more processors 910 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0151] In at least one embodiment, one or more processors 910 may further include a safety cluster engine, which includes but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safe mode, in at least one embodiment, two or more cores may operate in lockstep mode and may be used as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 910 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 910 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0152] In at least one embodiment, one or more processors 910 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by the video playback application to produce the final video to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 970, one or more surround cameras 974, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 904, which is configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, otherwise they are disabled.

[0153] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0154] In at least one embodiment, the video image synthesizer can also be configured to perform stereoscopic correction on the input stereoscopic lens frames. In at least one embodiment, the video image synthesizer can also be used for user interface synthesis when the operating system desktop is used, and one or more GPUs 908 are not required to continuously render new surfaces. In at least one embodiment, when one or more GPUs 908 are powered and actively performing 3D rendering, the video image synthesizer can be used to offload one or more GPUs 908 to improve performance and responsiveness.

[0155] In at least one embodiment, one or more of the SoCs 904 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 904 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0156] In at least one embodiment, one or more of the SoCs 904 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders ("codecs"), power management, and / or other devices. One or more SoCs 904 may be used to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 964, one or more RADAR sensors 960, etc., which may be connected via Ethernet), data from bus 902 (e.g., speed of vehicle 900, steering wheel position, etc.), data from one or more GNSS sensors 958 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 904 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to free one or more CPUs 906 from routine data management tasks.

[0157] In at least one embodiment, one or more SoC 904 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that utilizes and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, which provides a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoC 904 can be faster and more reliable than other systems, and even more energy efficient and space efficient. For example, in at least one embodiment, one or more accelerators 914, when combined with one or more CPUs 906, one or more GPUs 908, and one or more data storage devices 916, can provide a fast and effective platform for level 3-5 autonomous driving vehicles.

[0158] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0159] In at least one embodiment, multiple neural networks are allowed to be executed simultaneously and / or sequentially, and the results are allowed to be combined together to achieve Level 3-5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 920) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs that the neural network has not been specifically trained on. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of symbols and pass this semantic understanding to a path planning module running on the CPU Complex.

[0160] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks may be run simultaneously. For example, in at least one embodiment, a warning sign including: "Caution: flashing lights indicate icy conditions" and connected lights may be interpreted by multiple neural networks independently or collectively. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights may be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be run simultaneously, such as within a DLA and / or on one or more GPUs 908.

[0161] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 900. In at least one embodiment, the always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 904 provide protection against theft and / or carjacking.

[0162] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 996 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 904 use CNNs to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area where the vehicle is operating, as identified by one or more GNSS sensors 958. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 962 to execute emergency vehicle safety routines, slow down the vehicle, drive the vehicle to the side of the road, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0163] In at least one embodiment, the vehicle 900 may include one or more CPUs 918 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 904 via a high-speed interconnect (e.g., PCIe). For example, in at least one embodiment, the one or more CPUs 918 may include an X86 processor. In at least one embodiment, the one or more CPUs 918 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and one or more SoCs 904, and / or monitoring the status and health of one or more controllers 936 and / or an on-chip information system ("information SoC") 930.

[0164] In at least one embodiment, the vehicle 900 may include one or more GPUs 920 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 904 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 920 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 900 (e.g., sensor data).

[0165] In at least one embodiment, the vehicle 900 may further include a network interface 924, which may include, but is not limited to, one or more wireless antennas 926 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, the network interface 924 may be used to enable wireless connection with other vehicles and / or computing devices (e.g., a passenger's client device) through an Internet cloud service (e.g., using a server and / or other network device). In at least one embodiment, in order to communicate with other vehicles, a direct link may be established between the vehicle 90 and another vehicle and / or an indirect link may be established (e.g., through a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide the vehicle 900 with information about vehicles near the vehicle 900 (e.g., vehicles in front of, on the side of, and / or behind the vehicle 900). In at least one embodiment, the aforementioned functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 900.

[0166] In at least one embodiment, the network interface 924 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 936 to communicate via a wireless network. In at least one embodiment, the network interface 924 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. In at least one embodiment, for example, frequency conversion may be performed by a known process and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end function may be provided by a separate chip. In at least one embodiment, the network interface may include a wireless function for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0167] In at least one embodiment, the vehicle 900 may further include one or more data stores 928, which may include, but are not limited to, off-chip (e.g., one or more SoC 904) storage. In at least one embodiment, the one or more data stores 928 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard disk, and / or other components and / or devices that can store at least one bit of data.

[0168] In at least one embodiment, the vehicle 900 may further include one or more GNSS sensors 958 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 958 may be used, including, for example but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0169] In at least one embodiment, the vehicle 900 may further include one or more RADAR sensors 960. In at least one embodiment, one or more RADAR sensors 960 may be used by the vehicle 900 for remote vehicle detection, even in darkness and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 960 may be controlled and access object tracking data using a CAN bus and / or bus 902 (e.g., to transmit data generated by one or more RADAR sensors 960), and in some examples, Ethernet may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. In at least one embodiment, for example, but not limited to, one or more of the RADAR sensors 960 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 960 are pulse Doppler RADAR sensors.

[0170] In at least one embodiment, one or more RADAR sensors 960 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within 250m). In at least one embodiment, one or more RADAR sensors 960 can help distinguish between static objects and moving objects, and can be used by the ADAS system 938 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 960 included in the long-range RADAR system may include but are not limited to a single-base multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas can create a focused beam pattern designed to record the surroundings of the vehicle 900 at a higher speed with minimal traffic interference in adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view so that vehicles 900 entering or leaving the lane can be quickly detected.

[0171] In at least one embodiment, as an example, the medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 960 designed to be mounted at both ends of the rear bumper. In at least one embodiment, when mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the blind spots behind and beside the vehicle. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 938 for blind spot detection and / or lane change assistance.

[0172] In at least one embodiment, the vehicle 900 may further include one or more ultrasonic sensors 962. In at least one embodiment, one or more ultrasonic sensors 962 that may be positioned at the front, rear, and / or sides of the vehicle 900 may be used for parking assistance and / or creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 962 may be used, and different ultrasonic sensors 962 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor 962 may operate at a functional safety level of ASIL B.

[0173] In at least one embodiment, the vehicle 900 may include one or more LIDAR sensors 964. In at least one embodiment, the one or more LIDAR sensors 964 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 964 may be functional safety level ASIL B. In at least one embodiment, the vehicle 900 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 964 that may use Ethernet channels (e.g., provide data to a Gigabit Ethernet switch).

[0174] In at least one embodiment, one or more LIDAR sensors 964 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LIDAR sensors 964 may, for example, have an advertising range of approximately 100m, have an accuracy of 2cm-3cm, and support 100Mbps Ethernet connections. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 964 may be implemented as small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 900. In at least one embodiment, one or more LIDAR sensors 964, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, the forward one or more LIDAR sensors 964 may be configured for a horizontal field of view between 45 degrees and 95 degrees.

[0175] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 900. In at least one embodiment, the flash LIDAR unit includes but is not limited to a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 900 to the object. In at least one embodiment, the flash LIDAR can allow each laser flash to be used to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flash LIDAR sensors can be deployed, one sensor on each side of the vehicle 900. In at least one embodiment, the 3D flash LIDAR system includes but is not limited to a solid-state 3D line-of-sight array LIDAR camera with no moving parts except for a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as intensity data in the form of a 3D range point cloud and co-registered.

[0176] In at least one embodiment, the vehicle 900 may also include one or more IMU sensors 966. In at least one embodiment, the one or more IMU sensors 966 may be located at the rear axle center of the vehicle 900, in at least one embodiment. In at least one embodiment, the one or more IMU sensors 966 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 966 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, the one or more IMU sensors 966 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0177] In at least one embodiment, one or more IMU sensors 966 may be implemented as a miniature high-performance GPS-aided inertial navigation system ("GPS / INS") that combines micro-electromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 966 may enable the vehicle 900 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 966. In at least one embodiment, one or more IMU sensors 966 and one or more GNSS sensors 958 may be combined in a single integrated unit.

[0178] In at least one embodiment, the vehicle 900 can include one or more microphones 996 positioned within and / or around the vehicle 900. In at least one embodiment, among other things, the one or more microphones 996 can be used for emergency vehicle detection and identification.

[0179] In at least one embodiment, the vehicle 900 may further include any number of camera types, including one or more stereo cameras 968, one or more wide-angle cameras 970, one or more infrared cameras 972, one or more surround cameras 974, one or more long-range cameras 998, one or more mid-range cameras 976, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 900. In at least one embodiment, the type of camera used depends on the vehicle 900. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 900. In at least one embodiment, the number of cameras may vary depending on the embodiment. In at least one embodiment, for example, the vehicle 900 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present invention previously referred to herein. Fig. 9A and Fig. 9B Each camera can be described in more detail.

[0180] In at least one embodiment, the vehicle 900 may further include one or more vibration sensors 942. In at least one embodiment, one or more vibration sensors 942 may measure vibrations of a component (e.g., an axle) of the vehicle 900. In at least one embodiment, for example, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 942 are used, the difference between the vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0181] In at least one embodiment, the vehicle 900 may include an ADAS system 938. In at least one embodiment, the ADAS system 938 may include, but is not limited to, a SoC. In at least one embodiment, the ADAS system 938 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0182] In at least one embodiment, the ACC system may use one or more RADAR sensors 960, one or more LIDAR sensors 964, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 900 and automatically adjusts the speed of the vehicle 900 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 900 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0183] In at least one embodiment, the CACC system uses information from other vehicles, which can be received from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 924 and / or one or more wireless antennas 926. In at least one embodiment, a direct link can be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link can be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 900 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system can include one or both of the I2V and V2V information sources. In at least one embodiment, given the information of the vehicle ahead of vehicle 900, the CACC system can be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0184] In at least one embodiment, the FCW system is designed to warn the driver of the hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 960, which are coupled to a dedicated processor, DSP, FPGA and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of sounds, visual warnings, vibrations and / or rapid brake pulses.

[0185] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include technologies such as dynamic brake support and / or braking for impending collisions.

[0186] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver when the vehicle 900 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 900 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 900.

[0187] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker and / or vibration component.

[0188] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside of the rear camera range while the vehicle 900 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0189] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether a safe condition actually exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 900 itself decides whether to listen to the results of the main computer or the auxiliary computer (e.g., the first controller 936 or the second controller 936). In at least one embodiment, for example, the ADAS system 938 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant various software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 938 can be provided to a monitoring MCU. In at least one embodiment, if the outputs from the main computer and the auxiliary computer conflict, the supervisory MCU decides how to coordinate the conflict to ensure safe operation.

[0190] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the event that the confidence score does not meet the threshold, and in the event that the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0191] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based at least in part on outputs from the primary computer and the auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. In at least one embodiment, for example, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies metal objects that are not actually dangerous, such as drainage grates or manhole covers that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there are cyclists or pedestrians and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoCs 904.

[0192] In at least one embodiment, the ADAS system 938 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer will not cause a major error.

[0193] In at least one embodiment, the output of the ADAS system 938 can be input into the perception module of the main computer and / or the dynamic driving task module of the main computer. For example, in at least one embodiment, if the ADAS system 938 indicates a forward collision warning due to an object directly ahead, the perception block can use this information in identifying the object. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network that is trained to reduce the risk of false positives.

[0194] In at least one embodiment, the vehicle 900 may further include an infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, in at least one embodiment, the infotainment system SoC 930 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 930 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistants, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming media, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 900. For example, the infotainment SoC 930 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connections, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 934, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 930 may be further used to provide information (e.g., visual and / or auditory) to a user of the vehicle 900, such as information from an ADAS system 938, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0195] In at least one embodiment, the infotainment SoC 930 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 930 may communicate with other devices, systems, and / or components of the vehicle 900 via a bus 902 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 930 may be coupled to a monitoring MCU so that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of a main controller 936 (e.g., a main computer and / or backup computer of the vehicle 900). In at least one embodiment, the infotainment SoC 930 may enable the vehicle 900 to enter a driver-to-safety stop mode, as described herein.

[0196] In at least one embodiment, the vehicle 900 may further include a dashboard 932 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 932 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the dashboard 932 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 930 and the dashboard 932. In at least one embodiment, the dashboard 932 may be included as part of the infotainment SoC 930, and vice versa.

[0197] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Provides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Fig. 9C for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0198] In at least one embodiment, the Fig. 9C A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0199] Fig.9D According to at least one embodiment, a cloud-based server and Fig. 9A976 for communicating between autonomous vehicles 900. In at least one embodiment, system 976 may include, but is not limited to, one or more servers 978, one or more networks 990, and any number and type of vehicles, including vehicle 900. In at least one embodiment, one or more servers 978 may include, but are not limited to, multiple GPUs 984(A)-984(H) (collectively referred to herein as GPUs 984), PCIe switches 982(A)-982(D) (collectively referred to herein as PCIe switches 982), and / or CPUs 980(A)-980(B) (collectively referred to herein as CPUs 980), GPUs 984, CPUs 980, and PCIe switches 982 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 988 and / or PCIe connections 986 developed by NVIDIA. In at least one embodiment, GPUs 984 are connected via NVLink and / or NVSwitch SoC, and GPUs 984 and PCIe switches 982 are connected via PCIe interconnects. In at least one embodiment, although eight GPUs 984, two CPUs 980, and four PCIe switches 982 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 978 may include, but is not limited to, any combination of any number of GPUs 984, CPUs 980, and / or PCIe switches 982. For example, in at least one embodiment, one or more servers 978 may each include eight, sixteen, thirty-two, and / or more GPUs 984.

[0200] In at least one embodiment, one or more servers 978 may receive image data representing an image from a vehicle via one or more networks 990, the image showing an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 978 may transmit to the vehicle via one or more networks 990, a neural network 992, an updated neural network 992, and / or map information 994, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to the map information 994 may include but are not limited to updates to the HD map 922, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 992, the updated neural network 992, and / or the map information 994 may be generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 978 and / or other servers).

[0201] In at least one embodiment, one or more servers 978 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle, and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of the training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 990, and / or the machine learning model can be used by one or more servers 978 to remotely monitor the vehicle.

[0202] In at least one embodiment, one or more servers 978 may receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. In at least one embodiment, one or more servers 978 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 984, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 978 may include a deep learning infrastructure of a data center powered by a CPU.

[0203] In at least one embodiment, the deep learning infrastructure of one or more servers 978 may be capable of fast, real-time inference, and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 900. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 900, such as an image sequence and / or objects located in the image sequence by the vehicle 900 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by the vehicle 900, and, if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 900 is malfunctioning, the one or more servers 978 may send a signal to the vehicle 900 to instruct the fail-safe computer of the vehicle 900 to take control, notify passengers, and complete a safe parking maneuver.

[0204] In at least one embodiment, one or more servers 978 may include one or more GPUs 984 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, for example, in situations where performance is not critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, the hardware structure 715 is used to execute one or more embodiments. This article combines Fig. 7A and / or Figure 7B Details regarding hardware architecture 715 are provided.

[0205] Computer Systems

[0206] Fig.10 1000 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, the computer system 1000 may include, but is not limited to, components, such as a processor 1002, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, the computer system 1000 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1000 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0207] In at least one embodiment, the features can be used in other devices, such as handheld devices and embedded applications. In at least one embodiment, the handheld device may be a cellular phone, an Internet Protocol (Internet Protocol) device, a digital camera, a personal digital assistant ("PDA"), and / or a handheld PC. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0208] In at least one embodiment, computer system 1000 may include, but is not limited to, a processor 1002, which may include, but is not limited to, one or more execution units 1008 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, computer system 10 is a single-processor desktop or server system, or computer system 10 may be a multi-processor system. In at least one embodiment, processor 1002 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1002 may be coupled to a processor bus 1010, which may transmit data signals between processor 1002 and other components in computer system 1000.

[0209] In at least one embodiment, processor 1002 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1002 and / or may include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 1006 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0210] In at least one embodiment, an execution unit 1008, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1002. In at least one embodiment, the processor 1002 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1008 may include logic for processing a packed instruction set 1009. In at least one embodiment, by including the packed instruction set 1009 in the instruction set of a general-purpose processor, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1002. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0211] In at least one embodiment, execution unit 1008 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1000 may include, but is not limited to, memory 1020. In at least one embodiment, memory 1020 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 1020 may store instructions 1019 and / or data 1021 represented by data signals that may be executed by processor 1002.

[0212] In at least one embodiment, the system logic chip can be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1016, and the processor 1002 can communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 can provide a high bandwidth memory path 1018 to the memory 1020 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1016 can initiate data signals between the processor 1002, the memory 1020, and other components in the computer system 1000, and bridge data signals between the processor bus 1010, the memory 1020, and the system I / O 1022. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1016 may be coupled to the memory 1020 via a high bandwidth memory path 1018 , and the graphics / video card 1012 may be coupled to the MCH 1016 via an Accelerated Graphics Port (“AGP”) interconnect 1014 .

[0213] In at least one embodiment, computer system 1000 may use system I / O 1022 as a proprietary hub interface bus to couple MCH 1016 to I / O controller hub ("ICH") 1030. In at least one embodiment, ICH 1030 may provide direct connection to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1020, chipsets, and processor 1002. In at least one embodiment, examples may include, but are not limited to, an audio controller 1029, a firmware hub ("FlashBIOS") 1028, a wireless transceiver 1026, a data store 1024, a traditional I / O controller 1023 including a user input and keyboard interface, a serial expansion port 1027 (e.g., a universal serial bus (USB) port), and a network controller 1034. In at least one embodiment, data store 1024 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0214] Fig.10 A system is shown that includes interconnected hardware devices or "chips", or an exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Fig.10The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1000 are interconnected using a compute express link (CXL) interconnect.

[0215] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. Fig. 7A and / or Figure 7B Provide details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be Fig.10 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0216] In at least one embodiment, the Fig.10 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0217] Fig.11 1 is a block diagram illustrating an electronic device 1100 for utilizing a processor 1110 according to at least one embodiment. In at least one embodiment, the electronic device 1100 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0218] In at least one embodiment, system 1100 may include, but is not limited to, a processor 1110 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 1110 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High-Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus.

[0219] Fig.11 A system is shown that includes interconnected hardware devices or "chips", or an exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Fig.11 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.11One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0220] In at least one embodiment, Fig.11 It may include a display 1124, a touch screen 1125, a touch pad 1130, a near field communication unit (“NFC”) 1145, a sensor hub 1140, a thermal sensor 1146, a fast chipset (“EC”) 1135, a trusted platform module (“TPM”) 1138, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1122, a DSP 1160, a drive “SSD or HDD”) 1120 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1150, a Bluetooth unit 1152, a wireless wide area network unit (“WWAN”) 1156, a global positioning system (GPS) 1155, a camera (“USB 3.0 camera”) 1154 (e.g., a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1115 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0221] In at least one embodiment, other components may be communicatively coupled to the processor 1110 through the components described above. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to the sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and a touchpad 1130 may be communicatively coupled to the EC 1135. In at least one embodiment, a speaker 1163, an earphone 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1162, which in turn may be communicatively coupled to the DSP 1160. In at least one embodiment, the audio unit 1162 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1157 may be communicatively coupled to the WWAN unit 1156. In at least one embodiment, components such as the WLAN unit 1150 and the Bluetooth unit 1152 and the WWAN unit 1156 may be implemented as a next generation form factor (NGFF).

[0222] Reasoning and / or training logic 711 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BProvides details about the reasoning and / or training logic 711. In at least one embodiment, the reasoning and / or training logic 711 may be in the system Fig.11 for use in reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0223] In at least one embodiment, the Fig.11 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0224] Fig.12 A computer system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1200 is configured to implement the various processes and methods described throughout this disclosure.

[0225] In at least one embodiment, computer system 1200 includes, but is not limited to, at least one central processing unit ("CPU") 1202 connected to a communication bus 1210 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1200 includes, but is not limited to, main memory 1204 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1204 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1222 provides an interface to other computing devices and networks for receiving data using computer system 1200 and transmitting data to other systems.

[0226] In at least one embodiment, computer system 1200 includes, but is not limited to, input device 1208, parallel processing system 1212, and display device 1206, which may be implemented using cathode ray tubes ("CRT"), liquid crystal displays ("LCD"), light emitting diodes ("LED"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1208, such as a keyboard, mouse, touch pad, microphone, etc. In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system.

[0227] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BProvides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Fig.12 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0228] In at least one embodiment, the Fig.12 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0229] Fig.13 A computer system 1300 according to at least one embodiment is shown. In at least one embodiment, the computer system 1300 includes, but is not limited to, a computer 1310 and a USB disk 1320. In at least one embodiment, the computer 1310 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1310 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0230] In at least one embodiment, the USB disk 1320 includes, but is not limited to, a processing unit 1330, a USB interface 1340, and a USB interface logic 1350. In at least one embodiment, the processing unit 1330 may be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 1330 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1330 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1330 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing core 1330 is a visual processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0231] In at least one embodiment, USB interface 1340 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1340 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1350 can include any number and type of logic that enables processing unit 1330 to connect to a device (e.g., computer 1310) via USB connector 1340.

[0232] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Provides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Fig.13 In some embodiments, the present invention provides a method for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures calculated using neural network training operations, or neural network use cases described herein.

[0233] In at least one embodiment, the Fig.13 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0234] Fig.14 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In at least one embodiment, other logic and circuits may be included in addition to what is shown, such as additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0235] Fig.14 1 is a block diagram illustrating an exemplary system-on-chip (SOC) integrated circuit 1400 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1400 includes peripheral or bus logic, including a USB controller 1425, a UART controller 1430, a SPI / SDIO controller 1435, and an I2S / I2C controller 1440. In at least one embodiment, the integrated circuit 1400 may include a display device 1445, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industry processor interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash subsystem 1460 including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 to access SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1470 .

[0236] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A 7B provides details regarding the inference and / or training logic 715. In at least one embodiment, the inference and / or training logic 715 may be used in the integrated circuit 1400 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0237] In at least one embodiment, the Fig.14 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0238] Fig.15A An exemplary architecture is shown in which multiple GPUs 1510-1513 are communicatively coupled to multiple multi-core processors 1505-1506 via high-speed links 1540-1543 (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540-1543 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0239] In addition, in at least one embodiment, two or more GPUs 1510-1513 are interconnected via high-speed links 1529-1530, which may be implemented using the same or different protocols / links as used for high-speed links 1540-1543. Similarly, in at least one embodiment, two or more multi-core processors 1505-1506 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, in at least one embodiment, Fig.15A All communications between the various system components shown in can be accomplished using the same protocols / links (eg, through a common interconnect structure).

[0240] In at least one embodiment, each multi-core processor 1505-1506 is communicatively coupled to processor memory 1501-1502 via memory interconnects 1526-1527, respectively, and each GPU 1510-1513 is communicatively coupled to GPU memory 1520-1523 via GPU memory interconnects 1550-1553, respectively. In at least one embodiment, memory interconnects 1526-1527 and 1550-1553 may utilize the same or different memory access technologies. In at least one embodiment, by way of example and not limitation, processor memory 1501-1502 and GPU memory 1520-1523 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM) and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1501-1502 may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0241] As described herein, although the various multiprocessors 1505 and GPUs 1510 may be physically coupled to specific memories 1501, 1520, respectively, in at least one embodiment, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. In at least one embodiment, for example, processor memories 1501-1502 may each include 64GB of system memory address space and GPU memories 1520-1523 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0242] Fig. 15B Additional details for interconnection between multi-core processor 1507 and graphics acceleration module 1546 are shown according to an exemplary embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to processor 1507 via high-speed link 1540. In at least one embodiment, graphics acceleration module 1546 may optionally be integrated on the same package or chip as processor 1507.

[0243] In at least one embodiment, the processor 1507 is described to include a plurality of cores 1560A-1560D, each core having a translation lookaside buffer 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components not shown for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. In at least one embodiment, in addition, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by each group of cores 1560A-1560D. For example, at least one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches, wherein two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include Fig.15A Processor memory 1501-1502 in.

[0244] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1562A-1562D, 1556 and the system memory 1514 via inter-core communications over the coherency bus 1564. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate in response to detecting a read or write to a particular cache line over the coherency bus 1564. In at least one embodiment, a cache snooping protocol is implemented over the coherency bus 1564 to snoop cache accesses.

[0245] In at least one embodiment, the proxy circuit 1525 communicatively couples the graphics acceleration module 1546 to the coherence bus 1564, thereby allowing the graphics acceleration module 1546 to participate in the cache coherence protocol as a peer of the cores 1560A-1560D. In at least one embodiment, the interface 1535 provides a connection to the proxy circuit 1525 via a high-speed link 1540 (e.g., a PCIe bus, NVLink, etc.), and the interface 1537 connects the graphics acceleration module 1546 to the link 1540.

[0246] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1531, 1532, N of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1531, 1532, N may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1531, 1532, N may optionally include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU with multiple graphics processing engines 1531, 1532, N, or the graphics processing engines 1531, 1532, N may be individual GPUs integrated on a common package, line card, or chip.

[0247] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing the system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, the cache 1538 stores commands and data for efficient access by the graphics processing engines 1531-1532, N. In at least one embodiment, a fetch unit 1544 may be used to keep data stored in the cache 1538 and graphics memory 1533-1534, M consistent with the core caches 1562A-1562D, 1556 and the system memory 1514. As previously described, this task may be accomplished via proxy circuitry 1525 acting on behalf of cache 1538 and graphics memory 1533-1534, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0248] In at least one embodiment, a set of registers 1545 stores context data for threads executed by the graphics processing engines 1531-1532, N, and context management circuitry 1548 manages thread contexts. In at least one embodiment, for example, context management circuitry 1548 may perform save and restore operations to save and restore contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the graphics processing engine can execute the second thread). In at least one embodiment, for example, upon context switching, context management circuitry 1548 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). In at least one embodiment, it may subsequently restore register values ​​upon returning to the context. In at least one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0249] In at least one embodiment, the virtual / effective address from the graphics processing engine 1531 is converted by the MMU 1539 into a real / physical address in the system memory 1514. In at least one embodiment, the accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 can be dedicated to a single application executed on the processor 1507, or can be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1531-1532, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0250] In at least one embodiment, the accelerator integrated circuit 1536 performs as a bridge to the system of graphics acceleration modules 1546 and provides address translation and system memory cache services. In addition, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engines 1531-1532.

[0251] In at least one embodiment, any host processor can directly address these resources using effective address values ​​because the hardware resources of graphics processing engines 1531-1532 are explicitly mapped to the real address space seen by host processor 1507. In at least one embodiment, one function of accelerator integrated circuit 1536 is to physically separate graphics processing engines 1531-1532, N so that they appear to the system as independent units.

[0252] In at least one embodiment, one or more graphics memories 1533-1534, M are coupled to each graphics processing engine 1531-1532, N, respectively, and N = M. In at least one embodiment, graphics memories 1533-1534, M store instructions and data, which are processed by each graphics processing engine 1531-1532, N. In at least one embodiment, graphics memories 1533-1534, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0253] In at least one embodiment, to reduce data traffic on link 1540, a biasing technique is used to ensure that the data stored in graphics memory 1533-1534, M is the data most frequently used by graphics processing engines 1531-1532, N, and preferably not used (at least not frequently) by cores 1560A-1560D. In at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1531-1532, N) in caches 1562A-1562D, 1556 cores and system memory 1514.

[0254] Fig. 15C Another exemplary embodiment is shown in which an accelerator integrated circuit 1536 is integrated into the processor 1507, wherein the graphics processing engines 1531-1532, N communicate directly with the accelerator integrated circuit 1536 via the interface 1537 and the interface 1535 (which can also be used for any form of bus or interface protocol) through the high-speed link 1540. In at least one embodiment, the accelerator integrated circuit 1536 can perform operations related to Fig. 15B The same operations as described above. However, due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556, higher throughput is possible. In at least one embodiment, different programming models are supported, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0255] In at least one embodiment, the graphics processing engines 1531-1532, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 1531-1532, N, thereby providing virtualization within a VM / partition.

[0256] In at least one embodiment, the graphics processing engines 1531-1532, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize the graphics processing engines 1531-1532, N to allow each operating system to access. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns the graphics processing engines 1531-1532, N. In at least one embodiment, the operating system can virtualize the graphics processing engines 1531-1532, N to provide access to each process or application.

[0257] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engines 1531-1532, N use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1514 and can be addressed using the effective address to real address conversion techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1531-1532, N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0258] Fig.15D An exemplary accelerator integrated slice 1590 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1536. In at least one embodiment, the application is an effective address space 1582 in the system memory 1514, which stores a process element 1583. In at least one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executed on the processor 1507. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In one embodiment, the work descriptor (WD) 1584 contained in the process element 1583 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0259] In at least one embodiment, the graphics acceleration module 1546 and / or the individual graphics processing engines 1531-1532, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting the process state and sending the WD 1584 to the graphics acceleration module 1546 to start a job in a virtualized environment can be included.

[0260] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, since when a graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, when a graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0261] In operation, the WD acquisition unit 1591 in the accelerator integrated slice 1590 acquires the next WD 1584, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, the data from the WD 1584 can be stored in the register 1545 and used by the MMU 1539, the interrupt management circuit 1547 and / or the context management circuit 1548, as shown. In at least one embodiment, for example, an embodiment of the MMU 1539 includes a segment / page roaming circuit for accessing the segment / page table 1586 within the OS virtual address space 1585. In at least one embodiment, the interrupt management circuit 1547 can process the interrupt event 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, the effective address 1593 generated by the graphics processing engine 1531-1532, N is converted to a real address by the MMU 1539.

[0262] In at least one embodiment, the same set of registers 1545 is replicated for each graphics processing engine 1531-1532, N and / or graphics acceleration module 1546 and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integrated slice 1590. In at least one embodiment, exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0263]

[0264] In at least one embodiment, exemplary registers that may be initialized by the operating system are shown in Table 2.

[0265]

[0266] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531-1532, N. In at least one embodiment, it contains all the information needed by the graphics processing engine 1531-1532, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0267] Fig.15E Additional details of at least one embodiment of the sharing model are shown. In at least one embodiment, a hypervisor real address space 1598 is included, in which a process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 can be accessed via a hypervisor 1596, which virtualizes a graphics acceleration module engine for an operating system 1595.

[0268] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models where the graphics acceleration module 1546 is shared by multiple processes and partitions: time-slice sharing and graphics-directed sharing.

[0269] In at least one embodiment, in this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, in order for the graphics acceleration module 1546 to support virtualization of the hypervisor 1596, the graphics acceleration module 1546 may comply with the following provisions: 1) the application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, 2) the graphics acceleration module 1546 guarantees that the application's job request is completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and 3) fairness between the graphics acceleration module 1546 processes must be ensured when operating in a directed shared programming model.

[0270] In at least one embodiment, the application 1580 is required to make an operating system 1595 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1546 and can take the form of a graphics acceleration module 1546 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1546. In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is not needed if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0271] In at least one embodiment, upon receiving the system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 calls the hypervisor 1596 using the information shown in Table 3.

[0272]

[0273] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1596 verifies that operating system 1595 has registered and been granted permission to use graphics acceleration module 1546. Then, in at least one embodiment, hypervisor 1596 places process element 1583 into a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0274]

[0275]

[0276] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1590 registers 1545 .

[0277] In at least one embodiment, Fig.15F As shown, a unified memory is used, which can be addressed via a common virtual memory address space for accessing physical processor memories 1501-1502 and GPU memories 1520-1523. In this implementation, operations executed on GPUs 1510-1513 use the same virtual / effective memory address space to access processor memories 1501-1502, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501, a second portion is allocated to second processor memory 1502, a third portion is allocated to GPU memory 1520, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as an effective address space) is thus distributed in each of processor memories 1501-1502 and GPU memories 1520-1523, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0278] In at least one embodiment, bias / coherency management circuits 1594A-1594E within one or more MMUs 1539A-1539E ensure cache coherency between caches of one or more host processors (e.g., 1505) and GPUs 1510-1513 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.15F Multiple instances of bias / consistency management circuits 1594A- 1594E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 1505 and / or within an accelerator integrated circuit 1536 .

[0279] One embodiment allows the GPU attached memory 1520-1523 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance defects associated with full system cache coherence. In at least one embodiment, the ability to access the GPU attached memory 1520-1523 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, the arrangement allows the host processor 1505 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU attached memory 1520-1523 without cache coherence overhead may be critical to the execution time of the offloaded calculation. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1510-1513. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0280] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1510-1513 (e.g., for caching frequently / recently used entries of the bias table), the bias table can be implemented in the stolen memory range of one or more GPU attached memories 1520-1523. In at least one embodiment, alternatively, the entire bias table can be maintained within the GPU.

[0281] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU additional memory 1520-1523 is accessed, resulting in the following operations. In at least one embodiment, local requests from GPUs 1510-1513 to find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 1520-1523. In at least one embodiment, local requests from GPUs to find their pages in the host bias are forwarded to processors 1505 (e.g., via the high-speed link described above). In at least one embodiment, the request from processor 1505 to find the requested page in the host processor bias completes a request similar to a normal memory read. In at least one embodiment, alternatively, a request pointing to a GPU bias page can be forwarded to GPUs 1510-1513. In at least one embodiment, if the GPU is not currently using the page, the GPU can then migrate the page to the host processor bias. In at least one embodiment, the bias state of the page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or in limited cases by a purely hardware-based mechanism.

[0282] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that then calls the GPU's device driver, which then sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in certain migrations, perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1505 bias to GPU bias, but not for the reverse migration.

[0283] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU biased pages that cannot be cached by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is beneficial to ensure that GPU biased pages are pages required by the GPU and not by the host processor 1505, and vice versa.

[0284] In at least one embodiment, one or more hardware structures 715 are used to perform one or more embodiments. Fig. 7A and / or 7B provides details regarding hardware structure (x)715.

[0285] In at least one embodiment, the Figures 15A-15FA GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0286] Figures 16A-16B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0287] Fig.16A and 16B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.16A An exemplary graphics processor 1610 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Fig. 16B An additional exemplary graphics processor 1640 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Fig.16A The graphics processor 1610 is a low power graphics processor core. In at least one embodiment, Fig. 16B The graphics processor 1640 is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1610, 1640 may be Fig.14 A variant of graphics processor 1410.

[0288] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D to 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 can execute different shader programs via separate logic, so that the vertex processor 1605 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1615A-1615N use the primitives and vertex data generated by the vertex processor 1605 to generate a frame buffer displayed on a display device. In at least one embodiment, one or more fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0289] In at least one embodiment, graphics processor 1610 additionally includes one or more memory management units (MMUs) 1620A-1620B, one or more caches 1625A-1625B, and one or more circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide a mapping of virtual to physical addresses for graphics processor 1610, including for vertex processor 1605 and / or fragment processors 1615A-1615N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B may synchronize with other MMUs within the system, including with Fig.14 One or more MMUs associated with one or more application processors 1405, image processor 1415, and / or video processor 1420 enable each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable graphics processor 1610 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0290] In at least one embodiment, graphics processor 1640 includes Fig.16AOne or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B of a graphics processor 1610. In at least one embodiment, graphics processor 1640 includes one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F, to 1655N-1 and 1655N) that provide a unified shader core architecture in which a single core or a type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1655A-1655N and a tiling unit 1658 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0291] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Provides details about the inference and / or training logic 715. In at least one embodiment, the inference and / or training logic 715 may be implemented in an integrated circuit. Fig.16A and / or Fig. 16B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case described herein.

[0292] In at least one embodiment, the Fig.16A A GPU-based CRC processing unit is used in a system with 16B or 16B to perform CRC generation and / or checking.

[0293] Figures 17A-17B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Fig.17A shows that it can be included in Fig.14 Graphics core 1700 within graphics processor 1410 of FIG. 1400 and, in at least one embodiment, may be such as Fig. 16B Unified shader cores 1655A-1655N are shown. Fig. 17B A highly parallel general purpose graphics processing unit 1730 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0294] In at least one embodiment, graphics core 1700 includes a shared instruction cache 1702, texture units 1718, and cache / shared memory 1720 that are common to execution resources within graphics core 1700. In at least one embodiment, graphics core 1700 may include multiple slices 1701A-1701N or partitions of each core, and the graphics processor may include multiple instances of graphics core 1700. In at least one embodiment, slices 1701A-1701N may include support logic including a local instruction cache 1704A-1704N, a thread scheduler 1706A-1706N, a thread dispatcher 1708A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional function units (AFU 1712A-1712N), floating point units (FPU 1714A-1714N), integer arithmetic logic units (ALU 1716A-1716N), address calculation units (ACU 1713A-1713N), double precision floating point units (DPFPU 1715A-1715N), and matrix processing units (MPU 1717A-1717N).

[0295] In at least one embodiment, the FPU 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1715A-1715N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1717-1717N can perform various matrix operations to accelerate machine learning application frameworks, including enabling general matrix-to-matrix multiplication (GEMM) to support acceleration. In at least one embodiment, the AFU 1712A-1712N can perform additional logical operations that are not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0296] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BDetails are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in graphics core 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0297] Fig. 17B A general purpose processing unit (GPGPU) 1730 in at least one embodiment is shown, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1730 can be directly linked to other instances of GPGPU 1730 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1730 includes a host interface 1732 to enable connection with a host processor. In at least one embodiment, host interface 1732 is a PCI Express interface. In at least one embodiment, host interface 1732 can be a manufacturer-specific communication interface or communication structure. In at least one embodiment, GPGPU 1730 receives commands from a host processor and uses a global scheduler 1734 to assign execution threads associated with those commands to a group of computing clusters 1736A-1736H. In at least one embodiment, computing clusters 1736A-1736H share cache memory 1738. In at least one embodiment, cache memory 1738 may be used as a higher level cache for cache memory within compute clusters 1736A-1736H.

[0298] In at least one embodiment, GPGPU 1730 includes memory 1744A-1744B coupled to compute clusters 1736A-1736H via a set of memory controllers 1742A-1742B. In at least one embodiment, memory 1744A-1744B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0299] In at least one embodiment, computing clusters 1736A-1736H each include a set of graphics cores, such as Fig.17AThe graphics core 1700 may include multiple types of integer and floating point logic units that can perform computational operations at various precision ranges of the computer, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each computing cluster 1736A-1736H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of these floating point units may be configured to perform 64-bit floating point operations.

[0300] In at least one embodiment, multiple instances of GPGPU 1730 can be configured to function as a computing cluster. In at least one embodiment, the communications used by computing clusters 1736A-1736H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1730 communicate through a host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 with a GPU link 1740, enabling direct connection to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 are located in separate data processing systems and communicate through network devices accessible through host interface 1732. In at least one embodiment, GPU link 1740 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1732 .

[0301] In at least one embodiment, the GPGPU 1730 may be configured to train a neural network. In at least one embodiment, the GPGPU 1730 may be used within an inference platform. In at least one embodiment, in the case where the GPGPU 1730 is used for inference, the GPGPU 1730 may include fewer computing clusters 1736A-1736H relative to when the GPGPU 1730 is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1744A-1744B may differ between the inference and training configurations, with higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1730 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations of a deployed neural network.

[0302] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in GPGPU 1730 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0303] In at least one embodiment, the Fig.17A or Fig. 17B A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0304] Fig.18 A block diagram of a computer system 1800 according to at least one embodiment is shown. In at least one embodiment, the computer system 1800 includes a processing subsystem 1801 having one or more processors 1802 and a system memory 1804, which communicates via an interconnect path that may include a memory hub 1805. In at least one embodiment, the memory hub 1805 may be a separate component within a chipset component, or may be integrated within one or more processors 1802. In at least one embodiment, the memory hub 1805 is coupled to an I / O subsystem 1811 via a communication link 1806. In one embodiment, the I / O subsystem 1811 includes an I / O hub 1807, which may enable the computer system 1800 to receive input from one or more input devices 1808. In at least one embodiment, the I / O hub 1807 may enable a display controller, which may be included in one or more processors 1802, to provide output to one or more display devices 1810A. In at least one embodiment, the one or more display devices 1810A coupled to the I / O hub 1807 may include local, internal, or embedded display devices.

[0305] In at least one embodiment, the processing subsystem 1801 includes one or more parallel processors 1812 coupled to a memory hub 1805 via a bus or other communication link 1813, such as Fig.18. In at least one embodiment, the communication link 1813 may use any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or may be a vendor-specific communication interface or communication structure. In at least one embodiment, one or more parallel processors 1812 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 1812 form a graphics processing subsystem that may output pixels to one of one or more display devices 1810A coupled via an I / O hub 1807. In at least one embodiment, the parallel processor 1812 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1810B.

[0306] In at least one embodiment, a system storage unit 1814 can be connected to the I / O hub 1807 to provide a storage mechanism for the computer system 1800. In at least one embodiment, an I / O switch 1816 can be used to provide an interface mechanism to enable connections between the I / O hub 1807 and other components, such as a network adapter 1818 and / or a wireless network adapter 1819 that can be integrated into the platform, as well as various other devices that can be added through one or more additional devices 1820. In at least one embodiment, the network adapter 1818 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1819 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0307] In at least one embodiment, computer system 1800 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1807. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Fig.18 The communication paths between the various components in the NV-Link high-speed interconnect or interconnect protocol.

[0308] In at least one embodiment, one or more parallel processors 1812 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, parallel processors 1812 include circuits optimized for general processing. In at least one embodiment, the components of computer system 1800 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1812, memory hub 1805, processor 1802, and I / O hub 1807 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1800 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1800 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0309] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Provide details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be Fig.18 The system 1800 is used in order to perform reasoning or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0310] In at least one embodiment, the Fig.18 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0311] processor

[0312] Fig.19A 1900 according to at least one embodiment. In at least one embodiment, various components of parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, parallel processor 1900 is shown as a processor according to at least one embodiment. Fig.18 A variation of the one or more parallel processors 1812 shown.

[0313] In at least one embodiment, parallel processor 1900 includes parallel processing unit 1902. In at least one embodiment, parallel processing unit 1902 includes I / O unit 1904, which enables communication with other devices, including other instances of parallel processing unit 1902. In at least one embodiment, I / O unit 1904 can be directly connected to other devices. In at least one embodiment, I / O unit 1904 connects to other devices by using a hub or switch interface (e.g., memory hub 1905). In at least one embodiment, the connection between memory hub 1905 and I / O unit 1904 forms communication link 1813, such as Fig.18 In at least one embodiment, the I / O unit 1904 is connected to a host interface 1906 and a memory crossbar switch 1916, wherein the host interface 1906 receives commands for performing processing operations and the memory crossbar switch 1916 receives commands for performing memory operations.

[0314] In at least one embodiment, when the host interface 1906 receives the command buffer via the I / O unit 1904, the host interface 1906 can direct work operations to execute those commands to the front end 1908. In at least one embodiment, the front end 1908 is coupled with a scheduler 1910, which is configured to distribute commands or other work items to the processing cluster array 1912. In at least one embodiment, the scheduler 1910 ensures that the processing cluster array 1912 is properly configured and in a valid state before assigning tasks to the processing cluster array 1912. In at least one embodiment, the scheduler 1910 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 1912. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 1912 through one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1912 by scheduler 1910 logic within a microcontroller that includes scheduler 1910 .

[0315] In at least one embodiment, processing cluster array 1912 may include up to "N" processing clusters (e.g., cluster 1914A, cluster 1914B, through cluster 1914N). In at least one embodiment, each cluster 1914A-1914N of processing cluster array 1912 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1910 may allocate work to clusters 1914A-1914N of processing cluster array 1912 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1910, or may be assisted in part by compiler logic during compilation of program logic configured to be executed by processing cluster array 1912. In at least one embodiment, different clusters 1914A-1914N of processing cluster array 1912 may be allocated to process different types of programs or to perform different types of computations.

[0316] In at least one embodiment, processing cluster array 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1912 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1912 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0317] In at least one embodiment, processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1912 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1912 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1902 may transfer data from system memory via I / O units 1904 for processing. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 1922) during processing and then written back to system memory.

[0318] In at least one embodiment, when parallel processing unit 1902 is used to perform graphics processing, scheduler 1910 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1914A-1914N of processing cluster array 1912. In at least one embodiment, portions of processing cluster array 1912 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1914A-1914N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1914A-1914N for further processing.

[0319] In at least one embodiment, processing cluster array 1912 may receive processing tasks to be performed via scheduler 1910, which receives commands defining processing tasks from front end 1908. In at least one embodiment, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1910 may be configured to obtain an index corresponding to a task, or may receive an index from front end 1908. In at least one embodiment, front end 1908 may be configured to ensure that processing cluster array 1912 is configured to a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push-buffer, etc.).

[0320] In at least one embodiment, each of the one or more instances of parallel processing unit 1902 can be coupled to parallel processor memory 1922. In at least one embodiment, parallel processor memory 1922 can be accessed via memory crossbar switch 1916, which can receive memory requests from processing cluster array 1912 and I / O unit 1904. In at least one embodiment, memory crossbar switch 1916 can access parallel processor memory 1922 via memory interface 1918. In at least one embodiment, memory interface 1918 can include multiple partition units (e.g., partition unit 1920A, partition unit 1920B to partition unit 1920N), which can each be coupled to a portion of parallel processor memory 1922 (e.g., memory units). In at least one embodiment, the plurality of partition units 1920A-1920N are configured to be equal to the number of memory cells, such that the first partition unit 1920A has a corresponding first memory cell 1924A, the second partition unit 1920B has a corresponding memory cell 1924B, and the Nth partition unit 1920N has a corresponding Nth memory cell 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory devices.

[0321] In at least one embodiment, memory units 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 1924A-1924N, allowing partition units 1920A-1920N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 1922. In at least one embodiment, local instances of parallel processor memory 1922 may be excluded in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0322] In at least one embodiment, any of the clusters 1914A-1914N of the processing cluster array 1912 can process data to be written to any memory unit 1924A-1924N within the parallel processor memory 1922. In at least one embodiment, the memory crossbar 1916 can be configured to transmit the output of each cluster 1914A-1914N to any partition unit 1920A-1920N or another cluster 1914A-1914N, and the cluster 1914A-1914N can perform other processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with the memory interface 1918 through the memory crossbar 1916 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 1916 has connections to memory interface 1918 to communicate with I / O unit 1904, and connections to local instances of parallel processor memory 1922 to enable processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory that is not local to parallel processing unit 1902. In at least one embodiment, memory crossbar switch 1916 may use virtual channels to separate traffic flows between clusters 1914A-1914N and partition units 1920A-1920N.

[0323] In at least one embodiment, multiple instances of parallel processing unit 1902 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1902 may include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1902 or parallel processor 1900 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0324] Fig.19B is a block diagram of a partition unit 1920 according to at least one embodiment. In at least one embodiment, the partition unit 1920 is Fig.19A1920N). In at least one embodiment, partition unit 1920 includes L2 cache 1921, frame buffer interface 1925, and ROP 1926 (raster operation unit). In at least one embodiment, L2 cache 1921 is a read / write cache that is configured to perform load and store operations received from memory crossbar switch 1916 and ROP 1926. In at least one embodiment, L2 cache 1921 outputs read misses and urgent write-back requests to frame buffer interface 1925 for processing. In at least one embodiment, updates may also be sent to the frame buffer via frame buffer interface 1925 for processing. In at least one embodiment, frame buffer interface 1925 communicates with memory units (such as ROPs) in parallel processor memory. Fig.19A interacts with one of the memory units 1924A-1924N (e.g., within parallel processor memory 1922).

[0325] In at least one embodiment, ROP 1926 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1926 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1926 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1926 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0326] In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., Fig.19A In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 1916 rather than pixel fragment data transmission. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig. 22 2210), routed by processor 2202 for further processing, or by Fig.19A The processing entities within parallel processor 1900 are routed for further processing.

[0327] Fig.19C is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig.19AIn at least one embodiment, processing cluster 1914 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0328] In at least one embodiment, the operation of the processing cluster 1914 can be controlled by a pipeline manager 1932 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1932 Fig.19A The scheduler 1910 receives instructions and manages the execution of these instructions through the graphics multiprocessor 1934 and / or the texture unit 1936. In at least one embodiment, the graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 1914. In at least one embodiment, one or more instances of the graphics multiprocessor 1934 may be included in the processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 may process data, and the data crossbar 1940 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1932 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 1940.

[0329] In at least one embodiment, each graphics multiprocessor 1934 within a processing cluster 1914 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, these same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0330] In at least one embodiment, the instructions transmitted to the processing cluster 1914 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes the program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1934. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle of the thread group being processed. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1934, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1934.

[0331] In at least one embodiment, graphics multiprocessor 1934 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1934 can abandon the internal cache and use cache memory (e.g., L1 cache 1948) within processing cluster 1914. In at least one embodiment, each graphics multiprocessor 1934 can also access partition units (e.g., Fig.19A 1920A-1920N) that are shared between all processing clusters 1914 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1934 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1902 can be used as global memory. In at least one embodiment, processing cluster 1914 includes multiple instances of graphics multiprocessor 1934, which can share common instructions and data that can be stored in L1 cache 1948.

[0332] In at least one embodiment, each processing cluster 1914 may include a memory management unit ("MMU") 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1945 may reside in Fig.19A1918. In at least one embodiment, the MMU 1945 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more on tile partitioning) and cache line indexes (if used). In at least one embodiment, the MMU 1945 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1934 or L1 cache 1948 or processing cluster 1914. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0333] In at least one embodiment, the processing clusters 1914 can be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1934, and the texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to a data crossbar 1940 to provide the processed tasks to another processing cluster 1914 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1916. In at least one embodiment, a preROP 1942 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1934, direct the data to a ROP unit, which can communicate with a partition unit (e.g., Fig.19A In at least one embodiment, the PreROP 1942 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0334] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in graphics processing cluster 1914 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0335] Fig.19D A graphics multiprocessor 1934 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1934 is coupled to a pipeline manager 1932 of a processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 has an execution pipeline that includes, but is not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966. In at least one embodiment, the GPGPU cores 1962 and the load / store units 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968.

[0336] In at least one embodiment, the instruction cache 1952 receives a stream of instructions to be executed from the pipeline manager 1932. In at least one embodiment, the instructions are cached in the instruction cache 1952 and dispatched for execution by the instruction unit 1954. In one embodiment, the instruction unit 1954 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 1962. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1956 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1966.

[0337] In at least one embodiment, register file 1958 provides a set of registers for the functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands for data paths connected to the functional units (e.g., GPGPU core 1962, load / store unit 1966) of graphics multiprocessor 1934. In at least one embodiment, register file 1958 is divided between each functional unit such that a dedicated portion of register file 1958 is allocated to each functional unit. In at least one embodiment, register file 1958 is divided between different warps being executed by graphics multiprocessor 1934.

[0338] In at least one embodiment, the GPGPU cores 1962 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1934. In at least one embodiment, the GPGPU cores 1962 may be similar in architecture or the architecture may be different. In at least one embodiment, the first portion of the GPGPU core 1962 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1934 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1962 may also include fixed or special-function logic.

[0339] In at least one embodiment, the GPGPU core 1962 includes SIMD logic capable of executing a single instruction to multiple sets of data. In at least one embodiment, the GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0340] In at least one embodiment, the memory and cache interconnect 1968 is an interconnect network that connects each functional unit of the graphics multiprocessor 1934 to the register file 1958 and the shared memory 1970. In at least one embodiment, the memory and cache interconnect 1968 is a crossbar interconnect that allows the load / store unit 1966 to implement load and store operations between the shared memory 1970 and the register file 1958. In at least one embodiment, the register file 1958 can operate at the same frequency as the GPGPU core 1962, so that the latency of data transfer between the GPGPU core 1962 and the register file 1958 is very low. In at least one embodiment, the shared memory 1970 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1934. In at least one embodiment, the cache memory 1972 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1936. In at least one embodiment, the shared memory 1970 can also be used as a program managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1972, threads executing on GPGPU core 1962 may programmatically store data in shared memory.

[0341] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (e.g., inside a package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0342] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BDetails are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in graphics multiprocessor 1934 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0343] In at least one embodiment, the Figures 19A to 19D A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0344] Fig. 20 A multi-GPU computing system 2000 is shown according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2000 may include a processor 2002 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, the host interface switch 2004 is a PCI Express switch device that couples the processor 2002 to a PCI Express bus, and the processor 2002 may communicate with the GPGPUs 2006A-D via the PCI Express bus. In at least one embodiment, the GPGPUs 2006A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2016. In at least one embodiment, the GPU-to-GPU links 2016 are connected to each of the GPGPUs 2006A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU links 2016 enable direct communication between each GPGPU 2006A-D without communicating through the host interface bus 2004 to which the processor 2002 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2016, host interface bus 2004 remains available for system memory access or communication with other instances of multi-GPU computing system 2000, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2006A-D are connected to processor 2002 via host interface switch 2004, in at least one embodiment, processor 2002 includes direct support for P2P GPU link 2016 and can connect directly to GPGPUs 2006A-D.

[0345] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BDetails are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in multi-GPU computing system 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0346] In at least one embodiment, the Fig. 20 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0347] Fig.21 is a block diagram of a graphics processor 2100 according to at least one embodiment. In at least one embodiment, graphics processor 2100 includes ring interconnect 2102, pipeline front end 2104, media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, ring interconnect 2102 couples graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2100 is one of many processors integrated within a multi-core processing system.

[0348] In at least one embodiment, the graphics processor 2100 receives batches of commands via a ring interconnect 2102. In at least one embodiment, the incoming commands are interpreted by a command streamer 2103 in a pipeline front end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2103 provides the commands to a geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command streamer 2103 provides the commands to a video front end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2133 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate execution threads for thread execution resources provided by at least one graphics core 2180 .

[0349] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources with modular cores 2180A-2180N (sometimes referred to as core slices), each with multiple sub-cores 2150A-550N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 can have any number of graphics cores 2180A to 2180N. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A, which has at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor with a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each graphics core including a group of first sub-cores 2150A 2150N and a group of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units 2152A, 2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each of the sub-cores 2150A-2150N, 2160A, 2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0350] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details are provided regarding the inference and / or training logic 715. In at least one embodiment, the inference and / or training logic 715 may be used in the graphics processor 2100 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0351] In at least one embodiment, the Fig.21 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0352] Fig. 22is a block diagram illustrating a microarchitecture for a processor 2200 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2200 may execute instructions including x86 instructions, ARM instructions, special instructions for an application specific integrated circuit (ASIC), etc. In at least one embodiment, the processor 2200 may include registers for storing packed data, such as a 64-bit wide MMX 4800 in a microprocessor enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2200 can execute instructions to accelerate machine learning or deep learning algorithms, training, or reasoning.

[0353] In at least one embodiment, the processor 2200 includes an in-order front end ("front end") 2201 to extract instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 2201 may include several units. In at least one embodiment, an instruction prefetcher 2226 fetches instructions from a memory and provides the instructions to an instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2228 decodes the received instructions into one or more operations of so-called "microinstructions" or "microoperations" (also referred to as "micro-operations" or "microinstructions") that are executable by the machine. In at least one embodiment, the instruction decoder 2228 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2230 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters a complex instruction, microcode ROM 2232 provides the microinstructions necessary to complete the operation.

[0354] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2232. In at least one embodiment, the trace cache 2230 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 2232 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 completes the micro-operation sequencing of the instruction, the front end 2201 of the machine may resume fetching micro-operations from the trace cache 2230.

[0355] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2203 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions go down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory microinstruction queue 2242, an integer / floating point microinstruction queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2204, and a simple floating point scheduler ("simple FP scheduler") 2206. In at least one embodiment, the fast scheduler 2202, the slow / general purpose floating point scheduler 2204, and the simple floating point scheduler 2206 are also collectively referred to as "microinstruction schedulers 2202, 2204, 2206". Allocator / register renamer 2240 allocates machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, allocator / register renamer 2240 renames logical registers into entries in register files. In at least one embodiment, allocator / register renamer 2240 also allocates entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2242 for memory operations and integer / floating point microinstruction queue 2244 for non-memory operations, in front of memory scheduler 2246 and microinstruction schedulers 2202, 2204, 2206. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 determine when microinstructions are ready to execute based on the readiness of their slave input register operand sources and the availability of execution resource microinstructions that need to be completed. In at least one embodiment, fast scheduler 2202 can schedule on each half of the main clock cycle, while slow / general floating point scheduler 2204 and simple floating point scheduler 2206 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 arbitrate dispatch ports to schedule microinstructions for execution.

[0356] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / branch network 2208, floating point register file / branch network ("FP register file / branch network") 2210, address generation units ("AGU") 2212 and 2214, fast arithmetic logic units ("fast ALU") 2216 and 2218, slow arithmetic logic unit ("slow ALU") 2220, floating point ALU ("FP") 2222, and floating point move unit ("FP move") 2224. In at least one embodiment, integer register file / branch network 2208 and floating point register file / bypass network 2210 are also referred to herein as "register files 2208, 2210". In at least one embodiment, AGUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating point ALU 2222, and floating point move unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0357] In at least one embodiment, register files 2208, 2210 can be arranged between microinstruction schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222 and 2224. In at least one embodiment, integer register file / branch network 2208 performs integer operations. In at least one embodiment, floating point register file / branch network 2210 performs floating point operations. In at least one embodiment, each of register files 2208, 2210 can include but is not limited to a branch network that can bypass or forward the just completed result that has not yet been written to the register file to a new slave object. In at least one embodiment, register files 2208, 2210 can communicate data with each other. In at least one embodiment, integer register file / branch network 2208 can include but is not limited to two separate register files, one register file for low-order 32-bit data, and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2210 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands that are 64 to 128 bits wide.

[0358] In at least one embodiment, the execution units 2212, 2214, 2216, 2218, 2220, 2222, 2224 can execute instructions. In at least one embodiment, the register files 2208, 2210 store integer and floating point data operand values ​​that the microinstructions need to execute. In at least one embodiment, the processor 2200 may include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, 2224 and combinations thereof. In at least one embodiment, the floating point ALU 2222 and the floating point move unit 2224 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2222 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root and remainder micro-operations. In at least one embodiment, floating point hardware can be used to process instructions involving floating point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216, 2218. In at least one embodiment, fast ALUs 2216, 2218 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 2220 because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUS 2212, 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2222 and floating point move unit 2224 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0359] In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in processor 2200, processor 2200 can also include logic for handling memory misses. In at least one embodiment, if the data load in the data cache misses, there may be dependent operations running in the pipeline, which temporarily prevents the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0360] In at least one embodiment, "register" may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. On the contrary, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packaging data.

[0361] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details are provided regarding the inference and / or training logic 715. In at least one embodiment, part or all of the inference and / or training logic 715 may be incorporated into the execution block 2211 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the execution block 2211. In addition, in at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2211 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0362] In at least one embodiment, the Fig. 22 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0363] Fig.23 A deep learning application processor 2300 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2300 uses instructions that, if executed by the deep learning application processor 2300, cause the deep learning application processor 2300 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2300 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2300 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2300 includes, but is not limited to, processing clusters 2310(1)-2310(12), inter-chip links (“ICLs”) 2320(1)-2320(12), inter-chip controllers (“ICCs”) 2330(1)-2330(2), second generation high bandwidth memory (“HBM2”) 2340(1)-2340(4), memory controllers (“Mem Ctrlr”) 2342(1)-2342(4), high bandwidth memory physical layer (“HBM PHY”) 2344(1)-2344(4), a management controller central processing unit (“management controller CPU”) 2350, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”) 2360, peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2370, and sixteen-lane peripheral component interconnect express ports (“PCI Express”). x 16”)2380.

[0364] In at least one embodiment, the processing cluster 2310 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated at least in part based on one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2310 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2300 may include any number and type of processing clusters 2300. In at least one embodiment, the inter-chip link 2320 is bidirectional. In at least one embodiment, the inter-chip link 2320 and the inter-chip controller 2330 enable multiple deep learning application processors 2300 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2300 may include any number (including zero) and type of ICL 2320 and ICC 2330.

[0365] In at least one embodiment, HBM2 2340 provides a total of 32GB of memory. In at least one embodiment, HBM2 2340(i) is associated with both memory controller 2342(i) and HBM PHY 2344(i). In at least one embodiment, any number of HBM2 2340 can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controller 2342 and HBM PHY 2344. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2360 and DMA 2370 and / or PCIe2380 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0366] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details are provided regarding the inference and / or training logic 715. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2300. In at least one embodiment, the deep learning application processor 2300 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2300. In at least one embodiment, the processor 2300 can be used to perform one or more of the neural network use cases described herein.

[0367] Fig.242400 . In at least one embodiment, the neuromorphic processor 2400 may receive one or more inputs from a source external to the neuromorphic processor 2400. In at least one embodiment, these inputs may be transmitted to one or more neurons 2402 within the neuromorphic processor 2400. In at least one embodiment, the neurons 2402 and their components may be implemented using circuits or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, thousands of instances of neurons 2402, although any suitable number of neurons 2402 may be used. In at least one embodiment, each instance of a neuron 2402 may include a neuron input 2404 and a neuron output 2406. In at least one embodiment, a neuron 2402 may generate an output that may be transmitted to the inputs of other instances of the neuron 2402. In at least one embodiment, the neuron input 2404 and the neuron output 2406 may be interconnected via a synapse 2408.

[0368] In at least one embodiment, the neurons 2402 and synapses 2408 may be interconnected such that the neuromorphic processor 2400 operates to process or analyze information received by the neuromorphic processor 2400. In at least one embodiment, the neuron 2402 may send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2404 exceeds a threshold. In at least one embodiment, the neuron 2402 may sum or integrate the signal received at the neuron input 2404. For example, in at least one embodiment, the neuron 2402 may be implemented as a leaky integrate-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2402 may generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-trigger neuron may sum the signal received at the neuron input 2404 into a membrane potential, and may apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-trigger neuron may trigger if multiple input signals are received at the neuron input 2404 fast enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, the neuron 2402 may be implemented using circuits or logic that receive inputs, integrate the inputs to the membrane potential, and decay the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. In addition, in at least one embodiment, the neuron 2402 may include, but is not limited to, a comparator circuit or logic that generates an output spike at the neuron output 2406 when the result of applying the transfer function to the neuron input 2404 exceeds a threshold. In at least one embodiment, once the neuron 2402 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2402 may resume normal operation after a suitable period of time (or repair period).

[0369] In at least one embodiment, neurons 2402 may be interconnected via synapses 2408. In at least one embodiment, synapses 2408 may be operable to transmit a signal from an output of a first neuron 2402 to an input of a second neuron 2402. In at least one embodiment, a neuron 2402 may transmit information over more than one instance of synapse 2408. In at least one embodiment, one or more instances of a neuron output 2406 may be connected to an instance of a neuron input 2404 in the same neuron 2402 via an instance of synapse 2408. In at least one embodiment, an instance of a neuron 2402 that produces an output to be transmitted over an instance of synapse 2408 may be referred to as a "pre-synaptic neuron" relative to that instance of synapse 2408. In at least one embodiment, an instance of a neuron 2402 that receives an input transmitted through an instance of synapse 2408 may be referred to as a "post-synaptic neuron" relative to an instance of synapse 2408. In at least one embodiment, with respect to various instances of synapses 2408, because an instance of neuron 2402 can receive input from one or more instances of synapses 2408 and can also transmit output through one or more instances of synapses 2408, a single instance of neuron 2402 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0370] In at least one embodiment, neurons 2402 may be organized into one or more layers. In at least one embodiment, each instance of a neuron 2402 may have a neuron output 2406 that may fan out to one or more neuron inputs 2404 through one or more synapses 2408. In at least one embodiment, a neuron output 2406 of a neuron 2402 in a first layer 2410 may be connected to a neuron input 2404 of a neuron 2402 in a second layer 2412. In at least one embodiment, a layer 2410 may be referred to as a "feed-forward layer". In at least one embodiment, each instance of a neuron 2402 in an instance of a first layer 2410 may fan out to each instance of a neuron 2402 in a second layer 2412. In at least one embodiment, a first layer 2410 may be referred to as a "fully connected feed-forward layer". In at least one embodiment, each instance of a neuron 2402 in each instance of a second layer 2412 may fan out to less than all instances of a neuron 2402 in a third layer 2414. In at least one embodiment, a second layer 2412 may be referred to as a "sparsely connected feed-forward layer". In at least one embodiment, neurons 2402 in the second layer 2412 may fan out to neurons 2402 in multiple other layers, including also fanning out to neurons 2402 in the second layer 2412. In at least one embodiment, the second layer 2412 may be referred to as a "recurrent layer." The neuromorphic processor 2400 may include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including but not limited to sparsely connected feed-forward layers and fully connected feed-forward layers.

[0371] In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect the synapses 2408 to the neurons 2402. In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2402 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, the synapses 2408 may be connected to the neurons 2402 using an interconnect architecture such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnects and their components may be implemented using circuitry or logic.

[0372] Fig.2525 is a block diagram of a graphics processor 2500, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2500 communicates with registers on the graphics processor 2500 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2500 includes a memory interface 2514 for accessing memory. In at least one embodiment, the memory interface 2514 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0373] In at least one embodiment, the graphics processor 2500 also includes a display controller 2502 for driving display output data to a display device 2520. In at least one embodiment, the display controller 2502 includes hardware for one or more overlay planes of the display device 2520 and a combination of multiple layers of video or user interface elements. In at least one embodiment, the display device 2520 can be an internal or external display device. In at least one embodiment, the display device 2520 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2500 includes a video codec engine 2506 to encode, decode, or transcode media to, from, or between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1), and Joint Photographic Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG) formats.

[0374] In at least one embodiment, graphics processor 2500 includes a block image transfer (BLIT) engine 2504 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2510. In at least one embodiment, GPE 2510 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0375] In at least one embodiment, GPE 2510 includes a 3D pipeline 2512 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, 3D pipeline 2512 includes programmable and fixed function elements that perform various tasks and / or spawn execution threads to 3D / media subsystem 2515. While 3D pipeline 2512 can be used to perform media operations, in at least one embodiment, GPE 2510 also includes a media pipeline 2516 for performing media operations, such as video post-processing and image enhancement.

[0376] In at least one embodiment, the media pipeline 2516 includes fixed function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of or on behalf of the video codec engine 2506. In at least one embodiment, the media pipeline 2516 also includes a thread generation unit for generating threads for execution on the 3D / media subsystem 2515. In at least one embodiment, the generated threads perform computations for the media operations on one or more graphics execution units included in the 3D / media subsystem 2515.

[0377] In at least one embodiment, the 3D / media subsystem 2515 includes logic for executing threads generated by the 3D pipeline 2512 and the media pipeline 2516. In at least one embodiment, the 3D pipeline 2512 and the media pipeline 2516 send thread execution requests to the 3D / media subsystem 2515, which includes thread dispatch logic for arbitrating the various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2515 also includes shared memory, which includes registers and addressable memory to share data between threads and store output data.

[0378] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Detail is provided regarding the inference and / or training logic 715. In at least one embodiment, some or all of the inference and / or training logic 715 may be incorporated into the processor 2500. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs included in the 3D pipeline 2512. In addition, in at least one embodiment, the inference and / or training operations described herein may use Fig. 7A or Figure 7B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2500 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0379] Fig.26 is a block diagram of a graphics processing engine 2610 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2610 is Fig.25 2610. In at least one embodiment, media pipeline 2616 is optional and may not be explicitly included in GPE 2610. In at least one embodiment, separate media and / or graphics processors are coupled to GPE 2610.

[0380] In at least one embodiment, the GPE 2610 is coupled to or includes a command stream converter 2603 that provides a command stream to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, the command stream converter 2603 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, the command stream converter 2603 receives commands from the memory and sends the commands to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, the commands are instructions, primitives, or micro-operations obtained from a ring buffer that stores commands for the 3D pipeline 2512 and the media pipeline 2516. In at least one embodiment, the ring buffer may also include a batch command buffer that stores batches of multiple commands. In at least one embodiment, the commands for the 3D pipeline 2512 may also include references to data stored in the memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2512 and / or image data and memory objects for the media pipeline 2516. In at least one embodiment, the 3D pipeline 2512 and the media pipeline 2516 process commands and data by executing operations or by dispatching one or more execution threads to the graphics core array 2614. In at least one embodiment, the graphics core array 2614 includes one or more graphics core blocks (e.g., one or more graphics cores 2615A, one or more graphics cores 2615B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, the graphics execution resources including general and graphics-specific execution logic for performing graphics and compute operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic, including Fig. 7A and Figure 7B Inference and / or training logic 715 in.

[0381] In at least one embodiment, the 3D pipeline 2512 includes fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. In at least one embodiment, the graphics core array 2614 provides a unified execution resource block that is used to process shader programs. In at least one embodiment, the multi-purpose execution logic (e.g., execution units) within the graphics cores 2615A-2615B of the graphics core array 2614 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0382] In at least one embodiment, graphics core array 2614 also includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations.

[0383] In at least one embodiment, output data may output data to memory in a unified return buffer (URB) 2618, the output data being generated by threads executing on the graphics core array 2614. In at least one embodiment, URB 2618 may store data for multiple threads. In at least one embodiment, URB 2618 may be used to send data between different threads executing on the graphics core array 2614. In at least one embodiment, URB 2618 may also be used for synchronization between threads on the graphics core array 2614 and fixed function logic within the shared function logic 2620.

[0384] In at least one embodiment, graphics core array 2614 is scalable such that graphics core array 2614 includes a variable number of graphics cores, each graphics core having a variable number of execution units based on a target power and performance level for GPE 2610. In at least one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0385] In at least one embodiment, graphics core array 2614 is coupled to shared functionality logic 2620, which includes a plurality of resources shared between graphics cores in graphics core array 2614. In at least one embodiment, the shared functionality performed by shared functionality logic 2620 is embodied in hardware logic units that provide specialized, complementary functionality to graphics core array 2614. In at least one embodiment, shared functionality logic 2620 includes, but is not limited to, sampler unit 2621, math unit 2622, and inter-thread communication (ITC) logic 2623. In at least one embodiment, one or more caches 2625 are included in or coupled to shared functionality logic 2620.

[0386] In at least one embodiment, if the demand for a dedicated function is not sufficient to be included in the graphics core array 2614, shared functions are used. In at least one embodiment, a single instance of a dedicated function is used in shared function logic 2620 and shared among other execution resources within the graphics core array 2614. In at least one embodiment, a specific shared function may be included in shared function logic 2616 within the graphics core array 2614, where the specific shared function is within the shared function logic 2620 that is widely used by the graphics core array 2614. In at least one embodiment, shared function logic 2616 within the graphics core array 2614 may include some or all of the logic within shared function logic 2620. In at least one embodiment, all of the logic elements within shared function logic 2620 may be replicated within shared function logic 2626 of the graphics core array 2614. In at least one embodiment, shared function logic 2620 is excluded in favor of shared function logic 2626 within the graphics core array 2614.

[0387] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A 7B provides details about the inference and / or training logic 715. In at least one embodiment, some or all of the inference and / or training logic 715 may be incorporated into the graphics processor 2900. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline 2612, graphics core 2615, shared function logic 2626, shared function logic 2620, or Fig.26 In addition, in at least one embodiment, the reasoning and / or training operations described herein may use Fig. 7A or Figure 7BIn at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2610 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0388] In at least one embodiment, the Fig.26 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0389] Fig. 27 is a block diagram of the hardware logic of a graphics processor core 2700 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2700 is included within a graphics core array. In at least one embodiment, the graphics processor core 2700 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2700 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2700 can include a fixed function block 2730 coupled to multiple sub-cores 2701A-2701F, also referred to as sub-slices, which include modular blocks of general and fixed function logic.

[0390] In at least one embodiment, fixed function block 2730 includes geometry and fixed function pipelines 2736, which may be shared by all sub-cores in graphics processor 2700, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry fixed function pipeline 2736 includes a 3D fixed function pipeline, a video front end unit, a thread maker and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0391] In at least one fixed embodiment, the fixed function block 2730 also includes a graphics SoC interface 2737, a graphics microcontroller 2738, and a media pipeline 2739. In at least one embodiment, the graphics SoC interface 2737 provides an interface between the graphics core 2700 and other processor cores in the integrated circuit system on a chip. In at least one embodiment, the graphics microcontroller 2738 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 2700, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 2739 includes logic that helps decode, encode, pre-process, and / or post-process multimedia data including image and video data. In at least one embodiment, the media pipeline 2739 implements media operations via requests to calculation or sampling logic within the sub-cores 2701-2701F.

[0392] In at least one embodiment, the SoC interface 2737 enables the graphics core 2700 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2737 may also enable communication with fixed function devices within the SoC (e.g., a camera imaging pipeline), and enable the use and / or implementation of global memory atomics that may be shared between the graphics core 2700 and the CPU within the SoC. In at least one embodiment, the graphics SoC interface 2737 may also implement power management controls for the graphics processor core 2700, and enable interfaces between the clock domain of the graphics processor core 2700 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2737 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2739 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2736, geometry and fixed function pipeline 2714) when graphics processing operations are to be performed.

[0393] In at least one embodiment, the graphics microcontroller 2738 can be configured to perform various scheduling and management tasks for the graphics core 2700. In at least one embodiment, the graphics microcontroller 2738 can perform graphics and / or computational workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2702A-2702F, 2704A-2704F in the sub-cores 2701A-2701F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2700 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 2738 may also facilitate low power or idle states for graphics core 2700, thereby providing graphics core 2700 with the ability to save and restore registers across low power state transitions within graphics core 2700 independent of an operating system and / or graphics driver software on the system.

[0394] In at least one embodiment, the graphics core 2700 may have up to N modular sub-cores more or less than the sub-cores 2701A-2701F shown. For each set of N sub-cores, in at least one embodiment, the graphics core 2700 may also include shared function logic 2710, shared and / or cache memory 2712, geometry / fixed function pipelines 2714, and additional fixed function logic 2716 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2710 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2700. In at least one embodiment, the shared and / or cache memory 2712 may be the last level cache for the N sub-cores 2701A-2701F within the graphics core 2700, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2714 may be included in place of geometry / fixed function pipeline 2736 within fixed function block 2730 and may include similar logic units.

[0395] In at least one embodiment, the graphics core 2700 includes additional fixed function logic 2716, which may include various fixed function acceleration logic for use by the graphics core 2700. In at least one embodiment, the additional fixed function logic 2716 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and the culling pipeline within the geometry and fixed function pipelines 2716, 2736, it is an additional geometry pipeline that may be included in the additional fixed function logic 2716. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, so that shading can be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2716 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to as a replay pipeline in this case) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0396] In at least one embodiment, the additional fixed function logic 2716 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or inference.

[0397] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2701A-2701F, which can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 2701A-2701F includes multiple EU arrays 2702A-2702F, 2704A-2704F, thread dispatch and inter-thread communication (TD / IC) logic 2703A-2703F, 3D (e.g., texture) samplers 2705A-2705F, media samplers 2706A-2706F, shader processors 2707A-2707F, and shared local memory (SLM) 2708A-2708F. In at least one embodiment, the EU arrays 2702A-2702F, 2704A-2704F each include multiple execution units that are general purpose graphics processing units capable of servicing graphics, media, or compute operations, performing floating point and integer / fixed point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2703A-2703F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2705A-2705F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2706A-2706F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2701A-2701F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2701A-2701F may utilize shared local memory 2708A-2708F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0398] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Detail is provided regarding the inference and / or training logic 715. In at least one embodiment, some or all of the inference and / or training logic 715 may be incorporated into the graphics processor 2710. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the 3D pipeline 2710, the graphics microcontroller 2738, the geometry & fixed function pipelines 2714 and 2736, or Fig.26In addition, in at least one embodiment, the inference and / or training operations described herein may use the addition Fig. 7A or Figure 7B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2700 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0399] In at least one embodiment, the Fig. 27 A GPU-based CRC processing unit is used in a system to perform CRC generation and / or checking.

[0400] Fig.28A and 28B Thread execution logic 2800 is shown for an array of processing elements including a graphics processor core, according to at least one embodiment. Fig.28A At least one embodiment is shown in which thread execution logic 2800 is used. Fig.28B Exemplary internal details of an execution unit in accordance with at least one embodiment are shown.

[0401] like Fig.28A As shown in , in at least one embodiment, thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable execution unit array including a plurality of execution units 2807A-2807N and 2808A-2808N, a sampler 2810, a data cache 2812, and a data port 2814. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2808A, 2808B, 2808C, 2808D to 2808N-1 and 2808N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected by an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 2800 includes one or more connections to a memory (such as system memory or cache memory) through one or more of instruction cache 2806, data port 2814, sampler 2810, and execution unit 2807 or 2808. In at least one embodiment, each execution unit (e.g., 2808A) is an independent programmable general-purpose computing unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2807 and / or 2808 is scalable to include any number of separate execution units.

[0402] In at least one embodiment, execution units 2808A-2808N are primarily used to execute shader programs. In at least one embodiment, shader processor 2802 can process various shader programs and dispatch execution threads associated with shader programs via thread dispatcher 2804. In at least one embodiment, thread dispatcher 2804 includes logic for arbitrating thread initialization celebrations from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 2808A-2808N. For example, in at least one embodiment, a geometry pipeline can dispatch vertices, tessellation or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2804 can also process runtime thread generation requests from executing shader programs.

[0403] In at least one embodiment, the execution units 2808A-2808N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs in graphics libraries (such as Direct 3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 2808A-2808N includes one or more arithmetic logic units (ALUs) capable of executing multiple-issue single instruction multiple data (SIMD), and multi-threaded operations enable an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single-precision and double-precision floating-point operations, SIMD branch functions, logical operations, prior operations, and other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, dependency logic within execution units 2808A-2808N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, an execution unit can perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0404] In at least one embodiment, each of the execution units 2808A-2808N operates on an array of data elements. In at least one embodiment, the number of data elements is inferred as the "execution size" or number of lanes of the instruction. In at least one embodiment, the execution lanes are the logical units used for the execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2808A-2808N support integer and floating point data types.

[0405] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quadword (QW) size data elements), eight separate 32-bit packed data elements (doubleword (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements) or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0406] In at least one embodiment, one or more execution units may be combined into a fused execution unit 2809A-2809N having thread control logic (2807A-2807N) for executing a fused EU. In at least one embodiment, multiple EUs may be merged into one EU group. In at least one embodiment, each EU in the fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary according to various embodiments. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2809A-2809N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2809A includes a first EU 2808A, a second EU 2808B, and a thread control logic 2811A shared by the first EU 2807A and the second EU 2808A. In at least one embodiment, thread control logic 2807A controls threads executing on fused graphics execution unit 2809A, allowing each EU within fused execution units 2809A-2809N to execute using a common instruction pointer register.

[0407] In at least one embodiment, one or more internal instruction caches (e.g., 2806) are included in the thread execution logic 2800 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2810 includes a specialized texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0408] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2800 through the thread generation and dispatch logic. In at least one embodiment, once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2802 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, the pixel processor logic within the shader processor 2802 then executes the pixel or fragment shader program provided by the application program interface (API). In at least one embodiment, in order to execute the shader program, the shader processor 2802 dispatches the thread to the execution unit (e.g., 2808A) via the thread dispatcher 2804. In at least one embodiment, the shader processor 2802 uses the texture sampling logic in the sampler 2810 to access the texture data in the texture map stored in the memory. In at least one embodiment, arithmetic operations on texture data and input geometry data calculate pixel color data for each geometry fragment, or discard one or more pixels for further processing.

[0409] In at least one embodiment, data port 2814 provides a memory access mechanism for thread execution logic 2800 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2814 includes or is coupled to one or more cache memories (e.g., data cache 2812) to cache data for memory access via the data port.

[0410] like Fig.28BAs shown, in at least one embodiment, the graphics execution unit 2808 may include an instruction fetch unit 2837, a general register file array (GRF) 2824, an architectural register file array (ARF) 2826, a thread arbiter 2822, an issue unit 2830, a branch unit 2832, a set of SIMD floating point units (FPUs) 2834, and in at least one embodiment, a set of dedicated integer SIMD ALUs 2835. The GRF 2824 and ARF 2826 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in the graphics execution unit 2808. In at least one embodiment, the per-thread architectural state is maintained in the ARF 2826, while data used during...

Claims

1. A method for performing a cyclic redundancy check, include: Get the input data sequence; Obtaining a cyclic redundancy check sequence; distributing the sequence of input data to a thread among a plurality of threads of a graphics processing unit; assigning the cyclic redundancy check sequence to the thread among the plurality of threads of the graphics processing unit; performing a cyclic redundancy check operation on the input data sequence and the cyclic redundancy check sequence using the thread of the plurality of threads of the graphics processing unit; as well as A cyclic redundancy check result of the cyclic redundancy check operation is output.

2. The method of claim 1, wherein the cyclic redundancy check sequence is a first function of a generator polynomial, the input data sequence corresponds to the data polynomial, and the cyclic redundancy check result comprises a remainder of a second function of the data polynomial modulo the generator polynomial.

3. The method of claim 2, wherein the input data sequence is distributed to the plurality of threads include: The data polynomial is distributed among threads of the plurality of threads by parsing the data polynomial into a plurality of input data segments sized to fit a thread local memory data width.

4. The method of claim 3, wherein the cyclic redundancy check sequence is assigned to the plurality of threads include: At least one of the generator polynomial or the polynomial factors is distributed among threads of the plurality of threads by parsing at least one of the generator polynomial or the polynomial factors into a plurality of generator segments sized to fit a width of the thread local memory data.

5. The method according to claim 4, further comprising: include: storing the plurality of input data segments in a local memory of the thread; as well as The plurality of generated segments are stored in a global memory accessible to the plurality of threads of the graphics processing unit.

6. The method according to claim 4, further comprising: include: computing a precomputed generator segment independently of said input data sequence as a third function of thread position and said generator polynomial; as well as The pre-computed generated segments are stored in a global memory accessible to the plurality of threads of the graphics processing unit.

7. The method according to claim 4, further comprising: include: Determine thread position; determining an associated generation segment associated with the thread position; calculating a value of a thread output of a thread having the thread position among the plurality of threads; as well as Providing access to the value for the thread with the thread position is useful as a lookup table for finding a thread output for a given input data segment.

8. A cyclic redundancy checker, include: A plurality of first thread hardware units of a graphics processing unit, wherein the first thread hardware unit comprises: 1) The first execution core; 2) a local memory for storing an input data segment, wherein the input data segment is a portion of an input data sequence for which a cyclic redundancy check value is to be obtained; and 3) an interface for accessing a global memory of the graphics processing unit and accessible by the plurality of first thread hardware units, the interface for storing a plurality of generated segments in the global memory, wherein the generated segments are based on a cyclic redundancy check sequence; A plurality of second thread hardware units, wherein the second thread hardware units include: 1) a second execution core; and 2) an instruction cache having stored therein a first instruction for performing a multiplication operation on the input data segment and a generation segment of the plurality of generation segments to form a thread output of the first thread hardware unit, and a second instruction for performing an exclusive-OR operation on a plurality of thread outputs of the plurality of first thread hardware units; and Output, used to output the cyclic redundancy check value.

9. The cyclic redundancy checker as claimed in claim 8, further comprising: include: a comparator for comparing the cyclic redundancy check value with a received cyclic redundancy check value received in association with the input data segment; as well as A first storage for storing pre-computed generator segments computed as a first function of thread position and a generator polynomial, wherein the first storage is stored in a graphics processing unit global memory.

10. The cyclic redundancy checker of claim 8, wherein the plurality of second-thread hardware units comprises a plurality of third-thread hardware units, and the plurality of third-thread hardware units are used to perform a parallel tree of XOR operations.

11. The cyclic redundancy checker of claim 8, wherein the cyclic redundancy check sequence is a first function of a generator polynomial, the input data sequence corresponds to the data polynomial, and the cyclic redundancy check value comprises a remainder of a second function of the data polynomial modulo the generator polynomial.

12. The cyclic redundancy checker of claim 11, further comprising a thread manager for distributing the data polynomial among the threads of the plurality of first thread hardware units by parsing the data polynomial into a plurality of input data segments sized to fit a thread local memory data width.

13. The cyclic redundancy checker of claim 12 , wherein the interface distributes at least one of the generator polynomial or the polynomial factor among the threads of the plurality of first thread hardware units by parsing at least one of the generator polynomial or the polynomial factor into the plurality of generator segments sized to fit the thread local memory data width.

14. The cyclic redundancy checker according to claim 12, further comprising: include: A second storage in the global memory is used to store pre-computed generator segments independent of the input data sequence as a third function of thread position and the generator polynomial.

15. The cyclic redundancy checker according to claim 12, further comprising: include: and second storage in the global memory for a lookup table, wherein the lookup table includes a first set of pre-computed entries for a first thread having a first thread position, and wherein the first set of pre-computed entries includes values ​​of polynomial multiplications of possible values ​​of input data segments and a first generated segment associated with the first thread position.

16. A cyclic redundancy checker, include: A graphics processing unit, comprising a plurality of thread hardware units, wherein the plurality of thread hardware units comprises: a) a first threaded hardware unit comprising a first execution core, a first instruction cache, a first local memory, and a first load / store unit, the first load / store unit being coupled to a shared memory shared among threads of the plurality of threaded hardware units and to a global memory of the graphics processing unit; and b) a second thread hardware unit comprising a second execution core, a second instruction cache, a second local memory, and a second load / store unit, the second load / store unit being coupled to the shared memory and to the global memory, The first instruction cache includes a first set of instructions, the first set of instructions being used to: 1) obtaining a first input data segment, wherein the first input data segment is a first part of an input data sequence received by the cyclic redundancy checker; 2) obtaining a first cyclic redundancy check segment, wherein the first cyclic redundancy check segment is a first part of a cyclic redundancy check sequence; and 3) performing a first multiplication operation on the first input data segment and the first cyclic redundancy check segment to form a first thread output; and The second instruction cache includes a second set of instructions, the second set of instructions being used to: 1) obtaining a second input data segment, wherein the second input data segment is a second part of the input data sequence received by the cyclic redundancy checker; 2) obtaining a second cyclic redundancy check segment, wherein the second cyclic redundancy check segment is a second part of the cyclic redundancy check sequence; and 3) performing a second multiplication operation on the second input data segment and the second cyclic redundancy check segment to form a second thread output; and c) a third thread hardware unit, configured to perform a reduction operation on the first thread output and the second thread output to perform a cyclic redundancy check operation on the input data sequence and the cyclic redundancy check sequence to form a cyclic redundancy check result representing a cyclic redundancy check of the input data sequence.

17. The cyclic redundancy checker of claim 16, wherein the cyclic redundancy check sequence is a first function of a generator polynomial, the input data sequence corresponds to the data polynomial, and the cyclic redundancy check result comprises a remainder of a second function of the data polynomial modulo the generator polynomial.

18. The cyclic redundancy checker of claim 17 , wherein the graphics processing unit is configured to distribute the input data sequence to the first thread hardware unit and the second thread hardware unit by parsing the data polynomial into a plurality of input data segments sized to fit a thread local memory data width, thereby distributing the data polynomial among the first thread hardware unit and the second thread hardware unit.

19. The cyclic redundancy checker of claim 18, wherein the graphics processing unit is configured to distribute the cyclic redundancy check sequence to the first thread hardware unit and the second thread hardware unit. include: At least one of the generator polynomial or the polynomial factors is distributed among the first thread hardware unit and the second thread hardware unit by parsing at least one of the generator polynomial or the polynomial factors into a plurality of generator segments sized to fit the thread local memory data width.

20. The cyclic redundancy checker according to claim 17, further comprising: include: A second storage in the global memory is used to store pre-computed generator segments independent of the input data sequence as a third function of thread position and the generator polynomial.

21. The cyclic redundancy checker according to claim 17, further comprising: include: and second storage in the global memory for a lookup table, wherein the lookup table includes a first set of pre-computed entries for the first thread hardware unit having a first thread location, and wherein the first set of pre-computed entries includes values ​​of a polynomial multiplication of possible values ​​of an input data segment and a first generated segment associated with the first thread location.

22. A method for performing a cyclic redundancy check, include: Obtaining an input data sequence that can be represented as a binary polynomial; Obtaining a generating polynomial for a cyclic redundancy check (CRC) process; parsing the binary polynomial into a plurality of input data segments; Allocating a first input data segment of the plurality of input data segments to the first thread according to a first thread position of a first thread of a graphics processing unit GPU; allocating a second input data segment of the plurality of input data segments to the second thread according to a second thread position of the second thread of the GPU; Parsing the generator polynomial into a plurality of generator segments; assigning a first generating segment of the plurality of generating segments to the first thread, wherein the first generating segment is a first monomial modulo the generating polynomial, wherein a first order of the first monomial corresponds to the first thread position; assigning a second generation segment of the plurality of generation segments to the second thread, wherein the second generation segment is a second monomial modulo the generator polynomial, wherein a second order of the second monomial corresponds to the second thread position; performing, using the first thread, a first polynomial multiplication of the first input data segment and the first generated segment to form a first thread output; performing, using the second thread, a second polynomial multiplication of the second input data segment and the second generated segment to form a second thread output, wherein the second thread performs the second polynomial multiplication in parallel with the first thread performing the first polynomial multiplication; Using at least a third thread of the GPU, perform an XOR operation on the first thread output and the second thread output to form a third thread output; as well as Zero or more XOR operations are performed on the third thread output and threads assigned additional input data segments in addition to the first input data segment and the second input data segment to form a calculated CRC value, wherein the calculated CRC value includes a polynomial multiplication of the binary polynomial and a CRC monomial, and the order of the CRC monomial corresponds to the order of the generating polynomial modulo the generating polynomial.

23. The method of claim 22, wherein the generator polynomial is one or more of: P a ( x )=x 24 +x 23 +x 18 +x 17 +x 14 +x 11 +x 10 +x 7 +x 6 +x 5 +x 4 +x 3 +x+1 and P b ( x )=x 24 +x 23 +x 6 +x 5 +x+1.

24. The method of claim 22, further comprising: include: obtaining a received CRC value received in association with the input data sequence; as well as The received CRC value is compared to the calculated CRC value.

25. The method of claim 24, further comprising: include: determining whether the received CRC value and the calculated CRC value are different; as well as The difference between the received CRC value and the calculated CRC value is marked.

26. The method of claim 22, further comprising: include: The calculated CRC value associated with the input data sequence is provided.

27. The method of claim 22, wherein the calculated CRC value is calculated for data on an uplink from a mobile device to a cellular infrastructure serving a plurality of mobile devices.

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