Display substrate and display device

Abstract

A display substrate and a display device. In this display substrate, a first display area includes a first light-emitting unit column and a second light-emitting unit column, each light-emitting unit column connected to a column of first sub-pixel circuits. A second display area includes a third light-emitting unit column and a fourth light-emitting unit column, each light-emitting unit column connected to a column of first sub-pixel circuit pairs. A first sub-data line is connected to the first light-emitting unit column, a second sub-data line is connected to the second light-emitting unit column, a third sub-data line is connected to the third light-emitting unit column, and a fourth sub-data line is connected to the fourth light-emitting unit column. The first sub-pixel circuit pairs connected to the fourth light-emitting unit column and the first sub-pixel circuits connected to the second light-emitting unit column are located in different columns. The second sub-data line and the fourth sub-data line are connected via a data line connector, ensuring that data signals in the first display area match those in the second display area.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] With people's ever-increasing pursuit of visually appealing display products, narrow bezels and even full-screen displays are becoming a new trend in the development of organic light-emitting diode (OLED) display products. With the screen-to-body ratio of many mobile phones steadily increasing, full-screen displays have become a current trend. The front camera is key to full-screen design. To achieve a higher screen-to-body ratio, display products with notch screens, waterdrop screens, and punch-hole screens have emerged. These full-screen forms increase the screen-to-body ratio at the expense of the phone's appearance. Therefore, the design of an under-screen camera can both maintain the phone's appearance and improve the screen-to-body ratio. An under-screen camera means the front camera is located below the screen but does not affect the screen's display function. When the front camera is not in use, the screen above the camera can still display images normally. From the appearance, the under-screen camera does not have any camera hole, truly achieving a full-screen display effect. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate and a display device.

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a first display area and a second display area, the first display area comprising a plurality of first light-emitting units and a plurality of first sub-pixel circuits, the plurality of first light-emitting units comprising a first light-emitting unit column and a second light-emitting unit column adjacently arranged, each light-emitting unit column being connected to a corresponding column of first sub-pixel circuits, the second display area comprising a plurality of second light-emitting units and a plurality of second sub-pixel circuits, the plurality of second light-emitting units comprising a third light-emitting unit column and a fourth light-emitting unit column adjacently arranged, each light-emitting unit column in the second display area being connected to a column of first sub-pixel circuit pairs, each column of first sub-pixel circuit pairs comprising two adjacent columns of second sub-pixel circuits; a plurality of first sub-data lines, a plurality of second sub-data lines, a plurality of third sub-data lines, and a plurality of fourth sub-data lines extending along a second direction, each first sub-data line being connected to each first light-emitting unit column, each second sub-data line being connected to each second light-emitting unit column, each third sub-data line being connected to each third light-emitting unit column, and each fourth sub-data line being connected to each fourth light-emitting unit column, the second direction intersecting with the first direction. The arrangement direction of the first light-emitting unit column and the second light-emitting unit column is the same as the arrangement direction of the third light-emitting unit column and the fourth light-emitting unit column, a column of first sub-pixel circuits connected to the first light-emitting unit column and a column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column, and the first sub-data line and the third sub-data line are a continuous data line extending along the second direction; the two columns of second sub-pixel circuits connected to the fourth light-emitting unit column and the one column of first sub-pixel circuits connected to the second light-emitting unit column are located in different columns, the second sub-data line and the fourth sub-data line are connected through a data line connecting portion, and the extension direction of the data line connecting portion intersects with the second direction.

[0005] For example, in an embodiment of the present disclosure, a column of first sub-pixel circuits connected to the second light-emitting unit column and another column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column.

[0006] For example, in an embodiment of the present disclosure, the first display area further includes a fifth light-emitting unit column and a sixth light-emitting unit column arranged adjacent to each other, the first light-emitting unit column, the second light-emitting unit column, the fifth light-emitting unit column and the sixth light-emitting unit column are repeatedly arranged along the first direction, and the third light-emitting unit column and the fourth light-emitting unit column are alternately arranged along the first direction, and the display substrate further includes a plurality of fifth sub-data lines and a plurality of sixth sub-data lines extending along the second direction, each fifth sub-data line is connected to each fifth light-emitting unit column, and each sixth sub-data line is connected to each sixth light-emitting unit column, a column of first sub-pixel circuits connected to the fifth light-emitting unit column and a column of second sub-pixel circuits connected to the fourth light-emitting unit column are located in the same column, a column of first sub-pixel circuits connected to the sixth light-emitting unit column and another column of second sub-pixel circuits connected to the fourth light-emitting unit column are located in the same column, and a gap is provided between the sixth sub-data line or the fifth sub-data line and the fourth sub-data line.

[0007] For example, in an embodiment of the present disclosure, the first display area includes a plurality of first sub-light-emitting unit groups and a plurality of second sub-light-emitting unit groups arranged alternately along the first direction and the second direction, the first sub-light-emitting unit group includes the light-emitting units in the first light-emitting unit column and the second light-emitting unit column, the second sub-light-emitting unit group includes the light-emitting units in the fifth light-emitting unit column and the sixth light-emitting unit column, the second display area includes a plurality of third sub-light-emitting unit groups, each of the sub-light-emitting unit groups includes a first color light-emitting unit, a second color light-emitting unit pair and a third color light-emitting unit, the first color light-emitting unit and the third color light-emitting unit are arranged along the second direction, the second color light-emitting unit pair includes two second color light-emitting units arranged along the second direction, the first color light-emitting unit and the second color light-emitting unit pair are arranged along the first direction, and the arrangement direction of the first color light-emitting unit and the third color light-emitting unit in the first sub-light-emitting unit group is opposite to the arrangement direction of the first color light-emitting unit and the third color light-emitting unit in the second sub-light-emitting unit group, and the relative position distribution of each light-emitting unit in the first sub-light-emitting unit group is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group.

[0008] For example, in an embodiment of the present disclosure, the base substrate also includes a third display area, the second display area also includes a plurality of third sub-pixel circuits, the third display area includes a plurality of third light-emitting units, the plurality of third light-emitting units include a seventh light-emitting unit column and an eighth light-emitting unit column arranged adjacent to each other, the arrangement direction of the first light-emitting unit column and the second light-emitting unit column is the same as the arrangement direction of the seventh light-emitting unit column and the eighth light-emitting unit column, each light-emitting unit column in the third display area is connected to a column of second sub-pixel circuit pairs, and each column of second sub-pixel circuit pairs includes two adjacent columns of third sub-pixel circuits; the display substrate also includes a plurality of seventh sub-data lines and a plurality of eighth sub-data lines extending along the second direction, each seventh sub-data line is connected to each seventh light-emitting unit column, and each eighth sub-data line is connected to each eighth light-emitting unit column, and at least one of the seventh sub-data line and the eighth sub-data line is arranged between the third sub-data line and the fourth sub-data line.

[0009] For example, in an embodiment of the present disclosure, the seventh sub-data line and the eighth sub-data line are both arranged between the third sub-data line and the fourth sub-data line, and a gap is set between the eighth sub-data line and the fifth sub-data line to set the sub-data line connection portion.

[0010] For example, in an embodiment of the present disclosure, the multiple third sub-pixel circuits are configured to be connected to multiple fourth sub-light-emitting unit groups, respectively, the relative position distribution of each light-emitting unit in each of the fourth sub-light-emitting unit groups is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group, and the first sub-pixel circuit pair connected to the third sub-light-emitting unit group and the second sub-pixel circuit pair connected to the fourth light-emitting unit group are alternately arranged along the first direction and the second direction.

[0011] For example, in an embodiment of the present disclosure, the third display area includes a central area and an edge area surrounding the central area, and the edge area includes a plurality of dummy pixel circuits arranged along the first direction and the second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows.

[0012] For example, in an embodiment of the present disclosure, the multiple dummy pixel circuit columns in the third display area include a dummy pixel circuit column group consisting of four adjacent columns, each dummy pixel circuit column group includes a first dummy pixel circuit column, a second dummy pixel circuit column, a third dummy pixel circuit column and a fourth dummy pixel circuit column arranged in sequence along the first direction, and the display substrate also includes a first dummy data line, a second dummy data line, a third dummy data line and a fourth dummy data line, the first dummy data line is connected to the first dummy pixel circuit column, the second dummy data line is connected to the second dummy pixel circuit column, the third dummy data line is connected to the third dummy pixel circuit column, and the fourth dummy data line is connected to the fourth dummy pixel circuit column. The first sub-pixel circuits connected to the first light-emitting unit column and the first dummy pixel circuit column are located in the same column, the first sub-pixel circuits connected to the second light-emitting unit column and the second dummy pixel circuit column are located in the same column, the first sub-pixel circuits connected to the fifth light-emitting unit column and the third dummy pixel circuit column are located in the same column, the first sub-pixel circuits connected to the sixth light-emitting unit column and the fourth dummy pixel circuit column are located in the same column, the two sub-data lines connected to the first light-emitting unit group and the corresponding two dummy data lines are two continuous sub-data lines, or the two sub-data lines connected to the second light-emitting unit group and the corresponding two dummy data lines are two continuous data lines.

[0013] For example, in an embodiment of the present disclosure, the display substrate further includes a peripheral area located on a side of the third display area away from the first display area, and the two virtual data lines connected to the first light-emitting unit group or the second light-emitting unit group bypass the central area to respectively connect the seventh sub-data line and the eighth sub-data line in the peripheral area.

[0014] For example, in an embodiment of the present disclosure, the first dummy data line and the first sub-data line are a continuous data line, the second dummy data line and the second sub-data line are a continuous sub-data line, a gap is set between the third dummy data line and the fifth sub-data line, and a gap is set between the fourth dummy data line and the sixth sub-data line.

[0015] For example, in an embodiment of the present disclosure, the first dummy data line bypasses the central region to connect to the seventh sub-data line in the peripheral region, and the second dummy data line bypasses the central region to connect to the eighth sub-data line in the peripheral region.

[0016] Another embodiment of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0018] Figure 1 A schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure;

[0019] Figure 2 for Figure 1 A pixel circuit equivalent diagram of at least one of the second pixel circuit group and the third pixel circuit group shown;

[0020] Figure 3A A schematic diagram of a partial planar structure of an active semiconductor layer of a pixel circuit in a second display area according to an embodiment of the present disclosure;

[0021] Figure 3B A schematic diagram of the stacking of the active semiconductor layer and the first conductive layer in the second display area according to an embodiment of the present disclosure;

[0022] Figure 3C is a schematic diagram of a partial planar structure of a second conductive layer in a second display area according to an embodiment of the present disclosure;

[0023] Figure 3D A schematic diagram of stacking an active semiconductor layer, a first conductive layer, and a second conductive layer in a second display area according to an embodiment of the present disclosure;

[0024] Figure 3E A schematic diagram of a partial planar structure of a source / drain metal layer in a second display area according to an embodiment of the present disclosure;

[0025] Figure 3F A schematic diagram of stacking an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer in a second display area according to an embodiment of the present disclosure;

[0026] Figure 4A A schematic diagram of the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area provided according to an embodiment of the present disclosure;

[0027] Figure 4B for Figure 4A A schematic layer structure diagram of a light-emitting unit;

[0028] Figure 4C for Figure 4A Schematic diagram of the relationship between the second light-emitting unit group and the via holes in the second display area;

[0029] Figure 5AA schematic diagram of a structure of a portion of pixel circuits at the junction of a first display area and a second display area provided according to an embodiment of the present disclosure;

[0030] Figure 5B for Figure 5A Schematic diagram of the film layer structure where the data line connection part is located at the position shown;

[0031] Figure 5C for Figure 5A Schematic diagram of the film layer structure where the data line is located at the position shown;

[0032] Figure 5D for Figure 1 A partial plan view of a first display area and a second display area in the display substrate shown;

[0033] Figure 5E A partial plan view of a first display area and a second display area in a display substrate provided according to another example of an embodiment of the present disclosure;

[0034] Figure 6 A schematic diagram of a structure of a portion of pixel circuits at the junction of the edge areas of the first display area and the third display area provided according to an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of a second electrode of a light-emitting unit group located in a first display area according to an embodiment of the present disclosure;

[0036] Figure 8 A schematic diagram of a second electrode of a light-emitting unit group located at a non-edge portion of a second display area according to an embodiment of the present disclosure;

[0037] Figure 9 A schematic diagram of a second electrode of a light-emitting unit group located in a third display area according to an embodiment of the present disclosure;

[0038] Figure 10 A schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups in the second display area bordering the first display area provided according to an embodiment of the present disclosure; and

[0039] Figure 11 This is a schematic diagram of the second electrodes of the light-emitting units in the two columns of light-emitting unit groups in the second display area bordering the first display area according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] During the research, the inventors of this application found that: currently, in the organic light-emitting diode display device using the under-screen camera design, the display brightness and current of the low-density display area (L area) are at least twice as low as those of the high-density display area (H area), which will affect the display effect.

[0043] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a first display area, and a second display area. The first display area includes a plurality of first light-emitting units and a plurality of first sub-pixel circuits, the plurality of first light-emitting units including adjacent first and second light-emitting unit columns, each light-emitting unit column connected to a corresponding column of first sub-pixel circuits, the second display area includes a plurality of second light-emitting units and a plurality of second sub-pixel circuits, the plurality of second light-emitting units including adjacent third and fourth light-emitting unit columns, each light-emitting unit column in the second display area connected to a column of first sub-pixel circuit pairs, each column of first sub-pixel circuit pairs including two adjacent columns of second sub-pixel circuits, and a plurality of first sub-data lines, a plurality of second sub-data lines, a plurality of third sub-data lines, and a plurality of fourth sub-data lines extending along a second direction, each first sub-data line connected to each first light-emitting unit column, each second sub-data line connected to each second light-emitting unit column, each third sub-data line connected to each third light-emitting unit column, and each fourth sub-data line connected to each fourth light-emitting unit column, wherein the second direction intersects the first direction. The arrangement direction of the first and second light-emitting unit columns is the same as the arrangement direction of the third and fourth light-emitting unit columns. A column of first sub-pixel circuits connected to the first light-emitting unit column and a column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column. The first sub-data line and the third sub-data line are a single data line extending and continuous along the second direction. The two columns of second sub-pixel circuits connected to the fourth light-emitting unit column and the one column of first sub-pixel circuits connected to the second light-emitting unit column are located in different columns. The second sub-data line and the fourth sub-data line are connected via a data line connecting portion, and the extending direction of the data line connecting portion intersects the second direction. In the display substrate provided in the embodiment of the present disclosure, at the intersection of the pixel circuits in the first display area and the pixel circuits in the second display area, the second sub-data line and the fourth sub-data line are not connected, and the second sub-data line and the fourth sub-data line are connected via the data line connecting portion, thereby ensuring that the data signals transmitted from the data lines to the light-emitting units in the first display area match the data signals transmitted from the data lines to the light-emitting units in the second display area.

[0044] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0045] Figure 1 FIG. 1 is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure. Figure 1As shown, the display substrate includes a base substrate 10. The display substrate includes a first display area 100 and a second display area 200. For example, the display substrate also includes a third display area 300. For example, the second display area 200 is located around the third display area 300, for example, on both sides of the third display area 300 along the X direction, and the first display area 100 is located around the second display area 200 and the third display area 300. For example, the second display area 200 and the third display area 300 are located at the edges of the display area, that is, the display substrate includes a display area and a peripheral area surrounding the display area, and the edges of the second display area 200 and the third display area 300 away from the first display area 100 are connected to the peripheral area. In other words, the first display area 100 is only located on one side of the third display area 300 along the Y direction. For example, the shape of the third display area 300 can be rectangular, with two edges of the rectangle extending along the Y direction respectively connected to the second display area 200 located on both sides of the rectangle, one edge of the rectangle extending along the X direction is connected to the peripheral area, and the other edge is connected to the first display area 100. For example, the second display area 200 is located between the first display area 100 and the third display area 300 arranged along the X direction, and one of the two edges of the second display area 200 extending along the X direction is connected to the peripheral area, and the other edge is connected to the first display area 100 .

[0046] like Figure 1 As shown, the first display area 100 includes a plurality of first light-emitting element groups 110 and a plurality of first pixel circuit groups 120 respectively connected to the plurality of first light-emitting element groups 110. For example, one first light-emitting element group 110 can be connected to one first pixel circuit group 120 to drive the first light-emitting element group 110 to emit light, and the first light-emitting element group 110 and the first pixel circuit group 120 that drives the first light-emitting element group 110 to emit light are both located in the first display area 100.

[0047] like Figure 1As shown, the second display area 200 includes a plurality of second light-emitting unit groups 210 and a plurality of second pixel circuit groups 220, and the plurality of second light-emitting unit groups 210 are respectively connected to the plurality of second pixel circuit groups 220. For example, the second display area 200 also includes a plurality of third pixel circuit groups 230. For example, one second light-emitting unit group 210 can be connected to one second pixel circuit group 220 to drive the second light-emitting unit group 210 to emit light, and the second light-emitting unit group 210 and the second pixel circuit group 220 that drives the second light-emitting unit group 210 to emit light are both located in the second display area 200. For example, the third display area 300 includes a plurality of third light-emitting unit groups 310, and the plurality of third light-emitting unit groups 310 are respectively connected to the plurality of third pixel circuit groups 230, that is, the third light-emitting unit group 310 located in the third display area 300 is connected to the third pixel circuit group 230 located in the second display area 200, and the third light-emitting unit group 310 and the third pixel circuit group 230 that drives the third light-emitting unit group 310 to emit light are located in different display areas. For example, as Figure 1 As shown, the central area 301 of the third display area 300 is only provided with a transparent third light-emitting unit group 310, and no non-transparent pixel circuit group is provided. The central area 301 can be used as an under-screen camera area, which can have a high light transmittance to realize the camera function, and can also realize light emission by connecting with the pixel circuit groups in other areas without affecting the display function of the screen.

[0048] like Figure 1 As shown, the density of the plurality of second light-emitting unit groups 210 is less than the density of the plurality of first light-emitting unit groups 110. For example, the density of the plurality of third light-emitting unit groups 310 is less than the density of the plurality of first light-emitting unit groups 110. If the density (i.e., pixel density) of the light-emitting unit groups in the under-screen camera area (the central area of the third display area) is lower than the density of the light-emitting unit groups in the normal display area (the first display area), the camera can be set below the low pixel density area that allows more light to pass through. The above-mentioned "the density of the plurality of second light-emitting unit groups 210 and the density of the plurality of third light-emitting unit groups 310 are both less than the density of the plurality of first light-emitting unit groups 110" means that the number of second light-emitting unit groups is less than the number of first light-emitting unit groups under the same area.

[0049] For example, the first display area 100 is the main display area and has a higher resolution (PPI, Pixel Per Inch), that is, the first display area 100 is arranged with a higher density of sub-pixels for display. Each sub-pixel includes a light-emitting unit and a pixel circuit that drives the light-emitting unit. The third display area 300 can allow light incident from the display side of the display substrate to pass through the display substrate and reach the back side of the display substrate, thereby enabling the normal operation of components such as sensors located on the back side of the display substrate. The embodiments of the present disclosure are not limited to this. For example, the third display area 300 can also allow light emitted from the back side of the display substrate to pass through the display substrate and reach the display side of the display substrate. The third display area 300 and the second display area 200 also include multiple sub-pixels for display. However, since the pixel circuit of the sub-pixel is generally not light-transmitting, in order to improve the light transmittance of the central area 301 of the third display area 300, the light-emitting unit of the sub-pixel of the third display area 300 can be separated from the pixel circuit that drives the light-emitting unit from a physical position. For example, compared with the light-emitting unit group (for example) in the third display area 300 Figure 1 The pixel circuits connected to the third display area 300 (as shown in the box in the third display area 300) can be set in the second display area 200, thus occupying part of the space in the second display area 200; the remaining space in the second display area 200 is used to set the pixels of the second display area 200 (including the second pixel circuit group 220 and the second light-emitting unit group 210). For example, each dot-filled box in the second display area 200 represents a pixel. At this time, the pixels in the second display area 200 and the third pixel circuit group 230 connected to the third light-emitting unit group 310 in the third display area 300 are arranged in an array in the second display area 200. As a result, the resolution of the third display area 300 and the second display area 200 is lower than that of the first display area 100, that is, the density of pixels arranged for display in the third display area 300 and the second display area 200 is lower than the pixel density of the first display area 100.

[0050] Figure 2 for Figure 1 The equivalent diagram of the pixel circuit pairs in the second pixel circuit group and the third pixel circuit group is shown. Figure 2As shown, each pixel circuit group includes a plurality of pixel circuits 600. The second pixel circuit group 220 includes a plurality of first pixel circuit units 610, and the first pixel circuit unit 610 includes at least a first pixel circuit 611 and a second pixel circuit 612. For example, the first pixel circuit unit 610 may include two pixel circuits, and the first pixel circuit unit 610 may be referred to as a pixel circuit pair 610. The embodiment of the present disclosure schematically shows that the first pixel circuit unit includes two pixel circuits, but is not limited to this, and may also include three pixel circuits or more pixel circuits. For example, each light-emitting unit group includes a plurality of light-emitting units, the first pixel circuit group 210 includes a plurality of pixel circuits, and each pixel circuit is configured to be connected to one light-emitting unit to drive the light-emitting unit to emit light; the second pixel circuit group 220 includes a plurality of pixel circuit pairs 610, and each pixel circuit pair 610 of the second pixel circuit group 220 is configured to be connected to one light-emitting unit to drive the light-emitting unit to emit light.

[0051] For example, the third pixel circuit group 230 includes multiple second pixel circuit units, each of which includes at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be connected to the same light-emitting unit to drive the light-emitting unit to emit light. For example, the second pixel circuit unit may include two pixel circuits, and the second pixel circuit unit may also be referred to as a pixel circuit pair 610. The embodiment of the present disclosure schematically illustrates that the second pixel circuit unit includes two pixel circuits, but is not limited thereto and may also include three or more pixel circuits.

[0052] For example, the display substrate further includes a reset power signal line, a data line, a scan signal line, a power signal line, a reset control signal line, and a light emitting control signal line located on the base substrate. Figure 2 As shown, each pixel circuit 600 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first electrode of the threshold compensation transistor T2 is connected to the first electrode of the driving transistor T3, the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, the first electrode of the first reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit, the second electrode of the first reset control transistor T7 is connected to the light emitting unit, and the first electrode of the data writing transistor T4 is connected to the second electrode of the driving transistor T3. For example, Figure 2As shown, the pixel circuit of each sub-pixel further includes a storage capacitor C, a first light emission control transistor T6, a second light emission control transistor T5 and a second reset transistor T1. A gate of the data writing transistor T4 is electrically connected to the scan signal line to receive a scan signal Gate; a first electrode of the storage capacitor C is electrically connected to the power signal line, and a second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; a gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive a compensation control signal; a gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive a reset control signal Reset; a first electrode of the second reset transistor T1 is electrically connected to the reset power signal line to receive a reset signal Vinit, a second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and a gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive a reset control signal Reset; a gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive a light-emitting control signal EM; a first electrode of the second light-emitting control transistor T5 is electrically connected to the power signal line, a second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, and a gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The power signal line refers to a signal line for outputting a voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0053] For example, the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines, that is, the gate of the data writing transistor T3 is electrically connected to a first scanning signal line, and the gate of the threshold compensation transistor T2 is electrically connected to a second scanning signal line. The signals transmitted by the first scanning signal line and the second scanning signal line can be the same or different, thereby allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of controlling the pixel circuit.

[0054] For example, the light control signals input to the first light control transistor T6 and the second light control transistor T5 can be the same, that is, the gates of the first light control transistor T6 and the second light control transistor T5 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gates of the first light control transistor T6 and the second light control transistor T5 can also be electrically connected to different light control signal lines, respectively, and the signals transmitted by the different light control signal lines can be the same or different.

[0055] For example, the reset control signal input to the first reset transistor T7 and the second reset transistor T1 can be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can also be electrically connected to different reset control signal lines, respectively. In this case, the signals on the different reset control signal lines can be the same or different.

[0056] For example, Figure 2 As shown, when the display substrate is working, in the first stage of picture display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage, the same data signal Data is stored in the two N1 nodes of the two pixel circuits 600 through two connected data writing transistors T4, and two driving transistors T3 and two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 in the two pixel circuits 600 (i.e., the pixel circuit pair 610 composed of the first pixel circuit 611 and the second pixel circuit 612) are all turned on to transmit the same data signal to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits 600 are connected to jointly drive the same light-emitting unit 20 to emit light, which can achieve the purpose of increasing current and brightness.

[0057] It should be noted that, in the embodiment of the present disclosure, the pixel circuit of the sub-pixel can be Figure 2 In addition to the 7T1C structure (i.e., seven transistors and one capacitor) shown, structures including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, are not limited in the present disclosure. As long as the data writing transistors T4 of the two pixel circuits are connected, and the N4 nodes of the two pixel circuits are connected to achieve common driving of the same light-emitting unit, the result is sufficient.

[0058] Figure 3A FIG. 1 is a schematic diagram of a partial planar structure of an active semiconductor layer of a pixel circuit in a second display area according to an embodiment of the present disclosure. Figure 3AAs shown, the active semiconductor layer 3100 can be formed by patterning a semiconductor material. The active semiconductor layer 3100 can be used to form the active layer of the second reset transistor T1, threshold compensation transistor T2, drive transistor T3, data write transistor T4, second emission control transistor T5, first emission control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes an active layer pattern (channel region) and a doping region pattern (source and drain doping region) for each transistor in each sub-pixel. The active layer pattern and doping region pattern of each transistor in the same pixel circuit are integrated.

[0059] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be made conductive through doping, etc., to achieve electrical connection between the various structures. In other words, the active semiconductor layer of each transistor in each sub-pixel is a monolithic pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern, with the active layers of different transistors separated by doped structures.

[0060] For example, the active semiconductor layer 3100 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0061] Figure 3B Schematic diagram of the active semiconductor layer and first conductive layer stack within the second display area according to an embodiment of the present disclosure. The display substrate includes a gate insulating layer located on the side of the active semiconductor layer facing away from the base substrate, which is used to insulate the active semiconductor layer 3100 from the subsequently formed first conductive layer 3200 (i.e., the gate metal layer). Figure 3B The display substrate includes a first conductive layer 3200, which is disposed on the gate insulating layer to be insulated from the active semiconductor layer 3100. The first conductive layer 320 may include a second electrode CC2 of the capacitor C, a plurality of scan signal lines 430 extending along a first direction (the X direction in the figure), a plurality of reset control signal lines 440, a plurality of light emission control signal lines 450, and gates of a second reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data write transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0062] For example, Figure 3BAs shown, the gate of the data write transistor T3 may be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100; the gate of the first light emission control transistor T6 may be the first portion where the light emission control signal line 450 overlaps with the active semiconductor layer 3100, and the gate of the second light emission control transistor T5 may be the second portion where the light emission control signal line 450 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 may be the first portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 may be the second portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 may be a thin film transistor with a dual-gate structure, the first gate of the threshold compensation transistor T2 may be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100, and the second gate of the threshold compensation transistor T2 may be the portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100. As shown Figure 3B As shown, the gate of the driving transistor T1 may be the second electrode CC2 of the capacitor C.

[0063] It should be noted that Figure 3B The dotted rectangular boxes in the figure show the parts where the first conductive layer 3200 overlaps with the active semiconductor layer 3100. As the channel region of each transistor, the active semiconductor layers on both sides of each channel region are conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0064] For example, Figure 3B As shown, the scan signal line 430, the reset control signal line 440, and the light control signal line 450 are arranged along the second direction (Y direction). The scan signal line 430 is located between the reset control signal line 440 and the light control signal line 450. The first direction and the second direction in the embodiment of the present disclosure are directions that intersect with each other, for example, the first direction is perpendicular to the second direction. The first direction and the second direction in the embodiment of the present disclosure can be interchangeable.

[0065] For example, in the second direction, the second electrode CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scanning signal line 430 and the emission control signal line 450. The protruding structure P protruding from the scanning signal line 430 is located on a side of the scanning signal line 430 away from the emission control signal line 450.

[0066] For example, a first insulating layer is formed on the first conductive layer 3200 to insulate the first conductive layer 3200 from the second conductive layer 3300 to be formed subsequently.

[0067] Figure 3C is a schematic diagram of a partial planar structure of the second conductive layer in the second display area according to an embodiment of the present disclosure. Figure 3D FIG1 is a schematic diagram of the stacking of the active semiconductor layer, the first conductive layer and the second conductive layer in the second display area according to an embodiment of the present disclosure. Figures 3C to 3D As shown, the second conductive layer 330 includes a first electrode CC1 of a capacitor C and a plurality of reset power signal lines 410 extending along a first direction. The first electrode CC1 of the capacitor C and the second electrode CC2 of the capacitor C at least partially overlap to form a capacitor C.

[0068] like Figures 3C to 3D As shown, the display substrate provided by the embodiment of the present disclosure also includes a plurality of first connection portions 510, the first ends of at least some of the first connection portions 510 are connected to the second electrode of the data writing transistor T4 of the first pixel circuit 611 in the first pixel circuit unit, and the second ends of the first connection portions 510 are connected to the second electrode of the data writing transistor T4 of the second pixel circuit 612 in the first pixel circuit unit so that at least two data writing transistors T4 of the first pixel circuit unit are connected to the same data line, and along the second direction, the first connection portion 510 is located between the second electrode of the data writing transistor T2 in the first pixel circuit 611 and the first electrode of the first reset control transistor T7.

[0069] In the embodiment of the present disclosure, the second electrodes of the data writing transistors of at least two pixel circuits in the second display area are connected through a first connecting portion to drive a light-emitting unit to emit light, which can increase the current and brightness of the light-emitting unit in the second display area. For example, the current and brightness of the light-emitting unit in the second display area can be increased to 1.8 to 2 times that of the case where one pixel circuit is used for driving, thereby solving the problem of low current and brightness in the second display area and achieving a more uniform full-screen visual display effect.

[0070] For example, a first end of a portion of the first connection portion 510 is connected to the second electrode of the data write transistor T4 of the third pixel circuit in the second pixel circuit unit, and a second end of the first connection portion 510 is connected to the second electrode of the data write transistor T4 of the fourth pixel circuit in the second pixel circuit unit, so that at least two data write transistors T4 of the second pixel circuit unit are connected to the same data line, and along the second direction, the first connection portion 510 is located between the second electrode of the data write transistor T2 in the third pixel circuit and the first electrode of the first reset control transistor T7. For the convenience of subsequent description, the first pixel circuit unit and the second pixel circuit unit in this disclosure are collectively referred to as a pixel circuit pair, and the two pixel circuits included in each pixel circuit unit are both referred to as the first pixel circuit and the second pixel circuit, that is, the third pixel circuit in the second pixel circuit unit can be referred to as the first pixel circuit, and the fourth pixel circuit in the second pixel circuit unit can be referred to as the second pixel circuit.

[0071] For example, along the second direction, the first connection portion 510 is located between the second electrode of the threshold compensation transistor T3 and the first electrode of the first reset control transistor T7 in the first pixel circuit 611 .

[0072] For example, the first connection portion 510 is provided on the same layer as the reset power signal line 410 .

[0073] For example, a second insulating layer is formed on the second conductive layer 3300 to insulate the second conductive layer 3300 from the subsequently formed source-drain metal layer 3400 .

[0074] For example, Figure 3E Schematic diagram of a partial planar structure of a source / drain metal layer in a second display area according to an embodiment of the present disclosure. Figure 3F FIG1 is a schematic diagram of the stacking of the active semiconductor layer, the first conductive layer, the second conductive layer and the source / drain metal layer in the second display area according to an embodiment of the present disclosure. Figures 3E to 3F As shown, the source / drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along the second direction. The data line 420 is electrically connected to the second electrode of the data write transistor T2 via a via extending through the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line 460 is electrically connected to the first electrode of the second emission control transistor T5 via a via extending through the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal lines 460 and the data lines 420 are arranged alternately along the first direction. The power signal line 460 is electrically connected to the first electrode CC1 of the capacitor C via a via extending through the second insulating layer.

[0075] For example, a passivation layer and a planarization layer may be provided on a side of the source / drain metal layer 3400 away from the substrate to protect the source / drain metal layer 3400 .

[0076] For example, Figures 3D to 3F The schematic diagram shows a portion of the pixel circuits in the second pixel circuit group 220 and a portion of the pixel circuits in the third pixel circuit group 230. The disclosed embodiment schematically shows that both the second pixel circuit group 220 and the third pixel circuit group 230 include pixel circuit pairs, each including a first pixel circuit 611 and a second pixel circuit 612 arranged along a first direction. The second electrodes of the data write transistors T4 in the two pixel circuits in each pixel circuit pair are connected via a first connection portion 510 to drive the same light-emitting unit to emit light. The disclosed embodiment is not limited to this. For example, only the second pixel circuit group may include the aforementioned pixel circuit pairs, or only the third pixel circuit group may include the aforementioned pixel circuit pairs.

[0077] For example, Figures 3D to 3F As shown, the second pixel circuit group 220 and the third pixel circuit group 230 may include eight pixel circuits arranged in two rows, that is, four pixel circuit pairs arranged in a two-dimensional array. The first pixel circuit group does not include the above-mentioned pixel circuit pairs (not shown), and only includes four pixel circuits arranged in a two-dimensional array. The two adjacent pixel circuits arranged along the first direction in the first pixel circuit group each drive a light-emitting unit to emit light, and the two data writing transistors in the two adjacent pixel circuits are independent of each other and are respectively connected to different data lines. The layout difference between the first pixel circuit group and the second pixel circuit group in the embodiment of the present disclosure mainly lies in whether the first connecting portion is provided, and the setting of the position of the second pole of the data writing transistor connected to the first connecting portion.

[0078] For example, Figures 3D to 3FAs shown, the display substrate provided in the embodiments of the present disclosure can adopt a Quarter High Definition (QHD) resolution. However, because the distance along the second direction between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in each pixel circuit designed for this resolution is very small, for example, less than 2 microns, such as 1.4 to 1.8 microns, it is difficult to provide a first connection portion connecting the second electrodes (data input nodes) of the two data write transistors of the pixel circuit pair between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor. Since the pixel size in QHD resolution products is generally smaller than that in Full High Definition (FHD) resolution products, in the embodiments of the present disclosure, the pixel circuit with QHD resolution is designed to fit within the pixel pitch of FHD resolution. This increases the distance along the second direction between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in each pixel circuit to ensure that the data input nodes of the two pixel circuits of the pixel circuit pair are connected through the first connection portion.

[0079] For example, Figures 3D to 3F As shown, with respect to a display substrate, wherein the second display area includes a plurality of light-emitting units and a plurality of pixel circuits connected one-to-one with the plurality of light-emitting units, and a dummy pixel circuit that is not connected to any light-emitting unit is arranged between adjacent pixel circuits, in the embodiment of the present disclosure, a first connecting portion is used to connect the dummy pixel circuit with the pixel circuit connected to the light-emitting unit in the second display area. The dummy pixel circuit can be effectively utilized on the basis of minimizing changes to the overall structure of the pixel circuit, thereby increasing the current and brightness of the light-emitting unit in the second display area (and at least one of the third display area), thereby achieving a more uniform full-screen visual display effect.

[0080] For example, the distance between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 along the second direction is 7-12 μm to set the first connection portion 510 between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0081] For example, Figures 3A to 3FAs shown, each pixel circuit further includes: a second connection portion 520 and a third connection portion 530, which are provided in the same layer as the data line 420. The second connection portion 520 is configured to connect the second electrode of the threshold compensation transistor T2 and the gate of the driving transistor T3, and the third connection portion 530 is configured to connect the first electrode of the first reset control transistor T7 and the reset power signal line 410. For example, one end of the second connection portion 520 is electrically connected to the second electrode of the threshold compensation transistor T2 via a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, and the other end of the second connection portion 520 is electrically connected to the gate of the driving transistor T3 (i.e., the second electrode CC2 of the capacitor C) via a via penetrating the first insulating layer and the second insulating layer. One end of the third connection portion 530 is electrically connected to the reset power signal line 410 via a via penetrating the second insulating layer, and the other end of the third connection portion 530 is electrically connected to the first electrode of the first reset control transistor T7 via a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0082] For example, Figures 3A to 3F As shown, in the first pixel circuit 611, the distance between the adjacent edges of the second connection portion 520 and the third connection portion 530 in the second direction is 7 to 12 micrometers, so that the first connection portion 510 is disposed between the second connection portion 520 and the third connection portion 530. For example, in the first pixel circuit 611, the distance between the adjacent edges of the second connection portion 520 and the third connection portion 530 in the second direction may be 8 to 11 micrometers.

[0083] For example, Figures 3A to 3F As shown, the first connection portions 510 and the data lines 420 are located in different layers, and along a third direction perpendicular to the base substrate, each first connection portion 510 overlaps with the data lines 420 and the power signal line 460. For example, a data line 410 and a power signal line 460 are provided between the two data write transistors T4 included in the pixel circuit pair 610, and the first connection portion 510 connecting the two data write transistors T4 overlaps with both the data line 410 and the power signal line 460.

[0084] For example, Figures 3A to 3FAs shown, each pixel circuit further includes a fourth connection portion 540 disposed in the same layer as the data line 420. The fourth connection portion 540 is configured to connect the first connection portion 510 and the second electrode of the data writing transistor T4. A gap exists between the fourth connection portion 540 of one of the pixel circuit pairs 610 (e.g., the second pixel circuit 612) and the immediately adjacent data line 420. The fourth connection portion 540 of the other pixel circuit pair 610 (e.g., the first pixel circuit 611) is integrally structured with the data line 420, thereby enabling the pixel circuit pair 610 to be connected to only one data line 420. The phrase "a gap exists between the fourth connection portion 540 and the immediately adjacent data line 420" above refers to the absence of other data lines between the fourth connection portion 540 and the data line 420.

[0085] For example, Figure 1 、 Figures 3A to 3F As shown, a plurality of first pixel circuit groups 210 are arranged in an array along a first direction and a second direction. Along the first direction, a plurality of second pixel circuit groups 220 and a plurality of third pixel circuit groups 230 are alternately arranged. Along the second direction, a plurality of second pixel circuit groups 220 and a plurality of third pixel circuit groups 230 are alternately arranged, and the second pixel circuit groups 220 and the third pixel circuit groups 230 are connected to different data lines 420.

[0086] For example, a straight line extending along the first direction passes through the second electrodes of two data writing transistors in a pixel circuit pair, and the entire first connection portion extends along the first direction. For example, different pixel circuit groups are connected to different data lines, so the lengths of the first connection portions along the first direction in different pixel circuit groups can be different. For example, in the same pixel circuit group, the lengths of the first connection portions along the first direction in different pixel circuit pairs can also be different.

[0087] For example, Figure 3EAs shown, the fourth connecting portion 540 integral with the data line 420 is a first sub-portion 541, and the fourth connecting portion 540 spaced apart from the adjacent data line 420 is a second sub-portion 542. For example, in the second pixel circuit group including eight pixel circuits arranged in an array (four pixel circuits arranged in the row direction and two pixel circuits arranged in the column direction), in the second pixel circuit group, two first sub-portions 541 are arranged along the second direction (e.g., in a column), and two second sub-portions 542 are arranged along the second direction (e.g., in a column), and the first sub-portions 541 and the second sub-portions 542 are arranged alternately in the first direction (e.g., in the row direction). Similarly, the arrangement of the first sub-portion and the second sub-portion in the third pixel circuit group is the same as that of the first sub-portion and the second sub-portion in the second pixel circuit group. For the second and third pixel circuit groups arranged alternately along the second direction, the first sub-portion in the second pixel circuit group and the second sub-portion in the third pixel circuit group are located in different columns so that the second pixel circuit group and the third pixel circuit group are connected to different data lines.

[0088] Since there is no pixel circuit pair design in the first pixel circuit group, the fourth connection parts of two adjacent pixel circuits arranged along the first direction or the second direction in the first pixel circuit group are integrated with the data line to achieve electrical connection between each pixel circuit and the corresponding data line.

[0089] For example, Figures 3A to 3F As shown, the display substrate further includes a plurality of covering portions S disposed on the same layer as the first connecting portion 510. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2, and an active semiconductor layer 3100 located between the two gates. Along the third direction, the covering portion S overlaps with the active semiconductor layer 3100 between the two gates, the data line 420, and the power signal line 460.

[0090] For example, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, thereby affecting the leakage current of the threshold compensation transistor T2, and further affecting the luminous brightness. In order to maintain the voltage stability of the active semiconductor layer between the two channels of the threshold compensation transistor T2, a capacitor is formed between the cover portion S and the active semiconductor layer between the two channels of the threshold compensation transistor T2. The cover portion S can be connected to the power signal line 460 to obtain a constant voltage, so that the voltage of the active semiconductor layer in the floating state can be kept stable. The cover portion S overlaps with the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2, and can also prevent the active semiconductor layer between the two gates from being illuminated by light and changing its characteristics, such as preventing the voltage of this part of the active semiconductor layer from changing, so as to prevent crosstalk. For example, the power signal line 460 can be electrically connected to the cover portion S through a via penetrating the second insulating layer to provide a constant voltage to the cover portion S.

[0091] For example, the orthographic projection of the covering portion S overlapping with the active semiconductor layer on the first straight line extending along the first direction overlaps with the orthographic projection of the first connecting portion 510 on the first straight line, and the orthographic projection of the fourth connecting portion 540 on the second straight line extending along the second direction overlaps with the orthographic projection of the covering portion S on the second straight line. Therefore, in order to maintain a distance from the covering portion S set in the same layer, the first connecting portion 510 is set as a non-linear shape as a whole, such as a broken line shape.

[0092] For example, Figures 3A to 3F As shown, the first connection portion 510 includes a main connection portion 511 extending along the first direction and two end portions 512 located at both ends of the main connection portion 511 and extending along the second direction. The two end portions 512 are respectively connected to the two fourth connection portions 540 of the pixel circuit pair 610. The orthographic projections of the two end portions 512 on the second straight line overlap with the orthographic projection of the cover portion S on the second straight line. As a result, the main connection portion and the two end portions form a broken line shape to maintain a distance from the cover portion.

[0093] For example, in the second direction, the distance between the covering portion S and the second electrode of the threshold compensation transistor T2 is smaller than the distance between the covering portion S and the first electrode of the first reset control transistor T7, that is, the covering portion S is closer to the threshold compensation transistor T2. Therefore, for the convenience of design and to maintain a certain distance between the first connecting portion 510 and the covering portion S, the first connecting portion 510 is arranged closer to the first electrode of the first reset transistor T7. That is, in the Y direction, the distance between the main connecting portion 511 and the second electrode of the threshold compensation transistor T2 in the first pixel circuit 611 is larger than the distance between the main connecting portion 511 and the first electrode of the first reset control transistor T7 in the first pixel circuit 611.

[0094] For example, Figure 4A Schematic diagram of the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area according to an embodiment of the present disclosure. Figure 4B for Figure 4A Schematic layer structure diagram of a light-emitting unit. Figures 1 to 4B As shown, each light-emitting unit group includes multiple light-emitting units 20. For example, each light-emitting unit group includes a first-color light-emitting unit 201, a second-color light-emitting unit pair 202, and a third-color light-emitting unit 203. The first-color light-emitting unit 201 and the third-color light-emitting unit 203 are arranged along the second direction. The second-color light-emitting unit pair 202 includes two second-color light-emitting units arranged along the second direction, namely, a first light-emitting unit block 202-1 and a second light-emitting unit block 202-2. The first-color light-emitting units 201 and the second-color light-emitting unit pair 202 are arranged along the first direction. For example, the orthographic projection of the second electrode of the first-color light-emitting unit 201 on a straight line extending along the Y direction overlaps with the orthographic projection of the second electrode of the first light-emitting unit block 202-1 on the same line; and the orthographic projection of the second electrode of the third-color light-emitting unit 203 on a straight line extending along the Y direction overlaps with the orthographic projection of the interval between the second electrodes of the two second-color light-emitting units on the same line. For example, the orthographic projection of the main electrode (described later) of the third color light emitting unit 203 on the straight line extending in the direction does not overlap with the orthographic projections of the main electrodes of the two second color light emitting units on the straight line.

[0095] For example, each light-emitting unit 20 includes a first electrode 21, a light-emitting layer 23, and a second electrode 22, arranged in sequence perpendicular to the base substrate 10. The second electrode 12 is located on the side of the light-emitting layer 13 facing the base substrate 10. The display substrate also includes a pixel-defining layer 24. The pixel-defining layer 24 includes an opening for defining the light-emitting area of the sub-pixel. The opening exposes the second electrode 22 of the light-emitting unit 20. When the light-emitting layer 23 of a subsequent light-emitting unit 20 is formed in the opening of the pixel-defining layer 24, the light-emitting layer 23 contacts the second electrode 22, thereby driving the light-emitting layer 23 to emit light, forming an effective light-emitting area. The "effective light-emitting area" here can refer to a two-dimensional planar area parallel to the base substrate. It should be noted that due to process reasons, the size of the pixel-defining layer openings farther from the base substrate may be slightly larger than that closer to the base substrate, or may gradually increase in size from closer to the base substrate to farther away from the base substrate. Therefore, the size of the effective light-emitting area may vary slightly from the size of the pixel-defining layer openings at different locations, but the overall shape and size of the area are generally consistent. For example, the orthographic projection of the effective light-emitting area on the substrate substantially overlaps with the orthographic projection of the corresponding pixel-defining layer opening on the substrate. For example, the orthographic projection of the effective light-emitting area on the substrate completely falls within the orthographic projection of the corresponding pixel-defining layer opening on the substrate, and the two have similar shapes, and the projected area of the effective light-emitting area on the substrate is slightly smaller than the projected area of the corresponding pixel-defining layer opening on the substrate.

[0096] For example, the first color light-emitting unit can be one of a red light-emitting unit and a blue light-emitting unit, the third color light-emitting unit can be the other of the red light-emitting unit and the blue light-emitting unit, and the second color light-emitting unit pair can be a green light-emitting unit pair. This disclosure schematically illustrates that the first color light-emitting unit is a red light-emitting unit and the second color light-emitting unit is a green light-emitting unit.

[0097] For example, Figures 1 to 4BAs shown, each pixel circuit further includes a fifth connection portion 550 disposed in the same layer as the data line 420. The second electrode 22 of the light-emitting unit 20 located in the first display area 100 and the second display area 200 can be directly electrically connected to the second electrode of the first emission control transistor T6 via the fifth connection portion 550. For example, in the first display area 100, the second electrode of each light-emitting unit 20 in the first light-emitting unit group 110 can be directly electrically connected to the second electrode of the first emission control transistor T6 via the fifth connection portion 550 of the corresponding pixel circuit 600 in the first pixel circuit group 120. In the second display area 200, the second electrode of each light-emitting unit 20 in the second light-emitting unit group 210 can be directly electrically connected to the second electrode of the first emission control transistor T6 via the fifth connection portion 550 of the corresponding pixel circuit 600 in the second pixel circuit group 220. For example, in the second display area 200, the second electrode of each light-emitting unit 20 in the second light-emitting unit group 210 can be connected to the fifth connection portion 550 via the first via hole 561 in the passivation layer and the planarization layer.

[0098] For example, Figures 1 to 4B As shown, the second pixel circuit group 220 includes a plurality of pixel circuit pairs 610, and the second electrode 22 of each light-emitting unit 20 of the second light-emitting unit group 210 includes a main electrode and a connecting electrode. The shape of the main electrode is substantially the same as the shape of the effective light-emitting area of each light-emitting unit 20, and the connecting electrode is configured to be directly electrically connected to the fifth connecting portion 550 so as to be electrically connected to the second electrodes of the two first light-emitting control transistors T6 of the pixel circuit pair 610.

[0099] For example, Figures 1 to 4B As shown, the display substrate further includes a plurality of transparent traces 700 located between the second electrode 22 and the film layer where the data line 420 is located. Each transparent trace 700 extends along the first direction. For example, the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610. The transparent traces 700 are configured to connect the second electrodes 22 of the light-emitting cells 20 in the third light-emitting cell group 310 and the fifth connecting portion 550 to electrically connect the second electrodes 22 of each light-emitting cell 20 in the third light-emitting cell group 310 to the second electrodes of the two first light-emitting control transistors T6 of the pixel circuit pairs 610 in the third pixel circuit group 230.

[0100] For example, in the second display area 200, the transparent wiring 700 is electrically connected to the fifth connection portion 550 in the third pixel circuit group 310 through the passivation layer and the second via 562 in the flat layer; in the third display area 300, the second electrode 22 of the light-emitting unit 20 is connected to the transparent wiring 700 through the third insulating layer located between the transparent wiring 700 and the second electrode 22, thereby achieving connection with the pixel circuit 600 in the second display area 200.

[0101] For example, Figure 4C for Figure 4A Schematic diagram of the relationship between the second light emitting unit group and the via hole position in the second display area. Figure 4A and Figure 4C As shown, a first via group 5610 is formed by connecting a second light-emitting unit group 210 and a second pixel circuit group 220, and a second via group 562 is formed by connecting a third light-emitting unit group 310 and a third pixel circuit group 230. Along the first direction, the multiple first via groups 5610 and the multiple second via groups 5620 are arranged alternately; along the second direction, the multiple first via groups 5610 and the multiple second via groups 5620 are arranged alternately. Compared to the case where both the second and third light-emitting unit groups are connected to the fifth connection portion via the film layer containing transparent traces, in the disclosed embodiment, the second electrodes of the light-emitting units of the second light-emitting unit group are directly connected to the fifth connection portion, while the second electrodes of the light-emitting units of the third light-emitting unit group are connected to the fifth connection portion via transparent traces. This allows more space for the transparent traces and prevents signal crosstalk.

[0102] For example, Figure 5D for Figure 1 Partial plan view of the first display area and the second display area in the display substrate shown. Figure 1 and Figure 5D As shown, in one embodiment of the present disclosure, the first display area 100 and the second display area 200 of the display substrate include a plurality of pixel circuits 030 arranged along a first direction and a second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. The plurality of pixel circuits 030 located in the first display area 100 include a plurality of first sub-pixel circuits 031, and the plurality of pixel circuits 030 located in the second display area 200 include a plurality of second sub-pixel circuits 032. The plurality of first light-emitting units in the first display area 100 (i.e., the light-emitting units of the three colors included in the first light-emitting unit group 110, such as R, G1, G2, and B shown in the figure) are connected one-to-one with the plurality of first sub-pixel circuits 031, and each second light-emitting unit in the second display area 200 (i.e., the light-emitting units of the three colors included in the second light-emitting unit group 210, such as R, G1, G2, and B shown in the figure) is connected with at least two second sub-pixel circuits 032.

[0103] For example, Figure 1 As shown, the first display area 100 and the second display area 200 are connected in the Y direction (i.e., the extension direction of the data line). The third display area 300 includes a central area 301 and an edge area 302 surrounding the central area 301, and the edge area 302 of the third display area 300 is connected to the first display area 100 in the Y direction. For example, Figure 1The schematic diagram shows that the third display area 300 is rectangular in shape, the center area 301 of the third display area 300 is circular in shape, and the edge area 302 is the area within the rectangle excluding the circular center area. The present disclosure is not limited to this, and the shapes of the center area and edge areas of the third display area can be set according to actual product requirements.

[0104] For example, Figure 1 As shown, the central area 301 and the edge area 302 of the third display area 300 are both provided with a third light-emitting unit group 310, and the multiple third light-emitting unit groups 310 located in the third display area 300 are respectively electrically connected to the multiple third pixel circuit groups 230 in the second display area 200 via transparent traces 700 to drive the third light-emitting unit groups 310 to emit light. The central area 301 of the third display area 300 is only provided with a light-emitting unit group, without a pixel circuit group, thereby reducing the metal coverage area and achieving a higher light transmittance. In addition to the light-emitting unit group, the edge area 302 of the third display area 300 is also provided with a light-blocking structure, so that the third display area 300 forms a light-transmitting area with a preset shape (i.e., the central area 301). For example, in the embodiment of the present disclosure, the light-blocking structure provided in the peripheral area 302 of the third display area 300 can be a plurality of dummy pixel circuit groups 320. The plurality of dummy pixel circuit groups 320 include a portion located between the third light-emitting unit group 310 and the base substrate, and a portion located between adjacent third light-emitting unit groups 310. Each dummy pixel circuit group 320 is not connected to any light-emitting unit group and is merely a suspended pixel circuit. For example, the edge area 302 is a ring-shaped wiring area. For example, the data lines, scan signal lines, power signal lines, reset control lines, light-emitting control signal lines, reset power signal lines, and other lines connecting the third pixel circuit group are all located in the ring-shaped wiring area.

[0105] For example, Figure 1 As shown, the third light-emitting unit group 310 in the third display area 300 can be controlled in a half-left-half manner, with the third pixel circuit groups 230 in two second display areas 200, which are symmetrical about the center line of the third display area 300 extending in the Y direction, being controlled separately. For example, the third light-emitting unit group 310 located to the left of the aforementioned center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the left of the center line, and the third light-emitting unit group 310 located to the right of the aforementioned center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the right of the center line. The wiring used to drive the light-emitting units in the circular center area 301 is arranged in a dense pattern in the edge area 302, so that the circular center area 301, which serves as the under-screen display area, has the largest possible area.

[0106] For example, Figure 1As shown, the first display area 100 and the second display area 200 include a plurality of pixel circuits arranged along the first direction and the second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. For example, the edge area 302 of the third display area 300 includes a plurality of dummy pixel circuits 034 arranged along the first direction and the second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows. Here, the dummy pixel circuits in the third display area 300 are also referred to as pixel circuits. Although the dummy pixel circuits are not connected to any light-emitting unit, their structure can be roughly the same as the pixel circuit structure in other areas, for example, both include a 7T1C (i.e., seven transistors and one capacitor) structure. For example, a plurality of data lines 420 extending along the Y direction are respectively connected to the plurality of pixel circuit columns 32.

[0107] For example, Figures 1 to 4A As shown, each pixel circuit column 32 includes a pixel circuit column group consisting of four adjacent columns. Each pixel circuit column group includes a first pixel circuit column 321, a second pixel circuit column 322, a third pixel circuit column 323, and a fourth pixel circuit column 324 arranged in sequence along the X direction (i.e., a direction intersecting the extending direction of the data line 420). The first pixel circuit column 321, the second pixel circuit column 322, the third pixel circuit column 323, and the fourth pixel circuit column 324 in the first display area 100 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged in sequence along the X direction. At least part of the pixel circuits in the first pixel circuit column 321, at least part of the pixel circuits in the second pixel circuit column 322, at least part of the pixel circuits in the third pixel circuit column 323, and at least part of the pixel circuits in the fourth pixel circuit column 324 in the second display area 200 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged in sequence along the X direction.

[0108] For example, Figures 1 to 4A As shown, within the second display area 200, in at least one pixel circuit column group, the data output ends (i.e., fourth connection portions 540) of two pixel circuits located in the same pixel circuit row 31 and in the first pixel circuit column 321 and the second pixel circuit column 322 are electrically connected to form a first pixel circuit pair 601, and the data output ends (i.e., fourth connection portions 540) of two pixel circuits 600 located in the same pixel circuit row 31 and in the third pixel circuit column 323 and the fourth pixel circuit column 324 are electrically connected to form a second pixel circuit pair 602. The embodiment of the present disclosure schematically illustrates an example in which each pixel circuit column group within the second display area includes a first pixel circuit pair and a second pixel circuit pair, but is not limited thereto and can be configured according to actual product requirements.

[0109] For example, Figures 1 to 4AThe first display area 100, the second display area 200, and the third display area 300 each include a plurality of light-emitting units 20. The plurality of light-emitting units 20 in the first display area 100 are respectively connected to the plurality of pixel circuits 600 in the first display area 100. The plurality of light-emitting units 20 in the second display area 200 are respectively connected to a portion of the pixel circuits 600 in the second display area 200, and the plurality of light-emitting units 20 in the third display area 300 are respectively connected to another portion of the pixel circuits 600 in the second display area 200. That is, in the second display area 200, the light-emitting units 20 in the second light-emitting unit group 210 are connected to the pixel circuits 600 in the second pixel circuit group 220; and the light-emitting units 20 in the third light-emitting unit group 310 in the third display area 300 are connected to the pixel circuits 600 in the third pixel circuit group 230 in the second display area 200. The embodiment of the present disclosure schematically shows that the second display area only includes the second pixel circuit group and the third pixel circuit group, but is not limited to this. Depending on factors such as space design requirements in the product, the second display area may also include other pixel circuit groups, such as a dummy pixel circuit group (not connected to the light-emitting unit), etc.

[0110] For example, Figures 1 to 4A As shown, the second pixel circuit group 220 and the third pixel circuit group 230 in the second display area 200 both include a first pixel circuit pair 601 and a second pixel circuit pair 602. Then, in the second display area 200 and the third display area 300, the multiple light-emitting units 20 are respectively connected to the multiple first pixel circuit pairs 601 and the multiple second pixel circuit pairs 602 in the second display area 200.

[0111] For example, the light-emitting unit set in the first display area in the embodiment of the present disclosure can be called a first light-emitting unit, the light-emitting unit set in the second display area can be called a second light-emitting unit, and the light-emitting unit set in the third display area can be called a third light-emitting unit.

[0112] Because the second pixel circuit groups 220 and the third pixel circuit groups 230 are arranged alternately in both the X and Y directions, and the second pixel circuit groups 220 and the third pixel circuit groups 230 in the same column arranged in the Y direction are connected to different data lines 420, some of the pixel circuits in the first pixel circuit column 321 within the second display area 200 are connected to the first data line 421. For example, the pixel circuits in the second pixel circuit group 220 within the first pixel circuit column 321 are connected to the first data line 421, while the pixel circuits in the third pixel circuit group 230 within the first pixel circuit column 321 are not connected to the first data line 421. Similarly, some of the pixel circuits in the second pixel circuit column 322 within the second display area 200 are connected to the second data line 422. For example, the pixel circuits in the third pixel circuit group 230 within the second pixel circuit column 322 are connected to the second data line 422, while the pixel circuits in the second pixel circuit group 220 within the second pixel circuit column 322 are not connected to the second data line 422. Some pixel circuits in the third pixel circuit column 323 located in the second display area 200 are connected to the third data line 423, for example, the pixel circuits in the third pixel circuit group 230 located in the third pixel circuit column 323 are connected to the third data line 423, while the pixel circuits in the second pixel circuit group 220 located in the third pixel circuit column 323 are not connected to the third data line 423. Some pixel circuits in the fourth pixel circuit column 324 located in the second display area 200 are connected to the fourth data line 424, for example, the pixel circuits in the second pixel circuit group 220 located in the fourth pixel circuit column 324 are connected to the fourth data line 422, while the pixel circuits in the third pixel circuit group 230 located in the fourth pixel circuit column 324 are not connected to the fourth data line 424.

[0113] For example, Figures 1 to 4A As shown, multiple first pixel circuit pairs 601 connected to the multiple light-emitting units 20 of the second display area 200 are connected to the first data line 421, multiple second pixel circuit pairs 602 connected to the multiple light-emitting units 20 of the second display area 200 are connected to the fourth data line 424, multiple first pixel circuit pairs 601 connected to the multiple light-emitting units 20 of the third display area 300 are connected to the second data line 422, and multiple second pixel circuit pairs 601 connected to the multiple light-emitting units 20 of the third display area 300 are connected to the third data line 423.

[0114] For example, in the second pixel circuit group 220, the two pixel circuits in the first pixel circuit pair 601 are connected to the first data line 421, and the two pixel circuits in the second pixel circuit pair 602 are connected to the fourth data line 424. In the third pixel circuit group 230, the two pixel circuits in the first pixel circuit pair 601 are connected to the second data line 422, and the two pixel circuits in the second pixel circuit pair 602 are connected to the third data line 423.

[0115] For example, Figures 1 to 4A As shown, the first pixel circuit pair 601 connected to the first color light-emitting unit 201 and the third color light-emitting unit 203 in the second light-emitting unit group 210 is connected to the first data line 421, and the second pixel circuit pair 602 connected to the second color light-emitting unit pair 202 in the second light-emitting unit group 210 is connected to the fourth data line 424.

[0116] Figure 5A FIG1 is a schematic diagram of a structure of a portion of pixel circuits at the junction of the first display area and the second display area according to an embodiment of the present disclosure. Figure 5B for Figure 5A Schematic diagram of the film structure where the data line connection part is located at the position shown, Figure 5C for Figure 5A The schematic diagram of the film structure where the data line is located is shown. Figures 1 to 5DAs shown, at the boundary between the first display area 100 and the second display area 200, that is, the gap between the first sub-pixel circuit 031 and the second sub-pixel circuit 032, the second data line 422, the third data line 423, and the fourth data line 424 connected to at least one pixel circuit column group are disconnected to form a first break 4201, while the first data line 421 remains continuous without a break. In other words, the portion of the second data line 422 located in the second display area 200 is disconnected from the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200. Similarly, the portion of the third data line 423 located in the second display area 200 is disconnected from the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200; and the portion of the fourth data line 424 located in the second display area 200 is disconnected from the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200. The endpoint 4220 of the second data line 422 located in the first display area 100 close to the second display area 200 is connected to the endpoint 4240 of the fourth data line 424 located in the second display area 200 close to the first display area 100 through the data line connecting portion 560. The data line connecting portion 560 passes through the first break 4201 of the third data line 423. The first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 here can refer to a continuous data line, such as the first data line 421 is a continuous data line; they can also refer to discontinuous data lines connected to the same column of pixel circuits, such as the second data line 422, the third data line 423 and the fourth data line 424, thereby, the second data line 422 connected to the first sub-pixel circuit and the second data line 422 connected to the second sub-pixel circuit are configured to transmit different signals; the third data line 423 connected to the first sub-pixel circuit and the third data line 423 connected to the second sub-pixel circuit are configured to transmit different signals; the fourth data line 424 connected to the first sub-pixel circuit and the fourth data line 424 connected to the second sub-pixel circuit are configured to transmit different signals.

[0117] For example, the second data line 422 connected to the first sub-pixel circuit 031 and the second data line 422 connected to the second sub-pixel circuit 032 are configured to transmit different signals; the third data line 423 connected to the first sub-pixel circuit 031 and the third data line 423 connected to the second sub-pixel circuit 032 are configured to transmit different signals; the fourth data line 424 connected to the first sub-pixel circuit 031 and the fourth data line 424 connected to the second sub-pixel circuit 032 are configured to transmit different signals. Although the data lines located on the same straight line in the first display area and the second display area are referred to as the second data line, the third data line, or the fourth data line in different display areas are configured to transmit different signals.

[0118] For example, the embodiment of the present disclosure schematically shows that the endpoint of the second data line in the first display area close to the second display area is connected to the endpoint of the fourth data line in the second display area close to the first display area through a data line connecting portion, but is not limited to this. The endpoint of the second data line in the first display area close to the second display area can also be connected to the endpoint of the third data line in the second display area close to the first display area through a data line connecting portion.

[0119] In the embodiment of the present disclosure, the pixel circuit located in the first display area is called a first sub-pixel circuit, the pixel circuit connected to the light-emitting unit located in the second display area is called a second sub-pixel circuit, and the pixel circuit connected to the light-emitting unit located in the third display area is called a third sub-pixel circuit.

[0120] For example, Figure 5A As shown, the embodiment of the present disclosure takes the example that the multiple light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include first color light-emitting units and third color light-emitting units, the multiple light-emitting units 20 connected to the second pixel circuit column 322 in the first display area 100 include second color light-emitting unit pairs, the multiple light-emitting units 20 connected to the third pixel circuit column 323 in the first display area 100 include first color light-emitting units and third color light-emitting units, and the multiple light-emitting units 20 connected to the fourth pixel circuit column 324 in the first display area 100 include second color light-emitting unit pairs.

[0121] In the disclosed embodiment, data signals are transmitted from a source driver integrated circuit located on a side of the first display area away from the second display area via data lines to pixel circuits in the first and second display areas. The data signals transmitted to pixel circuits connected to light-emitting units of one color in the second display area should be identical to the data signals transmitted to pixel circuits connected to light-emitting units of the same color in the first display area. Therefore, when a column of pixel circuits in the first display area is connected to the same data line, while a pair of pixel circuits in the second display area is connected to the same data line, it is likely that the data signals transmitted to the pixel circuits connected to light-emitting units of the first color in the first display area will be identical to the data signals transmitted to the pixel circuit pairs connected to light-emitting units of the second color in the second display area, resulting in data signal mismatch between the first and second display areas.

[0122] For example, in the first display area 100, each first light-emitting cell group 110 includes a first-color light-emitting cell, a second-color light-emitting cell pair, and a third-color light-emitting cell. Each second-color light-emitting cell pair includes a first light-emitting cell block and a second light-emitting cell block. The first-color light-emitting cells and the third-color light-emitting cells are arranged in a direction parallel to the direction in which the data lines extend (the Y direction). The first light-emitting cell block and the second light-emitting cell block are arranged in the Y direction. The first-color light-emitting cells and the second-color light-emitting cell pairs are arranged in an X direction that intersects the Y direction. The first-color light-emitting cells in two adjacent first light-emitting cell groups point in opposite directions toward the third-color light-emitting cells. That is, the light-emitting cells connected to a row of pixel circuits in the first display area near the second display area and located in a pixel circuit column group are, in order, the first-color light-emitting cell, the first light-emitting cell block, the third-color light-emitting cell, and the second light-emitting cell block. The four light-emitting cells connected to the second row of pixel circuits in the pixel circuit column group and located in the first display area near the second display area are, in order, the third-color light-emitting cell, the second light-emitting cell block, the first-color light-emitting cell, and the first light-emitting cell block. Therefore, the first and third color light-emitting units connected to the pixel circuits of the first and third pixel circuit columns are arranged differently, and the first and second light-emitting unit blocks connected to the pixel circuits of the second and fourth pixel circuit columns are arranged differently. The data signals transmitted by the data lines are related to the arrangement of the corresponding color light-emitting units, and both the first and second display areas should transmit matching data signals according to the above light-emitting unit arrangements.

[0123] For example, Figures 1 to 5AAs shown, the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the second display area 200 include first-color light-emitting units 201 and third-color light-emitting units 203 arranged alternately. For example, the light-emitting units connected to the pixel circuits in the first pixel circuit column 321, which are located in a row in the second display area 200 near the first display area 100, are third-color light-emitting units 203. The plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include first-color light-emitting units and third-color light-emitting units arranged alternately. The light-emitting units connected to the pixel circuits in the first pixel circuit column 321, which are located in a row in the first display area 100 near the second display area 200, are first-color light-emitting units. Thus, a pixel circuit in a row of pixel circuits in the first display area close to the second display area and connected to the first data line is connected to a first color light-emitting unit, and a pixel circuit in a row of pixel circuits in the second display area close to the first display area and connected to the same first data line is connected to a third color light-emitting unit. The arrangement of the light-emitting units matches the data signal transmitted by the first data line, and the first data line can remain connected at the junction of the first display area and the second display area without being disconnected at the junction of the two display areas.

[0124] For example, Figures 1 to 5A As shown, the plurality of second color light-emitting cell pairs 202 connected to the fourth pixel circuit column 324 in the second display area 200 include alternating first light-emitting cell blocks 202-1 and second light-emitting cell blocks 202-2. For example, the light-emitting cell connected to the pixel circuit in the fourth pixel circuit column 324, located in a row in the second display area 200 near the first display area 100, is the second light-emitting cell block 202-2. The plurality of second color light-emitting cell pairs connected to the fourth pixel circuit column 324 in the first display area 100 include alternating first light-emitting cell blocks and second light-emitting cell blocks. The light-emitting cell connected to the pixel circuit in the fourth pixel circuit column 324, located in a row in the first display area 100 near the second display area 200, is also the second light-emitting cell block. Therefore, the light-emitting unit connected to the pixel circuit of the fourth pixel circuit column in a row of pixel circuits close to the second display area in the first display area and the light-emitting unit connected to the pixel circuit of the fourth pixel circuit column in a row of pixel circuits close to the first display area in the second display area are the same light-emitting unit, then the data signal of the fourth data line connected to the fourth pixel circuit column in the first display area and the data signal of the fourth data line connected to the fourth pixel circuit column in the second display area do not match, therefore, the fourth data line should be disconnected at the junction of the first display area and the second display area.

[0125] For example, Figures 1 to 5AAs shown, the multiple pairs of second-color light-emitting cells connected to the second pixel circuit column 322 in the first display area 100 include alternating first and second light-emitting cell blocks. The light-emitting cells connected to the pixel circuits in the second pixel circuit column 322, located in a row of the first display area 100 near the second display area 200, are the first light-emitting cell blocks. Consequently, the data signal of the fourth data line connected to the fourth pixel circuit column in the second display area matches the data signal of the second data line connected to the second pixel circuit column in the first display area. The portion of the second data line located in the first display area is disconnected from the portion located in the second display area at the boundary between the two display areas. The second data line located in the first display area is connected to the fourth data line located in the second display area via a data line connector, thereby satisfying unified algorithm processing requirements for the integrated circuit (IC) in the first and second display areas.

[0126] In the embodiment of the present disclosure, the second data line, the third data line, and the fourth data line are disconnected at the junction of the first display area and the second display area, and the endpoint of the second data line located in the first display area close to the second display area is connected with the endpoint of the fourth data line located in the second display area close to the first display area through the data line connecting portion, thereby ensuring that the data signal transmitted from the data line to the light-emitting unit in the first display area matches the data signal transmitted from the data line to the light-emitting unit in the second display area.

[0127] For example, Figures 5A to 5C As shown, the data line connector 560 is located on a different layer from the multiple data lines 420. For example, along a direction perpendicular to the substrate, the data line connector 560 overlaps with the power signal line 460. Because the data line connector needs to pass through the first break of the third data line and the two power signal lines to connect the endpoints of the second data line and the fourth data line, the data line connector needs to be located on a different layer from the data lines.

[0128] For example, Figures 5A to 5C As shown, the data line connection portion 560 and the reset power signal line 410 are located on the same layer for ease of design.

[0129] For example, Figures 5A to 5C As shown, a data line connection portion 560 is provided between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in two pixel circuits in a first pixel circuit row 31 adjacent to the second display area 200 in the first display area 100 and located in the third pixel circuit column 323 and the fourth pixel circuit column 324.

[0130] In the embodiment of the present disclosure, the junction of the first display area 100 and the second display area 200 refers to the interval between the first electrode of the first reset transistor and the second electrode of the data writing transistor in a row of pixel circuits 31 close to the second display area 200 in the first display area 100.

[0131] For example, in a row of pixel circuits 31 adjacent to the second display area 200 in the first display area 100, the distance between the second electrode of the threshold compensation transistor T2 and the second electrode of the first reset control transistor T7 in the second direction is 7 to 12 microns so that a data line connection portion 560 is set between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0132] For example, in the pixel circuit in the first display area 100, the distance between the adjacent edges of the second connection portion 520 and the third connection portion 530 in the second direction is 7 to 12 microns, so that the data line connection portion 560 is disposed between the second connection portion 520 and the third connection portion 530. In the embodiment of the present disclosure, although the first connection portion and the data line connection portion are respectively disposed at the second display area and the boundary between the first display area and the second display area, by adjusting the distance between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in the pixel circuit, both the first connection portion and the data line connection portion can be disposed in a larger space reserved between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in the pixel circuit to prevent interference with other signals.

[0133] For example, Figure 6 Schematic diagram of a portion of pixel circuit structure at the junction of the edge area of the first display area and the third display area provided according to an embodiment of the present disclosure. Figure 6As shown, the plurality of dummy pixel circuit columns in the third display area include a dummy pixel circuit column group consisting of four adjacent columns, each dummy pixel circuit column group includes a first dummy pixel circuit column 0341, a second dummy pixel circuit column 0342, a third dummy pixel circuit column 0343, and a fourth dummy pixel circuit column 0344 arranged in sequence along the second direction, at least part of the dummy pixel circuits 034 of the first dummy pixel circuit column 0341, at least part of the dummy pixel circuits 034 of the second dummy pixel circuit column 0342, and the third dummy pixel circuit column 0344. At least part of the dummy pixel circuits 034 of 43 and at least part of the dummy pixel circuits 034 of the fourth dummy pixel circuit column 0344 are respectively connected to the first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 arranged in sequence along the second direction, and the third data line 423 and the fourth data line 424 are disconnected at the interval between the dummy pixel circuit 034 and the first pixel circuit 031 (for example, the junction of the edge area 302 of the third display area 300 and the first display area 100) to form a second break 4202.

[0134] For example, the first dummy pixel circuit column 0341 , the second dummy pixel circuit column 0342 , the third dummy pixel circuit column 0343 and the fourth dummy pixel circuit column 0344 may also be referred to as the first pixel circuit column, the second pixel circuit column, the third pixel circuit column and the fourth pixel circuit column, respectively.

[0135] For example, Figures 1 to 6 As shown, the pixel circuit pair connected to the first color light-emitting unit and the third color light-emitting unit in the third light-emitting unit group 310 can be one of the first pixel circuit pair 601 and the second pixel circuit pair 602, and the pixel circuit pair connected to the second color light-emitting unit pair in the third light-emitting unit group 310 can be the other of the first pixel circuit pair 601 and the second pixel circuit pair 602.

[0136] For example, a pair of pixel circuits connected to the first color light-emitting cells and the third color light-emitting cells of the third light-emitting cell group 310 can be connected to one of the second data line 422 and the third data line 423, and a pair of pixel circuits connected to the first light-emitting cell block and the second light-emitting cell block of the third light-emitting cell group 310 can be connected to the other of the second data line 422 and the third data line 423. For example, a pair of pixel circuits connected to the first color light-emitting cells and the third color light-emitting cells of the third light-emitting cell group 310 can be connected to the third data line 423, and a pair of pixel circuits connected to the first light-emitting cell block and the second light-emitting cell block of the third light-emitting cell group 310 can be connected to the second data line 422. Because the second data line and the third data line are disconnected at the boundary between the first display area and the second display area, the pixel circuits connected to the third light-emitting cell group cannot receive a matching data signal from the data line in the first display area that is adjacent to the second display area. Therefore, in the embodiment of the present disclosure, the first data line and the second data line that are continuous at the junction of the edge area of the third display area and the first display area are respectively connected to the pixel circuit pair connected to the first light-emitting unit block and the second light-emitting unit block of the third light-emitting unit group 310 and the pixel circuit pair connected to the first color light-emitting unit and the third light-emitting unit of the third light-emitting unit group 310, so as to realize the input of the pixel circuit connected to the third light-emitting unit group and match the data signal, so as to meet the unified algorithm processing of the integrated circuit in the first display area and the third display area.

[0137] For example, the plurality of light-emitting units in the third display area 300 connected to the third pixel circuit column 323 of the second display area 200 include first-color light-emitting units and third-color light-emitting units arranged alternately, and the light-emitting units connected to the pixel circuits located in the first row and the third pixel circuit column 323 of the second display area 200, which are located away from the first display area 100, are third-color light-emitting units. The plurality of light-emitting units 20 in the first display area 100 connected to the first pixel circuit column 321 include first-color light-emitting units and third-color light-emitting units arranged alternately, and the data line connected to the pixel circuit located in a row of the third display area 300, which is close to the first display area 100 and is connected to the first-color light-emitting units, is the first data line.

[0138] For example, the plurality of light-emitting units in the third display area 300 connected to the second pixel circuit column 322 of the second display area 200 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the light-emitting units connected to the pixel circuits in the first row of the second display area 200, away from the first display area 100, and in the second pixel circuit column 322 are the second light-emitting unit blocks. The plurality of light-emitting units 20 in the first display area 100 connected to the second pixel circuit column 322 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the data line connected to the pixel circuits in a row of the third display area 300, which is close to the first display area 100, and connected to the first light-emitting unit block is the second data line. Thus, the data signals on the first data line and the second data line in the area where the first display area and the edge area of the third display area are connected respectively match the data signals on the third data line and the second data line in the second display area, while the data signals transmitted by the third data line and the fourth data line in the area where the first display area and the edge area of the third display area are connected do not match the data signals on the third data line and the second data line in the second display area. Then, at the junction of the edge area of the third display area and the first display area, the first data line and the second data line remain connected, while the third data line and the fourth data line are disconnected.

[0139] For example, Figures 1 to 6 As shown, the display substrate also includes a peripheral area 303 located on the side of the third display area 300 away from the first display area 100, the first data line 421 located in the edge area 302 of the third display area 300 bypasses the central area 301 to connect to the second data line 422 and the third data line 423 of the second display area 200 in the peripheral area 303, and the second data line 422 located in the edge area 302 of the third display area 300 bypasses the central area 301 to connect to the other of the second data line 422 and the third data line 423 of the second display area 200 in the peripheral area 303.

[0140] For example, the embodiment of the present disclosure schematically shows that the first data line 421 located in the edge area 302 of the third display area 300 bypasses the central area 301 to be connected to the third data line 423 of the second display area 200 in the peripheral area 303, and the second data line 422 located in the edge area 302 of the third display area 300 bypasses the central area 301 to be connected to the second data line 422 of the second display area 200 in the peripheral area 303, thereby facilitating the routing of the data lines in the third display area and the second display area.

[0141] For example, Figures 1-6As shown, another embodiment of the present disclosure provides a display substrate including a first display area 100 and a second display area 200. The first display area 100 includes a plurality of first light-emitting units 110-1 and a plurality of first sub-pixel circuits 031. The plurality of first light-emitting units 110-1 include adjacent first light-emitting unit columns 110-11 and second light-emitting unit columns 110-12. Each light-emitting unit column is connected to a corresponding column of first sub-pixel circuits 031. The second display area 120 includes a plurality of second light-emitting units 120-1 and a plurality of second sub-pixel circuits 032. The plurality of second light-emitting units 120-1 include adjacent third light-emitting unit columns 120-11 and fourth light-emitting unit columns 120-12. Each light-emitting unit column in the second display area 200 is connected to a column of first sub-pixel circuit pairs 032-1. Each column of first sub-pixel circuit pairs 032-1 includes two adjacent columns of second sub-pixel circuits 032.

[0142] For example, Figures 1-6 As shown, the display substrate also includes a plurality of first sub-data lines 4210, a plurality of second sub-data lines 4220, a plurality of third sub-data lines 4230 and a plurality of fourth sub-data lines 4240 extending along the second direction, each first sub-data line 4210 is connected to each first light-emitting unit column 110-11, each second sub-data line 4220 is connected to each second light-emitting unit column 110-12, each third sub-data line 4230 is connected to each third light-emitting unit column 120-11, and each fourth sub-data line 4240 is connected to each fourth light-emitting unit column 120-12, and the second direction intersects with the first direction.

[0143] For example, Figures 1-6 As shown, the arrangement direction of the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12 is the same as the arrangement direction of the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12, a column of first sub-pixel circuits 031 connected to the first light-emitting unit column 110-11 and a column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column, the first sub-data line 4210 and the third sub-data line 4230 are a data line extending and continuous along the second direction; the two columns of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 and the one column of first sub-pixel circuits 031 connected to the second light-emitting unit column 110-12 are all located in different columns, the second sub-data line 4220 and the fourth sub-data line 4240 are connected through the data line connecting portion 560, and the extending direction of the data line connecting portion 560 intersects with the second direction.

[0144] The first sub-data line 4210, the second sub-data line 4220, the third sub-data line 4230 and the fourth sub-data line 4240 here have different meanings from the first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 in the above embodiment. The first sub-data line 4210 here refers only to the data line connected to the pixel circuit in the first display area among the first data lines 421 in the above embodiment. The second sub-data line 4220 here refers to the data line connected to the pixel circuit in the first display area among the second data lines 422 in the above embodiment. The third sub-data line 4230 here refers only to the data line connected to the pixel circuit in the second display area among the first data lines 421 in the above embodiment. The fourth sub-data line 4240 here refers only to the data line connected to the pixel circuit in the second display area among the fourth data lines 424 in the above embodiment.

[0145] At the intersection of the pixel circuit of the first display area and the pixel circuit of the second display area, the second sub-data line and the fourth sub-data line are disconnected, and the second sub-data line and the fourth sub-data line are connected through the data line connecting portion, thereby ensuring that the data signal transmitted from the data line to the light-emitting unit in the first display area matches the data signal transmitted from the data line to the light-emitting unit in the second display area.

[0146] For example, Figures 1-6 As shown, a column of first sub-pixel circuits 031 connected to the second light emitting unit column 110 - 12 and another column of second sub-pixel circuits 032 connected to the third light emitting unit column 120 - 11 are located in the same column.

[0147] For example, Figures 1-6 As shown, the first display area 100 also includes a fifth light-emitting unit column 110-13 and a sixth light-emitting unit column 110-14 arranged adjacent to each other, the first light-emitting unit column 110-11, the second light-emitting unit column 110-12, the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14 are repeatedly arranged along the first direction, and the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12 are alternately arranged along the first direction.

[0148] For example, Figures 1-6 As shown, the display substrate further includes a plurality of fifth sub-data lines 4250 and a plurality of sixth sub-data lines 4260 extending along the second direction, each fifth sub-data line 4250 is connected to each fifth light-emitting unit column 110-13, and each sixth sub-data line 4260 is connected to each sixth light-emitting unit column 110-14.

[0149] For example, Figures 1-6As shown, a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column, a column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and another column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column, and a gap is set between the sixth sub-data line 4260 or the fifth sub-data line 4250 and the fourth sub-data line 4240. Figure 5D In the schematic diagram, the pixel circuit connected to the sixth sub-data line 4260 and the pixel circuit connected to the fourth sub-data line 4240 are located in the same column, and a gap is provided between the sixth sub-data line 4260 and the fourth sub-data line 4240. However, the present invention is not limited to this. When the pixel circuit connected to the fourth sub-data line and the pixel circuit connected to the fifth sub-data line are located in the same column, a gap is provided between the fourth sub-data line and the fifth sub-data line. The fifth sub-data line 4250 here refers only to the data line connected to the pixel circuit in the first display area among the third data lines 423 in the above embodiment, and the sixth sub-data line 4260 here refers to the data line connected to the pixel circuit in the first display area among the fourth data lines 424 in the above embodiment.

[0150] For example, Figure 5E A partial plan view of a first display area and a second display area in a display substrate provided according to another example of an embodiment of the present disclosure. Figure 5E The example shown is the same as Figure 5D The examples shown differ in the arrangement of the pixels. Figure 5D The pixel arrangement in the example shown is GGRB arrangement. Figure 5E The pixel arrangement in the example shown is realRGB arrangement. Figure 5EAs shown, every six RGB light-emitting units in the first display area 100 form a repeating cycle. The data line 420 connected to the first column of R light-emitting units in the first display area 100 and the data line 420 connected to the first column of R light-emitting units in the second display area 100 are the same continuous data line; there is a gap between the data line 420 connected to the second column of G light-emitting units in the first display area 100 and the data line 420 connected to the second column of R light-emitting units in the second display area 100, and the data line 420 connected to the second column of G light-emitting units in the first display area 100 is connected to the data line 420 connected to the third column of G (or fourth column of G) light-emitting units in the second display area 100 through the data line connecting portion 560; there is a gap between the data line 420 connected to the third column of B light-emitting units in the first display area 100 and the data line 420 connected to the third column of G light-emitting units in the second display area 100. There is a gap between the data line 420 connected to the third column B light-emitting unit of the first display area 100 and the data line 420 connected to the fifth column B (or sixth column B) light-emitting unit of the second display area 100 through the data line connecting portion 560; there is a gap between the data line 420 connected to the fourth column G light-emitting unit of the first display area 100 and the data line 420 connected to the fourth column G light-emitting unit of the second display area 100; there is a gap between the data line 420 connected to the fifth column R light-emitting unit of the first display area 100 and the data line 420 connected to the fifth column B light-emitting unit of the second display area 100; there is a gap between the data line 420 connected to the sixth column G light-emitting unit of the first display area 100 and the data line 420 connected to the sixth column B light-emitting unit of the second display area 100. The embodiments of the present disclosure are not limited to the above-mentioned connection, as long as an R light-emitting unit in the first display area and an R light-emitting unit in the second display area are connected to the same data line, a B light-emitting unit in the first display area and a B light-emitting unit in the second display area are connected to the same data line, and a G light-emitting unit in the first display area and a G light-emitting unit in the second display area are connected to the same data line.

[0151] For example, Figures 1-6 As shown, the first display area 100 includes a plurality of first sub-light-emitting unit groups 1-1 and a plurality of second sub-light-emitting unit groups 1-2 arranged alternately along the first direction and the second direction, the first sub-light-emitting unit group 1-1 includes the light-emitting units in the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12, the second sub-light-emitting unit group 1-2 includes the light-emitting units in the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14, and the second display area 200 includes a plurality of third sub-light-emitting unit groups 1-3.

[0152] For example, Figures 1-6As shown, each sub-light-emitting unit group includes a first-color light-emitting unit R, a second-color light-emitting unit pair G1 and G2, and a third-color light-emitting unit B. The first-color light-emitting unit R and the third-color light-emitting unit B are arranged along the second direction. The second-color light-emitting unit pair G1 and G2 includes two second-color light-emitting units arranged along the second direction. The first-color light-emitting unit R and the second-color light-emitting unit pair G1 and G2 are arranged along the first direction. The arrangement direction of the first-color light-emitting unit R and the third-color light-emitting unit B in the first sub-light-emitting unit group 1-1 is opposite to the arrangement direction of the first-color light-emitting unit R and the third-color light-emitting unit B in the second sub-light-emitting unit group 1-2. The relative position distribution of the light-emitting units in the first sub-light-emitting unit group 1-1 is the same as the relative position distribution of the light-emitting units in the third sub-light-emitting unit group 1-3. The embodiment of the present disclosure illustratively takes the first-color light-emitting unit as a red light-emitting unit, the second-color light-emitting unit pair as a green light-emitting unit pair, and the third-color light-emitting unit as a blue light-emitting unit as an example, but is not limited to this. For example, the first color light emitting unit may be a blue light emitting unit, the second color light emitting unit pair may be a green light emitting unit pair, and the third color light emitting unit may be a red light emitting unit. For example, the first color light emitting unit may be a green light emitting unit, the second color light emitting unit pair may be a red light emitting unit pair, and the third color light emitting unit may be a blue light emitting unit.

[0153] For example, Figures 1-6 As shown, the base substrate also includes a third display area 300, the second display area 200 also includes a plurality of third sub-pixel circuits 033, the third display area 300 includes a plurality of third light-emitting units 130-1, the plurality of third light-emitting units 130-1 include a seventh light-emitting unit column 130-11 and an eighth light-emitting unit column 130-12 arranged adjacent to each other, the arrangement direction of the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12 is the same as the arrangement direction of the seventh light-emitting unit column 130-11 and the eighth light-emitting unit column 130-12, each light-emitting unit column in the third display area 300 is connected to a column of second sub-pixel circuit pairs 033-1, and each column of second sub-pixel circuit pairs 033-1 includes two adjacent columns of third sub-pixel circuits 033.

[0154] For example, Figures 1-6 As shown, the display substrate further includes a plurality of seventh sub-data lines 4270 and a plurality of eighth sub-data lines 4280 extending along the second direction, each seventh sub-data line 4270 is connected to each seventh light-emitting unit column 130-11, and each eighth sub-data line 4280 is connected to each eighth light-emitting unit column 130-12.

[0155] For example, Figures 1-6As shown, at least one of the seventh sub-data line 4270 and the eighth sub-data line 4280 is disposed between the third sub-data line 4230 and the fourth sub-data line 4240. The seventh sub-data line 4270 here refers only to the data line connected to the pixel circuit in the second display area among the second data lines 422 in the above embodiment, and the eighth sub-data line 4280 here refers to the data line connected to the pixel circuit in the second display area among the third data lines 423 in the above embodiment.

[0156] For example, Figures 1-6 As shown, the seventh sub-data line 4270 and the eighth sub-data line 4280 are both disposed between the third sub-data line 4230 and the fourth sub-data line 4240 , and a gap is provided between the eighth sub-data line 4280 and the fifth sub-data line 4250 to dispose the data line connecting portion 560 .

[0157] For example, a break is formed between the eighth sub-data line 4280 and the fifth sub-data line 4250 at a position between the pixel circuit in the first display area and the pixel circuit in the second display area, and the connecting portion 560 is provided at the break.

[0158] For example, Figures 1-6 As shown, multiple third sub-pixel circuits 033 are configured to be connected to multiple fourth sub-light-emitting unit groups 1-4, the relative position distribution of each light-emitting unit in each fourth sub-light-emitting unit group 1-4 is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group 1-3, and the first sub-pixel circuit pair 032-1 connected to the third sub-light-emitting unit group 1-3 and the second sub-pixel circuit pair 033-1 connected to the fourth light-emitting unit group 1-4 are alternately arranged along the first direction and the second direction.

[0159] For example, Figures 1-6 As shown, the third display area 300 includes a central area 301 and an edge area 302 surrounding the central area 301. The edge area 302 includes a plurality of dummy pixel circuits arranged along a first direction and a second direction to form a plurality of dummy pixel circuit columns 320-1 and a plurality of dummy pixel circuit rows 320-2.

[0160] For example, Figures 1-6 As shown, the multiple dummy pixel circuit columns 320-1 in the third display area 300 include a dummy pixel circuit column group 3201 consisting of four adjacent columns, and each dummy pixel circuit column group 3201 includes a first dummy pixel circuit column 0341, a second dummy pixel circuit column 0342, a third dummy pixel circuit column 0343 and a fourth dummy pixel circuit column 0343 arranged in sequence along the first direction.

[0161] For example, Figures 1-6As shown, the display substrate also includes a first dummy data line 431, a second dummy data line 432, a third dummy data line 433 and a fourth dummy data line 434. The first dummy data line 431 is connected to the first dummy pixel circuit column 0341, the second dummy data line 432 is connected to the second dummy pixel circuit column 0342, the third dummy data line 433 is connected to the third dummy pixel circuit column 0343, and the fourth dummy data line 434 is connected to the fourth dummy pixel circuit column 0344.

[0162] For example, Figures 1-6 As shown, a column of first sub-pixel circuits 031 connected to the first light-emitting cell column 110-11 and a first dummy pixel circuit column 0341 are located in the same column, a column of first sub-pixel circuits 031 connected to the second light-emitting cell column 110-12 and a second dummy pixel circuit column 0342 are located in the same column, a column of first sub-pixel circuits 031 connected to the fifth light-emitting cell column 110-13 and a third dummy pixel circuit column 0343 are located in the same column, and a column of first sub-pixel circuits 031 connected to the sixth light-emitting cell column 110-14 and a fourth dummy pixel circuit column 0344 are located in the same column. The two data lines connected to the first light-emitting cell group 1-1 and the corresponding two dummy data lines are continuous data lines, or the two data lines connected to the second light-emitting cell group 1-2 and the corresponding two dummy data lines are continuous data lines. Figure 6 It is schematically shown that the two data lines connected to the first light emitting unit group 1 - 1 and the corresponding two dummy data lines are two continuous data lines.

[0163] For example, Figures 1-6 As shown, the display substrate also includes a peripheral area 400 located on the side of the third display area 300 away from the first display area 100, and two virtual data lines connected to the first light-emitting unit group 1-1 or the second light-emitting unit group 1-2 bypass the central area 301 to connect the seventh sub-data line 4270 and the eighth sub-data line 4280 in the peripheral area 400 respectively.

[0164] For example, Figures 1-6 As shown, the first dummy data line 431 and the first sub-data line 4210 are a continuous data line, the second dummy data line 432 and the second sub-data line 4220 are a continuous data line, a gap is set between the third dummy data line 433 and the fifth sub-data line 4250, and a gap is set between the fourth dummy data line 434 and the sixth sub-data line 4260.

[0165] For example, Figures 1-6 As shown, the first dummy data line 431 bypasses the central region 301 to connect to the seventh sub-data line 4270 in the peripheral region 400 , and the second dummy data line bypasses the central region to connect to the eighth data line in the peripheral region.

[0166] For example, Figure 7 is a schematic diagram of a second electrode of a light-emitting unit group located in a first display area according to an embodiment of the present disclosure, Figure 8 Schematic diagram of the second electrode of the light-emitting unit group located at the non-edge of the second display area according to an embodiment of the present disclosure, Figure 9 Schematic diagram of the second electrode of the light emitting unit group located in the third display area according to an embodiment of the present disclosure. Figures 1 to 9 As shown, the second electrode 22 of each light-emitting unit 20 includes a main electrode 22-1 and a connecting electrode 22-2. The main electrode 22-1 has a shape substantially identical to the shape of the effective light-emitting area of each light-emitting unit 20. The connecting electrode 22-2 is configured to be electrically connected to the second electrode of the first light-emitting control transistor T6 of the pixel circuit via a fifth connecting portion 550. Each light-emitting unit group located in the display area includes a plurality of light-emitting units of different colors. For example, each light-emitting unit group includes a first-color light-emitting unit 201, a second-color light-emitting unit pair 202, and a third-color light-emitting unit 203.

[0167] For example, Figures 1 to 9 As shown, the area of the main electrode 22-1 of the one-color light-emitting unit located in at least one of the non-edge area of the second display area 200 and the third display area 300 is larger than the area of the main electrode 22-1 of the light-emitting unit 20 located in the first display area 100 and having the same color as the one-color light-emitting unit. The area of the main electrode of each color light-emitting unit is related to the area of its effective light-emitting area. In the embodiment of the present disclosure, by setting the area of the main electrode of the one-color light-emitting unit located in at least one of the non-edge area of the second display area and the third display area to be larger than the area of the main electrode of the light-emitting unit located in the first display area and having the same color as the one-color light-emitting unit, the area of the effective light-emitting area of the one-color light-emitting unit located in at least one of the non-edge area of the second display area and the third display area can be designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the first display area and having the same color as the one-color light-emitting unit.

[0168] In the embodiment of the present disclosure, since the density of the light-emitting unit groups in the second display area and the third display area are both lower than the density of the light-emitting unit groups in the first display area, by setting the area of the main electrode in the light-emitting unit of at least one of the second display area and the third display area to be larger than the area of the main electrode in the light-emitting unit of the first display area, so that the area of the effective light-emitting area of the light-emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be larger than the area of the effective light-emitting area of the light-emitting unit of the same color as the above-mentioned light-emitting unit located in the first display area, the brightness of at least one of the second display area and the third display area can be increased on the basis of ensuring the life of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0169] For example, the embodiment of the present disclosure schematically shows that the area of the main electrode 22-1 of a light-emitting unit of one color located in the non-edge area of the second display area 200 and the third display area 300 is larger than the area of the main electrode 22-1 of the light-emitting unit 20 located in the first display area 100 and having the same color as the above-mentioned light-emitting unit of one color, so that the area of the effective light-emitting area of the light-emitting unit of one color located in the non-edge area of the second display area and the third display area is designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the first display area and having the same color as the above-mentioned light-emitting unit of one color. In this way, the brightness of the second display area and the third display area can be increased on the basis of ensuring the life of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0170] For example, in one example of the presently disclosed embodiment, each light-emitting unit in the first display area, the second display area, and the third display area is connected to a pixel circuit, that is, each light-emitting unit in the second display area and the third display area may not be connected to a pixel circuit pair, but only to a pixel circuit. In this case, the density of the light-emitting unit groups in the second display area and the third display area is less than the density of the light-emitting unit group in the first display area. By setting the area of the main electrode in the light-emitting unit in at least one of the second display area and the third display area to be larger than the area of the main electrode in the light-emitting unit in the first display area, the effective light-emitting area of the light-emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be larger than the effective light-emitting area of the light-emitting unit of the same color as the light-emitting unit of the first display area, thereby making the display effect of each display area as uniform as possible.

[0171] For example, in another example of the presently disclosed embodiment, each pixel circuit group includes a plurality of pixel circuits, and at least one of the second pixel circuit group and the third pixel circuit group in the second display area includes a plurality of pixel circuit pairs, and the two pixel circuits included in each pixel circuit pair are configured to be electrically connected to the second electrode of the same light-emitting unit. For example, the second pixel circuit group and the third pixel circuit group in the second display area each include a plurality of pixel circuit pairs, and each pixel circuit pair in the second pixel circuit group is connected to each light-emitting unit in the second light-emitting unit group, and each pixel circuit pair in the third pixel circuit group is connected to each light-emitting unit in the third light-emitting unit group. The density of the light-emitting unit groups in the second display area and the third display area is lower than that of the light-emitting unit group in the first display area. The scheme of designing the pixel circuits connected to the light-emitting units in the second display area and the third display area as pixel circuit pairs is combined with the scheme of setting the area of the main electrode in the light-emitting units in the second display area and the third display area to be larger than the area of the main electrode in the light-emitting units in the first display area. On the basis of ensuring the life of the light-emitting materials of the light-emitting units, the current and brightness of the light-emitting units in the second display area and the third display area can be increased to 1.8 to 2 times that of the case of one pixel circuit driving, thereby solving the problem of low current and brightness in the second display area and the third display area, and achieving a more uniform full-screen visual display effect.

[0172] For example, Figures 1 to 9 As shown, each light-emitting unit group includes a first color light-emitting unit 201, and the area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in the non-edge area of the second display area 200 and at least one of the third display area 300 to the area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0173] For example, the area ratio of the effective light-emitting area of each first color light-emitting unit 201 located in the non-edge area of the second display area 200 and at least one of the third display area 300 to the area ratio of the effective light-emitting area of each first color light-emitting unit 201 located in the first display area 100 is 2.

[0174] For example, Figures 1 to 9 As shown, the main electrode 2011 and the effective light-emitting area of the first color light-emitting unit 201 located in each display area are both hexagonal in shape, and the area of the connecting electrode 2012 of the first color light-emitting unit 201 located at the non-edge of the second display area 200 can be larger than the area of the connecting electrode 2012 of the first color light-emitting unit 201 located in the first display area 100 to achieve connection with the pixel circuit pair.

[0175] For example, Figures 1 to 9As shown, the area ratio of the main electrode 2021 of each second color light-emitting unit pair 202 located in the non-edge area of the second display area 200 and at least one of the third display area 300 to the area ratio of the main electrode 2021 of each second color light-emitting unit pair 202 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0176] For example, the ratio of the effective light-emitting area of each second color light-emitting unit pair 202 located in the non-edge area of the second display area 200 and the third display area 300 to the effective light-emitting area of each second color light-emitting unit pair 202 located in the first display area 100 is 2.

[0177] For example, Figures 1 to 9 As shown, the ratio of the area of the main electrode 2021-1 of each first light-emitting unit block 202-1 located in at least one of the non-edge area of the second display area 200 and the third display area 300 to the area of the main electrode 2021-1 of each first light-emitting unit block 202-1 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1. For example, the ratio of the area of the main electrode 2021-2 of each second light-emitting unit block 202-2 located in at least one of the non-edge area of the second display area 200 and the third display area 300 to the area of the main electrode 2021-2 of each second light-emitting unit block 202-2 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0178] For example, the area of the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the non-edge region of the second display area 200 is larger than the area of the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the first display area 100. For example, the area of the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 is larger than the area of the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the first display area 100 to facilitate connection with the pixel circuit pair.

[0179] For example, the area ratio of the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of the second display area 200 and at least one of the third display area 300 to the area ratio of the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100 is 1.5~2.5, for example, 1.9~2.1.

[0180] For example, the ratio of the area of the main electrode 2031 of each third color light emitting unit 203 located in the non-edge area of the second display area 200 and the third display area 300 to the area of the main electrode 2031 of each third color light emitting unit 203 located in the first display area 100 is 2. For example, the ratio of the area of the effective light emitting area of each third color light emitting unit 203 located in the non-edge area of the second display area 200 and the third display area 300 to the area of the effective light emitting area of each third color light emitting unit 203 located in the first display area 100 is 2.

[0181] For example, the area of the connection electrode 2032 of each third color light emitting unit 203 located in the non-edge area of the second display area 200 is larger than the area of the connection electrode 2032 of each third color light emitting unit 203 located in the first display area 100 to achieve connection with the pixel circuit pair.

[0182] For example, the main electrode and the effective light-emitting area of the third color light-emitting unit in each display area are both hexagonal in shape.

[0183] For example, Figure 8 and Figure 9 As shown, the second electrodes of the light-emitting units of the light-emitting unit group in the second display area are directly connected to the pixel circuit pair, so the area of the connection electrode of the light-emitting units in the second display area is larger, while the second electrodes of the light-emitting units of the light-emitting unit group in the third display area are connected to the pixel circuit pair in the second display area through a transparent wiring, so the area of the connection electrode of the light-emitting units in the third display area can be set to be smaller.

[0184] For example, Figure 10 Schematic diagram of the second electrode of each light emitting unit in the two rows of light emitting unit groups in the second display area bordering the first display area according to an embodiment of the present disclosure. Figures 1 to 10 As shown, the shape and area of the main electrode 2011 of each first color light-emitting unit 201 in a row of light-emitting unit groups adjacent to the first display area 100 in the second display area 200 in the Y direction are substantially the same as the shape and area of the main electrode 2011 of each first color light-emitting unit 201 located in the first display area 100. In the embodiment of the present disclosure, the shape and area of the main electrode of each first color light-emitting unit in two rows of light-emitting unit groups adjacent to each other in the Y direction in the second display area are set to be substantially the same, that is, the area of the main electrode of the first color light-emitting unit located at the edge of the second display area is designed to be different from the area of the main electrode of the first color light-emitting unit located in the non-edge area of the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0185] For example, Figures 1 to 10As shown, the ratio of the area of the main electrode 2021 of each second color light-emitting cell pair 202 in a row of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the first direction to the area of the main electrode 2021 of each second color light-emitting cell pair 202 located in the first display area 100 is 0.9 to 1.1. In the embodiment of the present disclosure, the area of the main electrode of each second color light-emitting cell in two rows of light-emitting cell groups in the second display area adjacent to each other in the Y direction in the first display area is set to be approximately the same, that is, the area of the main electrode of the second color light-emitting cell located at the edge of the second display area is designed to be different from the area of the main electrode of the second color light-emitting cell located in the non-edge area of the second display area. This can increase the brightness of most of the second color light-emitting cells in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting cells.

[0186] For example, Figures 1 to 10 As shown, the shape of the main electrodes 2021 of the two second color sub-pixels included in the second color sub-pixel pair 202 within the first display area 100 is different from the shape of the two main electrodes 2021 of each second color light-emitting unit pair 202 of a row of light-emitting unit groups in the second display area 200 that are adjacent to the first display area 100 in the first direction.

[0187] In the embodiment of the present disclosure, the size of the gap of the pixel defining layer (PDL gap) between two adjacent light-emitting units located in the non-edge area of the second display area is approximately the same as the size of the PDL gap between two adjacent light-emitting units located in the edge area of the second display area, so that the second display area displays image light uniformity.

[0188] For example, Figures 1 to 10 As shown, the main electrodes 2021 of the two second-color sub-pixels included in the second-color sub-pixel pair 202 in the first display area 100 are both pentagonal in shape, and each pentagon includes a first side 1 extending along the X direction, two second sides 2 extending along the Y direction, and two third sides 3 connected to the two second sides 2. The two third sides 3 intersect to form a sharp angle, and the two sharp angles of the main electrodes 2021 of the two second-color sub-pixels are close to each other. Each main electrode 2021 of each second-color light-emitting cell pair 202 in a row of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the Y direction includes a fourth side 4 extending along the X direction, two fifth sides 5 extending along the Y direction, two sixth sides 6 connected to the two fifth sides 5, and a seventh side 7 connecting the two sixth sides 6. The two seventh sides 7 of the main electrodes 2021 of the two second-color sub-pixels are close to each other.

[0189] For example, Figures 7 to 10As shown, the length of the second side 2 of the main electrode 2021 of the second color light-emitting unit of the first display area 100 is less than the length of the fifth side 5 of the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 to ensure that the area of the main electrode of the second color light-emitting unit of the first display area is roughly equal to the area of the main electrode of the second color light-emitting unit at the edge of the second display area.

[0190] For example, Figures 7 to 10 As shown, when the area of the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or the third color light-emitting unit) and the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or the third color light-emitting unit) in the non-edge area of the second display area 200, the center line connecting the two main electrodes of each second color light-emitting unit pair in a row of light-emitting unit groups adjacent to the first display area 100 in the first direction of the second display area 200 is not parallel to the center line connecting the two main electrodes of each second color light-emitting unit pair in the first display area.

[0191] When the area of the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure that the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or third color light-emitting unit) and the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or third color light-emitting unit) in the non-edge area of the second display area 200 are close, if the shape of the main electrode of the second color light-emitting unit at the edge of the second display area 200 is a pentagon with sharp corners, there will be a spatial conflict with the connecting electrode of the first color light-emitting unit (or third color light-emitting unit). Therefore, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area no longer includes sharp corners. At this time, in order to ensure that the area of the main electrode of the second color light-emitting unit at the edge of the second display area is roughly the same as the area of the main electrode of the second color light-emitting unit at the edge of the second display area, it is necessary to compensate for the shape of the main electrode of the second color light-emitting unit at the edge of the second display area, that is, to add two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6, so as to ensure that the main electrode of the second color light-emitting unit at the edge of the second display area has no spatial conflict and achieves that its area is equal to that of the second color light-emitting unit in the first display area.

[0192] For example, Figures 1 to 10As shown, the shape and area of the main electrode 2031 of each third color light-emitting unit 203 in a row of light-emitting unit groups adjacent to the first display area 100 in the second display area 200 in the Y direction are substantially the same as the shape and area of the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100. In the embodiment of the present disclosure, the shape and area of the main electrode of each third color light-emitting unit in two rows of light-emitting unit groups adjacent to each other in the Y direction in the second display area are set to be substantially the same, that is, the area of the main electrode of the third color light-emitting unit located at the edge of the second display area is designed to be different from the area of the main electrode of the third color light-emitting unit located in the non-edge area of the second display area. This can increase the brightness of most of the third color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0193] For example, Figure 11 Schematic diagram of the second electrode of each light emitting unit in two columns of light emitting unit groups in the second display area bordering the first display area according to an embodiment of the present disclosure. Figure 11 As shown, in a column of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the X direction, the second color light-emitting cell pairs 202 are located on the side of the first color light-emitting cell 201 and the third color light-emitting cell 203 closer to the first display area 100. The area and shape of the main electrodes 2021 of each second color light-emitting cell pair 202 in this column of light-emitting cell groups are substantially the same as the area and shape of the main electrodes 2021 of each second color light-emitting cell pair 202 located in the first display area 100. In the embodiment of the present disclosure, the shape and area of the main electrodes of each second color light-emitting cell pair in two columns of light-emitting cell groups in the second display area adjacent to the first display area in the X direction are set to be substantially the same. That is, the area of the main electrodes of the second color light-emitting cell pairs located at the edge of the second display area is designed to be different from the area of the main electrodes of the second color light-emitting cell pairs located in the non-edge area of the second display area. This can increase the brightness of most of the second color light-emitting cell pairs in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two columns of light-emitting cells.

[0194] For example, a third pixel circuit group is provided between two adjacent second light-emitting cell groups arranged along the Y direction, thereby eliminating the need for a light-emitting cell group in the gap between the two adjacent second light-emitting cell groups arranged along the Y direction. In the first display area 100, a gap is provided between two adjacent first light-emitting cell groups in a column of a plurality of first light-emitting cell groups adjacent to the second display area 200 in the X direction. This gap includes a first pixel circuit group that is not connected to the light-emitting cell group. Furthermore, along the X direction, this first pixel circuit group and the light-emitting cell groups in a column of second light-emitting cell groups adjacent to the first display area 100 are located on the same straight line. This balances the brightness distribution between the first and second display areas in the X direction.

[0195] For example, Figure 11 As shown, in a column of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the X direction, the ratio of the area of the main electrode 2011 of each first-color light-emitting cell 201 to the area of the main electrode 2011 of each first-color light-emitting cell 201 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1. For example, in a column of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the X direction, the ratio of the area of the effective light-emitting area of each first-color light-emitting cell 201 to the area of the effective light-emitting area of each first-color light-emitting cell 201 located in the first display area 100 is 2. In the embodiment of the present disclosure, while ensuring that the main electrodes of the light-emitting units in a column of light-emitting units in the second display area that is adjacent to the first display area in the X direction do not conflict in space, the shape and area of the main electrodes of the first color light-emitting units located at the edge of the second display area are substantially the same as the shape and area of the main electrodes of the first color light-emitting units located in the non-edge area of the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing the main electrodes of the two columns of light-emitting units from conflicting in space.

[0196] For example, Figure 11As shown, in a column of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the X direction, the ratio of the area of the main electrode 2031 of each third-color light-emitting cell 203 to the area of the main electrode 2031 of each third-color light-emitting cell 203 located in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1. For example, in a column of light-emitting cell groups in the second display area 200 adjacent to the first display area 100 in the X direction, the ratio of the area of the effective light-emitting area of each third-color light-emitting cell 203 to the area of the effective light-emitting area of each third-color light-emitting cell 203 located in the first display area 100 is 2. In the embodiment of the present disclosure, while ensuring that the main electrodes of the light-emitting units in a column of light-emitting units in the second display area that is adjacent to the first display area in the X direction do not conflict in space, the shape and area of the main electrodes of the third-color light-emitting units located at the edge of the second display area are substantially the same as the shape and area of the main electrodes of the third-color light-emitting units located in the non-edge area of the second display area. This can increase the brightness of most of the third-color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing the main electrodes of the two columns of light-emitting units from conflicting in space.

[0197] Another embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned display substrates.

[0198] In a display device provided by an example of an embodiment of the present disclosure, two pixel circuits in the second display area drive a light-emitting unit to emit light, which can increase the current and brightness of the light-emitting unit in at least one of the second display area and the third display area, thereby achieving a more uniform full-screen visual display effect.

[0199] In a display device provided by an example of an embodiment of the present disclosure, by setting the area of the main electrode in the light-emitting unit of at least one of the second display area and the third display area to be larger than the area of the main electrode in the light-emitting unit of the first display area, the area of the effective light-emitting area of the light-emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be larger than the area of the effective light-emitting area of the light-emitting unit of the same color as the above-mentioned light-emitting unit located in the first display area, the brightness of at least one of the second display area and the third display area can be increased on the basis of ensuring the life of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0200] In a display device provided by an example of an embodiment of the present disclosure, the design of data lines at the junction of the first display area and the second display area and the first display area and the third display area can meet the unified algorithm processing of the integrated circuit (IC) in the first display area and the second display area.

[0201] There are a few points to note:

[0202] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0203] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0204] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a first display area and a second display area, wherein the first display area includes a plurality of first light-emitting units and a plurality of first sub-pixel circuits, the plurality of first light-emitting units including a first light-emitting unit column and a second light-emitting unit column disposed adjacently, each light-emitting unit column being connected to a corresponding column of first sub-pixel circuits, the second display area includes a plurality of second light-emitting units and a plurality of second sub-pixel circuits, the plurality of second light-emitting units including a third light-emitting unit column and a fourth light-emitting unit column disposed adjacently, each light-emitting unit column in the second display area being connected to a column of first sub-pixel circuit pairs, each column of first sub-pixel circuit pairs including two adjacent columns of second sub-pixel circuits; a plurality of first sub-data lines, a plurality of second sub-data lines, a plurality of third sub-data lines, and a plurality of fourth sub-data lines extending along the second direction, wherein each first sub-data line is connected to each first light-emitting unit column, each second sub-data line is connected to each second light-emitting unit column, each third sub-data line is connected to each third light-emitting unit column, and each fourth sub-data line is connected to each fourth light-emitting unit column; Wherein, the arrangement direction of the first light emitting unit column and the second light emitting unit column is the same as the arrangement direction of the third light emitting unit column and the fourth light emitting unit column; A column of first sub-pixel circuits connected to the first light-emitting unit column and a column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column, and the first sub-data line and the third sub-data line are a data line extending and continuous along the second direction; The two columns of second sub-pixel circuits connected to the fourth light-emitting unit column and the one column of first sub-pixel circuits connected to the second light-emitting unit column are located in different columns, the second sub-data line is connected to the fourth sub-data line via a data line connecting portion, and an extending direction of the data line connecting portion intersects with the second direction; Two columns of first pixel circuit pairs connected to the adjacent third light-emitting unit column and the fourth light-emitting unit column include four columns of second sub-pixel circuits arranged along a first direction, and the first sub-pixel circuits connected to the adjacent first light-emitting unit column and the second light-emitting unit column are arranged in two columns, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, wherein A column of first sub-pixel circuits connected to the second light-emitting unit column and another column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column.

3. The display substrate according to claim 2, wherein: The first display area further includes a fifth light-emitting unit column and a sixth light-emitting unit column adjacent to each other, the first light-emitting unit column, the second light-emitting unit column, the fifth light-emitting unit column and the sixth light-emitting unit column are repeatedly arranged along the first direction, and the third light-emitting unit column and the fourth light-emitting unit column are alternately arranged along the first direction; The display substrate further includes a plurality of fifth sub-data lines and a plurality of sixth sub-data lines extending along the second direction, each fifth sub-data line is connected to each fifth light-emitting unit column, and each sixth sub-data line is connected to each sixth light-emitting unit column; A column of first sub-pixel circuits connected to the fifth light-emitting unit column and a column of second sub-pixel circuits connected to the fourth light-emitting unit column are located in the same column, a column of first sub-pixel circuits connected to the sixth light-emitting unit column and another column of second sub-pixel circuits connected to the fourth light-emitting unit column are located in the same column, and a gap is set between the sixth sub-data line or the fifth sub-data line and the fourth sub-data line.

4. The display substrate according to claim 3, wherein: The first display area includes a plurality of first sub-light emitting unit groups and a plurality of second sub-light emitting unit groups alternately arranged along the first direction and the second direction, the first sub-light emitting unit groups include light emitting units in the first light emitting unit column and the second light emitting unit column, the second sub-light emitting unit group includes light emitting units in the fifth light emitting unit column and the sixth light emitting unit column, and the second display area includes a plurality of third sub-light emitting unit groups; Each of the sub-light-emitting unit groups includes a first color light-emitting unit, a second color light-emitting unit pair, and a third color light-emitting unit, the first color light-emitting unit and the third color light-emitting unit are arranged along the second direction, the second color light-emitting unit pair includes two second color light-emitting units arranged along the second direction, the first color light-emitting unit and the second color light-emitting unit pair are arranged along the first direction, and the arrangement direction of the first color light-emitting unit and the third color light-emitting unit in the first sub-light-emitting unit group is opposite to the arrangement direction of the first color light-emitting unit and the third color light-emitting unit in the second sub-light-emitting unit group, and the relative position distribution of each light-emitting unit in the first sub-light-emitting unit group is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group.

5. The display substrate according to claim 4, wherein: The base substrate further includes a third display area, the second display area further includes a plurality of third sub-pixel circuits, the third display area includes a plurality of third light-emitting units, the plurality of third light-emitting units include a seventh light-emitting unit column and an eighth light-emitting unit column arranged adjacent to each other, the first light-emitting unit column and the second light-emitting unit column are arranged in the same direction as the seventh light-emitting unit column and the eighth light-emitting unit column, each light-emitting unit column in the third display area is connected to a column of second sub-pixel circuit pairs, and each column of second sub-pixel circuit pairs includes two adjacent columns of third sub-pixel circuits; The display substrate further includes a plurality of seventh sub-data lines and a plurality of eighth sub-data lines extending along the second direction, each seventh sub-data line is connected to each seventh light-emitting unit column, and each eighth sub-data line is connected to each eighth light-emitting unit column; At least one of the seventh sub-data line and the eighth sub-data line is disposed between the third sub-data line and the fourth sub-data line. The display substrate according to claim 5 , wherein: The seventh sub-data line and the eighth sub-data line are both disposed between the third sub-data line and the fourth sub-data line, and a gap is provided between the eighth sub-data line and the fifth sub-data line to provide the data line connecting portion.

7. The display substrate according to claim 5, wherein: The plurality of third sub-pixel circuits are configured to be connected to a plurality of fourth sub-light-emitting unit groups, respectively, and the relative position distribution of the light-emitting units in each of the fourth sub-light-emitting unit groups is the same as the relative position distribution of the light-emitting units in the third sub-light-emitting unit group; The first sub-pixel circuit pairs connected to the third sub-light emitting unit group and the second sub-pixel circuit pairs connected to the fourth sub-light emitting unit group are alternately arranged along the first direction and the second direction.

8. The display substrate according to any one of claims 5 to 7, wherein: The third display area includes a central area and an edge area surrounding the central area. The edge area includes a plurality of dummy pixel circuits arranged along the first direction and the second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows.

9. The display substrate according to claim 8, wherein: The plurality of dummy pixel circuit columns in the third display area include dummy pixel circuit column groups consisting of four adjacent columns, each dummy pixel circuit column group including a first dummy pixel circuit column, a second dummy pixel circuit column, a third dummy pixel circuit column, and a fourth dummy pixel circuit column sequentially arranged along the first direction; The display substrate further includes a first dummy data line, a second dummy data line, a third dummy data line, and a fourth dummy data line, the first dummy data line being connected to the first dummy pixel circuit column, the second dummy data line being connected to the second dummy pixel circuit column, the third dummy data line being connected to the third dummy pixel circuit column, and the fourth dummy data line being connected to the fourth dummy pixel circuit column; A column of first sub-pixel circuits connected to the first light-emitting unit column and the first dummy pixel circuit column are located in the same column, a column of first sub-pixel circuits connected to the second light-emitting unit column and the second dummy pixel circuit column are located in the same column, a column of first sub-pixel circuits connected to the fifth light-emitting unit column and the third dummy pixel circuit column are located in the same column, and a column of first sub-pixel circuits connected to the sixth light-emitting unit column and the fourth dummy pixel circuit column are located in the same column; The two sub-data lines connected to the first sub-light emitting unit group and the corresponding two dummy data lines are two continuous sub-data lines, or the two sub-data lines connected to the second sub-light emitting unit group and the corresponding two dummy data lines are two continuous data lines.

10. The display substrate according to claim 9, wherein: The display substrate also includes a peripheral area located on a side of the third display area away from the first display area, and the two dummy data lines connected to the first sub-light-emitting unit group or the second sub-light-emitting unit group bypass the central area to respectively connect the seventh sub-data line and the eighth sub-data line in the peripheral area.

11. The display substrate according to claim 10, wherein: The first dummy data line and the first sub-data line are a continuous data line, the second dummy data line and the second sub-data line are a continuous sub-data line, a gap is set between the third dummy data line and the fifth sub-data line, and a gap is set between the fourth dummy data line and the sixth sub-data line.

12. The display substrate according to claim 11, wherein: The first dummy data line bypasses the central region to connect to the seventh sub-data line in the peripheral region, and the second dummy data line bypasses the central region to connect to the eighth sub-data line in the peripheral region.

13. A display device comprising the display substrate according to any one of claims 1 to 12.

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