A composite channel structure high electron mobility transistor and a method for manufacturing the same

Abstract

The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology, specifically relating to a high electron mobility transistor with a composite channel structure and its fabrication method. Background Technology

[0002] With the development of terahertz technology, high electron mobility transistors (HEMTs) need to meet the requirements of the terahertz frequency band as much as possible. The frequency range of terahertz is from 0.1THz to 10THz, which lies between microwaves and infrared.

[0003] In existing technologies, HEMTs typically use gallium arsenide (GaAs) as the material. However, GaAs-based HEMTs operate at low frequencies, failing to meet the requirements of the terahertz band. Furthermore, while gallium nitride (GaN)-based HEMTs can meet the terahertz band requirements, their low electron mobility and poor noise performance prevent them from maintaining good device characteristics in low-voltage and low-power applications. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high electron mobility transistor with a composite channel structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A high electron mobility transistor with a composite channel structure, the transistor comprising: a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP secondary channel, and a first undoped In... 0.22 Ga 0.78 As secondary channel, undoped In 0.7 Ga 0.3 As main channel, second undoped In 0.22 Ga 0.78 As secondary channel, undoped InAlAs isolation layer, delta-doping layer, undoped InAlAs barrier layer, n + InGaAs source cap layer, n + An InGaAs drain cap layer, source electrode, drain electrode, passivation layer, and gate electrode are included; wherein, an undoped InAlAs buffer layer is located above a semi-insulating InP substrate; an InP secondary channel is located above the undoped InAlAs buffer layer; and a first undoped In... 0.22 Ga 0.78 The As secondary channel is located above the InP secondary channel; undoped In 0.7 Ga 0.3 As the main channel is located in undoped In 0.22 Ga 0.78 Above the secondary channel; the second undoped In0.22 Ga 0.78 As the secondary channel is located in undoped In 0.7 Ga 0.3 As above the main channel; the undoped InAlAs isolation layer is located above the second undoped In... 0.22 Ga 0.78 Above the As secondary channel; the delta-doping layer is located above the undoped InAlAs isolation layer; the undoped InAlAs barrier layer is located above the delta-doping layer; n + The InGaAs source cap layer is located on one side above the undoped InAlAs barrier layer; n + The InGaAs drain cap layer is located on the other side above the undoped InAlAs barrier layer; the source electrode is located at n + Above the InGaAs source cap layer; the drain electrode is located at n + Above the InGaAs drain cap layer; the passivation layer is located at n + InGaAs source cap layer, source electrode and n + Between the InGaAs drain cap layer and the drain electrode; the passivation layer has a concave structure, with both ends of the concave structure connected to n. + InGaAs source cap layer, source electrode, n + The InGaAs drain cap layer and the inner side of the drain electrode are in contact; one end is connected to n + The entire inner region of the InGaAs source cap layer and a portion of the inner region of the source electrode are in contact, and the other end is in contact with the entire inner region of the n+InGaAs drain cap layer and a portion of the inner region of the drain electrode; the recessed region of the concave structure includes a gate region groove in the middle; the gate electrode is located in the gate region groove and contacts the undoped InAlAs barrier layer, and its thickness is greater than the thickness of the gate region groove.

[0006] In one embodiment of the present invention, the thickness of the undoped InAlAs buffer layer is 300–500 nm, and the In composition is 52%; the thickness of the InP secondary channel is 2–5 nm; the first undoped In... 0.22 Ga 0.78 The As secondary channel thickness is 2–3 nm; undoped In 0.7 Ga 0.3 The thickness of the As main channel is 2–3 nm; the second undoped In... 0.22 Ga 0.78 The thickness of the As secondary channel is 2–3 nm; the thickness of the undoped InAlAs isolation layer is 2–3 nm, with an In composition of 52%; the delta-doping layer is planar doped with a doping concentration of 5 × 10⁻⁶. 12 cm -2The undoped InAlAs barrier layer has a thickness of 12–15 nm and an In composition of 52%. + InGaAs source cap layer and n + The InGaAs drain cap layer is 30 nm thick and has a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The In content is 60%; the passivation layer thickness is 50-100 nm.

[0007] In one embodiment of the present invention, a source metal interconnect 1121 is disposed on the source electrode 112; wherein, the source metal interconnect 1121 covers the entire area of ​​the upper surface of the source electrode 112 and a portion of the upper surface of the passivation layer 114.

[0008] The beneficial effects of this invention are:

[0009] This invention can improve the breakdown voltage of InP-based HEMTs, maintain the output characteristics and cutoff frequency of high In-component channels, improve the uniformity and repeatability of transistors, and meet the application requirements of InP-based electronic devices in low-power, low-noise, and digital circuit fields.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a high electron mobility transistor structure with a composite channel structure provided in an embodiment of the present invention;

[0012] Figure 2 This is a schematic diagram of a method for fabricating a high electron mobility transistor with a composite channel structure provided in an embodiment of the present invention;

[0013] Figure 3A-3M This is a schematic diagram of the fabrication process of a high electron mobility transistor with a composite channel structure provided in an embodiment of the present invention. Detailed Implementation

[0014] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0015] Example 1

[0016] Please see Figure 1 , Figure 1 This is a schematic diagram of a high electron mobility transistor structure with a composite channel provided in an embodiment of the present invention. The transistor includes:

[0017] 101. Semi-insulating InP substrate, 102. Undoped InAlAs buffer layer, 103. InP sub-channel, 104. First undoped InP substrate. 0.22 Ga 0.78 As secondary channel 104, undoped In 0.7 Ga 0.3 As main channel 105, second undoped In 0.22 Ga 0.78 As secondary channel 106, undoped InAlAs isolation layer 107, delta-doping layer 108, undoped InAlAs barrier layer 109, n + InGaAs source cap layer 110, n + The InGaAs drain cap layer 111, source electrode 112, drain electrode 113, passivation layer 114, and gate electrode 115; wherein,

[0018] Undoped InAlAs buffer layer 102 is located above semi-insulating InP substrate 101;

[0019] The InP sub-channel 103 is located above the undoped InAlAs buffer layer 102;

[0020] First undoped In 0.22 Ga 0.78 As secondary channel 104 is located above InP secondary channel 103;

[0021] Undoped In 0.7 Ga 0.3 As the main channel 105 is located in undoped In 0.22 Ga 0.78 Above As secondary channel 104;

[0022] Second undoped In 0.22 Ga 0.78 As secondary channel 106 is located in undoped In 0.7 Ga 0.3 Above As main channel 105;

[0023] Undoped InAlAs isolation layer 107 is located at the second undoped In 0.22 Ga 0.78 Above As secondary channel 106;

[0024] delta-doping layer 108 is located above undoped InAlAs isolation layer 107;

[0025] The undoped InAlAs barrier layer 109 is located above the delta-doping layer 108;

[0026] n +The InGaAs source cap layer 110 is located on one side above the undoped InAlAs barrier layer 109;

[0027] n + The InGaAs drain cap layer 111 is located on the other side above the undoped InAlAs barrier layer 109;

[0028] Source electrode 112 is located at n + Above the InGaAs source cap layer 110;

[0029] Drain electrode 113 is located at n + Above the InGaAs drain cap layer 111;

[0030] Passivation layer 114 is located in n + InGaAs source cap 110, source electrode 112 and n + Between the InGaAs drain cap layer 111 and the drain electrode 113;

[0031] The passivation layer 114 has a concave structure, with the two ends of the concave structure respectively connected to n. + InGaAs source cap layer 110, source electrode 112, n + The InGaAs drain cap layer 111 and the inner side of the drain electrode 113 are in contact; wherein, one end is in contact with n + The entire inner region of the InGaAs source cap layer 110 and a portion of the inner region of the source electrode 112 are in contact with each other, and the other end is in contact with the entire inner region of the n+InGaAs drain cap layer 111 and a portion of the inner region of the drain electrode 113; the recessed region of the concave structure includes a gate region groove in the middle.

[0032] The gate electrode 115 is located in the gate region groove and contacts the undoped InAlAs barrier layer 109, and its thickness is greater than the thickness of the gate region groove.

[0033] The high electron mobility transistor with composite channel structure described in this invention refers to In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As / InP composite channel structure high electron mobility transistor.

[0034] The structural feature of this invention is that: the InP secondary channel differs from the traditional In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78The As composite channel forms a four-layer composite channel structure, with the InP sub-channel at the bottom of the entire channel structure.

[0035] Optionally, the thickness of the undoped InAlAs buffer layer 102 is 300–500 nm, and the In composition is 52%.

[0036] Optionally, the thickness of the InP sub-channel 103 is 2–5 nm.

[0037] Optionally, the first undoped In 0.22 Ga 0.78 The thickness of the As secondary channel 104 is 2-3 nm.

[0038] Optional, undoped In 0.7 Ga 0.3 The thickness of the As main channel 105 is 2-3 nm.

[0039] Optionally, a second undoped In 0.22 Ga 0.78 The thickness of the As secondary channel 106 is 2-3 nm.

[0040] Optionally, the undoped InAlAs isolation layer 107 has a thickness of 2–3 nm and an In composition of 52%.

[0041] Optionally, the delta-doping layer 108 is planar doped with a doping concentration of 5 × 10⁸. 12 cm -2 .

[0042] Optionally, the undoped InAlAs barrier layer 109 has a thickness of 12–15 nm and an In composition of 52%.

[0043] Optional, n + InGaAs source cap layer 110 and n + The InGaAs drain cap layer 111 has a thickness of 30 nm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The In component is 60%.

[0044] Optionally, the passivation layer 114 has a thickness of 50–100 nm.

[0045] Optionally, the passivation layer is a SiN layer.

[0046] Optionally, a source metal interconnect 1121 is provided on the source electrode 112; wherein, the source metal interconnect 1121 covers the entire area of ​​the upper surface of the source electrode 112 and a part of the upper surface of the passivation layer 114.

[0047] Optionally, a drain metal interconnect 1131 is provided on the drain electrode 113; wherein the drain metal interconnect 1131 covers the entire area of ​​the upper surface of the drain electrode 113 and a part of the upper surface of the passivation layer 114.

[0048] Optionally, a gate metal interconnect 1151 is provided on the gate electrode 115; wherein the gate metal interconnect 1151 covers the entire area of ​​the upper surface of the gate electrode 115 and extends to cover a portion of the upper surface of the passivation layer 114.

[0049] The purpose of this invention is to target InP-based In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 To address the issue of excessively low breakdown voltage in high electron mobility transistors (HEMTs) with composite channel structures, an In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As / InP composite channel HEMT and its fabrication method are proposed to improve the breakdown voltage of InP-based HEMTs, maintain the relatively high output characteristics and cutoff frequency of high In composition channels, and manufacture devices with uniformity and repeatability to meet the application requirements of InP-based electronic devices in low power consumption, low noise, and digital circuit fields.

[0050] This invention combines the InP secondary channel with the traditional In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As composite channel composition In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 The As / InP four-layer composite channel effectively utilizes the high and low field mobility of the high-In-content InGaAs material and the high breakdown voltage and high saturation electron velocity of InP, ensuring the same level of output current while significantly improving the transistor's breakdown voltage. Furthermore, the high-In-content InGaAs channel provides terahertz-level cutoff and maximum oscillation frequencies, and the addition of the InP secondary channel does not negatively impact these values.

[0051] In summary, the composite channel high electron mobility transistor provided by this invention combines the InP secondary channel with the traditional In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As composite channel composition In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 The As / InP four-layer composite channel structure effectively utilizes the high and low field mobility of InGaAs material with high In content and the high breakdown voltage and high saturation electron velocity of InP material. This allows for both maintaining the same level of output current and significantly increasing the transistor's breakdown voltage. Furthermore, since electrons still primarily transport in the main channel under non-high field breakdown conditions, it offers advantages over traditional In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 Compared to the As composite channel structure, the addition of an InP secondary channel in this invention to form a composite channel does not negatively affect the values ​​of the cutoff frequency and the maximum oscillation frequency. Therefore, the high electron mobility transistor provided by this invention has a larger breakdown voltage, and its DC-IV characteristics and frequency characteristics can meet the simulation theoretical expectations.

[0052] Example 2

[0053] Please see Figure 2 , Figure 2 This is a schematic diagram of a method for fabricating a high electron mobility transistor with a composite channel structure according to an embodiment of the present invention. The method includes:

[0054] Step 1: Grow an undoped InAlAs buffer layer on a semi-insulating InP substrate.

[0055] It should be noted that the present invention can utilize the MOCVD (Metal Organic Chemical Vapor Deposition) method to prepare high electron mobility transistors with composite channel structures.

[0056] Step 2: Grow an InP secondary channel on an undoped InAlAs buffer layer.

[0057] Step 3: Grow the first undoped In on the InP secondary channel 0.22 Ga 0.78 As secondary channel.

[0058] Step 4: In the first undoped In 0.22 Ga 0.78 Undoped In is grown on the secondary channel. 0.7 Ga 0.3 As the main channel.

[0059] Step 5: In undoped In 0.7 Ga 0.3 As the second undoped In is grown on the main channel 0.22 Ga 0.78 As secondary channel.

[0060] Step 6: In the second undoped In 0.22 Ga 0.78 An undoped InAlAs isolation layer is grown on the As secondary channel.

[0061] Step 7: Grow a delta-doping layer on the undoped InAlAs isolation layer according to the first doping concentration.

[0062] The growth parameters of the delta-doping layer include only introducing a silicon source, and the delta-doping layer is planar doped.

[0063] Optionally, the first doping concentration is 5 × 10⁻⁶. 12 cm -2 The second doping concentration is 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 .

[0064] Step 8: Grow an undoped InAlAs barrier layer on the delta-doping layer.

[0065] Step 9: According to the second doping concentration, grow n on the undoped InAlAs barrier layer. + InGaAs source cap layer and n + InGaAs drain cap layer.

[0066] Optionally, the preset etching parameters include etching gas carbon tetrafluoride (CF4) plasma and etching rate of 0.5 nm / s.

[0067] For example, using the MOCVD method to grow n on an undoped InAlAs barrier layer + InGaAs cap layer, doping concentration 5×10 18 cm -3 ~3×10 19 cm -3 n +The InGaAs cap layer is 30nm thick, and then only the source and drain cap layers are left by etching.

[0068] Step 10: In n + InGaAs source cap layer and n + Source and drain electrodes are fabricated on the InGaAs drain cap layer.

[0069] Step 11: A passivation layer with a concave structure is deposited on the device surface using PECVD process, and then etched away according to preset etching parameters to obtain the gate region groove.

[0070] For example, a SiN passivation layer with a thickness of 50–100 nm is deposited on the device surface, and the gate region groove is exposed by etching.

[0071] Step 12: The gate electrode is obtained in the gate region groove through photolithography and evaporation.

[0072] Step 13: Obtain the lead electrode.

[0073] Optionally, step 13 includes:

[0074] Fabricate source metal interconnects on the source electrode;

[0075] Drain metal interconnects are fabricated on the drain electrode;

[0076] A gate metal interconnect is fabricated on the gate electrode.

[0077] See Figure 3A-3M , Figure 3A-3M This is a schematic diagram of the fabrication process of a high electron mobility transistor with a composite channel structure provided in an embodiment of the present invention.

[0078] For example, using the method for fabricating a high electron mobility transistor with a composite channel structure provided by this invention, an InP secondary channel of 3 nm is fabricated. 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 In with a channel of 2 / 3 / 2nm 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As / InP composite channel structure high electron mobility transistor:

[0079] See Figure 3AOn a semi-insulating InP substrate, an undoped InAlAs buffer layer with a thickness of 500 nm was epitaxially grown using MOCVD process. The process conditions were 650℃, the MO source was TMIn and TMAl, and the special gas used was AsH3.

[0080] See Figure 3B On an undoped InAlAs buffer layer, an InP sub-channel was epitaxially grown using MOCVD. The InP sub-channel thickness was 5 nm, the process temperature was 650 °C, the MO source was TMIn, and the special gas used was PH3.

[0081] See Figure 3C On the InP secondary channel, the first undoped In was epitaxially grown using MOCVD technology. 0.22 Ga 0.78 As the secondary channel, the first undoped In 0.22 Ga 0.78 The As secondary channel thickness is 2nm, the process temperature is 650℃, the MO source is TMIn and TMGa, and the special gas used is AsH3.

[0082] See Figure 3D In 0.22 Ga 0.78 On the As secondary channel, undoped In was epitaxially grown using MOCVD technology. 0.7 Ga 0.3 As the main channel, undoped In 0.7 Ga 0.3 The As main channel thickness is 3nm, the process temperature is 650℃, the MO source is TMIn and TMGa, and the special gas used is AsH3.

[0083] See Figure 3E In 0.7 Ga 0.3 On the As main channel, a second undoped In was epitaxially grown using MOCVD. 0.22 Ga 0.78 As the secondary channel, the second undoped In 0.22 Ga 0.78 The As secondary channel thickness is 2nm, the process temperature is 650℃, the MO source is TMIn and TMGa, and the special gas used is AsH3.

[0084] See Figure 3F Undoped InAlAs isolation layers were epitaxially grown on undoped InGaAs channels using MOCVD. The thickness of the undoped InAlAs isolation layer was 3 nm. The process conditions were 650 °C, the MO source was TMI and TMI, and the special gas used was AsH3.

[0085] See Figure 3GA delta-doping layer was epitaxially grown on an undoped InAlAs isolation layer using MOCVD at 650°C. Only the SiH4 doping source was activated, with a doping concentration of 5 × 10⁻⁶. 12 cm -2 .

[0086] See Figure 3H On the upper delta-doping layer, an undoped InAlAs barrier layer was epitaxially grown using MOCVD technology. The thickness of the undoped InAlAs barrier layer was 12 nm. The process conditions were 650 °C, the MO source was TMI and TMI, and the special gas used was AsH3.

[0087] See Figure 3I First, on the undoped InAlAs barrier layer, n is epitaxially grown using MOCVD technology. + InGaAs cap layer, n + The InGaAs cap layer thickness is 30 nm, the process conditions are 650℃, the MO source is TMI / TMGa, the specialty gas used is AsH3, the doping source is SiH4, and the doping concentration is 3×10⁻⁶. 19 cm -3 Then, the source and drain cap layers are fabricated: first, a spin coater is used at a speed of 3500 rpm to obtain a photoresist mask; then, an electron beam lithography machine is used for exposure to form the mask patterns of the source and drain regions. Next, the substrate with the mask is etched using an ICP98c inductively coupled plasma etching machine under the following conditions: Cl2 / N2 gas flow rate of 10 sccm / 60 sccm, ICP power source power of 350W, bias power source power of 120W, cavity pressure of 4 mTorr, temperature of 150℃, and etching time of 0.5 min to etch the n-type cap layers outside the source and drain regions. + InGaAs cap layer etching.

[0088] See Figure 3JFabrication of source and drain electrodes: A spin coater was used at 5000 rpm to obtain a photoresist mask with a thickness of 0.8 μm. Next, the mask was baked in a high-temperature oven at 80℃ for 10 min, followed by exposure using an NSR1755I7A lithography machine to form the source and drain region mask patterns. Then, the source and drain electrodes were fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The source and drain metals were sequentially selected as Ti / Al / Ni / Au, with Ti thicknesses of 20 nm, Al thicknesses of 120 nm, Ni thicknesses of 45 nm, and Au thicknesses of 55 nm. After the ohmic contact metals were evaporated, metal stripping was performed. Finally, the ohmic contact metals were alloyed using an RTP500 rapid thermal annealing furnace at 870℃ in a N2 atmosphere for 30 s, completing the fabrication of the source and drain electrodes.

[0089] See Figure 3K First, a 100 nm thick SiN passivation layer was deposited on the top InAlAs barrier layer using a PECVD 790 deposition equipment with NH3 as the N source and SiH4 as the Si source at a deposition temperature of 250 °C. The deposited passivation layer exhibited a concave structure. Then, positive photoresist was spun onto the epitaxial material surface at a rotation speed of 5000 rpm to obtain a 0.8 μm thick photoresist mask, which was then baked in a high-temperature oven at 80 °C for 10 min. The gate electrode pattern was then obtained using an NSR1755I7A lithography machine. Next, the SiN passivation layer in the gate region was removed by etching in CF4 plasma at an etching rate of 0.5 nm / s using an ICP98c inductively coupled plasma etching machine, resulting in a gate region groove.

[0090] See Figure 3L Fabrication of the gate electrode: First, a photoresist mask with a thickness of 0.8 μm was obtained by spin-coating at 5000 rpm. Next, the mask was baked in a high-temperature oven at 80°C for 10 min and exposed using an NSR1755I7A lithography machine. The photolithography alignment formed a gate region mask pattern covering the entire gate trench. Finally, the gate metal was evaporated at a rate of 0.1 nm / s using an Ohmiker-50 electron beam evaporation stage, covering the top of the InAlAs barrier layer. The gate metal was selected as Ni / Au, with a Ni thickness of 20 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain the complete gate electrode.

[0091] See Figure 3MFabrication of interconnect leads: First, a spin coater is used to spin-coat positive adhesive at a speed of 5000 rpm; then, an NSR1755I7A lithography machine is used for exposure to form an electrode lead mask pattern; next, an Ohmiker-50 electron beam evaporation stage is used to evaporate the lead electrode metal on the substrate with the mask fabricated at an evaporation rate of 0.3 nm / s. The metals selected are Ti with a thickness of 20 nm and Au with a thickness of 200 nm; finally, after the lead electrode metal evaporation is completed, it is peeled off to obtain the complete lead electrode.

[0092] In summary, the composite channel high electron mobility transistor provided by this invention combines the InP secondary channel with the traditional In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 As composite channel composition In 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 The As / InP four-layer composite channel structure effectively utilizes the high and low field mobility of InGaAs material with high In content and the high breakdown voltage and high saturation electron velocity of InP material. This allows for both maintaining the same level of output current and significantly increasing the transistor's breakdown voltage. Furthermore, since electrons still primarily transport in the main channel under non-high field breakdown conditions, it offers advantages over traditional In... 0.22 Ga 0.78 As / In 0.7 Ga 0.3 As / In 0.22 Ga 0.78 Compared to the As composite channel structure, the addition of an InP secondary channel in this invention to form a composite channel does not negatively affect the values ​​of the cutoff frequency and the maximum oscillation frequency. Therefore, the high electron mobility transistor provided by this invention has a larger breakdown voltage, and its DC-IV characteristics and frequency characteristics can meet the simulation theoretical expectations.

[0093] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high electron mobility transistor with a composite channel structure, characterized in that, The transistor includes: Semi-insulating InP substrate (101), undoped InAlAs buffer layer (102), InP sub-channel (103), first undoped In 0.22 Ga 0.78 As secondary channel (104), undoped In 0.7 Ga 0.3 As main channel (105), second undoped In 0.22 Ga 0.78 As secondary channel (106), undoped InAlAs isolation layer (107), delta-doping layer (108), undoped InAlAs barrier layer (109), n + InGaAs source cap layer (110), n + The InGaAs drain cap layer (111), source electrode (112), drain electrode (113), passivation layer (114), and gate electrode (115) are as follows: An undoped InAlAs buffer layer (102) is located above a semi-insulating InP substrate (101); The InP secondary channel (103) is located above the undoped InAlAs buffer layer (102); wherein, the InP secondary channel and the In0.22Ga0.78As / In0.7Ga0.3As / In0.22Ga0.78As composite channel form a four-layer composite channel structure, with the InP secondary channel at the bottom of the entire channel structure; the first undoped In 0.22 Ga 0.78 The As subchannel (104) is located above the InP subchannel (103); Undoped In 0.7 Ga 0.3 As main channel (105) is located in undoped In 0.22 Ga 0.78 Above the secondary channel (104); Second undoped In 0.22 Ga 0.78 As secondary channel (106) is located in undoped In 0.7 Ga 0.3 Above the main channel (105); The undoped InAlAs isolation layer (107) is located at the second undoped In 0.22 Ga 0.78 Above the secondary channel (106); The delta-doping layer (108) is located above the undoped InAlAs isolation layer (107); An undoped InAlAs barrier layer (109) is located above the delta-doping layer (108); n + The InGaAs source cap layer (110) is located on one side above the undoped InAlAs barrier layer (109); n + The InGaAs drain cap layer (111) is located on the other side above the undoped InAlAs barrier layer (109); The source electrode (112) is located at n + Above the InGaAs source cap layer (110); The drain electrode (113) is located at n + Above the InGaAs drain cap layer (111); The passivation layer (114) is located at n + InGaAs source cap (110), source electrode (112) and n + Between the InGaAs drain cap layer (111) and the drain electrode (113); The passivation layer (114) has a concave structure, with the two ends of the concave structure respectively connected to n. + InGaAs source cap layer (110), source electrode (112), n + The inner sides of the InGaAs drain cap layer (111) and drain electrode (113) are in contact; one end is in contact with n + The entire inner region of the InGaAs source cap layer (110) and a portion of the inner region of the source electrode (112) are in contact, and the other end is in contact with the entire inner region of the n+InGaAs drain cap layer (111) and a portion of the inner region of the drain electrode (113); the recessed region of the concave structure includes a gate region groove in the middle. The gate electrode (115) is located in the gate region groove and contacts the undoped InAlAs barrier layer (109), and its thickness is greater than the thickness of the gate region groove; The undoped InAlAs buffer layer (102) has a thickness of 300~500nm and an In composition of 52%. The thickness of the InP subchannel (103) is 2~5 nm; First undoped In 0.22 Ga 0.78 The thickness of the As secondary channel (104) is 2~3 nm; Undoped In 0.7 Ga 0.3 The thickness of the As main channel (105) is 2~3nm; Second undoped In 0.22 Ga 0.78 The thickness of the As secondary channel (106) is 2~3 nm; The thickness of the undoped InAlAs isolation layer (107) is 2~3 nm, and the In composition is 52%; The delta-doping layer (108) is planar doped with a doping concentration of 5 × 10⁸. 12 cm -2 ; The thickness of the undoped InAlAs barrier layer (109) is 12~15 nm, and the In composition is 52%. n + InGaAs source cap (110) and n + The InGaAs drain cap layer (111) has a thickness of 30 nm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The In component is 60%; The passivation layer (114) has a thickness of 50~100nm.

2. The transistor according to claim 1, characterized in that, A source metal interconnect (1121) is disposed on the source electrode (112); wherein, The source metal interconnect (1121) covers the entire area of ​​the upper surface of the source electrode (112) and part of the upper surface of the passivation layer (114).

3. The transistor according to claim 1, characterized in that, A drain metal interconnect (1131) is disposed on the drain electrode (113); wherein, The drain metal interconnect (1131) covers the entire area of ​​the upper surface of the drain electrode (113) and part of the upper surface of the passivation layer (114).

4. The transistor according to claim 1, characterized in that, A gate metal interconnect (1151) is disposed on the gate electrode (115); wherein, The gate metal interconnect (1151) covers the entire area of ​​the upper surface of the gate electrode (115) and extends to cover a portion of the upper surface of the passivation layer (114).

5. A method for fabricating a high electron mobility transistor with a composite channel structure, characterized in that, The method includes: Step 1: Grow an undoped InAlAs buffer layer on a semi-insulating InP substrate; Step 2: Grow an InP sub-channel on an undoped InAlAs buffer layer; wherein the InP sub-channel and the In0.22Ga0.78As / In0.7Ga0.3As / In0.22Ga0.78As composite channel form a four-layer composite channel structure, with the InP sub-channel at the bottom of the entire channel structure. Step 3: Grow the first undoped In on the InP secondary channel 0.22 Ga 0.78 As secondary channel; Step 4: In the first undoped In 0.22 Ga 0.78 Undoped In is grown on the secondary channel. 0.7 Ga 0.3 As the main channel; Step 5: In undoped In 0.7 Ga 0.3 As the second undoped In is grown on the main channel 0.22 Ga 0.78 As secondary channel; Step 6: In the second undoped In 0.22 Ga 0.78 An undoped InAlAs isolation layer is grown on the As secondary channel; Step 7: Grow a delta-doping layer on the undoped InAlAs isolation layer according to the first doping concentration; Step 8: Grow an undoped InAlAs barrier layer on the delta-doping layer; Step 9: According to the second doping concentration, grow n on the undoped InAlAs barrier layer. + InGaAs source cap layer and n + InGaAs drain cap layer; Step 10: In n + InGaAs source cap layer and n + Source and drain electrodes are fabricated on the InGaAs drain cap layer; Step 11: A passivation layer with a concave structure is deposited on the device surface using PECVD process, and then etched away according to preset etching parameters to obtain the gate region groove. Step 12: The gate electrode is obtained in the gate region groove through photolithography and evaporation processes; Step 13: Obtain the lead electrodes; The undoped InAlAs buffer layer (102) has a thickness of 300~500nm and an In composition of 52%. The thickness of the InP subchannel (103) is 2~5 nm; First undoped In 0.22 Ga 0.78 The thickness of the As secondary channel (104) is 2~3 nm; Undoped In 0.7 Ga 0.3 The thickness of the As main channel (105) is 2~3nm; Second undoped In 0.22 Ga 0.78 The thickness of the As secondary channel (106) is 2~3 nm; The thickness of the undoped InAlAs isolation layer (107) is 2~3 nm, and the In composition is 52%; The delta-doping layer (108) is planar doped with a doping concentration of 5 × 10⁸. 12 cm -2 ; The thickness of the undoped InAlAs barrier layer (109) is 12~15 nm, and the In composition is 52%. n + InGaAs source cap (110) and n + The InGaAs drain cap layer (111) has a thickness of 30 nm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The In component is 60%; The passivation layer (114) has a thickness of 50~100nm.

6. The method according to claim 5, characterized in that, The first doping concentration is 5×10 12 cm -2 The second doping concentration is 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 .

7. The method according to claim 5, characterized in that, The preset etching parameters include etching gas tetrafluoride plasma and etching rate of 0.5 nm / s.

8. The method according to claim 5, characterized in that, Step 13 includes: Fabricate source metal interconnects on the source electrode; Drain metal interconnects are fabricated on the drain electrode; A gate metal interconnect is fabricated on the gate electrode.

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