Single-edge delay circuit and double-edge delay circuit

Abstract

This invention discloses a single-edge delay circuit and a double-edge delay circuit. The single-edge delay circuit includes a frequency divider and an oscillator circuit. The controlled terminal of the frequency divider and the first controlled terminal of the oscillator circuit are both connected to the signal to be delayed. The second controlled terminal of the oscillator circuit is connected to the output terminal of the frequency divider, and the output terminal of the oscillator circuit is connected to the input terminal of the frequency divider. When the signal to be delayed is received, the frequency divider is activated, and the oscillator circuit begins to oscillate and outputs a clock signal to the frequency divider. The frequency divider then outputs a preset frequency-divided signal to the oscillator circuit according to the clock signal. When the oscillator circuit receives the preset frequency-divided signal, it stops oscillating. At this time, the frequency divider outputs the delayed signal. This invention utilizes a combination of a frequency divider and an oscillator circuit to achieve a relatively large delay time for the signal to be delayed with lower area overhead.

Description

Technical Field

[0001] This invention relates to the field of delay circuit technology, and particularly to a single-edge delay circuit and a double-edge delay circuit. Background Technology

[0002] Delay circuits are widely used in various circuits, such as those in System on Chip (SoC) chips. Delay circuits include single-edge delay circuits (circuits that delay on the rising edge or the falling edge) and double-edge delay circuits (circuits that delay on both the rising and falling edges).

[0003] Current delay circuits are mainly implemented using RC delay circuits. However, there is a trade-off between delay time and size in RC delay circuits. Specifically, when implementing a longer delay, the RC delay circuit will occupy a larger area. In particular, when implementing a longer delay, the RC delay circuit needs to use a resistor R or capacitor C with a larger value. A larger resistor R and capacitor C will undoubtedly increase the size of the RC delay circuit, thus causing the RC delay circuit to occupy a larger area. Summary of the Invention

[0004] The main objective of this invention is to provide a single-edge delay circuit, which aims to provide a delay circuit with a longer delay time in the same volume.

[0005] To achieve the above objectives, the present invention proposes a single-edge delay circuit for delaying a signal to be delayed. The single-edge delay circuit includes:

[0006] A frequency divider has a controlled terminal, an input terminal, and an output terminal. When the frequency divider receives the signal to be delayed at its controlled terminal, it divides the clock signal connected to its input terminal and outputs a preset divided signal and a delay signal.

[0007] An oscillation circuit has a first controlled terminal, a second controlled terminal, and an output terminal. The oscillation circuit is used to output the clock signal to the frequency divider when it receives the delay signal at its first controlled terminal, and to stop outputting the clock signal to the frequency divider when it receives the preset frequency division signal at its second controlled terminal.

[0008] In one embodiment, the frequency divider outputs multiple frequency-divided signals, and the single-edge delay circuit further includes:

[0009] The delay selection circuit has an input terminal and an output terminal. The input terminal of the delay selection circuit is connected to the output terminal of the frequency divider, and the output terminal of the delay selection circuit is connected to the second controlled terminal of the oscillation circuit. The delay selection circuit is used to select one of the frequency division signals from multiple frequency division signals according to the delay requirement and output it as the preset frequency division signal to the oscillation circuit.

[0010] In one embodiment, the oscillation circuit includes a charging circuit, a first capacitor, a shaping circuit, and a discharge circuit;

[0011] The charging circuit has the controlled terminal connected to the signal to be delayed, and the input terminal of the charging circuit is connected to the power supply.

[0012] A first capacitor, the first terminal of which is connected to the output terminal of the charging circuit, and the second terminal of which is grounded;

[0013] A shaping circuit, wherein the input terminal of the shaping circuit is connected to the first terminal of the first capacitor;

[0014] The discharge circuit has a first input terminal connected to the output terminal of the shaping circuit, a second input terminal connected to the delay selection circuit, and an output terminal connected to the first capacitor. The discharge circuit is used to periodically discharge the energy of the first capacitor according to the shaping signal output by the shaping circuit, and stops working when the preset frequency division signal is received.

[0015] In one embodiment, the discharge circuit includes an AND logic circuit and a first discharge switch. The first input terminal of the AND logic circuit is connected to the output terminal of the shaping circuit, the second input terminal of the AND logic circuit is connected to the delay selection circuit, and the output terminal of the AND logic circuit is connected to the controlled terminal of the first discharge switch. The input terminal of the first discharge switch is connected to the first terminal of the first capacitor, and the output terminal of the first discharge switch is grounded.

[0016] In one embodiment, the discharge circuit includes an OR logic circuit and a second discharge switch. The first input terminal of the OR logic circuit is connected to the output terminal of the shaping circuit, the second input terminal of the OR logic circuit is connected to the delay selection circuit, and the output terminal of the OR logic circuit is connected to the controlled terminal of the second discharge switch. The input terminal of the second discharge switch is connected to a power supply, and the output terminal of the second discharge switch is connected to the first terminal of the first capacitor.

[0017] In one embodiment, the charging circuit includes: a first electronic switch and a second electronic switch;

[0018] The controlled terminal of the first electronic switch is interconnected with the controlled terminal of the second electronic switch to serve as the controlled terminal of the charging circuit. The output terminal of the first electronic switch is interconnected with the output terminal of the second electronic switch to serve as the output terminal of the charging circuit. The input terminal of the first electronic switch is the input terminal of the charging circuit, and the output terminal of the second electronic switch is grounded.

[0019] In one embodiment, the shaping circuit includes a Schmitt trigger and a plurality of inverters connected in series;

[0020] The input terminal of the Schmitt trigger is the input terminal of the shaping circuit, and the output terminal of the Schmitt trigger is connected to the input terminal of the plurality of inverters connected in series. The output terminal of the plurality of inverters connected in series is the output terminal of the shaping circuit.

[0021] In one embodiment, the oscillation circuit further includes:

[0022] The second capacitor has its first terminal connected to the output terminal of any one of the plurality of inverters connected in series, and its second terminal grounded.

[0023] In one embodiment, the single-edge delay circuit further includes:

[0024] A delay signal access circuit is provided, wherein the input terminal of the delay signal access circuit is used to receive the delay signal, and the output terminal of the delay signal access circuit is connected to the controlled terminal of the frequency divider and the first controlled terminal of the oscillation circuit. The delay signal access circuit is used for:

[0025] The signal to be delayed is inverted and then output.

[0026] The present invention also proposes a dual-edge delay circuit, comprising:

[0027] The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal.

[0028] The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal.

[0029] The first single-edge delay circuit and the second single-edge delay circuit are connected in series;

[0030] Wherein, the first single-edge delay circuit is the single-edge delay circuit described above; and / or, the second single-edge delay circuit is the single-edge delay circuit described above.

[0031] The present invention also proposes a dual-edge delay circuit, comprising:

[0032] The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal.

[0033] The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal.

[0034] The D flip-flop has its set-to-1 terminal connected to the output of the first single-edge delay circuit, and its set-to-0 terminal connected to the output of the second single-edge delay circuit. Both the input terminal d and the clock input terminal of the D flip-flop are connected to the power supply, and the output terminal of the D flip-flop is the output of the double-edge delay circuit.

[0035] Wherein, the first single-edge delay circuit is the single-edge delay circuit described above; and / or, the second single-edge delay circuit is the single-edge delay circuit described above.

[0036] In this invention, rising edge delay is used as an example for explanation. Upon receiving the rising edge of the signal to be delayed, the oscillation circuit starts oscillating and outputs a clock signal. Simultaneously, the frequency divider divides the clock signal and outputs the divided signals sequentially until the frequency divider outputs a preset divided signal. At this point, the oscillation circuit receives the preset divided signal and stops oscillating. The time from receiving the rising edge of the signal to be delayed to the time the frequency divider outputs the preset divided signal is the delay time of the rising edge of the signal to be delayed, and the frequency divider outputs the delayed signal. This achieves the delay of one rising edge of the signal to be delayed; the falling edge delay works similarly. Waiting for the next rising or falling edge of the signal to be delayed, the above process is repeated until each rising or falling edge of the signal to be delayed is sequentially delayed. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0038] Figure 1 This is a circuit block diagram of an embodiment of the single-edge delay circuit of the present invention;

[0039] Figure 2 This is a circuit diagram of an embodiment of the single-edge delay circuit of the present invention;

[0040] Figure 3 for Figure 2 The circuit diagram shown contains signal waveforms for key nodes.

[0041] Figure 4 for Figure 2 The circuit diagram shown contains signal waveforms for key nodes.

[0042] Figure 5 This is a circuit diagram of another embodiment of the single-edge delay circuit of the present invention;

[0043] Figure 6 for Figure 5 The circuit diagram shown contains signal waveforms for key nodes.

[0044] Figure 7 This is a circuit diagram of another embodiment of the single-edge delay circuit of the present invention;

[0045] Figure 8 for Figure 7 The circuit diagram shown contains signal waveforms for key nodes.

[0046] Figure 9 This is a circuit diagram of another embodiment of the single-edge delay circuit of the present invention;

[0047] Figure 10 for Figure 9 The circuit diagram shown contains signal waveforms for key nodes.

[0048] Figure 11 This is a circuit block diagram of the dual-edge delay circuit of the present invention;

[0049] Figure 12 for Figure 11 The circuit diagram shown contains signal waveforms for key nodes.

[0050] Figure 13 This is a circuit block diagram of the dual-edge delay circuit of the present invention;

[0051] Figure 14 for Figure 13 The circuit diagram shown contains signal waveforms for key nodes.

[0052] Explanation of icon numbers:

[0053] label name label name 1 First single-edge delay circuit U1 or logic circuit 2 Second single-edge delay circuit smt Schmitt trigger 10 Oscillating circuit U21~U23 Multiple inverters 20 Frequency divider U24 First inverter 30 Delay selection circuit U25 Second inverter 11 Charging circuit U3 or logic circuit 12 Shaping circuit U4 buffer 13 Bleeding circuit D1~D4 First to fourth D triggers M1 First electronic switch C1 First capacitor M2 Second electronic switch C2 Second capacitor M3 First discharge switch D D flip-flop M4 Second discharge switch

[0054] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0056] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0057] This invention proposes a single-edge delay circuit for delaying and then outputting the signal in to be delayed.

[0058] Reference Figure 1 In one embodiment, the single-edge delay circuit includes:

[0059] Frequency divider 20 has a controlled terminal, an input terminal, and an output terminal. The controlled terminal is connected to the signal to be delayed, in. When the controlled terminal receives the signal to be delayed, in, the frequency divider 20 divides the clock signal clk connected to its input terminal and outputs a preset divided frequency signal q. <m>and the delayed signal out;

[0060] The oscillation circuit 10 has a first controlled terminal, a second controlled terminal, and an output terminal. The first controlled terminal is connected to the signal to be delayed, in. When the oscillation circuit 10 receives the signal to be delayed, in, it outputs the clock signal clk to the frequency divider 20, and receives a preset frequency division signal q at its second controlled terminal. <m>When the clock signal clk is stopped from being output to the frequency divider 20, the clock signal clk is stopped.

[0061] In this embodiment, receiving the signal to be delayed, in, can refer to receiving the rising edge signal and / or falling edge signal of the signal to be delayed, which can be determined according to whether the signal to be delayed, in, needs to be delayed by the rising edge or the falling edge in the actual application.

[0062] The frequency divider 20 can be implemented using D flip-flops, JK flip-flops, or other flip-flops; no specific limitation is made here, as long as it satisfies the requirement of dividing the clock signal clk. The frequency divider can output multiple divided signals q. <0> q <1> q <2> , ..., q <n-1> 、q <n>Preset frequency division signal q <m>It can be multiple frequency-divided signals q <0> q <1> q <2> , ..., q <n-1> 、q <n>Any one of the following can be selected as the preset frequency division signal and connected to the oscillation circuit 10 according to the actual delay requirements. In practical applications, the output port of the preset frequency division signal can be directly connected to the second controlled terminal of the oscillation circuit 10, or a selection circuit can be set to select one from multiple frequency division signal output interfaces and connect it to the second controlled terminal of the oscillation circuit 10. Where m is less than or equal to n.

[0063] The oscillation circuit 10 can be any type of controllable oscillation circuit 10, and is not limited here, as long as it can start oscillating and output a clock signal when it receives the delay signal in at its first controlled terminal, and receive the preset frequency division signal q at its second controlled terminal. <m>The oscillation will stop when the time comes.

[0064] Reference Figure 1 This embodiment uses rising edge delay as an example for explanation. When the rising edge of the signal to be delayed, in, is received, the oscillation circuit 10 starts oscillating and outputs a clock signal clk. The frequency divider 20 divides the clock signal clk and outputs the divided signal q in sequence. <0> q <1> q <2> , ......, q <n>At this point, the frequency division signal q can be selected. <0> q <1> q <2> , ......, q <n>One of them is used as the preset frequency division signal q <m>Connected to the second controlled terminal of the oscillation circuit, the frequency divider 20 outputs the preset frequency division signal q. <m>At that time, the oscillation circuit 10 receives the preset frequency division signal q. <m>And then stop oscillation. At this time, from the moment the rising edge of the delay signal in is received until the frequency divider 20 outputs the preset frequency division signal q <m>The time at which the rising edge of the signal to be delayed, in, is delayed is the time when the frequency divider's preset frequency division signal q is delayed. <m>Alternatively, its inverted signal is the signal out1 after the signal to be delayed is delayed by the rising edge.

[0065] In this way, a delay is achieved for one rising edge of the signal to be delayed, in. Then, the above process is repeated when the next rising edge of the signal to be delayed, in arrives, ultimately achieving a delay for each rising edge of the signal to be delayed, in sequence. It is easy to understand that to delay each falling edge of the signal to be delayed, it is only necessary to adjust the frequency divider 20 and the oscillation circuit 10 from rising edge triggering to falling edge triggering; the principle is the same and will not be elaborated here.

[0066] It should be noted that traditional RC delay circuits require a significant increase in the value of resistors or capacitors when a longer delay time is needed, which means increasing the size of the capacitors or resistors. This, in turn, requires a substantial increase in the area occupied by the resistors and capacitors. For chips, area resources are very precious, and an increase in the area occupied not only means an increase in cost but also an increase in power consumption.

[0067] The single-edge delay circuit of this invention is implemented using a frequency divider 20 and an oscillator circuit 10. By simply increasing the division factor of the frequency divider 20 and outputting a preset frequency-divided signal with a later rising edge to the oscillator circuit 10, a longer delay time can be achieved. For example, taking a frequency divider composed of multiple cascaded D flip-flops as an example, the technical solution of this application only needs to add one D flip-flop to double the division factor of the frequency divider, thereby doubling the delay time. Compared with traditional RC delay circuits, this solution can achieve a larger delay in a smaller volume, which is beneficial for reducing the area occupied by the delay circuit and effectively saving chip area resources.

[0068] Reference Figure 2 and Figure 5 In some embodiments, the frequency divider 20 can be implemented as a D flip-flop, then n D flip-flops can output n divided frequency signals q. <0> q <1> q <2> , ..., q <n>(or qb) <0> ,qb <1> ,qb <2> ... qb <n>The frequency division signal here is labeled q. <n>Or qb <n>For ease of reading only, when the output terminal q of a D flip-flop is used to output a frequency-divided signal, it is labeled as q. <n>When the frequency-divided signal is output using the inverting output terminal qb of the D flip-flop, it is labeled as qb. <n>The number of D flip-flops can be set according to the actual delay requirements. Each additional D flip-flop doubles the delay time of the single-edge delay circuit. In practical applications, the frequency division signal output from either the q terminal of the D flip-flop or its inverted output qb terminal can be selected as the preset frequency division signal based on the control requirements of the oscillation circuit.

[0069] Furthermore, when a single-edge delay circuit is needed to achieve rising edge delay, the signal output from the q terminal of the D flip-flop can be selected as the rising edge delay signal out1 of the signal to be delayed, in. When a single-edge delay circuit is needed to achieve falling edge delay, the signal output from the inverted output qb terminal of the D flip-flop can be selected as the falling edge delay signal out2 of the signal to be delayed, in.

[0070] In this embodiment, n equals 4, and the four D flip-flops are sequentially labeled as the first D flip-flop D1 to the fourth D flip-flop D4. The connection relationship of the D flip-flops forming the frequency divider is described. There are two specific implementations of the D flip-flops forming the frequency divider 20.

[0071] For a specific implementation of the frequency divider 20 using D flip-flops, please refer to [reference needed]. Figure 2 The input terminals d of the first to fourth D flip-flops D1 to D4 are connected to their inverted output terminals qb. The clock terminal of the first D flip-flop D1 is the input terminal of the frequency divider 20, receiving the clock signal clk. The clock terminals of the second to fourth D flip-flops D2 to D4 are connected to the inverted output terminals qb of the previous stage D flip-flops. The reset terminals of the first to fourth D flip-flops D1 to D4 are interconnected and serve as the controlled terminals of the frequency divider 20, receiving the delay signal in. The output terminals q of the first to fourth D flip-flops D1 to D4 output the divided frequency signal q. <0> q <1> q <2> q <3> Alternatively, the inverting output terminal qb outputs the frequency-divided signal qb respectively. <0> ,qb <1> ,qb <2> ,qb <3> .

[0072] For a detailed implementation of the frequency divider 20 using D flip-flops, please refer to [reference 2]. Figure 5 The input terminals d of the first to fourth D flip-flops D1 to D4 are connected to their own output terminals q. The clock terminal of the first D flip-flop D1 is the input terminal of the frequency divider 20. The clock terminals of the second to fourth D flip-flops D2 to D4 are connected to the output terminals q of the previous stage D flip-flops. The reset terminals of the first to fourth D flip-flops D1 to D4 are interconnected and serve as the controlled terminals of the frequency divider 20, receiving the signal in to be delayed. The output terminals q of the first to fourth D flip-flops D1 to D4 output the divided frequency signal q. <0> q <1> q <2> q <3> Alternatively, the inverting output terminal qb outputs the frequency-divided signal qb respectively. <0> ,qb <1> ,qb <2> ,qb <3> .

[0073] Reference Figure 1 In one embodiment, the single-edge delay circuit further includes a delay selection circuit 30, having an input terminal and an output terminal. The input terminal of the delay selection circuit 30 is connected to the output terminal of the frequency divider 20, and the output terminal of the delay selection circuit 30 is connected to the second controlled terminal of the oscillation circuit 10. The delay selection circuit 30 is used to select from multiple frequency-divided signals q according to the delay requirements. <0> q <1> q <2> , ......, q <n>In the process, one of the channels is selected as the preset frequency division signal q. <m>And output to the oscillation circuit 10.

[0074] For example, the delay selection circuit 30 can be implemented using selection switches in conjunction with a control module. The number of selection switches can be the same as the number of frequency division signals. The input terminals of multiple selection switches are sequentially connected to one frequency division signal. The control module selects the corresponding selection switch to open according to the delay requirements, so as to use the frequency division signal as the preset frequency division signal q. <m>The output is sent to the oscillation circuit 10 to stop the oscillation. With this configuration, the control module only needs to select the appropriate frequency division signal as the preset frequency division signal q based on the actual delay requirement (the longer the required delay time, the larger the period of the frequency division signal). <m>This allows for programmable control over the delay time.

[0075] In contrast, achieving programmable delay time in an RC delay circuit typically involves assigning a selector switch to each resistor and capacitor. The number of selector switches corresponds to the total number of resistors and capacitors. A programmable resistor selection module controls the opening and closing of these switches, thereby controlling the number of resistors and capacitors involved in the delay circuit and adjusting their values ​​to regulate the delay. However, this approach requires a large number of selector switches due to the large number of resistors and capacitors, increasing chip area. Furthermore, the selector switches have a certain on-resistance, which reduces the delay accuracy of the RC delay circuit, as the delay time is adjusted by changing the values ​​of resistors or capacitors (R or C).

[0076] The single-edge delay circuit of this application doubles the period of the maximum-period frequency divider signal by adding one more D flip-flop, thus doubling the delay time and the adjustable range of the delay time. In other words, the single-edge delay circuit of this application only requires adding one D flip-flop and one selection switch to double the adjustable range of the delay time. In contrast, an RC delay circuit requires doubling the number of resistors and capacitors, and consequently, the number of selection switches, to double the delay time. Therefore, the increase in the number of selection switches required to increase the delay time adjustment range in this application is far less than that in the RC delay circuit, which helps reduce the area occupied by the single-edge delay circuit. At the same time, it avoids the problem of reduced delay accuracy caused by the on-resistance of the selection switches in the RC delay circuit.

[0077] Reference Figures 2 to 4 In one embodiment, the oscillation circuit 10 includes a charging circuit 11, a first capacitor C1, a shaping circuit 12, and a discharge circuit 13.

[0078] The charging circuit 11 has the controlled terminal connected to the delay signal in, and the input terminal of the charging circuit 11 is connected to the power supply.

[0079] The first capacitor C1 has its first end connected to the output end of the charging circuit 11, and its second end grounded.

[0080] Shaping circuit 12, the input terminal of which is connected to the first terminal of the first capacitor C1;

[0081] Discharge circuit 13, wherein the first input terminal of discharge circuit 13 is connected to the output terminal of shaping circuit 12, the second input terminal of discharge circuit 13 is connected to delay selection circuit, and the output terminal of discharge circuit 13 is connected to the first capacitor C1. Discharge circuit 13 is used to periodically discharge the energy of the first capacitor C1 according to the shaping signal output by shaping circuit 12, and upon receiving the preset frequency division signal q... <m>Stop working at that time.

[0082] In this embodiment, the implementation of the charging circuit 11 is not limited, as long as it satisfies the requirement of outputting power to the first capacitor C1 and charging it when triggered by the delay signal in. (Refer to...) Figure 2 In some embodiments, the charging circuit 11 includes a first electronic switch M1 and a second electronic switch M2. The controlled terminal of the first electronic switch M1 is interconnected with the controlled terminal of the second electronic switch M2, serving as the controlled terminal of the charging circuit 11. The output terminal of the first electronic switch M1 is interconnected with the output terminal of the second electronic switch M2, serving as the output terminal of the charging circuit 11. The input terminal of the first electronic switch M1 is the input terminal of the charging circuit 11, and the output terminal of the second electronic switch M2 is grounded. The first electronic switch M1 and the second electronic switch M2 can be one or more combinations of transistors, MOSFETs, or IGBTs. The turn-on levels of the first electronic switch M1 and the second electronic switch M2 are opposite. This configuration ensures that when no delay signal in is received, the first electronic switch M1 is off and the second electronic switch M2 is on, thereby discharging the first capacitor C1. This ensures that when the delay signal in is received, the first electronic switch M1 is on and the second electronic switch M2 is off, and the power supply charges the first capacitor C1 starting from the ground voltage. Figure 2 In this context, vdd represents the power supply, and ib represents the charging current.

[0083] The implementation scheme of the shaping circuit 12 is not limited, as long as it can shape the voltage at the first terminal of the first capacitor C1 and output a shaped signal. (Continue referring to...) Figure 2 In some embodiments, the shaping circuit 12 includes a Schmitt trigger (SMT) and multiple inverters (three in this embodiment) connected in series, U21-U23. The input of the Schmitt trigger (SMT) is the input of the shaping circuit 12, and the output of the Schmitt trigger (SMT) is connected to the input of the multiple inverters U21-U23 connected in series. The output of the multiple inverters U21-U23 connected in series is the output of the shaping circuit 12. The multiple inverters U21-U23 connected in series are used to delay the output signal of the Schmitt trigger.

[0084] The implementation scheme of the discharge circuit 13 is not limited, as long as it satisfies the requirement of periodically discharging the first capacitor C1 according to the level change of the shaping signal, so that the first capacitor C1 is repeatedly charged and discharged. (Refer to...) Figure 2 In some embodiments, the discharge circuit 13 includes an AND logic circuit U1 and a first discharge switch M3. The first input terminal of the AND logic circuit U1 is connected to the output terminal of the shaping circuit 12, the second input terminal of the AND logic circuit U1 is connected to the delay selection circuit, and the output terminal of the AND logic circuit U1 is connected to the controlled terminal of the first discharge switch M3. The input terminal of the first discharge switch M3 is connected to the first terminal of the first capacitor C1, and the output terminal of the first discharge switch M3 is grounded. The first discharge switch M3 is activated by a high level and deactivated by a low level. The first discharge switch M3 can be one or a combination of transistors, MOSFETs, or IGBTs.

[0085] To better illustrate the technical principles of this embodiment, the following is provided: Figure 2 The principle of the single-edge delay circuit shown is explained. Figure 2 The circuit shown implements a delay on the rising edge of the signal to be delayed. (Refer to...) Figure 2 In this embodiment, the input terminal of the oscillation circuit 10 is also provided with a first inverter U24. Figure 2 A specific implementation of a frequency divider 20 using D flip-flops, wherein the number of D flip-flops is four, and based on the oscillation circuit of this embodiment, qb is selected. <2> As a preset frequency division signal.

[0086] Reference Figure 3 , Figure 3 for Figure 2 The key node signals of the single-edge delay circuit shown are: where in represents the signal to be delayed, Vcap represents the voltage value of the first capacitor C1, and clk represents the clock signal clk.

[0087] qb <0> ,qb <1> ,qb <2> q1 represents the output waveform of the inverted output terminals of the first to third D flip-flops, and q2 represents the output waveform of the output terminal of the third D flip-flop.

[0088] Reference Figure 2 and 3 Before the rising edge of the delay signal in arrives, the delay signal in is at a low level, the second electronic switch M2 of the charging circuit 11 is turned on, and the first capacitor C1 is discharged. At the same time, the reset terminals of all D flip-flops on the frequency divider 20 are enabled, and the output terminals q0, q1, q2, and q3 of all D flip-flops output a low level, while the inverting output terminals qb0, qb1, qb2, and qb3 output a high level. The delay selection circuit connects qb2 to the second input terminal of the AND logic circuit U1. At this time, since qb2 is at a high level, that is, the second input terminal of the AND logic circuit U1 is continuously at a high level, therefore, the output level of the AND logic circuit U1 is completely determined by the level of its first input terminal.

[0089] When the delay signal in has a rising edge, the first electronic switch M1 of the charging circuit 11 is turned on and the second electronic switch M2 is turned off. The first capacitor C1 is charged until the voltage Vcap of the first capacitor C1 is charged to the upper threshold voltage of the Schmitt trigger smt. The Schmitt trigger smt outputs a low level. After being inverted by the three inverters U21 to U23, it outputs a high level to the first input terminal of the AND logic circuit U1. This causes the AND logic circuit U1 to output a high level to control the first discharge switch M3 to turn on, discharging the first capacitor C1. When the voltage Vcap of the first capacitor C1 is discharged to the lower threshold voltage of the Schmitt trigger smt, the Schmitt trigger smt outputs a high level. After being inverted by the three inverters U21 to U23, it outputs a low level to the first input terminal of the AND logic circuit U1. This causes the AND logic circuit U1 to output a low level to control the first discharge switch M3 to turn off. This forms a feedback loop. Through the continuous opening and closing of the first discharge switch M3, the oscillation circuit 10 starts oscillating and outputs a clock signal clk during the charging and discharging process of the first capacitor.

[0090] Reference Figure 2 and Figure 3 Then, on the frequency divider side, the selected frequency divider signal is qb. <2> Before transitioning to a low level, the second input terminal of the logic circuit U1 is at a high level, and the output level of the logic circuit U1 depends entirely on the output level of the shaping circuit 12 connected to its first input terminal. At this time, the inverted output terminals of the first D flip-flop D1 and the second D flip-flop D2 sequentially output low-level signals until the inverted output terminal qb of the third D flip-flop outputs a low-level preset frequency division signal qb. <2> At this time, the second input terminal of logic circuit U1 is fixed at a low level, so its output terminal can only output a low level. Consequently, the first discharge switch M3 is continuously opened, causing the oscillation circuit 10 to stop oscillating. The signal q output from the output terminal q of the third D flip-flop... <2> This is the signal out1 after the rising edge of the signal to be delayed, with a delay time of T1.

[0091] Reference Figure 4 After the oscillation circuit 10 stops oscillating, it restarts oscillation when the next rising edge of the signal to be delayed, in, arrives, and outputs a clock signal clk. The frequency divider divides the clock signal, and the above action is repeated multiple times, thereby delaying each rising edge of the signal to be delayed, in. Here, th represents the high-level time of the signal to be delayed, in, and tl represents the low-level time of the signal to be delayed, in.

[0092] Reference Figure 5 In one embodiment, the discharge circuit 13 includes an OR logic circuit U3 and a second discharge switch M4. The first input terminal of the OR logic circuit U3 is connected to the output terminal of the shaping circuit 12, the second input terminal of the OR logic circuit U3 is connected to the delay selection circuit, and the output terminal of the OR logic circuit U3 is connected to the controlled terminal of the second discharge switch M4. The input terminal of the second discharge switch M4 is connected to the power supply, and the output terminal of the second discharge switch M4 is connected to the first terminal of the first capacitor C1.

[0093] In this embodiment, the input terminal of the oscillation circuit 10 may also be provided with a buffer U4.

[0094] In this embodiment, the second discharge switch M4 can be one or a combination of the first discharge switch M3, which can be a transistor, a MOSFET, or an IGBT.

[0095] To better illustrate the technical principles of this embodiment, the following is provided: Figure 5 The single-edge delay circuit shown will be explained below. Figure 5 The circuit shown implements a delay on the rising edge of the signal to be delayed. (Refer to...) Figure 5 In this embodiment, the input terminal of the oscillation circuit 10 is also provided with a first buffer U4. Figure 5 The second specific implementation uses D flip-flops to construct the frequency divider 20, and the number of D flip-flops is 4. Based on the oscillation circuit of this embodiment, q is selected. <2> As a preset frequency division signal.

[0096] Reference Figure 6 , Figure 6 for Figure 5 The key node signals of the single-edge delay circuit shown are: in, Vcap, clk, and q. <0> q <1> q <2> This represents the output signal at the output terminals of the first to third D flip-flops, D1 to D3.

[0097] Reference Figure 5 and Figure 6 Before the rising edge of the delay signal in arrives, the delay signal in is at a low level. The first electronic switch M1 of the charging circuit 11 is turned on, the voltage Vcap of the first capacitor C1 is discharged, and at the same time, the reset terminals rb of all D flip-flops on the frequency divider 20 are enabled. The output terminals q0, q1, q2, and q3 of all D flip-flops output a low level, while the inverting output terminals qb0, qb1, qb2, and qb3 output a high level. The delay selection circuit selects to connect q2 to the second input terminal of the OR logic circuit U3. At this time, since q2 is at a low level, that is, the first input terminal of the OR logic circuit U3 is continuously at a low level. Therefore, the output level of the OR logic circuit U3 is determined by the level of its first input terminal.

[0098] When the delay signal in appears with a rising edge, the second electronic switch M2 of the charging circuit 11 is turned on and the first electronic switch M1 is turned off. The first capacitor C1 is charged until the voltage Vcap of the first capacitor C1 is charged to the lower threshold voltage of the Schmitt trigger smt. The Schmitt trigger smt outputs a high level. After being inverted by the three inverters U21 to U23, it outputs a low level to the first input terminal of the OR logic circuit U3. Thus, the OR logic circuit U3 outputs a low level to control the second discharge switch M4 to turn on, discharging the first capacitor C1. When the voltage Vcap of the first capacitor C1 is discharged to the upper threshold voltage of the Schmitt trigger smt, the Schmitt trigger smt outputs a low level. After being inverted by the three inverters U21 to U23, it outputs a high level to the second input terminal of the OR logic circuit. Then, the OR logic circuit U3 outputs a high level to control the second discharge switch M4 to turn off. This cycle is formed, and through the continuous opening and closing of the second discharge switch M4, the oscillation circuit 10 starts oscillating and outputs the clock signal clk during the charging and discharging process of the first capacitor.

[0099] Reference Figure 5 and Figure 6 On the frequency divider 20 side, the q signal selected as the preset frequency division signal... <2> Before transitioning to a high level, either the second input of logic circuit U3 is at a low level, or the output level of logic circuit U3 depends entirely on the output level of shaping circuit 12 connected to its first input. In the frequency divider, the outputs of the first D flip-flop D1 and the second D flip-flop D2 sequentially output high-level signals until the inverted output q of the third D flip-flop. <2> Output a high-level preset frequency division signal q <2> .

[0100] At this time, the second input terminal of the OR logic circuit is fixed at a high level. Regardless of the level connected to the first input terminal of the OR logic circuit, the OR logic circuit U3 can only output a high level, thus keeping the second discharge switch M4 off, causing the oscillation circuit 10 to stop oscillating. The signal q output from the output terminal qb of the third D flip-flop... <2> This is the rising edge delay signal out1 of the signal to be delayed, with a delay time of T1.

[0101] After the oscillation circuit 10 stops oscillating, it resumes oscillation when the next rising edge of the signal in to be delayed arrives, and outputs a clock signal clk. The frequency divider divides the clock signal, and the above actions are repeated multiple times, thereby delaying each rising edge of the signal in to be delayed.

[0102] Reference Figure 2 and Figure 5 In one embodiment, the oscillation circuit 10 further includes:

[0103] The second capacitor C2 has its first terminal connected to the output terminal of any one of the multiple inverters connected in series, and its second terminal grounded.

[0104] The second capacitor C2 can increase the pulse width of the shaping signal, thereby increasing the opening time of the first discharge switch M3 / second discharge switch M4, so that the charge of the first capacitor C1 can be fully discharged in time, that is, ensuring that each charging of the first capacitor starts from the ground level, i.e., zero level, and is charged to the threshold of the Schmitt trigger SMT.

[0105] Reference Figure 7 and Figure 9 In one embodiment, the single-edge delay circuit further includes:

[0106] A delay signal access circuit is provided, wherein the input terminal of the delay signal access circuit is used to input the delay signal in, and the output terminal of the delay signal access circuit is connected to the controlled terminal of the frequency divider 20 and the first controlled terminal of the oscillation circuit 10. The delay signal access circuit is used for:

[0107] The signal in to be delayed is inverted and then output.

[0108] In this embodiment, the circuit for the signal to be delayed can be an inverter or an odd number of inverters.

[0109] Based on the above description, Figure 2 and Figure 5 The circuit shown implements a rising edge delay for the signal to be delayed, in. It is understandable that... Figure 2 or Figure 5 Based on this, the signal to be delayed, in, is inverted and output to the oscillation circuit and frequency divider. The frequency-divided signal output from the non-inverting output terminal of the frequency divider's D flip-flop is selected and output to the oscillation circuit 10. At this time, the output signal from the inverting output terminal of the frequency divider's D flip-flop is the signal out2 after the falling edge of the signal to be delayed, with a delay time of T2.

[0110] Specifically, this embodiment is in Figure 2 and Figure 5 Based on the circuit shown, a second inverter U25 is added to invert the signal in to be delayed and output it to the oscillation circuit and frequency divider.

[0111] Reference Figure 8 , Figure 8 for Figure 7 The key node signals of the single-edge delay circuit shown are: in, in_, in_, and Vcap, where in is the signal to be delayed; qb is the voltage across the first capacitor; and qb is the voltage across the first capacitor. <2> The signal output from the inverting output terminal qb of the third D flip-flop, which is also the preset frequency division signal, q <2> The signal output at the output terminal q of the third D flip-flop, q <2> _n is q <2> The signal after being inverted is the signal out2 after the falling edge of the signal to be delayed.

[0112] Similarly, refer to Figure 10 , Figure 10 for Figure 9 The key node signal of the single-edge delay circuit shown is the output signal qb from the inverting output terminal of the frequency divider. <2> That is, the signal out2 is the signal to be delayed after the falling edge of the signal to be delayed.

[0113] Reference Figure 11 The present invention also proposes a dual-edge delay circuit, comprising:

[0114] The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal.

[0115] The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal.

[0116] The first single-edge delay circuit and the second single-edge delay circuit are connected in series;

[0117] Wherein, the first single-edge delay circuit is the single-edge delay circuit described above; and / or, the second single-edge delay circuit is the single-edge delay circuit described above. That is, the first single-edge delay circuit can be the single-edge delay circuit described above, or the second single-edge delay circuit can be the single-edge delay circuit described above, or both the first and second single-edge delay circuits can be the single-edge delay circuits described above. In other words, one of the first and second single-edge delay circuits is a rising edge delay circuit, and the other is a falling edge delay circuit. In this embodiment, the first single-edge delay circuit 1 is a rising edge delay circuit, and the second single-edge delay circuit 2 is a falling edge delay circuit, as an example. The output key node waveform of the dual-edge delay circuit in this embodiment is referred to... Figure 12 .

[0118] Since this dual-edge delay circuit adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0119] Furthermore, this embodiment can also include an enable circuit that outputs an enable signal. The dual-edge delay circuit only operates when it receives the enable signal. (See reference...) Figure 12 , Figure 12 for Figure 11 The key node signal waveforms of the double-edge delay circuit are shown.

[0120] Where enable represents the enable signal, in represents the delay signal in, Vcap1 represents the voltage of the first capacitor C1 of the first single-edge delay circuit 1, and qb <2> _1 represents the preset frequency division signal q of the first single-edge delay circuit 1. <m>qb2_1 is the output of the first single-edge delay circuit 1, which is the signal out1 after the falling edge delay of the signal in to be delayed. out1b represents the inverted signal out1 after the falling edge delay of the signal in to be delayed (because the second single-edge delay circuit 2 is a combination of an inverter and a rising edge delay circuit), Vcap2 represents the voltage of the first capacitor C1 of the second single-edge delay circuit 2, and qb2_2 represents the delayed signal out output by the second single-edge delay circuit 2.

[0121] The first single-edge delay circuit 1 delays the rising edge of the signal in to be delayed, and then outputs the upper edge delayed signal out1 to the second single-edge delay circuit 2 for the falling edge delay. At this time, the output signal qb2_2 of the second single-edge delay circuit 2 is the double-edge delayed signal out3.

[0122] Reference Figure 13 The present invention also proposes a dual-edge delay circuit, comprising:

[0123] The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal.

[0124] The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal.

[0125] D flip-flop D, the set-to-1 terminal of D flip-flop D is connected to the output terminal of the first single-edge delay circuit, and the set-to-0 terminal of D flip-flop D is connected to the output terminal of the second single-edge delay circuit; the input terminal d and the clock input terminal of D flip-flop D are both connected to the power supply, and the output terminal of D flip-flop D is the output terminal of the double-edge delay circuit; since this double-edge delay circuit adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here.

[0126] Wherein, the first single-edge delay circuit is the single-edge delay circuit described above; and / or, the second single-edge delay circuit is the single-edge delay circuit described above. That is, the first single-edge delay circuit can be the single-edge delay circuit described above, or the second single-edge delay circuit can be the single-edge delay circuit described above, or both the first and second single-edge delay circuits can be the single-edge delay circuits described above. In other words, one of the first and second single-edge delay circuits is a rising edge delay circuit, and the other is a falling edge delay circuit.

[0127] This embodiment uses the first single-edge delay circuit 1 as a rising edge delay circuit and the second single-edge delay circuit 2 as a falling edge delay circuit as an example for illustration. The output key node waveforms of the dual-edge delay circuit in this embodiment are shown in the reference diagram. Figure 14 In this circuit, in represents the signal to be delayed, Vcap1 represents the voltage of the first capacitor C1 of the first single-edge delay circuit 1, out_rd represents the signal out1t after the falling edge delay of the signal to be delayed output by the first single-edge delay circuit 1. sb represents the voltage at the set terminal of the D flip-flop D, Vcap2 represents the voltage of the first capacitor C1 of the second single-edge delay circuit 2, out_fd represents the delayed signal out output by the second single-edge delay circuit 2, and out3 represents the output signal at the output terminal of the D flip-flop D, which is the delayed signal out output by the double-edge delay circuit in this embodiment.

[0128] In this embodiment, the first single-edge delay circuit 1 delays the rising edge of the signal to be delayed, in. The rising edge of the delayed signal out_rd, after passing through an inverter, enables the set-1 input of the D flip-flop D, causing the D flip-flop D to output a high-level signal. The second single-edge delay circuit 2 delays the falling edge of the signal to be delayed, in. The falling edge of the delayed signal out_fd, after passing through an inverter, enables the set-0 input of the D flip-flop D, causing the D flip-flop D to output a low-level signal. Thus, the signal output by the D flip-flop D is the signal out3, which is the result of simultaneously delaying both the rising and falling edges of the signal to be delayed, in.

[0129] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.< / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / m> < / n> < / n-1> < / m> < / n> < / n-1> < / m> < / m>

Claims

1. A single-edge delay circuit for delaying a signal to be delayed, characterized in that, The single-edge delay circuit includes: A frequency divider has a controlled terminal, an input terminal, and an output terminal. When the frequency divider receives the signal to be delayed at its controlled terminal, it divides the clock signal connected to its input terminal and outputs a preset divided signal and a delay signal. An oscillation circuit has a first controlled terminal, a second controlled terminal, and an output terminal. The oscillation circuit is used to output the clock signal to the frequency divider when it receives the delay signal at its first controlled terminal, and to stop outputting the clock signal to the frequency divider when it receives the preset frequency division signal at its second controlled terminal. The frequency divider outputs multiple frequency-divided signals, and the single-edge delay circuit further includes: A delay selection circuit has an input terminal and an output terminal. The input terminal of the delay selection circuit is connected to the output terminal of the frequency divider, and the output terminal of the delay selection circuit is connected to the second controlled terminal of the oscillation circuit. The delay selection circuit is used to select one of the frequency division signals from multiple frequency division signals according to the delay requirement and output it as the preset frequency division signal to the oscillation circuit. The oscillation circuit includes a charging circuit, a first capacitor, a shaping circuit, and a discharge circuit. The charging circuit has the controlled terminal connected to the signal to be delayed, and the input terminal of the charging circuit is connected to the power supply. A first capacitor, the first terminal of which is connected to the output terminal of the charging circuit, and the second terminal of which is grounded; A shaping circuit, wherein the input terminal of the shaping circuit is connected to the first terminal of the first capacitor; The discharge circuit has a first input terminal connected to the output terminal of the shaping circuit, a second input terminal connected to the delay selection circuit, and an output terminal connected to the first capacitor. The discharge circuit is used to periodically discharge the energy of the first capacitor according to the shaping signal output by the shaping circuit, and to stop working when the preset frequency division signal is received. The single-edge delay circuit also includes: A delay signal access circuit is provided, wherein the input terminal of the delay signal access circuit is used to access the delay signal, the output terminal of the delay signal access circuit is connected to the controlled terminal of the frequency divider and the first controlled terminal of the oscillation circuit, and the delay signal access circuit is used to invert the delay signal and output it.

2. The single-edge delay circuit as described in claim 1, characterized in that, The discharge circuit includes an AND logic circuit and a first discharge switch. The first input terminal of the AND logic circuit is connected to the output terminal of the shaping circuit. The second input terminal of the AND logic circuit is connected to the delay selection circuit. The output terminal of the AND logic circuit is connected to the controlled terminal of the first discharge switch. The input terminal of the first discharge switch is connected to the first terminal of the first capacitor. The output terminal of the first discharge switch is grounded.

3. The single-edge delay circuit as described in claim 1, characterized in that, The discharge circuit includes an OR logic circuit and a second discharge switch. The first input terminal of the OR logic circuit is connected to the output terminal of the shaping circuit, the second input terminal of the OR logic circuit is connected to the delay selection circuit, and the output terminal of the OR logic circuit is connected to the controlled terminal of the second discharge switch. The input terminal of the second discharge switch is connected to the power supply, and the output terminal of the second discharge switch is connected to the first terminal of the first capacitor.

4. The single-edge delay circuit as described in claim 1, characterized in that, The charging circuit includes: a first electronic switch and a second electronic switch; The controlled terminal of the first electronic switch is interconnected with the controlled terminal of the second electronic switch to serve as the controlled terminal of the charging circuit. The output terminal of the first electronic switch is interconnected with the output terminal of the second electronic switch to serve as the output terminal of the charging circuit. The input terminal of the first electronic switch is the input terminal of the charging circuit, and the output terminal of the second electronic switch is grounded.

5. The single-edge delay circuit as described in claim 1, characterized in that, The shaping circuit includes a Schmitt trigger and multiple inverters connected in series. The input terminal of the Schmitt trigger is the input terminal of the shaping circuit, and the output terminal of the Schmitt trigger is connected to the input terminal of the plurality of inverters connected in series. The output terminal of the plurality of inverters connected in series is the output terminal of the shaping circuit.

6. A double-edge delay circuit, characterized in that, include: The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal. The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal. The first single-edge delay circuit and the second single-edge delay circuit are connected in series; Wherein, the first single-edge delay circuit is the single-edge delay circuit as described in any one of claims 1-5; And / or, the second single-edge delay circuit is a single-edge delay circuit as described in any one of claims 1-5.

7. A double-edge delay circuit, characterized in that, include: The first single-edge delay circuit has an input terminal and an output terminal. The first single-edge delay circuit is used to delay the rising edge of the signal connected to its input terminal. The second single-edge delay circuit has an input terminal and an output terminal. The second single-edge delay circuit is used to delay the falling edge of the signal connected to its input terminal. The D flip-flop has its set-to-1 terminal connected to the output of the first single-edge delay circuit, and its set-to-0 terminal connected to the output of the second single-edge delay circuit. Both the input terminal d and the clock input terminal of the D flip-flop are connected to the power supply, and the output terminal of the D flip-flop is the output of the double-edge delay circuit. Wherein, the first single-edge delay circuit is the single-edge delay circuit as described in any one of claims 1-5; And / or, the second single-edge delay circuit is a single-edge delay circuit as described in any one of claims 1-5.

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