Host resident translation lookaside buffer validity checking techniques

Abstract

This application relates to host resident translation layer validity check techniques. Disclosed herein are devices and techniques for verifying host generated physical addresses at a memory device during a host resident FTL mode of operation to deter erroneous or potentially malicious access to the memory device, specifically by: receiving, at a memory device, an operation command from a host device including a first signature and a PBA; generating a second signature; comparing the first signature to the second signature; performing an operation when a match result indicates the first signature is the same as the second signature; and not performing the operation using the PBA when the match result indicates the first signature does not match the second signature.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is Chinese invention patent application No. 201980062579.5, entitled "Host Resident Translation Layer Validity Check Technology", filed on September 23, 2019.

[0003] Priority application

[0004] This application claims priority to U.S. Application No. 16 / 140,952, filed on September 25, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0005] This application relates to memory devices, and more specifically, to host resident translation layer validity checking technology. Background Technology

[0006] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, Read-Only Memory (ROM), Electrically Erasable Programmable Memory (EEPROM), Erasable Programmable Memory (EPROM), and Resistive Variable Memory, such as Phase-Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), 3D XPoint... TM Memory, etc.

[0007] Memory cells are typically arranged in matrices or arrays. Multiple matrices or arrays can be combined into a memory device, and multiple devices can be combined to form the storage capacity of a memory system, such as solid-state drives (SSDs) and universal flash memory (UFS). TM ) device, MultiMediaCard (MMC) solid-state storage device, embedded MMC device (eMMC) TM )wait.

[0008] A memory system may include one or more processors or other memory controllers for executing logic functions to operate the memory device or interface with an external system. A memory matrix or array may contain blocks of memory cells organized into several physical pages. The memory system may receive commands from a host associated with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, erase operations to erase data from the memory device, or perform one or more other memory operations.

[0009] Memory is used as a volatile and non-volatile data storage device for a wide variety of electronic applications, including, for example, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players), movie players, and other electronic devices. Memory cells can be arranged in an array, wherein the array is used in the memory device.

[0010] Many electronic devices comprise several main components: a host processor (e.g., a central processing unit (CPU) or other main processor); main memory (e.g., one or more volatile or non-volatile memory devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.); and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, read-only memory (ROM), SSD, MMC or other memory card structures or combinations, or combinations of volatile and non-volatile memory, etc.). In some instances, the electronic device may include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuitry, a baseband processor, or one or more transceiver circuits, etc. Summary of the Invention

[0011] One aspect of this application provides a method for validating a host resident translation layer for a memory device, the method comprising: receiving an operation command from a host device at the memory device, wherein the operation command includes a physical block address (PBA) and a first signature; generating a second signature at the memory device based on the PBA; determining that the first signature and the second signature do not match; and, in response to determining that the first signature and the second signature do not match, not executing the operation command using the PBA.

[0012] Another aspect of this application provides a memory device, the memory device including: a controller configured to perform operations including: receiving an operation command at the memory device from a host device, wherein the operation command includes a physical block address (PBA) and a first signature; generating a second signature at the memory device based on the PBA; determining that the first signature and the second signature do not match; and in response to determining that the first signature and the second signature do not match, not performing the operation command using the PBA.

[0013] Another aspect of this application provides a machine-readable medium storing instructions that, when executed by a memory device, cause the memory device to perform an operation, the operation comprising: receiving an operation command at the memory device from a host device, wherein the operation command includes a physical block address (PBA) and a first signature; generating a second signature at the memory device based on the PBA; determining that the first signature and the second signature do not match; and, in response to determining that the first signature and the second signature do not match, not executing the operation command using the PBA. Attached Figure Description

[0014] In drawings that are not necessarily drawn to scale, similar designations may describe similar components in different views. Similar designations with different letter suffixes may indicate different instances of similar components. The drawings are intended to illustrate, rather than limit, the various embodiments discussed in this document.

[0015] Figure 1 This describes an example system of an environment containing one or more instances of a memory device on which the subject matter of the present invention can be implemented.

[0016] Figure 2 The flowcharts generally illustrate example methods for performing memory operations on a flash memory system using a host-resident FTL.

[0017] Figure 3 This flowchart illustrates a general method for effectively monitoring and updating host mapping table data used for host-resident FTL operations.

[0018] Figure 4 A block diagram illustrating an instance machine on which any one or more of the techniques (e.g., methods) discussed in this article can be executed. Detailed Implementation

[0019] For example, flash memory-based storage devices such as NAND flash memory can use a flash translation layer (FTL) to translate the logical address of an I / O request (often called a logical block address (LBA)) into a corresponding flash memory address (sometimes called a physical address or physical block address (PBA)) stored in one or more FTL mapping tables. The LBA can be a logical address used by the host to manage data, and the PBA can be a physical address used by the flash memory to manage data storage and retrieval. Mobile storage devices typically have a size-constrained cache and therefore often lack the memory to store the entire mapping table. Therefore, only portions of the mapping table can be retrieved from flash memory on demand, which can lead to degraded random access performance.

[0020] To improve random access performance, the techniques described herein utilize host-resident memory, in addition to memory cells coupled to the host memory device, as a cache for the FTL mapping table. With a host-resident FTL, reading FTL data from host memory is faster than reading FTL data from flash memory, and the host can initiate a memory operation by retrieving the physical block address (PA) of the flash memory and including the PBA in a memory request to the flash memory. The PBA can be retrieved by the host using the host's FTL memory cache and the host's LBA. Upon receiving a memory request, the flash memory system can immediately retrieve the data associated with the PBA without the latency associated with accessing the flash memory-based mapping table and obtaining the PBA using the LBA.

[0021] In some implementations of host-resident FTL, the improvement in random read workload performance can be significant. However, the inventors have identified techniques for host-resident FTL that can help verify the integrity of host memory requests. A direct implementation of host-resident FTL can assume that the mapping table remains accurate between host-initiated operations. However, memory systems or memory devices connected to the host typically perform housekeeping operations, such as garbage collection and wear leveling, between host-initiated operations or during host idle periods. Housekeeping operations move data around the mapping table resident at the memory device and often correct and update said mapping table. Without some validity checks, a direct implementation of host-resident FTL, such as the memory system blindly using a host-provided PBA to access flash data, can often result in the memory system accessing flash memory at incorrect or unexpected PBAs.

[0022] Figure 1The description includes an example of an environment 100 containing a host 105 and a memory device 110 configured to communicate via a communication interface. The host 105 or memory device 110 may be included in a variety of products 150, such as IoT devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, mobile phones, drones, etc.) used to support the processing, communication, or control of the product 150.

[0023] Memory device 110 includes a memory controller 115 or controller circuitry and a memory array 120, comprising, for example, one or more individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked in multiple layers and coupled to form physical pages, thereby increasing the storage density of memory devices (e.g., storage devices) within a given occupied area (i.e., external dimensions). In one example, memory device 110 may be a discrete memory device.

[0024] One or more communication interfaces 111 can be used to transfer data between the memory device 110 and one or more other components of the host 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect High Speed ​​(PCIe) interface, a Universal Serial Bus (USB) interface, a UFS interface, or an eMMC interface. TM An interface, or one or more other connectors or interfaces. Host device 105 may include a host system, electronic devices, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some instances, host 105 may be a device with reference to... Figure 4 Machine 400 is a part or all of the components discussed in the machine. Data can be transferred between memory device 110 and other components via an input / output (I / O) bus, which may include one or more latches for temporarily storing data during data transfer (e.g., before reading from or writing to the memory array).

[0025] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to transfer data to one or more memory cells, planes, subblocks, areas, or pages of the memory array (e.g., write or erase) or to transfer data from the foregoing (e.g., read). The memory controller 115 may, in particular, include circuitry or firmware, comprising one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuits, control circuitry, or components configured to control access on the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more I / O circuitry (and corresponding latches), caches, lines, or interfaces for transferring data to or from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0026] The array controller 135 may in particular include circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing data from one or more memory cells of the memory device 110 coupled to the memory controller 115. These memory operations may be based on, for example, host commands received from host 105, or generated internally by the memory manager 125 (e.g., in conjunction with wear leveling, error detection, or correction).

[0027] Array controller 135 may include an error correction code (ECC) component 140, which may in particular include an ECC engine or other circuitry configured to detect or correct errors associated with writing or reading data from one or more memory cells of memory device 110 coupled to memory controller 115. ECC component 140 may, for example, detect or calculate the bit error rate (BER) associated with performing multiple memory operations. BER may correspond to bit errors occurring in latches of the I / O bus, internal errors of memory controller 115, errors occurring in one or more of the NAND array, or errors occurring in any one or more of the multi-level cells (MLCs) of memory device 110. The memory controller 115 can be configured to effectively detect and recover from errors associated with various operations or data storage (e.g., bit errors, operational errors, crash conditions, barriers, hang-ups, etc.), while maintaining the integrity of data transferred between the host 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., decommission) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors. The array controller 135 can transmit detected BER information to the memory manager 125 for storage and tracking. The memory controller 115 may contain a command queue (not shown) that tracks memory commands received from the host. Commands in the queue can be executed by the memory controller 115 in a first-in-first-out (FIFO) manner, stacked, out of order, according to priority, or in any other suitable order.

[0028] The described memory device 110 includes a signature circuitry system 160 associated with a memory array 120. In some embodiments, a memory controller 115 of the memory device 110 may include a control circuitry system configured to implement the functions of the signature circuitry system 160. In other embodiments, the signature circuitry system 160 may include a separate control circuitry system for implementing the described functionality. In still other embodiments, the control circuitry system may be partitioned between the signature circuitry system 160 and the memory controller 115 to implement the described functions of the signature circuitry system 160. In the depicted example, an array controller 135 forms part of the memory controller 115, and the signature circuitry system 160 forms part of the array controller. In other embodiments, the signature circuitry system 160 may be external to and / or outside the array controller 135. For example, the signature circuitry system 160 (or any individual component thereof) may be a separate component coupled to one or more components in the environment 100. However, the additional functionality of the signature circuitry system 160 is physically located to verify the PBA provided by the host 105 to prevent erroneous or malicious access to the memory device.

[0029] The memory manager 125 may include, in particular, circuitry or firmware, such as several components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection (e.g., BER monitoring) or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host) into device commands (e.g., commands associated with the operation of the memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to implement various memory management functions).

[0030] Memory manager 125 may include a collection of management tables 130 configured to maintain various information associated with one or more components of memory device 110 (e.g., various information associated with a memory array coupled to memory controller 115 or one or more memory cells and may include FTL tables). For example, management table 130 may contain information about FTL mappings of one or more memory cell blocks coupled to memory controller 115, block age, block erase counts, error history, error parameter information, host reset timeout values, memory operation command delays, or one or more error counts (e.g., write operation error counts, read bit error counts, read operation error counts, erase error counts, etc.). In some instances, a bit error may be termed an uncorrectable bit error if the number of errors detected for one or more of the error counts (e.g., error parameters) exceeds a threshold (e.g., an allowable error threshold). Management table 130 may, in particular, maintain counts of correctable or uncorrectable bit errors.

[0031] Memory array 120 may contain multiple memory cells arranged, for example, in devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (each cell storing two data bits (i.e., 4 programmable states)) may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but requires half the write time and twice the program / erase (P / E) cycles compared to the corresponding TLC memory device. Other examples may contain other numbers or arrangements. In some examples, the memory device or portions thereof may operate selectively in SLC mode or in a desired MLC mode (such as TLC, QLC, etc.).

[0032] In operation, data is typically written to or read from memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as needed. The data transfer size of memory device 110 is typically referred to as a page, while the data transfer size of the host device is typically referred to as a sector.

[0033] Different types of memory cells or memory arrays 120 may offer different page sizes, or may require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which may result in the need for different amounts of metadata to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data compared to a memory device with a lower bit error rate). As an example, an MLC NAND flash device may have a higher bit error rate than its corresponding Single-Level Cell (SLC) NAND flash device. Therefore, an MLC device may require more bytes of metadata for erroneous data than its corresponding SLC device.

[0034] Figure 2 This flowchart illustrates an example method 200 for performing memory operations at a flash memory system using aspects of a host-resident FTL. In some instances, the method may assist in verifying that a PBA received from the host corresponds to an LBA provided by the host. Without some form of verification, a malicious host may provide an LBA and an irrelevant PBA, which could result in access to flash memory data that is not intended to be accessible by the host or used by the host in a specific host memory request received at the memory system. At 201, the memory system may receive a host memory request containing a PBA and a signature during host-resident FTL operation. At 203, the memory controller may generate a second signature. At 205, the memory controller may compare a first signature with the second signature to provide a matching result. At 207, if the matching result indicates that the first signature matches the second signature, the memory controller may use the PBA received from the host to execute the memory request. At 209, when the matching result indicates that the first signature does not match the second signature, the memory does not use the first signature to execute the memory request.

[0035] In some instances, a memory request received from the host may contain an LBA. It is assumed that LBAs are mapped to PBAs. In some instances, the memory controller may contain a second mapping table that contains or indicates LBAs that the memory controller can associate with the received memory request, and can determine whether the received LBA is a valid LBA for the received memory request. If an LBA is not indicated as valid for the memory request or is not allocated, the memory controller does not proceed to further process the memory request. In some instances, the memory controller may contain a table or record indicating PBAs that are accessible by the memory request, and can determine whether the received PBA is a valid PBA for the received memory request. If a PBA is not indicated as valid for access by the memory request, the memory controller does not proceed to further process the memory request.

[0036] In some instances, the signature provided by the host in a memory request can be generated by the memory device using the same method used to generate a second signature. When mapping table information is provided from the memory device to the host for use during host-resident FTL operation mode, the memory device can generate and provide a signature for each PBA. When a memory request is received during host-resident FTL operation mode, generating and matching a second signature based on the PBA received from the host ensures that the PBA has not been unintentionally or intentionally altered.

[0037] Figure 3 The flowchart illustrates an example of a method for generating each signature. At 301, the hash circuit may receive a PBA and a token from a record of a mapping table. The record may contain an associated LBA, such that the record includes a mapping from a host LBA to a memory device PBA. The token may be a value or a sequence of values. The token may be a secret token assigned to or generated by the memory device. At 303, the hash circuit may generate a hash using one of several hash algorithms or routines. Such algorithms may include, but are not limited to, keyless cryptographic hash functions, such as Blake, ECOH, FSB, GOST, HAS-160, HAVAL, JH, one of the Message-Digest (MDn) family of functions, one of the Secure Hash Algorithm (SAH-n) family of functions, etc. In some instances, the hash circuit may receive a pad, a pad value, or a sequence of pads. In some instances, the pad may provide an indication of how the cryptographic hash function terminates. At 305, the signature may be a subset of the hash and may be extracted from the hash. In some instances, LBAs can be used as pointers to extract signatures from hashes. For example, if a hash circuit produces a 256-bit hash and the signature is 32 bits, an LBA can be used to determine from which bit position in the hash that the 32-bit signature can be extracted. In some instances, hash circuit systems may include pointer functions that use LBAs as parameters to specify the bit positions to be used to extract the signature from the hash. In some instances, LBAs can be used to identify the starting point for the sequence number of bits or bytes used to extract the signature. In some situations, memory device manufacturers or users may attempt to keep pointer functions secret to deter attempts to compromise the memory device or a system containing the memory device.

[0038] Figure 4This diagram illustrates an instance machine 400 on which any one or more of the techniques (e.g., methods) discussed herein can be executed. In alternative embodiments, machine 400 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 400 may operate as a server or client in a server-client network environment. In one instance, machine 400 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 400 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, IoT device, automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as encompassing any collection of machines, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations, that individually or jointly execute one or more sets of instructions to perform any one or more of the methodologies discussed herein.

[0039] As described herein, an instance may comprise, or be operable through, logic, components, devices, packages, or mechanisms. A circuit system is an assembly (e.g., a collection) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members can be flexible over time and with changes in the underlying hardware. A circuit contains components that can perform a specific task individually or in combination when operating. In an instance, the hardware of a circuit system can be designed immutably to perform a specific operation (e.g., hardwired). In an instance, the hardware of a circuit may contain physically connected components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., invariant magnetism of concentrated particles, electrically movable placement, etc.) to encode instructions for a specific operation. When connecting physical components, the fundamental electrical properties of the hardware components are altered, for example, from an insulator to a conductor, or vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to create portions of the circuit system components in the hardware via variable connections to perform a specific task when operating. Therefore, when the device is operational, the computer-readable medium is communicatively coupled to other components of the circuit system. In one example, any one of the physical components can be used in more than one part of more than one circuit. For example, under operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused by a second circuit of the first circuit system, or reused at a different time by a third circuit of the second circuit system.

[0040] Machine (e.g., computer system) 400 (e.g., host 105, memory device 110, etc.) may include processing device 402 (e.g., hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core or any combination thereof, such as memory controller of memory device 110, etc.), main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage system 418, some or all of which may communicate with each other via an interlink (e.g., bus) 430.

[0041] Processing device 402 may represent one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 may be configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communication via network 420.

[0042] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) storing one or more sets of instructions 426 or software embodying any or more of the methods or functions described herein. Instructions 426 may also reside wholly or at least partially in main memory 404 or processing device 402 during execution by computer system 400, both of which constitute machine-readable storage medium. Machine-readable storage medium 424, data storage system 418, or main memory 404 may correspond to... Figure 1 The memory device 110.

[0043] In one implementation, instruction 426 includes instructions for implementing the above-mentioned... Figure 2 or Figure 3The functional instructions for one or more host-resident FTL operations discussed. Although machine-readable storage medium 424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media. In one example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles having invariant (e.g., rest) mass. Thus, a centralized machine-readable medium is a non-transitory propagating signal. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0044] Machine 400 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In one example, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. Machine signal generating devices (e.g., speakers), or one or more sensors, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors. Machine 400 may include an output controller, such as serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.)) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0045] Instructions 426 (e.g., software, programs, operating systems (OS), etc.) or other data stored on data storage device 418 may be accessed by main memory 404 for use by processing device 402. Main memory 404 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage device than data storage device 418 (e.g., SSD) which is suitable for long-term storage (including when in a “shutdown” condition). Instructions 426 or data for use by the user or machine 400 are typically loaded into main memory 404 for use by processing device 402. When main memory 404 is full, virtual space from data storage device 418 may be allocated to supplement main memory 404; however, because data storage device 418 is typically slower than main memory 404, and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience due to storage device latency (compared to main memory 404, e.g., DRAM). Additionally, the use of data storage device 418 for virtual memory can significantly reduce the available lifespan of data storage device 418.

[0046] Compared to virtual memory, virtual memory compression (e.g., Linux) TM The kernel feature “ZRAM” uses a portion of memory as a compressed block storage device to avoid paging of data storage device 418. Paging may only occur in the compressed block when it is necessary to write such data to data storage device 418. Virtual memory compression increases the available size of main memory 404 while reducing wear and tear on data storage device 418.

[0047] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., microSD cards). TM (e.g., card, etc.). An MMC device contains several parallel interfaces (e.g., 8-bit parallel interfaces) with a host (e.g., a host device) and is typically a component that can be removed from and is decoupled from the host. In contrast, eMMC... TM The device, attached to the circuit board and treated as a host component, boasts read speeds comparable to those based on Serial ATA. TM SSD devices (Serial Advanced Technology (AT) attached, or SATA) are examples of this. However, the demand for mobile device performance continues to increase in order to fully enable virtual or augmented reality devices, take advantage of increased network speeds, and so on. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices, which include the controller and firmware, communicate with the host using a low-voltage differential signaling (LVDS) serial interface with a dedicated read / write path, further advancing read / write speeds.

[0048] The system can further utilize any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive commands 424 on network 420 via network interface device 408 using a transmission medium. Example communication networks can include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards, referred to as… The IEEE 802.16 series of standards are called This includes standards such as IEEE 802.15.4 series and point-to-point (P2P) networks. In one example, network interface device 408 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to communication network 420. In one example, network interface device 408 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmitting medium" should be considered to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 400, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0049] Additional notes and examples

[0050] Example 1 is a method comprising: receiving an operation command from a host device at a memory device, wherein the command includes a logical block address (LBA), a physical block address (PBA), and a first signature; generating a second signature at the memory device; comparing the first signature with the second signature to provide a matching result; performing an operation when the matching result indicates that the first signature and the second signature are the same; and performing the operation without using the PBA when the matching result indicates that the first signature does not match the second signature.

[0051] In Example 2, the object described in Example 1 includes determining that the logical block address is allocated for an operation associated with the operation command.

[0052] In Example 3, the object according to any one of Examples 1 to 2 includes determining that the LBA is not assigned to an operation associated with the operation command and that the operation is not performed.

[0053] In Example 4, the subject matter according to any one of Examples 1 to 3, wherein the memory device is a flash memory device.

[0054] In Example 5, the subject matter according to any one of Examples 1 to 4, wherein the memory device is a NAND memory device.

[0055] In Example 6, the subject matter according to any one of Examples 1 to 5 includes the first signature generated at the memory device.

[0056] In Example 7, the object according to Example 6 includes sending logical block address mapping information from the memory device to the host device, wherein the logical block address mapping information includes the first signature.

[0057] In Example 8, the subject matter according to any one of Examples 6 to 7, wherein generating the first signature comprises: receiving the PBA and a token associated with the memory device at a hash circuit; and generating a first hash using the PBA, the token, and the hash circuit.

[0058] In Example 9, according to the subject matter described in Example 8, generating the first signature includes receiving a cryptographic value at the hash circuit and generating the first hash using the cryptographic value.

[0059] In Example 10, the subject matter according to any one of Examples 8 to 9 includes extracting a first subset of the first hash to provide the first signature, wherein the extraction of the first subset begins at a position within the first hash where the extraction of the first subset begins with a first number of consecutive bytes of the first hash, the position being determined using a logical block address mapped to the PBA.

[0060] In Example 11, according to the subject matter described in Example 10, generating the second signature includes: receiving the PBA and the token associated with the memory device at the hash circuit; and generating the second hash.

[0061] In Example 12, according to the subject matter described in Example 11, generating the first signature includes receiving a cryptographic value at the hash circuit and using the cryptographic value to generate the second hash.

[0062] In Example 13, the subject matter according to any one of Examples 11 to 12 includes extracting a second subset of the second hash to provide the second signature, wherein the extraction of the second subset begins at a position within the second hash where the first number of consecutive bytes of the second hash are extracted, the position being determined using the logical block address received from the host device.

[0063] Example 14 is a memory device comprising: a cache configured to maintain a portion of a mapping table of the memory device; a flash memory configured to store and retrieve user data of a host device and to store the mapping table of the memory device; and a controller circuitry configured to: receive a command at the memory device from a host device to perform a memory operation, wherein the command includes a logical block address (LBA), a physical block address (PBA), and a first signature; generate a second signature at a hash circuitry of the controller; compare the first signature with the second signature to provide a matching result; perform the memory operation using the PBA when the matching result indicates that the first signature and the second signature are the same; and not perform the memory operation using the PBA when the matching result indicates that the first signature does not match the second signature.

[0064] In Example 15, the subject matter is as described in Example 14, wherein the controller is configured to generate the first signature.

[0065] In Example 16, according to the subject matter of Example 15, wherein the controller is configured to send logical block address mapping information from the memory device to the host device, wherein the logical block address mapping information includes the first signature.

[0066] In Example 17, according to any one of Examples 15 to 16, the controller is configured to map the LBA to the PBA of the flash memory to execute the hashing routine of the hashing circuit system to generate a first hash based on the PBA and the token of the memory device.

[0067] In Example 18, according to the subject matter of Example 17, wherein the controller is configured to receive a sequence of keybooks and execute the hashing routine of the hashing circuit system to generate the first hash based on the PBA, the token, and the sequence of keybooks.

[0068] In Example 19, the subject matter according to any one of Examples 17 to 18, wherein the controller is configured to extract a first subset of the first hash to provide the first signature.

[0069] In Example 20, according to the object described in Example 19, wherein the controller is configured to generate a pointer to a location within the hash where the extraction of the first subset begins, wherein the pointer is derived from the LBA.

[0070] In Example 21, according to any one of Examples 17 to 20, the controller is configured to: receive the PBA received from the host; execute the hash routine of the hash circuit system to generate a second hash based on the PBA and the token of the memory device; and extract a second subset of the second hash to provide the second signature.

[0071] Example 22 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any of Examples 1 to 21.

[0072] Example 23 is an apparatus that includes components for implementing any of Examples 1 to 21.

[0073] Example 24 is a system that implements any of Examples 1 to 21.

[0074] Example 25 is a method for implementing any of Examples 1 through 21.

[0075] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. Furthermore, the inventors also contemplate examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0076] In this document, as is common in patent documents, the term “a” is used to include one or more, regardless of any other examples or uses of “at least one” or “one or more.” In this document, the term “or” is used to refer to a non-exclusive “or,” such that “A or B” may include “A but not B,” “B but not A,” and “A and B” unless otherwise indicated. In the appended claims, the terms “comprising” and “in which” are used as common equivalents to the corresponding terms “including” and “wherein.” Similarly, in the appended claims, the terms “comprising” and “including” are open-ended. Systems, apparatuses, articles, or processes that include elements in addition to those listed after such terms in the claims are still considered to be within the scope of the claims. Furthermore, in the appended claims, the terms “first,” “second,” and “third,” etc., are used merely as illustrative marks and are not intended to impose numerical requirements on their objects.

[0077] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as (but not limited to) a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, including processors or groups of multi-core devices.

[0078] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. An operation that places a memory cell in a given state is referred to herein as “programming” and may include both writing to and erasing from a memory cell (e.g., a memory cell may be programmed into an erased state).

[0079] According to one or more embodiments of the present disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, transfer, adapt, derive, limit, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count the operations of the memory device when the operation of the memory device occurs, track the memory device operation that started it, evaluate the memory device characteristics corresponding to the wear state, etc.).

[0080] According to one or more embodiments of this disclosure, a memory access device may be configured to provide wear cycle information to the memory device with respect to each memory operation. Memory device control circuitry (e.g., control logic) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0081] The methods described herein can be implemented, at least in part, by a machine, apparatus, or computer. Some examples may include computer-readable media, apparatus-readable media, or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to: hard disks, removable disks, removable optical discs (e.g., compressed optical discs and digital video optical discs), magnetic tape cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, etc.

[0082] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. The abstract is submitted under the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be construed as expecting that unclaimed disclosed features are necessary for any claim. In fact, the subject matter of the invention may lie in fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and these embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents thereof.

[0083] Translation of attached images

[0084] Figure 1

[0085] 115 Memory Controller

[0086] 125 Management

[0087] 130 Flash Transition Layer Table

[0088] CONTROL

[0089] ECC Error Correction Code

[0090] 160 Signature Circuit

[0091] 3D NAND

[0092] 105 host

[0093] Figure 2

[0094] 201 Receive host memory request containing physical block address and signature during host resident flash transition layer operation mode

[0095] 203 Generate a second signature

[0096] 205. Compare the first signature with the second signature to provide a matching result.

[0097] MATCH

[0098] 207 Execute memory request

[0099] NO MATCH (Not Matching)

[0100] 209 Memory request not executed

[0101] Figure 3

[0102] 301 Receives the physical block address and token at the hash circuit.

[0103] 303 Hash generated based on physical block address and token

[0104] 305 Use a portion of the hash of the logical block address associated with the physical block address as the signature.

[0105] Figure 4

[0106] 402 processing device

[0107] 426 Instruction

[0108] 404 Main Memory

[0109] 426 Instruction

[0110] 408 Network Interface Device

[0111] 420 Network

[0112] 430 bus

[0113] 406 Static Memory

[0114] 418 Data storage device

[0115] 424 Machine-readable media

[0116] 426 Instruction

Claims

1. A method for validating the host resident translation layer of a memory device, the method comprising: At the memory device, an operation command is received from the host device, wherein the operation command includes a physical block address (PBA) and a first signature; The PBA and the token of the memory device are used as inputs to the hash function at the memory device to generate a hash; A subset of the hash is extracted to provide a second signature, the subset being extracted using a function of the logical block address (LBA) in the operation command received from the host device; It is determined that the first signature and the second signature do not match; and In response to determining that the first signature and the second signature do not match, the operation command is not executed using the PBA.

2. The method of claim 1, further comprising generating the token.

3. The method according to claim 1, further comprising: A second operation command is received from the host device at the memory device, wherein the second operation command includes a second physical block address (PBA) and a third signature; The second hash is generated at the memory device using the second PBA and the token as inputs to the hash function; A second subset of the second hash is extracted to provide a fourth signature, the second subset being extracted using a function of the second logical block address (LBA) in the second operation command received from the host device; It is determined that the third signature matches the fourth signature; as well as In response to determining that the third signature matches the fourth signature, the operation is performed using the second PBA.

4. The method of claim 1, further comprising: A portion of a flash translation table, including the PBA, is provided to the host device.

5. The method of claim 4, wherein the portion of the flash translation table includes the first signature corresponding to the PBA.

6. A memory device comprising: A controller configured to perform operations including: At the memory device, an operation command is received from the host device, wherein the operation command includes a physical block address (PBA) and a first signature; The PBA and the token of the memory device are used as inputs to the hash function at the memory device to generate a hash; A subset of the hash is extracted to provide a second signature, the subset being extracted using a function of the logical block address (LBA) in the operation command received from the host device; It is determined that the first signature and the second signature do not match; and In response to determining that the first signature and the second signature do not match, the operation command is not executed using the PBA.

7. The memory device of claim 6, wherein the operation further includes generating the token.

8. The memory device of claim 6, wherein the operation further comprises: A second operation command is received from the host device at the memory device, wherein the second operation command includes a second physical block address (PBA) and a third signature; The second hash is generated at the memory device using the second PBA and the token as inputs to the hash function; A second subset of the second hash is extracted to provide a fourth signature, the second subset being extracted using a function of the second logical block address (LBA) in the second operation command received from the host device; It is determined that the third signature matches the fourth signature; as well as In response to determining that the third signature matches the fourth signature, the operation is performed using the second PBA.

9. The memory device of claim 6, wherein the operation further comprises: A portion of a flash translation table, including the PBA, is provided to the host device.

10. The memory device of claim 9, wherein the portion of the flash memory translation table includes the first signature corresponding to the PBA.

11. A machine-readable medium storing instructions that, when executed by a controller of a memory device, cause the controller to perform an operation, the operation comprising: At the memory device, an operation command is received from the host device, wherein the operation command includes a physical block address (PBA) and a first signature; The PBA and the token of the memory device are used as inputs to the hash function at the memory device to generate a hash; A subset of the hash is extracted to provide a second signature, the subset being extracted using a function of the logical block address (LBA) in the operation command received from the host device; It is determined that the first signature and the second signature do not match; and In response to determining that the first signature and the second signature do not match, the operation command is not executed using the PBA.

12. The machine-readable medium of claim 11, wherein the operation further comprises generating the token.

13. The machine-readable medium of claim 11, wherein the operation further comprises: A second operation command is received from the host device at the memory device, wherein the second operation command includes a second physical block address (PBA) and a third signature; The second hash is generated at the memory device using the second PBA and the token as inputs to the hash function; A second subset of the second hash is extracted to provide a fourth signature, the second subset being extracted using a function of the second logical block address (LBA) in the second operation command received from the host device; It is determined that the third signature matches the fourth signature; as well as In response to determining that the third signature matches the fourth signature, the operation is performed using the second PBA.

14. The machine-readable medium of claim 11, wherein the operation further comprises: A portion of a flash translation table, including the PBA, is provided to the host device.

15. The machine-readable medium of claim 14, wherein the portion of the flash translation table includes the first signature corresponding to the PBA.

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