A computing chip, an electronic device, and a data transmission method between computing chips

Abstract

The present application relates to a computing chip, an electronic device, and a data transmission method between computing chips, and belongs to the field of data transmission technology. The computing chip includes: a data operation unit and a remote data acquisition unit. The data operation unit is used to generate a command information packet and store it in a local memory; the remote data acquisition unit is used to package the command information packet in the local memory that accesses the same target computing chip to form a remote command packet, and send the remote command packet to the target computing chip; and is also used to receive the remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet to the local memory. In the present application, the data operation unit does not directly access the memory of other computing chips, but uses an asynchronous method to access the memory of other computing chips, so that large data storage is not required, thereby reducing the area of ​​the chip; avoiding a small transmission length and improving bus efficiency.

Description

Technical Field

[0001] The present application belongs to the technical field of data transmission, and specifically relates to a computing chip, an electronic device, and a data transmission method between computing chips. Background Art

[0002] Currently, high-speed data exchange between computing chips uses peer-to-peer (P2P) technology, which enables computing chips to directly access the memory of the target computing chip through a PCI Express (PCIe) switch. That is, the data operation unit inside the computing chip can directly access the memory of other computing chips through the PCIe switch, avoiding the use of the host-side memory as a transit point, greatly reducing the delay in data exchange.

[0003] The existing P2P access method also poses a challenge to the data operation unit inside the computing chip. Due to the large transmission delay of PCIe, the data operation unit inside the computing chip needs to use a large data buffer to hide the access data delay between computing chips, otherwise there will be transmission gaps, which leads to the excessive size of the computing chip. For the PCIe bus, the larger the data transmission capacity, the higher the transmission efficiency. This is often inconsistent with the transmission characteristics of the data operation unit of the computing chip. The data operation unit may have a large number of discontinuous addresses for random access, and the direct transmission method through PCIe will also reduce the transmission efficiency. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a computing chip, an electronic device and a data transmission method between computing chips, so as to improve the problem that existing computing chips need to use large data buffers to hide the access data delay between computing chips, resulting in the problem that the area of ​​the computing chip is too large.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a computing chip, which is connected to a local memory, and includes: a data operation unit and a remote data acquisition unit. The data operation unit is used to generate a command information packet and store it in the local memory; the remote data acquisition unit is used to package the command information packets in the local memory that access the same target computing chip to form a remote command packet, and send the remote command packet to the target computing chip; and is also used to receive a remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet in the local memory. In the embodiment of the present application, by adding a remote data acquisition unit inside the computing chip, the data operation unit in the computing chip does not directly access the memory of other computing chips, but accesses the memory of other computing chips in an asynchronous manner with the help of the remote data acquisition unit. Specifically, the data operation unit does not access the memory of other computing chips in real time, but first saves the command information packet for accessing other computing chips in the local memory, and then the remote data acquisition unit packages and sends it to other computing chips for memory access request, avoiding all data operation units directly accessing the interface (such as PCIe interface), thereby saving the internal connection of the chip. At the same time, since all data operation units do not directly access the interface, it will not cause congestion of the access interface, thereby avoiding the data operation unit from needing a large data cache to hide the access data delay between computing chips, saving the storage area of ​​the chip.

[0007] In combination with a possible implementation of the first aspect of the embodiment, when the remote data acquisition unit packages the command information packets accessing the same target computing chip in the local memory to form a remote command packet, it is specifically used to: take out the command information packets from the local memory, wherein each command information packet corresponds to a unique serial number; package the command information packets accessing the same target computing chip and their unique serial numbers as the load information of the remote command packet to obtain the remote command packet. In the embodiment of the present application, by packaging the command information packets accessing the same target computing chip and their unique serial numbers as the load information of the remote command packet, and using the designated information as the header information of the remote command packet, while ensuring that the data can be transmitted normally, the other end can accurately distinguish which command information packet's memory access data is when acquiring the data, to avoid confusion.

[0008] In combination with a possible implementation of the first aspect embodiment, when the remote data acquisition unit stores the memory access data in the remote data packet into the local memory, it is specifically used to: obtain the address offset of the local memory corresponding to the unique serial number in the remote data packet, wherein the unique serial number is the unique serial number of the command information packet corresponding to the remote data packet, and different command information packets correspond to different unique serial numbers and address offsets; determine the local memory access address based on the address offset and the preset base address of the local memory; store the memory access data in the remote data packet into the local memory based on the local memory access address. In the embodiment of the present application, different command information packets correspond to different unique serial numbers and address offsets, so that when the memory access data corresponding to the command information packet is received, it is only necessary to obtain the address offset corresponding to the unique serial number of the command information packet, and in combination with the preset base address, the local memory access address of the memory access data in the local memory can be obtained, so that the data of the other end and the data of the local end can be stored in the same memory without confusion, and the number of required memories can be further reduced to reduce the area of ​​the chip.

[0009] In combination with a possible implementation of the first aspect of the embodiment, the remote data acquisition unit is also used to count the remote command packets sent to obtain a first value, and to count the response packets returned by the target computing chip to obtain a second value, and to control the number of remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip for each remote command packet received. In the embodiment of the present application, the remote command packets sent and their corresponding response packets are counted separately, and the number of remote command packets sent is controlled thereby, so that the target computing chip can be prevented from receiving overflow of packets, thereby avoiding deadlock of the link.

[0010] In combination with a possible implementation of the first aspect, the computing chip further includes: a remote data packet generation unit for receiving a remote command packet sent by a source computing chip, and decompressing the received remote command packet to obtain a command information packet therein; and obtaining corresponding memory access data from a local memory based on the command information packet therein, and packaging the corresponding memory access data into a remote data packet and sending it to the source computing chip. In the embodiment of the present application, a remote data packet generation unit is newly added to decompress the remote command packet, and based on the decompressed command information packet, the corresponding memory access data is obtained from the local memory, and then the memory access data is packaged into a remote data packet and sent to the source computing chip, thereby achieving the purpose of indirect access to the memory.

[0011] In combination with a possible implementation method of the first aspect, the packet structure of the remote data packet and the remote command packet is consistent, both including header information and load information, and the header information includes the packet sequence number, load number, packet type, source computing chip sequence number, and target computing chip sequence number. In an embodiment of the present application, the packet sequence number, the number of payloads, the packet type, the source computing chip sequence number, and the target computing chip sequence number are used as header information, so that the packet structures of the remote data packet and the remote command packet can be consistent. For example, both include header information and payload information, and the header information includes the packet sequence number, the number of payloads, the packet type, the source computing chip sequence number, and the target computing chip sequence number, thereby facilitating the computing chip to parse the remote command packet and the remote data packet. At the same time, the remote command packet and the remote data packet can be distinguished only by the packet type in the header information, where the packet comes from can be known according to the source computing chip sequence number, and the packet can be verified based on the target computing chip sequence number (for example, after the target computing chip receives the packet, it is found that the target computing chip sequence number in the packet is inconsistent with the sequence number of its own computing chip, then the packet is an erroneous packet), the load number in the load information can be quickly known based on the load number, and the packet can be quickly traced based on the packet sequence number.

[0012] In combination with a possible implementation method of the first aspect embodiment, data is transmitted between different computing chips through the PCIe protocol, and the remote data packet and the remote command packet include a BAR address, wherein the BAR address in the remote data packet is the address of the remote data acquisition unit in the opposite computing chip, and the BAR address in the remote command packet is the address of the remote data packet generation unit in the opposite computing chip. In the embodiment of the present application, since the data operation unit in the present application does not directly access the memory of other computing chips, but uses the remote data acquisition unit and the remote data packet generation unit to access the memory of other computing chips in an indirect manner, the BAR address carried in the remote command packet does not need to include the storage address of the local memory corresponding to the opposite computing chip, and thus there is no need to map the entire storage space to the BAR, which solves the problem in the prior art that as the storage space of the computing chip becomes larger, the host CPU (Central Processing Unit) may not be able to allocate BAR space for all computing chips.

[0013] In a second aspect, an embodiment of the present application also provides an electronic device, comprising: a PCIe switch; and at least two computing chips, each computing chip being connected to the PCIe switch, and each computing chip being used to: generate a command information packet and store it in a local memory; package the command information packets in the local memory that access the same target computing chip to form a remote command packet, and send the remote command packet to the target computing chip; receive a remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet to the local memory.

[0014] In combination with a possible implementation manner of the second aspect embodiment, each computing chip is also used to: receive a remote command packet sent by a source computing chip, and decompress the received remote command packet to obtain a command information packet therein; obtain corresponding memory access data from a local memory based on the command information packet therein; and package the corresponding memory access data into a remote data packet and send it to the source computing chip.

[0015] In combination with a possible implementation method of the second aspect, each computing chip is also used to count the remote command packets sent to obtain a first value, and to count the response packets returned by the target computing chip to obtain a second value, and to control the number of remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

[0016] In a third aspect, an embodiment of the present application also provides a method for data transmission between computing chips, including: generating a command information packet and storing it in a local memory; packaging the command information packets in the local memory that access the same target computing chip to form a remote command packet, and sending the remote command packet to the target computing chip; receiving a remote data packet returned by the target computing chip based on the remote command packet, and storing the memory access data in the remote data packet in the local memory.

[0017] In combination with a possible implementation manner of the third aspect embodiment, the method also includes: when receiving a remote command packet sent by a source computing chip, decompressing the received remote command packet to obtain a command information packet therein; obtaining corresponding memory access data from a local memory based on the command information packet therein, and packaging the corresponding memory access data into a remote data packet and sending it to the source computing chip.

[0018] In combination with a possible implementation method of the third aspect, the method also includes: counting the remote command packets sent to obtain a first value; counting the response packets returned by the target computing chip to obtain a second value, and controlling the number of remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

[0019] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by implementing the embodiments of the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in the field of technology, other drawings can also be obtained based on these drawings without creative work. As shown in the drawings, the above and other purposes, features and advantages of the present application will be clearer. The same reference numerals indicate the same parts in all the drawings. The drawings are not deliberately scaled to the actual size, and the focus is on showing the main purpose of the present application.

[0021] Figure 1 A schematic diagram of the structure of a computing chip connected to a local memory provided in an embodiment of the present application is shown.

[0022] Figure 2 A schematic diagram of the structure of a command information packet provided in an embodiment of the present application is shown.

[0023] Figure 3 A schematic diagram of the structure of a remote command packet provided in an embodiment of the present application is shown.

[0024] Figure 4 A schematic diagram of the structure of a remote data acquisition unit provided in an embodiment of the present application is shown.

[0025] Figure 5 A schematic structural diagram of a remote data packet generating unit provided in an embodiment of the present application is shown.

[0026] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown.

[0027] Figure 7 A schematic structural diagram of another electronic device provided in an embodiment of the present application is shown.

[0028] Figure 8 A flow chart of a data transmission method between computing chips provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0030] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it is not necessary to further define and explain it in the subsequent drawings. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0031] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0032] In view of the existing P2P (Peer-to-Peer) access method, the data operation unit inside the computing chip needs to use a large data buffer to hide the access data delay between computing chips, which leads to the problem of the computing chip being too large in area. For the PCIe bus, the larger the data transmission capacity, the higher the transmission efficiency. This is often inconsistent with the transmission characteristics of the data operation unit of the computing chip. The data operation unit may have a large number of discontinuous address random accesses, and the method of directly transmitting through PCIe will also reduce the transmission efficiency. The embodiment of the present application provides a computing chip, such as Figure 1 As shown, the computing chip includes: a remote data acquisition unit, a remote data packet generation unit and a plurality of data operation units, wherein the remote data acquisition unit, the remote data packet generation unit and each data operation unit are connected to the local memory through a local memory interface. It should be noted that the remote data acquisition unit and the remote data packet generation unit can also be integrated together into a whole, and the local memory can also be integrated into the computing chip, so it cannot be Figure 1 The exemplary scenarios are to be understood as limitations of the present application.

[0033] In the embodiment of the present application, a remote data acquisition unit and a remote data packet generation unit are newly added inside the computing chip, so that the data operation unit in the computing chip does not directly access the memory of other computing chips, but accesses the memory of other computing chips indirectly and asynchronously with the help of the remote data acquisition unit and the remote data packet generation unit.

[0034] The so-called asynchronous mode means that the data operation unit in the computing chip does not need to access the memory of other computing chips in real time, but first saves the command information packet for accessing other computing chips in the local memory, and then the remote data acquisition unit packages and sends it to other computing chips for memory access request. It avoids all data operation units directly accessing the interface (such as PCIe interface), thereby saving the internal connection of the chip. At the same time, since all data operation units do not directly access the interface, it will not cause access interface congestion, thereby avoiding the need for a large data cache for the data operation unit to hide the access data delay between computing chips, saving the storage area of ​​the chip.

[0035] For a better understanding, the following will be combined Figure 1 The functions of each module of the computing chip are explained.

[0036] The data operation unit is used to generate command information packets and store them in the local memory, and access other computing chips through the command information packets. The data operation unit generates access addresses and access lengths for accessing the memories of other computing chips, and stores these information in the local memory in the format of command information packets. The data operation unit can generate command information packets through programming.

[0037] In one implementation, the structure of the command information packet may be as follows: Figure 2 As shown. It is understandable that Figure 2 The positions of the fields in the command packet shown are interchangeable, so you cannot Figure 2 The positions shown are to be understood as limitations of the application.

[0038] The length of the command information packet can be 64 bits (Bit), and can include four fields. The first field 201 is from bit 0 to bit 3, which is the target computing chip serial number, a total of 4 bits, indicating that 16 computing chips can be accessed. The second field 202 is from bit 4 to bit 6, which is the access length of the target computing chip memory, a total of 3 bits, which can represent 1 to 8 lengths, such as 000 for length 1, 001 for length 2, 010 for length 3, ..., 111 for length 8; the length is generally aligned according to the data bit width, for example, the data bit width is 256 bits, indicating that the size of each memory access is 256 bits * length. The third field 203 is from bit 7 to bit 41, which is the access address of the target computing chip memory, a total of 35 bits. The fourth field 204 is from bit 42 to bit 63, which is the local memory address offset, which is used to calculate the address of the local memory where the data of the target computing chip is stored after it is returned.

[0039] The remote data acquisition unit is used to pack the command information packets accessing the same target computing chip in the local memory into a remote command packet, and send the remote command packet to the target computing chip; and is also used to receive the remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet into the local memory. In one embodiment, when the remote data acquisition unit packs the command information packet into the remote command packet, it can take out the command information packet from the local memory and assign a unique serial number (packet ID) to each command information packet; then, the command information packet accessing the same target computing chip and its unique serial number are packed together as the load information of the remote command packet, and the specified information, such as the source computing chip serial number, the target computing chip serial number and the packet serial number of the remote command packet, the number of loads, the packet type, etc. are used as the header information of the remote command packet, so as to obtain a remote command packet containing the header information and the load information. Among them, each command information corresponds to a unique serial number, and the unique serial number may not be assigned by the remote data acquisition unit, for example, it may be assigned by the data operation unit when generating the command information packet.

[0040] If different computing chips are connected through a PCIe switch, that is, data is transmitted between computing chips through the PCIe protocol, then the computing chip also includes a PCIe interface, and accordingly, the remote command packet also includes a BAR (Base Address Register) address, and the BAR address does not include the storage address of the local memory corresponding to the target computing chip. Since the data operation unit in the embodiment of the present application does not directly access the memory of other computing chips, but uses the remote data acquisition unit and the remote data packet generation unit to access the memory of other computing chips in an indirect manner, the BAR address carried in the remote command packet does not need to include the storage address of the local memory corresponding to the opposite computing chip, and thus there is no need to map the entire storage space to the BAR, which solves the problem in the prior art that as the storage space of the computing chip becomes larger, the host CPU (Central Processing Unit) may not be able to allocate BAR space for all computing chips.

[0041] It should be noted that, with the existing P2P access method, the PCIe switch uses a base address register (BAR) to represent the storage space that each computing chip can access. If you want to access the entire storage space of the computing chip, you need to map the entire storage space to the BAR. The BAR space of the computing chip is uniformly allocated by the host CPU. As the storage space of the computing chip becomes larger, the host CPU may not be able to allocate BAR space for all computing chips, especially for some low-end CPUs.

[0042] If the computing chips transmit data via the PCIe protocol, the BAR address in the remote command packet is the address of the remote data packet generation unit in the target computing chip. In this case, the remote command packet includes the BAR address of the target computing chip, header information, and payload information. Its structure is as follows: Figure 3 In order to efficiently transmit the load information, the header information in this application is encoded into the low bit of the target computing chip of the PCIe address, and the high bit of the PCIe address is the BAR address of the target computing chip.

[0043] In order to facilitate the parsing of remote command packets and remote data packets by the computing chip, a unified packet structure is defined in the present application, that is, the packet structures of the remote command packets and remote data packets are consistent, for example, both include header information, payload information, and the BAR address of the target computing chip. Among them, for the remote command packet, the BAR address is the address of the remote data packet generation unit in the opposite computing chip, and for the remote data packet, the BAR address is the address of the remote data acquisition unit in the opposite computing chip. If the remote data packet generation unit and the remote data acquisition unit are integrated together, then for the remote command packet and the remote data packet, their BAR addresses are the same.

[0044] The header information includes the following specified fields: packet number, payload number, packet type, source computing chip number, and target computing chip number. In addition, it may also include a reserved bit field. For example:

[0045] The first field 301, from bit 0 to bit 4, is reserved to facilitate alignment of the transmission address.

[0046] The second field 302, from bit 5 to bit 8, is the serial number of the target computing chip. This field can be used to help verify whether the packet is correct. For example, if the target computing chip receives a packet and finds that the serial number of the target computing chip in the packet is wrong (that is, the serial number of the target computing chip in the packet is inconsistent with the serial number of its own computing chip), it means that an incorrect packet was received.

[0047] The third field 303, from bit 9 to bit 12, is the serial number of the source computing chip, which is used to indicate which computing chip sent the remote command packet or remote data packet.

[0048] The fourth field 304 from bit 13 to bit 14 is the packet type, which is used to distinguish remote command packets from remote data packets. If the value of the packet type field is 1, it means that the packet type is a remote command packet. If it is 0, it means that the packet is a remote data packet. Of course, it can also be vice versa.

[0049] The fifth field 305, from bit 15 to bit 19, is the number of payloads. The length of the payload varies depending on the packet type. For example, if it is a remote command packet, the content of the payload is the command information packet generated by the data operation unit, and the payload length is 64 bits. If it is a remote data packet, the content of the payload is the memory access data returned by the target computing chip, and the payload length is 256 bits. For a PCIe payload with a maximum length of 256 bytes, the maximum number of command payloads is 32, and the maximum number of data payloads is 8.

[0050] The sixth field 306, from bit 20 to bit 27, is the packet sequence number. In one embodiment, if a remote data packet only includes memory access data corresponding to a command information packet, then the packet sequence number field may be valid only for the data packet type (that is, in this embodiment, the field is empty for the remote command packet), and its value comes from the unique sequence number corresponding to the command information packet when the memory access data corresponding to the command information packet is packaged. In another embodiment, the packet sequence number field may be valid for both the data packet type, and its value may be the packet sequence number assigned to it by the remote data packet generation unit when forming the remote data packet; at the same time, it is also valid for the command packet type, and its value may be the packet sequence number assigned to it by the remote data acquisition unit when forming the remote command packet, or it may be the packet sequence number of the remote command packet, which is convenient for subsequent tracing. In other words, if the packet sequence number field is only valid for the data packet type, the field is empty for the remote command packet. If the packet sequence number field is valid for both the command packet type and the data packet type, the packet sequence number field is not empty, and the packet sequence number of the remote command packet and the packet sequence number of the remote data packet can be the same (to facilitate subsequent tracing) or different.

[0051] It is understandable that the positions of the various fields in the above header information are interchangeable, and therefore the positions of the above examples cannot be understood as limitations to the present application.

[0052] Field 307, from bit 28 to bit 47, is the BAR address of the target computing chip. The BAR address is placed in the high bit of the PCIe address. PCIe transmission is routed through this address, that is, the PCIe switch can find the corresponding target computing chip through this address. Each computing chip only needs to allocate 256 megabytes of BAR space.

[0053] The payload information contains several data with a length of 256 bits. Figure 3 The first data, the second data, the third data...the eighth data, etc. in the load information shown are either a command information packet and its unique serial number, or the memory access data corresponding to the command information packet (the packet serial number at this time is the unique serial number of the command information packet), or the memory access data corresponding to the command information packet and the unique serial number of the command information packet (the packet serial number at this time can be the packet serial number assigned to it when forming the data packet, or it can be the packet serial number of the remote command packet).

[0054] Among them, after receiving the remote command packet sent by the source computing chip (the computing chip that sends the remote command packet), the target computing chip decompresses the remote command packet to obtain the command information packet therein, obtains the corresponding memory access data from the local memory based on the command information packet, and then packs the memory access data into a remote data packet and sends it to the source computing chip.

[0055] When packing the memory access data corresponding to the command information packet to form a remote data packet, only the memory access data corresponding to one command information packet may be packed to form one remote data packet. In this case, one remote data packet only includes the memory access data corresponding to one command information packet. Of course, in order to reduce the number of remote data packets sent, when packing the memory access data to form a remote data packet, the computing chip may pack the memory access data corresponding to the command information packets from the same source computing chip to form a remote data packet. In this case, one remote data packet may include the memory access data corresponding to multiple command information packets.

[0056] In one implementation, the remote data packet may be generated by a remote data packet generation unit in a computing chip. The remote data packet generation unit is used to receive a remote command packet sent by a source computing chip (i.e., a source computing chip that sends a remote data packet), decompress the remote command packet, obtain a command information packet therein, obtain corresponding memory access data from a local memory based on the command information packet therein, package the memory access data corresponding to the command information packet to form a remote data packet, and send it to the source computing chip.

[0057] When the remote data packet generation unit packages the memory access data corresponding to the command information packet, the memory access data corresponding to the command information packet is used as the payload of the remote data packet, and the designated information, such as the source computing chip serial number, the target computing chip serial number, and the packet serial number of the remote data packet, the number of payloads, and the packet type are used as the header information of the remote data packet, thereby obtaining a remote data packet containing the header information and the payload information. If a remote data packet corresponds to a command information packet, the packet serial number of the remote data packet may be the unique serial number of the command information packet. If a remote data packet corresponds to multiple command information packets, the payload portion includes the memory access data corresponding to the multiple command information packets and their respective unique serial numbers, and the packet serial number at this time may be the serial number assigned to the remote data packet during packaging.

[0058] It should be noted that if the computing chips transmit data via the PCIe protocol, the remote data packet also includes a BAR address, which is the address of the remote data acquisition unit in the computing chip at the other end.

[0059] After receiving the remote data packet returned by the target computing chip based on the remote command packet, the remote data acquisition unit is also used to store the memory access data in the remote data packet to the local memory. In one embodiment, the process of storing the memory access data in the remote data packet to the local memory can be: obtaining the address offset of the local memory corresponding to the unique serial number in the remote data packet, obtaining the local memory access address based on the address offset and the preset base address of the local memory, and storing the memory access data in the remote data packet at the local memory access address of the local memory. The unique serial number is the unique serial number of the command information packet corresponding to the memory access data in the remote data packet.

[0060] Among them, when the remote data acquisition unit packs the command information packet, it will save the address offset of the local memory in the command information packet and the corresponding unique serial number of the command information packet. After the target computing chip returns the data, it will find the corresponding address offset based on the unique serial number of the command information packet, and then combine it with the base address of the local memory to obtain the address of the returned data in the local memory, that is, the address of the returned data in the local memory is equal to the local memory base address plus the local memory address offset.

[0061] If a remote data packet corresponds to a command information packet, the unique serial number can be obtained from the packet serial number field of the remote data packet. If a remote data packet corresponds to multiple command information packets, the unique serial number corresponding to each command information packet can be obtained from the payload information of the remote data packet. For example, assuming that the remote data packet is obtained by packaging the memory access data corresponding to 5 command information packets of the same source computing chip, the remote data packet contains the memory access data corresponding to each of the 5 command information packets and the unique serial number.

[0062] It should be noted that if the computing chips transmit data through the PCIe protocol, the computing chip also includes a PCIe interface for connecting to a PCIe switch, and the PCIe switch is used to connect different computing chips. The PCIe interface is used to convert the external packets of the computing chip into PCIe protocol packets, and send them to other computing chips through the PCIe switch, or to receive PCIe protocol packets sent by other computing chips through the PCIe switch, and send them to the remote data acquisition unit or the remote data packet generation unit.

[0063] Optionally, the structure of the remote data acquisition unit is as follows: Figure 4 As shown, the remote data acquisition unit includes: a command decoding module 401, a local packet reading module 402, a command packet packaging module 403, a remote command packet sending module 404, an output flow control module 405, a remote data packet receiving module 406 and a local memory write request module 407.

[0064] The command decoding module 401 is responsible for receiving the start command from the control engine, and the control local packet reading module 402 is responsible for reading the command information packet generated by the data operation unit from the local memory.

[0065] The command packet packaging module 403 is responsible for receiving the command information packets returned by the local memory and packaging them into remote command packets. There is a separate packaging queue for each target computing chip. When 32 command information packets form a remote command packet, it can be sent to the remote packet sending module 404. If the number of the last command information packets cannot meet 32, a remote command packet will be directly formed and sent to the remote command packet sending module 404.

[0066] The remote command packet sending module 404 is mainly responsible for sending the remote command packet to the PCIe switch through the PCIe interface, and the PCIe switch sends it to the corresponding target computing chip.

[0067] The output flow control module 405 mainly prevents the remote data packet receiving module 406 of the target computing chip from overflowing, thereby avoiding the deadlock of the link. Among them, the output flow control module 405 counts to obtain a first value each time the remote command packet sending module 404 sends a remote command packet, and the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet. The output flow control module 405 counts to obtain a second value each time the remote data packet receiving module 406 receives a response packet. The output flow control module 405 controls the number of packets sent through the first value and the second value. For example, when sending packets, the difference between the first value and the second value cannot exceed a preset threshold value, thereby avoiding the deadlock of the link.

[0068] The remote data packet receiving module 406 is responsible for receiving the remote data packet and sending it to the local memory write request module 407 .

[0069] The local memory write request module 407 is responsible for storing the data of the remote data packet in the local memory, wherein the local memory address offset comes from the storage of the command packet packaging module 403 .

[0070] Optionally, in one implementation mode, the structure of the remote data packet generating unit is as follows: Figure 5 As shown, it includes: a remote command packet receiving module 501, a remote packet unpacking module 502, a local memory read data buffer 503 and a remote data packet sending module 504.

[0071] The remote command packet receiving module 501 is mainly responsible for receiving remote command packets. For each source computing chip, there is an independent command packet buffer. The remote packet unpacking module 502 is mainly responsible for parsing the remote command packet and issuing a memory access request to the local memory. The local storage read data buffer 503 is mainly responsible for receiving the data returned by the local memory. The remote data packet sending module 504 is mainly responsible for packaging the data returned by the memory into a remote data packet and sending the remote data packet to the corresponding computing chip.

[0072] The computing chip shown in this application can be used as both a source computing chip and a target computing chip. Figure 6 The electronic device shown is described below. Figure 6 As shown, the electronic device includes: a PCIe switch, a first computing chip and its local memory, a second computing chip and its local memory. It should be noted that: Figure 6 Only the case of two computing chips is shown, but it can actually be expanded to any number.

[0073] In order to better understand the data transmission process between computing chips, assume Figure 6 The first computing chip is the source computing chip, and the second computing chip is the target computing chip. The interaction process of these two computing chips will be used to describe the process of data transmission between computing chips. It should be noted that this process can be extended to multiple computing chips.

[0074] The source computing chip generates a command information packet and stores it in a local memory, and packages the command information packets in the local memory that access the same target computing chip to form a remote command packet, and sends the remote command packet to the target computing chip. The data operation unit in the source computing chip may generate a command information packet and store it in a local memory, and the remote data acquisition unit in the source computing chip packages the command information packets in the local memory that access the same target computing chip to form a remote command packet, and sends the remote command packet to the target computing chip through a PCIe switch.

[0075] When the source computing chip sends a remote command packet, it counts the sent remote command packets to obtain a first value, and counts the response packets returned by the target computing chip to obtain a second value, and controls the number of remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

[0076] After receiving the remote command packet, the PCIe switch finds the corresponding target computing chip based on the BAR address in the remote command packet (the address of the remote data packet generation unit in the target computing chip), and then sends the remote command packet to the target computing chip.

[0077] After receiving the remote command packet, the target computing chip decompresses the remote command packet to obtain the command information packet therein, obtains the corresponding memory access data from the local memory based on the command information packet, and packages the memory access data corresponding to the command information packet to form a remote data packet, and sends it to the source computing chip. It can be a remote data packet generation unit in the target computing chip, which, after receiving the remote command packet, decompresses the remote command packet to obtain the command information packet therein, obtains the corresponding memory access data from the local memory based on the command information packet, and then packages the memory access data corresponding to the command information packet to form a remote data packet, and sends it to the source computing chip through the PCIe switch.

[0078] After receiving the remote data packet, the PCIe switch finds the corresponding source computing chip based on the BAR address in the remote data packet (the address of the remote data acquisition unit in the source computing chip), and then sends the remote data packet to the source computing chip.

[0079] After receiving the remote data packet returned by the target computing chip based on the remote command packet, the source computing chip stores the memory access data in the remote data packet in the local memory. After receiving the remote data packet, the remote data acquisition unit in the source computing chip acquires the unique serial number (the unique serial number of the command information packet) in the remote data packet, acquires the address offset of the local memory corresponding to the unique serial number, determines the local memory access address based on the address offset and the preset base address of the local memory, and then stores the memory access data in the local memory access address of the local memory.

[0080] Through the above-mentioned interaction mode, the data transmission between the computing chips is completed. Of course, the above-mentioned exchange mode can also be reversed, that is, the first computing chip is the target computing chip, and the second computing chip is the source computing chip.

[0081] In addition, the above-mentioned electronic device may also include a host CPU and a host memory, the host CPU is connected via a PCIe switch, and the host memory is connected to the host CPU. The host CPU is used to send commands to the computing chip and control the computing chip, for example, to control the computing chip to generate command information packets for accessing other computing chips. In addition, the computing chip may further include a data transfer unit. The data transfer unit is mainly responsible for transferring data from the host memory to the local memory, or transferring data from the local memory to the host memory. At this time, the structural principle of the electronic device is as follows: Figure 7 As shown, compared to Figure 6 The electronic device also includes a host CPU and a host memory. In addition, the computing chip also includes a data handling unit.

[0082] The local memory shown in this application can be, but is not limited to, random access memory (RAM), read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), etc.

[0083] It should be noted that the implementation principle and technical effects of the computing chip in the electronic device embodiment are the same as those in the aforementioned computing chip embodiment. For the sake of brief description, for matters not mentioned in the electronic device embodiment, reference may be made to the corresponding contents in the aforementioned computing chip embodiment.

[0084] Based on the same inventive concept, the embodiment of the present application also provides a data transmission method between computing chips, which is applied to computing chips. Figure 8 Explain it.

[0085] S1: Generate a command information packet and store it in the local memory.

[0086] The data operation unit in the computing chip may generate the command information packet and store it in the local memory.

[0087] S2: Packing command information packets in the local memory for accessing the same target computing chip into a remote command packet, and sending the remote command packet to the target computing chip.

[0088] It may be a remote data acquisition unit in a computing chip, which packages command information packets in a local memory for accessing the same target computing chip to form a remote command packet, and sends the remote command packet to the target computing chip.

[0089] When the command information packets accessing the same target computing chip in the local memory are packaged to form a remote command packet, the process may be to take out the command information packets from the local memory, wherein each command information packet corresponds to a unique serial number; package the command information packets accessing the same target computing chip and their unique serial numbers as the load information of the remote command packet, and use the designated information as the header information of the remote command packet to obtain the remote command packet.

[0090] S3: Receive the remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet into the local memory.

[0091] It may be a remote data acquisition unit in a computing chip, which receives a remote data packet returned by a target computing chip based on a remote command packet, and stores the memory access data in the remote data packet into a local memory.

[0092] In an optional implementation, before the memory access data in the remote data packet is stored in the local memory, the remote data packet can be verified for error. For example, the target computing chip serial number in the remote data packet is obtained. If the serial number is inconsistent with the serial number of the computing chip itself, the remote data packet can be considered to be erroneous. If the serial numbers are consistent, the remote data packet can be considered to have passed the error verification.

[0093] In an optional implementation, when storing memory access data in a remote data packet into a local memory, the address offset of the local memory corresponding to the unique serial number in the remote data packet can be obtained, wherein the unique serial number is the unique serial number of the command information packet corresponding to the memory access data, and the local memory access address is determined based on the address offset and a preset base address of the local memory, and then the memory access data in the remote data packet is stored in the local memory according to the local memory access address.

[0094] In an optional implementation, the method also includes: when receiving a remote command packet sent by a source computing chip, decompressing the remote command packet to obtain a command information packet therein; acquiring corresponding memory access data from a local memory based on the command information packet therein; packaging the memory access data corresponding to the command information packet to form a remote data packet, and sending the remote data packet to the source computing chip.

[0095] Optionally, when packaging the memory access data corresponding to the command information packet to form the remote data packet, the memory access data corresponding to the command information packet from the same source computing chip may be packaged to form the remote data packet.

[0096] Optionally, the method also includes counting the remote command packets sent to obtain a first value; counting the response packets returned by the target computing chip to obtain a second value, and controlling the number of remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip for each remote command packet received.

[0097] The data transmission method between computing chips provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned computing chip embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding contents in the aforementioned computing chip embodiment.

[0098] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0099] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0100] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0101] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A computing chip, characterized in that: The computing chip is connected to the local memory, and the computing chip includes: A data operation unit, used for generating a command information packet and storing it in the local memory; A remote data acquisition unit, used to package command information packets in the local memory for accessing the same target computing chip to form a remote command packet, and send the remote command packet to the target computing chip; and also used to receive a remote data packet returned by the target computing chip based on the remote command packet, and store the memory access data in the remote data packet to the local memory; The remote data acquisition unit is also used to count the remote command packets sent to obtain a first value, and to count the response packets returned by the target computing chip to obtain a second value, and to control the number of the remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

2. The computing chip according to claim 1, characterized in that: When the remote data acquisition unit packages the command information packets for accessing the same target computing chip in the local memory to form a remote command packet, it is specifically used to: Retrieving a command information packet from the local memory, wherein each command information packet corresponds to a unique serial number; The command information packet accessing the same target computing chip and its unique serial number are packaged as the load information of the remote command packet to obtain the remote command packet.

3. The computing chip according to claim 1, characterized in that: When the remote data acquisition unit stores the access data in the remote data packet into the local memory, it is specifically used to: Obtaining the address offset of the local memory corresponding to the unique serial number in the remote data packet, wherein the unique serial number is the unique serial number of the command information packet corresponding to the remote data packet, and different command information packets correspond to different unique serial numbers and address offsets; Determining a local memory access address based on an address offset and a preset base address of the local memory; The memory access data in the remote data packet is stored in the local memory based on the local memory access address.

4. The computing chip according to claim 1, characterized in that: The computing chip also includes: a remote data packet generation unit, which is used to receive a remote command packet sent by a source computing chip, and decompress the received remote command packet to obtain a command information packet therein; and based on the command information packet therein, obtain corresponding memory access data from the local memory, and pack the corresponding memory access data into a remote data packet and send it to the source computing chip.

5. The computing chip according to claim 1, characterized in that: The packet structures of the remote data packet and the remote command packet are consistent, both including header information and load information, and the header information includes a packet sequence number, a load number, a packet type, a source computing chip sequence number, and a target computing chip sequence number.

6. The computing chip according to claim 1, characterized in that: Data is transmitted between different computing chips via the PCIe protocol, and the remote data packet and the remote command packet include a BAR address, wherein the BAR address in the remote data packet is the address of a remote data acquisition unit in the opposite computing chip, and the BAR address in the remote command packet is the address of a remote data packet generation unit in the opposite computing chip.

7. An electronic device, characterized in that: include: PCIe switch; and At least two computing chips, each of which is connected to the PCIe switch, and each of which is used to: Generate a command information packet and store it in a local memory; Packing command information packets in the local memory for accessing the same target computing chip into a remote command packet, and sending the remote command packet to the target computing chip; Receiving a remote data packet returned by the target computing chip based on the remote command packet, and storing the memory access data in the remote data packet into the local memory; Each of the computing chips is also used to count the remote command packets sent to obtain a first value, and to count the response packets returned by the target computing chip to obtain a second value, and to control the number of the remote command packets sent according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

8. The electronic device according to claim 7, characterized in that: Each of the computing chips is further used for: Receive the remote command packet sent by the source computing chip, and decompress the received remote command packet to obtain the command information packet therein; Acquire corresponding memory access data from the local memory based on the command information packet; The corresponding memory access data is packaged into a remote data packet and sent to the source computing chip.

9. A data transmission method between computing chips, characterized in that: include: Generate a command information packet and store it in a local memory; Packing command information packets in the local memory for accessing the same target computing chip into a remote command packet, and sending the remote command packet to the target computing chip; Receiving a remote data packet returned by the target computing chip based on the remote command packet, and storing the memory access data in the remote data packet into the local memory; The method further comprises: Counting the sent remote command packets to obtain a first value; The response packets returned by the target computing chip are counted to obtain a second value, and the number of the remote command packets sent is controlled according to the first value and the second value, wherein the target computing chip returns a response packet to the source computing chip each time it receives a remote command packet.

10. The method according to claim 9, characterized in that The method further comprises: When receiving a remote command packet sent by a source computing chip, decompress the received remote command packet to obtain a command information packet therein; Based on the command information packet, corresponding memory access data is obtained from the local memory, and the corresponding memory access data is packaged into a remote data packet and sent to the source computing chip.

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