Internal voltage generation circuit

Abstract

Embodiments of the present disclosure relate to an internal voltage generation circuit. An internal voltage generation circuit can include an oscillation circuit, a signal generation circuit, and a pumping circuit. The oscillation circuit can generate an oscillation signal. The signal generation circuit can generate a first pumping driving signal and a second pumping driving signal based on the oscillation signal. The pumping circuit can generate a pumping voltage through a pumping operation based on the first pumping driving signal and the second pumping driving signal.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0165765, filed on December 1, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Various embodiments relate generally to an internal voltage generation circuit, and in particular to an internal voltage generation circuit capable of generating a pumped voltage through a pumping operation.

[0004] Related Art

[0005] Generally, a semiconductor device including a volatile memory device and a non-volatile memory device is provided with an internal voltage generation circuit for generating an internal voltage. The internal voltage generation circuit receives a power supply voltage and a ground voltage, and generates an internal voltage having various voltage levels. The internal voltage generation circuit can be designed according to a target voltage level. The internal voltage generation circuit includes a component for generating an internal voltage through a pumping operation. The internal voltage generation circuit is capable of generating an internal voltage having a voltage level higher than the power supply voltage, and is capable of generating an internal voltage having a voltage level lower than the ground voltage through a pumping operation. Hereinafter, the internal voltage generated through the pumping operation will be referred to as a "pumped voltage".

[0006] The pumped voltage is generated through a pumping operation of the internal voltage generation circuit. Generally, the pumping operation causes a ripple in the pumped voltage. The ripple generated in the pumped voltage is noise in the pumped voltage. Furthermore, the noise in the pumped voltage becomes a factor that hinders the semiconductor device from performing a normal operation. SUMMARY

[0007] According to an embodiment of the disclosure, the internal voltage generation circuit can include an oscillation circuit configured to generate an oscillation signal based on an enable signal, a signal generation circuit configured to generate a first pumped driving signal and a second pumped driving signal in a pumping period to correspond to the oscillation signal, and configured to generate the first pumped driving signal and the second pumped driving signal in a maintenance period to include at least one of a first edge and a second edge of the oscillation signal, and a pumping circuit configured to generate the pumped voltage through a pumping operation based on the first pumped driving signal and the second pumped driving signal.

[0008] According to an embodiment of the disclosure, an internal voltage generation circuit includes an oscillation circuit configured to generate an oscillation signal through an oscillation operation based on an enable signal, a signal generation circuit configured to generate a first pump driving signal and a second pump driving signal in a pump period to correspond to the oscillation signal, and configured to generate the first pump driving signal and the second pump driving signal in a sustain period to form an edge based on a comparison signal, a pump circuit configured to generate a pump voltage through a pump operation based on the first pump driving signal and the second pump driving signal, and a comparison circuit configured to generate the comparison signal by comparing the pump voltage with a reference voltage corresponding to a target voltage of the pump voltage.

[0009] According to an embodiment of the disclosure, a method of a pump voltage includes generating a driving signal, and performing a single pump operation to pump a voltage each time the driving signal transitions, wherein the generation of the driving signal includes generating the driving signal until the pump voltage reaches a target voltage, and generating the driving signal that transitions each time the pump voltage becomes lower than the target voltage after the pump voltage reaches the target voltage. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a configuration of an internal voltage generation circuit according to an embodiment of the disclosure.

[0011] Figure 2 is a diagram illustrating Figure 1 a configuration of a signal generation circuit of

[0012] Figure 3 is a circuit diagram illustrating Figure 1 a configuration of a pump circuit of

[0013] Figure 4 is a diagram illustrating Figure 3 a pump operation of the pump circuit in

[0014] Figure 5 is a diagram illustrating Figure 1 an overall pump operation of the internal voltage generation circuit in

[0015] Figure 6 is a block diagram illustrating a configuration of an internal voltage generation circuit according to an embodiment of the disclosure.

[0016] Figure 7 is a diagram illustrating Figure 6 a configuration of a signal generation circuit of

[0017] Figure 8 is a diagram illustrating Figure 6 an overall pump operation of the internal voltage generation circuit in DETAILED DESCRIPTION

[0018] The specification of the present disclosure provides structural details and functional details for various embodiments. However, the scope of the present invention is not limited to or by any disclosed embodiment nor to any particular details provided herein. That is, those skilled in the art will appreciate from the present disclosure that any embodiment can be modified in various ways and can take various forms. Accordingly, the present invention includes all such modifications falling within the scope of the claims and their equivalents. Furthermore, embodiments do not necessarily include all stated objects or effects, nor do they necessarily include only such objects or effects. Therefore, the scope of the present invention is not limited thereto.

[0019] Throughout the specification, reference to “an embodiment” or the like is not necessarily to one embodiment only, and different references to “an embodiment” or the like do not necessarily refer to the same embodiment. As used herein, the term “embodiment” does not necessarily refer to all embodiments.

[0020] The terms such as “first” and “second” are used to distinguish one element from another element having the same or similar name. A first element in one example can be named as a second element in another example, rather than indicating any substantial change in the element itself.

[0021] The singular is intended to include the plural, unless otherwise clearly indicated or clearly contradicted by context. Open terms such as “comprising” or “having” are to be understood as indicating the presence of the stated features, numbers, steps, operations, elements, parts, or combinations thereof, but not excluding the presence or possibility of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof.

[0022] In each step, symbols (e.g., a, b, and c) are used for ease of description, not necessarily indicating any particular order of steps or operations. Steps / operations can be performed in any suitable order according to the teachings herein, unless a particular order is explicitly described or the context indicates such an order. In some cases, two or more steps / operations can be performed substantially simultaneously.

[0023] Unless otherwise defined, all terms used in this document, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Unless explicitly defined in the application, terms defined in commonly used dictionaries are to be interpreted as having a context reflected in their usage in the relevant technical field, and not in an idealized or overly formal way unless expressly so defined.

[0024] Various embodiments are directed to providing an internal voltage generation circuit capable of generating a pumping voltage even through minimal pumping operation.

[0025] Embodiments of the present disclosure have the effect of minimizing pumping operation, thereby minimizing the ripple generated in the pumping voltage.

[0026] Figure 1 is a block diagram illustrating a configuration of an internal voltage generation circuit 10 according to an embodiment of the disclosure.

[0027] Referring to Figure 1 , the internal voltage generation circuit can include an oscillation circuit 100, a signal generation circuit 200, and a pumping circuit 300.

[0028] The oscillation circuit 100 can be configured to generate an oscillation signal OSC based on an enable signal EN. The enable signal EN can be a signal for enabling or disabling the internal voltage generation circuit. The oscillation circuit 100 can generate the oscillation signal OSC through an oscillation operation. The oscillation signal OSC can be a clock signal that is toggled at a predetermined frequency. The oscillation signal OSC can include a rising edge corresponding to a first edge and a falling edge corresponding to a second edge.

[0029] The signal generation circuit 200 can be configured to generate a first pumping drive signal CK_P1 and a second pumping drive signal CK_P2 corresponding to the oscillation signal OSC in a pumping period. The first pumping drive signal CK_P1 can be a signal corresponding to the rising edge of the oscillation signal OSC, and the second pumping drive signal CK_P2 can be a signal corresponding to the falling edge of the oscillation signal OSC. In addition, the pumping period can be a period in which a pumping operation is performed in order to increase a voltage level of a pumping voltage V_PMP to a preset target voltage level.

[0030] In addition, the signal generation circuit 200 can be configured to generate the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 each including at least one edge of the rising edge and the falling edge of the oscillation signal OSC in a maintenance period. The maintenance period can be an operation period after the pumping period. In other words, the maintenance period can be a period in which a pumping operation is performed in order to increase the voltage level of the pumping voltage V_PMP to the preset voltage level again when the voltage level of the pumping voltage V_PMP is lower than the preset target voltage level after the pumping period. As will be described below with reference to Figure 5 Again described, in the maintenance period, the first pumping drive signal CK_P1 can include an edge that transitions to logic "high" in response to the rising edge of the oscillation signal OSC, and the second pumping drive signal CK_P2 can include an edge that transitions to logic "low" in response to the rising edge of the oscillation signal OSC. Alternatively, in the maintenance period, the second pumping drive signal CK_P2 can include an edge that transitions to logic "high" in response to the falling edge of the oscillation signal OSC, and the first pumping drive signal CK_P1 can include an edge that transitions to logic "low" in response to the falling edge of the oscillation signal OSC.

[0031] The pumping circuit 300 can be configured to generate a pumping voltage V_PMP through a pumping operation based on a first pumping driving signal CK_P1 and a second pumping driving signal CK_P2. The pumping circuit 300 can simultaneously receive the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2, and perform the pumping operation.

[0032] In the pumping period, the internal voltage generation circuit according to an embodiment of the disclosure can generate the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 in response to the oscillation signal OSC, and perform the pumping operation. Also, in the sustain period, the internal voltage generation circuit can generate the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 each including at least one edge of rising and falling edges of the oscillation signal OSC, and perform the pumping operation.

[0033] To this end, the internal voltage generation circuit can perform a single pumping operation based on the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 in the sustain period. Hereinafter, for convenience of description, the single pumping operation is defined as a "unit pumping operation". The unit pumping operation can cause as much ripple as that caused by the single pumping operation in the pumping voltage V_PMP. In other words, the internal voltage generation circuit according to an embodiment of the disclosure is capable of minimizing the ripple generated in the pumping voltage V_PMP through the unit pumping operation.

[0034] Meanwhile, the internal voltage generation circuit according to an embodiment of the disclosure can include a comparison circuit 400.

[0035] The comparison circuit 400 can be configured to generate a comparison signal VCMP by comparing a reference voltage V_REF corresponding to a target voltage of the pumping voltage V_PMP with the pumping voltage V_PMP. Accordingly, when the pumping voltage V_PMP has a voltage level lower than the reference voltage V_REF, the comparison circuit 400 can generate the comparison signal VCMP for performing the pumping operation. When the pumping voltage V_PMP has a voltage level higher than the reference voltage V_REF, the comparison circuit 400 can generate the comparison signal VCMP for stopping the pumping operation.

[0036] Figure 2 is a diagram illustrating a configuration of a signal generation circuit 200 in Figure 1 .

[0037] Referring to Figure 2 , the signal generation circuit 200 can include an edge detection circuit 210, a signal transmission circuit 220, and a signal output circuit 230.

[0038] The edge detection circuit 210 can be configured to generate an edge detection signal DET_E by detecting rising and falling edges of the oscillation signal OSC in a sustain period. The edge detection circuit 210 can generate the edge detection signal DET_E by comparing a logic level of an output signal OUT of a latch circuit LC to be described below with a logic level of the oscillation signal OSC. Reference will be made to FIG. 2 for a detailed description of the edge detection signal DET_E. Figure 5 The edge detection signal DET_E will be described in detail.

[0039] The signal transmission circuit 220 can be configured to transmit the oscillation signal OSC as a first oscillation signal OSC1 and a second oscillation signal OSC2 based on the edge detection signal DET_T and the comparison signal VCMP. The signal transmission circuit 220 can output the oscillation signal OSC as the first oscillation signal OSC1 and the second oscillation signal OSC2 in a pumping period. Further, the signal transmission circuit 220 can transmit at least one edge of rising and falling edges of the oscillation signal OSC as the first oscillation signal OSC1 and the second oscillation signal OSC2 in a sustain period. In an embodiment, the signal transmission circuit 220 can include a first inverter INV1, a first AND gate AND1, and a second AND gate AND2.

[0040] The first inverter INV1 can receive and invert the oscillation signal OSC and output the inverted signal. The first AND gate AND1 can receive the oscillation signal OSC, the edge detection signal DET_E, and the comparison signal VCMP and output the first oscillation signal OSC1. The second AND gate AND2 can receive an output signal of the first inverter INV1, the edge detection signal DET_E, and the comparison signal VCMP and output the second oscillation signal OSC2.

[0041] The signal output circuit 230 can be configured to generate a first pumping driving signal CK_P1 and a second pumping driving signal CK_P2 based on the first oscillation signal OSC1 and the second oscillation signal OSC2. In an embodiment, the signal output circuit 230 can include a latch circuit LC, a buffer circuit BF, and a second inverter INV2.

[0042] The latch circuit LC can be configured to receive the first oscillation signal OSC1 and the second oscillation signal OSC2 and perform a latching operation. For example, the latch circuit LC can be implemented as an SR latch including a first input terminal S, a second input terminal R, and an output terminal Q. That is, the latch circuit LC can receive the first oscillation signal OSC1 through the first input terminal S and perform a set operation, and can receive the second oscillation signal OSC2 through the second input terminal R and perform a reset operation. Accordingly, the latch circuit LC can output and substantially maintain the output signal OUT having, for example, a logic "high" through the set operation, and can output and substantially maintain the output signal OUT having, for example, a logic "low" through the reset operation.

[0043] The buffer circuit BF can be an output circuit for receiving the output signal OUT of the latch circuit LC and outputting the first pump driving signal CK_P1. The second inverter INV2 can be an output circuit for inverting the output signal OUT of the latch circuit LC and outputting the second pump driving signal CK_P2. It will be described again in more detail with reference to Figure 5 the first pump driving signal CK_P1 and the second pump driving signal CK_P2 output from the signal output circuit 230.

[0044] Figure 3 is a circuit diagram illustrating a configuration of the pump circuit 300 in Figure 1 .

[0045] Referring to Figure 3 , the pump circuit 300 can include a charge / discharge circuit 310 and a pump output circuit 320.

[0046] The charge / discharge circuit 310 can be configured to charge and discharge a first charge / discharge node VP1 based on the first pump driving signal CK_P1 and to charge and discharge a second charge / discharge node VP2 based on the second pump driving signal CK_P2. In an embodiment, the charge / discharge circuit 310 can include a first NMOS transistor N1 and a second NMOS transistor N2.

[0047] The first NMOS transistor N1 can have a drain terminal and a source terminal connected between the voltage input terminal V_IN and the first charge / discharge node VP1, and a gate terminal connected to the second charge / discharge node VP2. The second NMOS transistor N2 can have a drain terminal and a source terminal connected between the voltage input terminal V_IN and the second charge / discharge node VP2, and a gate terminal connected to the first charge / discharge node VP1. The voltage input terminal V_IN can receive a voltage provided for a pumping operation. The first charge / discharge node VP1 can be connected to the first capacitor C1 receiving the first pump driving signal CK_P1, and the second charge / discharge node VP2 can be connected to the second capacitor C2 receiving the second pump driving signal CK_P2. Accordingly, the first charge / discharge node VP1 can be charged and discharged based on the first pump driving signal CK_P1, and the second charge / discharge node VP2 can be charged and discharged based on the second pump driving signal CK_P2.

[0048] The pump output circuit 320 can be configured to output the charge that has been stored in the first charge / discharge node VP1 as the pump voltage V_PMP based on the first pump driving signal CK_P1, and configured to output the charge that has been stored in the second charge / discharge node VP2 as the pump voltage V_PMP based on the second pump driving signal CK_P2. In an embodiment, the pump output circuit 320 can include a first PMOS transistor P1 and a second PMOS transistor P2.

[0049] The first PMOS transistor P1 can have a source terminal and a drain terminal connected between the first charge / discharge node VP1 and an output terminal of the pump voltage V_PMP, and a gate terminal connected to the second charge / discharge node VP2. The second PMOS transistor P2 can have a source terminal and a drain terminal connected between the second charge / discharge node VP2 and the output terminal of the pump voltage V_PMP, and a gate terminal connected to the first charge / discharge node VP1.

[0050] As described above, the first charge / discharge node VP1 can be charged and discharged based on the first pump driving signal CK_P1, and the second charge / discharge node VP2 can be charged and discharged based on the second pump driving signal CK_P2. The first PMOS transistor P1 can be turned on and off according to the voltage level of the second charge / discharge node VP2, and the second PMOS transistor P2 can be turned on and off according to the voltage level of the first charge / discharge node VP1. Accordingly, the pump output circuit 320 can output the charge that has been stored in the second charge / discharge node VP2 as the pump voltage V_PMP based on the first pump driving signal CK_P1, and can output the charge that has been stored in the first charge / discharge node VP1 as the pump voltage V_PMP based on the second pump driving signal CK_P2.

[0051] Figure 4 is a graph illustrating a pump operation of the pump circuit 300 in Figure 3 .

[0052] Figure 4 Signal waveforms corresponding to the first pump driving signal CK_P1, the second pump driving signal CK_P2, the first charge / discharge node VP1, the second charge / discharge node VP2, the pump voltage V_PMP, and the voltage input terminal V_IN, respectively, are illustrated.

[0053] Referring to Figure 3 and Figure 4 , the charge / discharge circuit 310 can charge the first charge / discharge node VP1 at a time point ① at which the first pump driving signal CK_P1 transitions from logic "high" to logic "low". At this time, the pump output circuit 320 can output the charge that has been stored in the first charge / discharge node VP1 as the pump voltage V_PMP at the time point ① at which the second pump driving signal CK_P2 transitions from logic "low" to logic "high". That is, the pump circuit 300 can perform a unit pump operation at the time point ① at which the first pump driving signal CK_P1 transitions from logic "high" to logic "low" and the second pump driving signal CK_P2 transitions from logic "low" to logic "high". The time point ① at which the first pump driving signal CK_P1 transitions from logic "high" to logic "low" can correspond to a falling edge of the oscillation signal OSC. Accordingly, the pump circuit 300 can perform a unit pump operation based on the falling edge of the oscillation signal OSC.

[0054] Meanwhile, the charge / discharge circuit 310 can charge the second charge / discharge node VP2 at time point ② at which the second pump driving signal CK_P2 transitions from logic "high" to logic "low". At this time, the pump output circuit 320 can output the charge that has been stored in the second charge / discharge node VP2 as the pump voltage V_PMP at time point ② at which the first pump driving signal CK_P1 transitions from logic "low" to logic "high". That is, the pump circuit 300 can perform a unit pump operation at time point ② at which the second pump driving signal CK_P2 transitions from logic "high" to logic "low" and the first pump driving signal CK_P1 transitions from logic "low" to logic "high". The time point ② at which the first pump driving signal CK_P1 transitions from logic "low" to logic "high" can correspond to a rising edge of the oscillation signal OSC. Accordingly, the pump circuit 300 can perform a unit pump operation based on the rising edge of the oscillation signal OSC.

[0055] The internal voltage generation circuit according to an embodiment of the disclosure can perform a unit pump operation including a single pump operation based on a rising edge or a falling edge of an oscillation signal OSC.

[0056] Figure 5 is a graph illustrating a whole pump operation of the internal voltage generation circuit in Figure 1 . Figure 5 Signal waveforms corresponding to the pump voltage V_PMP, the oscillation signal OSC, the first pump driving signal CK_P1, the second pump driving signal CK_P2, and the comparison signal VCMP, respectively, are illustrated.

[0057] Hereinafter, for convenience of description, the whole pump operation of the internal voltage generation circuit will be described with reference to Figure 1 , Figure 2 and Figure 5 Hereinafter, a pump period will be referred to as "T1" and a sustain period will be referred to as "T2".

[0058] First, in the pump period "T1", Figure 2 The signal generation circuit 200 in Figure 1The pump circuit 300 in the internal voltage generation circuit 200 can generate a pump voltage V_PMP based on a first pump driving signal CK_P1 and a second pump driving signal CK_P2. Accordingly, the internal voltage generation circuit can generate the pump voltage V_PMP through a pump operation corresponding to the oscillation signal OSC switched in the pump period "T1".

[0059] Next, at an initial stage of a sustain period T2 after the pump period "T1", the pump voltage V_PMP can be higher than a reference voltage V_REF corresponding to a target voltage level. Accordingly, the comparison signal VCMP can have a logic "low". Then, when the pump voltage V_PMP becomes lower than the reference voltage V_REF, the comparison signal VCMP can be enabled to a logic "high".

[0060] At this time, Figure 2 The edge detection circuit 210 in the internal voltage generation circuit 200 can generate an edge detection signal DET_E by comparing a logic level of an output signal OUT of the latch circuit LC with a logic level of the oscillation signal OSC. When the logic level of the output signal OUT of the latch circuit LC and the logic level of the oscillation signal OSC are both logic "low" due to the comparison of the logic level of the output signal OUT with the logic level of the oscillation signal OSC, the edge detection signal DET_E can be enabled to a logic "high". Accordingly, the signal transmission circuit 220 can transmit a rising edge of the oscillation signal OSC as a first oscillation signal OSC1 based on the logic "high" comparison signal VCMP and the logic "high" edge detection signal DET_E. In addition, the signal transmission circuit 220 can invert the rising edge of the oscillation signal OSC and transmit the inverted oscillation signal OSC as a second oscillation signal OSC2.

[0061] Subsequently, the latch circuit LC can perform a set operation based on the first oscillation signal OSC1. The latch circuit LC can output and substantially maintain the output signal OUT having a logic "high" based on the first oscillation signal OSC1. The output signal OUT of the latch circuit LC can correspond to the first pump driving signal CK_P1, and a signal obtained by inverting the output signal OUT of the latch circuit LC can correspond to the second pump driving signal CK_P2. As a result, the first pump driving signal CK_P1 can include an edge that transitions to a logic "high" in response to the rising edge of the oscillation signal OSC, and is substantially maintained as a logic "high". In addition, the second pump driving signal CK_P2 can include an edge that transitions to a logic "low" in response to the rising edge of the oscillation signal OSC, and is substantially maintained as a logic "low".

[0062] Subsequently, Figure 1The pumping circuit 300 in the first embodiment can perform a unit pumping operation based on the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2. As described above, the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 can be signals corresponding to rising edges of the oscillation signal OSC. That is, the pumping circuit 300 can perform a unit pumping operation based on rising edges of the oscillation signal OSC.

[0063] Further, by the unit pumping operation, the voltage level of the pumping voltage V_PMP can be higher than the voltage level of the reference voltage V_REF. Accordingly, the comparison signal VCMP can be disabled to be logic "low". Then, when the voltage level of the pumping voltage V_PMP becomes lower than the reference voltage V_REF again, the comparison signal VCMP can be enabled to be logic "high" again.

[0064] As described above, when the voltage level of the output signal OUT of the latch circuit LC and the voltage level of the oscillation signal OSC are both logic "high" due to comparing the logic level of the output signal OUT with the logic level of the oscillation signal OSC, the edge detection signal DET_E can be enabled to be logic "high". Accordingly, the signal transmission circuit 220 can transmit a falling edge of the oscillation signal OSC as the first oscillation signal OSC1. Further, the signal transmission circuit 220 can invert the falling edge of the oscillation signal OSC and transmit the inverted oscillation signal OSC as the second oscillation signal OSC2. Subsequently, the latch circuit LC can perform a reset operation based on the second oscillation signal OSC2 corresponding to the falling edge of the oscillation signal OSC. That is, the latch circuit LC can output and substantially maintain the output signal OUT having logic "low" based on the second oscillation signal OSC2. As a result, the first pumping drive signal CK_P1 can include an edge that transitions to logic "low" in response to the falling edge of the oscillation signal OSC and substantially maintains logic "low". Further, the second pumping drive signal CK_P2 can include an edge that transitions to logic "high" in response to the falling edge of the oscillation signal OSC and substantially maintains logic "high".

[0065] Subsequently, Figure 1 The pumping circuit 300 in the first embodiment can perform a unit pumping operation based on the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2. As described above, the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 can be signals corresponding to rising edges of the oscillation signal OSC. That is, the pumping circuit 300 can perform a unit pumping operation based on rising edges of the oscillation signal OSC. Then, by the unit pumping operation, the voltage level of the pumping voltage V_PMP can become higher than the voltage level of the reference voltage V_REF.

[0066] The internal voltage generation circuit according to an embodiment of the disclosure can generate the pump voltage V_PMP through a unit pumping operation corresponding to a rising edge or a falling edge of the oscillation signal OSC. Accordingly, a minimum ripple is caused only in the pump voltage V_PMP due to the unit pumping operation as a single pumping operation.

[0067] Figure 6 is a block diagram illustrating a configuration of an internal voltage generation circuit 10A according to an embodiment of the disclosure.

[0068] Referring to Figure 6 , the internal voltage generation circuit can include an oscillation circuit 100A, a signal generation circuit 200A, a pump circuit 300A, and a comparison circuit 400A.

[0069] The oscillation circuit 100A can be configured to generate an oscillation signal OSC through an oscillation operation based on an enable signal EN. The enable signal EN can be a signal for enabling the internal voltage generation circuit. The oscillation operation of the oscillation circuit 100A can be controlled based on operation period information INF_T. As will be described again below, the operation period information INF_T can be a signal corresponding to a pumping period and a sustaining period. Accordingly, the oscillation operation of the oscillation circuit 100A can be enabled in the pumping period based on the operation period information INF_T. Further, the oscillation operation of the oscillation circuit 100A can be disabled in the sustaining period based on the operation period information INF_T.

[0070] The signal generation circuit 200A can be configured to generate a first pump driving signal CK_P1 and a second pump driving signal CK_P2 corresponding to the oscillation signal OSC in the pumping period. The first pump driving signal CK_P1 can be a signal corresponding to a rising edge of the oscillation signal OSC, and the second pump driving signal CK_P2 can be a signal corresponding to a falling edge of the oscillation signal OSC.

[0071] Further, the signal generation circuit 200A can be configured to generate the first pump driving signal CK_P1 and the second pump driving signal CK_P2 each including an edge formed based on a comparison signal VCMP in the sustaining period. As will be described again below with reference to Figure 8 As will be described again below, the first pump driving signal CK_P1 and the second pump driving signal CK_P2 each include an edge having a logic level that is transitioned based on the comparison signal VCMP in the sustaining period.

[0072] The pumping circuit 300A can be configured to generate a pumping voltage V_PMP through a pumping operation based on a first pumping driving signal CK_P1 and a second pumping driving signal CK_P2. The pumping circuit 300A can simultaneously receive the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 and perform the pumping operation. The pumping circuit 300A can perform a unit pumping operation based on the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 generated in a sustain period.

[0073] The comparison circuit 400A can be configured to generate a comparison signal VCMP by comparing a reference voltage V_REF corresponding to a target voltage of the pumping voltage V_PMP with the pumping voltage V_PMP. Accordingly, when the pumping voltage V_PMP has a voltage level lower than that of the reference voltage V_REF, the comparison circuit 400A can generate the comparison signal VCMP for performing the pumping operation. When the pumping voltage V_PMP has a voltage level higher than that of the reference voltage V_REF, the comparison circuit 400A can generate the comparison signal VCMP for stopping the pumping operation.

[0074] In the pumping period, the internal voltage generation circuit according to an embodiment of the disclosure is capable of generating a first pumping driving signal CK_P1 and a second pumping driving signal CK_P2 corresponding to the oscillation signal OSC and performing the pumping operation. Further, in the sustain period, the internal voltage generation circuit is capable of generating the first pumping driving signal CK_P1 and the second pumping driving signal CK_P2 each including an edge formed based on the comparison signal VCMP. In addition, the internal voltage generation circuit is capable of disabling the oscillation operation of the oscillation circuit 100A in the sustain period, thereby minimizing power consumed during the oscillation operation. Also, the internal voltage generation circuit is capable of performing a unit pumping operation in the sustain period, thereby minimizing a ripple generated in the pumping voltage V_PMP.

[0075] Meanwhile, the internal voltage generation circuit according to an embodiment of the disclosure can further include a period setting circuit 500A.

[0076] The period setting circuit 500A can be configured to generate operation period information INF_T corresponding to the pumping period and the sustain period based on an enable signal EN and the comparison signal VCMP. For reference, in the operation period information INF_T, a starting time point of the pumping period T1 can be defined based on the enable signal EN. It will be referred to Figure 8 The comparison signal VCMP is described in more detail, but the comparison signal VCMP can have a logic "high" in the pumping period and then can be transitioned to a logic "low". Accordingly, the operation period information INF_T can define a starting time point of the sustain period T2 based on a time point at which the comparison signal VCMP is transitioned to the logic "low".

[0077] As described above, the operation period information INF_T can be supplied to the oscillation circuit 100A to control its oscillation operation. Further, the operation period information INF_T can be supplied to the signal generation circuit 200A to select a signal for generating the first pump driving signal CK_P1 and the second pump driving signal CK_P2. The selection of the signal will be described in more detail with reference to Figure 7 The selection of the signal will be described in more detail with reference to

[0078] Figure 7 is a diagram illustrating a configuration of the signal generation circuit 200A in Figure 6

[0079] With reference to Figure 7 , the signal generation circuit 200A can include an edge generation circuit 210A, a signal selection circuit 220A, and a signal output circuit 230A.

[0080] The edge generation circuit 210A can be configured to generate edges in the output signal OUT based on the comparison signal VCMP. For example, the edge generation circuit 210A can be implemented by a T flip-flop including an input terminal T and an output terminal Q. That is, the edge generation circuit 210A can sequentially generate an edge that transitions to logic “high” and an edge that transitions to logic “low” in the output signal OUT at the output terminal Q based on the comparison signal VCMP input to the input terminal T. Thus, the output signal OUT of the edge generation circuit 210A can include the edge that transitions to logic “high” and can substantially maintain logic “high”. Further, the output signal OUT of the edge generation circuit 210A can include the edge that transitions to logic “low” and can substantially maintain logic “low”.

[0081] The signal selection circuit 220A can be configured to output the oscillation signal OSC or the output signal OUT of the edge generation circuit 210A based on the operation period information INF_T. In an embodiment, the signal selection circuit 220A can include a first transmission gate TG1, a second transmission gate TG2, a first inverter INV1, and a second inverter INV2.

[0082] ​The first transmission gate TG1 can input and output the oscillation signal OSC based on the operation period information INF_T. The input / output operation of the first transmission gate TG1 can be controlled based on the operation period information INF_T and an output signal of the first inverter INV1, which is a signal obtained by inverting the operation period information INF_T. For example, the first transmission gate TG1 can be turned on when the operation period information INF_T has a logic "high". Also, the second transmission gate TG2 can input and output the output signal OUT of the edge generation circuit 210A based on the operation period information INF_T. The input / output operation of the second transmission gate TG2 can be controlled based on the operation period information INF_T and an output signal of the second inverter INV2, which is a signal obtained by inverting the operation period information INF_T. For example, the second transmission gate TG2 can be turned on when the operation period information INF_T has a logic "low".

[0083] The signal output circuit 230A can be configured to generate the first pump driving signal CK_P1 and the second pump driving signal CK_P2 based on the output signal of the signal selection circuit 220A. In an embodiment, the signal output circuit 230A can include a buffer circuit BF and a third inverter INV3.

[0084] The buffer circuit BF can receive the output signal of the signal selection circuit 220A and output the first pump driving signal CK_P1. The third inverter INV3 can invert the output signal of the signal selection circuit 220A and output the inverted signal as the second pump driving signal CK_P2.

[0085] The internal voltage generation circuit according to an embodiment of the disclosure can select a signal for generating the first pump driving signal CK_P1 and the second pump driving signal CK_P2 based on the operation period information INF_T. That is, the internal voltage generation circuit can generate the first pump driving signal CK_P1 and the second pump driving signal CK_P2 by using the oscillation signal OSC in a pump period. Also, the internal voltage generation circuit can generate the first pump driving signal CK_P1 and the second pump driving signal CK_P2 by using the output signal OUT of the edge generation circuit 210A in a sustain period.

[0086] Figure 8 is a graph illustrating the overall pump operation of the internal voltage generation circuit in Figure 6 . Figure 8 Signal waveforms corresponding to the operation period information INF_T, the comparison signal VCMP, the first pump driving signal CK_P1, and the second pump driving signal CK_P2, respectively, are illustrated.

[0087] Referring to Figure 6 to Figure 8, based on the enable signal EN and the comparison signal VCMP, the operation period information INF_T can have a logic "high" period. The logic "high" period of the operation period information INF_T can correspond to a pumping period T1. In the pumping period T1, a first transfer gate TG1 of the signal selection circuit 220A in Figure 7 can be turned on. That is, the oscillation signal OSC can be output to the signal output circuit 230A. Accordingly, the signal output circuit 230A can generate the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 based on the oscillation signal OSC. Subsequently, Figure 6 the pumping circuit 300A in can generate the pumping voltage V_PMP based on the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2.

[0088] Next, in the sustain period T2, the operation period information INF_T can have a logic "low". At this time, the oscillation operation of the oscillation circuit 100A in Figure 6 can be disabled. Meanwhile, Figure 7 the edge generation circuit 210A in can sequentially generate an edge that transitions to a logic "high" and an edge that transitions to a logic "low" in the output signal OUT based on the comparison signal VCMP. Subsequently, in the sustain period T2, a second transfer gate TG2 of the signal selection circuit 220A in Figure 7 can be turned on. That is, the output signal OUT of the edge generation circuit 210A can be output to the signal output circuit 230A. Accordingly, the signal output circuit 230A can generate the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 based on the output signal OUT of the edge generation circuit 210A. From Figure 8 it can be seen that the first pumping drive signal CK_P1 can include an edge that transitions to a logic "high" based on the comparison signal VCMP enabled at the time point ① and substantially maintains a logic "high". Further, the second pumping drive signal CK_P2 can include an edge that transitions to a logic "low" and substantially maintains a logic "low". Subsequently, the first pumping drive signal CK_P1 can include an edge that transitions to a logic "low" based on the comparison signal VCMP enabled at the time point ② and substantially maintains a logic "low". Further, the second pumping drive signal CK_P2 can include an edge that transitions to a logic "high" and substantially maintains a logic "high". Figure 6 the pumping circuit 300A in can generate the pumping voltage V_PMP based on the first pumping drive signal CK_P1 and the second pumping drive signal CK_P2 through a unit pumping operation.

[0089] The internal voltage generation circuit according to the embodiment of the present disclosure can control an oscillation operation based on operation period information INF T. Further, the internal voltage generation circuit can generate a first pump driving signal CK P1 and a second pump driving signal CK P2, each of which includes an edge formed based on a comparison signal VCMP, and perform a unit pump operation.

[0090] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims.

Claims

1. An internal voltage generation circuit comprising: an oscillation circuit that generates an oscillation signal based on an enable signal; a signal generation circuit that generates first and second pump driving signals in a pumping period to correspond to the oscillation signal, and generates the first and second pump driving signals in a sustaining period to include at least one of first and second edges of the oscillation signal; a pump circuit that generates a pump voltage by a pump operation based on the first and second pump driving signals; and a comparison circuit that generates a comparison signal by comparing a reference voltage of a target voltage corresponding to the pump voltage with the pump voltage, wherein the signal generation circuit includes: an edge detection circuit that generates an edge detection signal by detecting the first and second edges of the oscillation signal in the sustaining period; a signal transmission circuit that transmits the oscillation signal as first and second oscillation signals based on the edge detection signal and the comparison signal; and a signal output circuit that generates the first and second pump driving signals based on the first and second oscillation signals. 2.The internal voltage generation circuit according to claim 1, wherein the pump circuit performs a unit pump operation including a single pump operation in the sustaining period based on the first and second pump driving signals. 3.The internal voltage generation circuit according to claim 1, wherein the signal transmission circuit outputs the oscillation signal as the first and second oscillation signals in the pumping period, and outputs at least one of the first and second edges of the oscillation signal as the first and second oscillation signals in the sustaining period. 4.The internal voltage generation circuit according to claim 1, wherein the signal output circuit includes: a latch circuit that receives the first and second oscillation signals to perform a latch operation; and an output circuit that outputs the first and second pump driving signals based on an output signal of the latch circuit. 5.The internal voltage generation circuit according to claim 4, wherein the latch operation is set based on the first oscillation signal, and the latch operation is reset based on the second oscillation signal. 6.The internal voltage generation circuit according to claim 4, wherein the edge detection circuit generates the edge detection signal by comparing a logic level of the output signal of the latch circuit with a logic level of the oscillation signal. 7.The internal voltage generation circuit according to claim 1, wherein the pump circuit includes: a charge / discharge circuit that charges and discharges a first charge / discharge node based on the first pump driving signal, and charges and discharges a second charge / discharge node based on the second pump driving signal; and a voltage holding circuit that holds a voltage of the first charge / discharge node based on the first pump driving signal, and holds a voltage of the second charge / discharge node based on the second pump driving signal. ​ ​ a pump output circuit that outputs, as the pump voltage, charge stored in the first charge / discharge node based on the first pump drive signal and outputs, as the pump voltage, charge stored in the second charge / discharge node based on the second pump drive signal.

8. An internal voltage generation circuit comprising: an oscillation circuit that generates an oscillation signal through an oscillation operation based on an enable signal; a signal generation circuit that generates a first pump drive signal and a second pump drive signal in a pump period to correspond to the oscillation signal and generates the first pump drive signal and the second pump drive signal in a sustain period to form edges based on a comparison signal; a pump circuit that generates a pump voltage through a pump operation based on the first pump drive signal and the second pump drive signal; a comparison circuit that generates the comparison signal by comparing the pump voltage with a reference voltage corresponding to a target voltage of the pump voltage; and a period setting circuit that generates operation period information indicating the pump period and the sustain period based on the enable signal and the comparison signal, wherein the signal generation circuit includes: an edge generation circuit that generates edges on an output signal based on the comparison signal; a signal selection circuit that outputs the oscillation signal or an output signal of the edge generation circuit based on the operation period information; and a signal output circuit that generates the first pump drive signal and the second pump drive signal based on an output signal of the signal selection circuit.

9. The internal voltage generation circuit according to claim 8, wherein the oscillation operation of the oscillation circuit is enabled in the pump period and is disabled in the sustain period.

10. The internal voltage generation circuit according to claim 8, wherein a logic level of the first pump drive signal and a logic level of the second pump drive signal are inverted in the sustain period based on the comparison signal.

11. The internal voltage generation circuit according to claim 8, wherein the pump circuit performs a unit pump operation including a single pump operation in the sustain period based on the first pump drive signal and the second pump drive signal.

12. The internal voltage generation circuit according to claim 8, wherein the edge generation circuit generates, sequentially on the output signal, a first edge that inverts to a first logic level and a second edge that inverts to a second logic level based on the comparison signal.

13. The internal voltage generation circuit according to claim 8, wherein the pump circuit includes: a charge / discharge circuit that charges and discharges a first charge / discharge node based on the first pump drive signal and charges and discharges a second charge / discharge node based on the second pump drive signal; and a pump output circuit that outputs, as the pump voltage, charge stored in the first charge / discharge node based on the first pump drive signal and outputs, as the pump voltage, charge stored in the second charge / discharge node based on the second pump drive signal. ​ 14. A method of pumping a voltage, the method comprising: generating an oscillation signal based on an enable signal; and generating a first pump drive signal and a second pump drive signal in a pumping period to correspond to the oscillation signal, and generating the first pump drive signal and the second pump drive signal in a sustain period to include at least one of a first edge and a second edge of the oscillation signal; generating a pump voltage by a pumping operation based on the first pump drive signal and the second pump drive signal; and generating a comparison signal by comparing a reference voltage corresponding to a target voltage of the pump voltage with the pump voltage, wherein the generating of the oscillation signal comprises: generating the oscillation signal until the pump voltage reaches a target voltage, and generating the oscillation signal that transitions whenever the pump voltage becomes lower than the target voltage after the pump voltage reaches the target voltage, and wherein the generating of the first pump drive signal and the second pump drive signal comprises: generating an edge detection signal by detecting the first edge and the second edge of the oscillation signal in the sustain period; transmitting the oscillation signal as a first oscillation signal and a second oscillation signal based on the edge detection signal and the comparison signal; and generating the first pump drive signal and the second pump drive signal based on the first oscillation signal and the second oscillation signal.

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