Conditional row activation and access during refresh of memory devices, and associated methods and systems

Abstract

This invention relates to conditional row activation and access during a refresh of a memory device, and related methods and systems. The memory device can perform operations on the activated rows simultaneously with the refresh operation. In some embodiments, the memory device receives an activation (ACT) command for a segment of the memory bank while performing a refresh operation on the memory bank. The memory device can execute the ACT command if certain conditions are met without corrupting the data being refreshed. Subsequently, the memory device generates a signal indicating that the ACT command has been accepted to activate the row identified by the ACT command. Furthermore, the memory device can execute subsequent access commands for the row in parallel with the refresh operation.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically to conditional row activation and access during the refresh of memory devices, and associated methods and systems. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Memory devices are frequently provided as internal, semiconductor integrated circuits, and / or external removable devices within computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), requires a power source to maintain its data. In contrast, non-volatile memory retains its stored data even without external power. Non-volatile memory can be used in various technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improving memory devices typically includes increasing memory cell density, increasing read / write speeds or additionally reducing operating latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Summary of the Invention

[0003] In one aspect, this disclosure relates to an apparatus comprising: a storage bank of memory cells, wherein the storage bank includes a plurality of segments each having a set of word lines; and a circuit system configured to: receive an activation (ACT) command for a first segment of the plurality of segments while performing a refresh operation on the storage bank; determine, in response to receiving the ACT command, whether to activate a first word line of the set of word lines of the first segment; and generate a signal indicating whether the first word line has been activated.

[0004] In another aspect, this disclosure relates to a method comprising: receiving, while performing a refresh operation on a memory bank, an activation (ACT) command for a first segment of a plurality of segments, the memory bank including the plurality of segments each having a set of word lines; determining, in response to receiving the ACT command, whether to activate a first word line of the set of word lines of the first segment; and generating a signal indicating whether the first word line has been activated.

[0005] In other aspects, this disclosure relates to a system comprising: a host device; and a memory device coupled to the host device, the memory device including: a bank of memory cells having a plurality of segments each having a set of word lines; and a circuit system configured to: receive an activation (ACT) command for a first segment of the plurality of segments while performing a refresh operation on the bank; determine, in response to receiving the ACT command, whether to activate a first word line of the set of word lines of the first segment; and generate a signal indicating whether the first word line has been activated. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. Components in the drawings are not necessarily drawn to scale. The focus is on clearly illustrating the principles of the invention.

[0007] Figure 1 A block diagram illustrating an embodiment of a memory device according to the present invention.

[0008] Figure 2A A block diagram illustrating the memory cell storage bank of a memory device according to an embodiment of the present invention, and Figure 2B A block diagram illustrating a segment of the memory bank of a memory cell according to an embodiment of the present invention.

[0009] Figure 3 A block diagram of a system having a memory device configured according to an embodiment of the present invention.

[0010] Figure 4 A flowchart illustrating a method for operating a memory device according to an embodiment of the present invention. Detailed Implementation

[0011] Methods, systems, and apparatuses for memory devices (e.g., DRAM) that provide conditional row activation and access during refresh operations are disclosed. Some semiconductor memory devices, such as DRAM, store data as charge accumulated in cell capacitors (“cells”). Due to the voltage difference between the capacitor and surrounding components, the charge accumulated in the cell capacitor may escape (which may be referred to as “leakage”) to surrounding components connected to the cell capacitor (e.g., metal wires, semiconductor junctions of transistors). A refresh operation may update the cell charge before it decreases to a point where the charge level no longer corresponds to the original bit value (which can cause a bit error). Therefore, a host device (e.g., a memory controller) may need to periodically issue refresh commands to maintain the integrity of data stored in the memory device.

[0012] A refresh command may be associated with a duration (e.g., tRFC) during which the refresh command is executed. In some embodiments, the duration associated with a refresh command is determined based on the storage capacity of the memory device and / or the number of memory cells to be refreshed in response to the refresh command—e.g., tRFC1 associated with a REFab command for refreshing memory cells of all memory banks in the memory array, a REFsb command for refreshing memory cells of a single memory bank in the memory array, etc. After a refresh command (e.g., REFab command, REFsb command) is issued, the entire memory device (e.g., for the REFab command) or a single memory bank of the memory device (e.g., for the REFsb command) may be blocked for the duration (e.g., tRFC1 for the REFab command, tRFCsb for the REFsb command) to avoid subsequent operations that could cause data corruption. In some cases, the command and / or data bus between the memory device and the host device may remain idle throughout the tRFC cycle. Therefore, the total bandwidth of the memory device may be reduced due to the duration (e.g., tRFC) associated with the refresh command, during which the command and / or data bus is not utilized.

[0013] Several embodiments of the present invention relate to improving the overall command and / or data bandwidth of a memory device by allowing a host device to issue an Activation (ACT) command during a tRFC cycle after issuing a refresh command—for example, when a refresh command is issued to a single bank or the entire bank of memory. For example, the specifications of the memory device (e.g., a datasheet) may describe that, after a refresh command is issued to the memory device, the host device may issue an ACT command to the memory device during the tRFC cycle associated with the refresh command. Furthermore, during a predetermined time period after the issuance of the ACT command, the specifications may instruct the host device to monitor indicator signals at predetermined pins of the memory device.

[0014] An indicator signal informs the host device whether an ACT command has been accepted. If the indicator signal indicates that an ACT command has been accepted (e.g., the row of the memory targeted by the ACT command has been activated), the host device can issue a command for that row to perform memory operations associated with that row while simultaneously performing a refresh operation on the memory. In this way, the command and / or data bus can be utilized for at least a portion of the tRFC cycle, thereby increasing the overall bandwidth of the memory device.

[0015] In this regard, the memory device can be configured to determine whether to execute an ACT command based on certain conditions—and thus, conditional row activation. In some embodiments, the memory device makes this determination based on which row (e.g., which address) the refresh operation is taking place in the memory and how the row targeted by the introduced ACT command is aligned with the row being refreshed. This determination is made to prevent corruption of the data being refreshed, as described in more detail herein. If the memory device determines to execute the introduced ACT command, then the memory device also generates an indicator signal indicating that the row is active. The memory device transmits the indicator signal to the host device via a predetermined pin of the memory device for a predetermined period of time specified in the data table. Similarly, if the memory device determines not to execute the introduced ACT command (e.g., to avoid data corruption during a refresh operation), then the memory device generates an indicator signal indicating that the row is not yet active, allowing the memory device to transmit the indicator signal to the host device.

[0016] refer to Figure 1 A memory device supporting embodiments of the present invention is described. References Figure 2A and 2B A more detailed description of the memory bank of the memory cell supporting embodiments of the present invention is provided. (See also...) Figure 3 A memory system comprising a memory device according to embodiments of the present invention is described. References Figure 4 A method for operating a memory device according to an embodiment of the present invention is described.

[0017] Figure 1 A block diagram illustrating an embodiment of the memory device 100 according to the present invention is provided. The memory device 100 may include a memory cell array, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., ...). Figure 1 The memory bank in the example comprises 0 to 15, and each memory bank may include multiple word lines (WL), multiple bit lines (BL), and multiple memory cells (e.g., m × n memory cells) arranged at the intersections of the word lines (e.g., m word lines, which may also be referred to as rows) and the bit lines (e.g., n bit lines, which may also be referred to as columns or number lines). In some embodiments, each memory bank includes multiple segments, each having a set of word lines. The set of word lines within a segment may be configured to share a sense amplifier (SAMP), as referenced. Figure 2A and 2B More detailed description. In some embodiments, each bit line address (each column address) associated with a particular row may include multiple memory cells coupled via a hierarchical bit line architecture having local and master / global bit lines—for example, multiple bit lines (columns) across multiple memory banks.

[0018] Memory cells may include any of several different memory media types, including capacitive, phase-change, magnetoresistive, ferroelectric, etc. In some embodiments, a portion of the memory array 150 may be configured to store ECC bits. The selection of word lines WL may be performed by row decoder 140, and the selection of bit lines BL may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may then be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that can act as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0019] The memory device 100 may employ multiple external terminals, including command and address terminals coupled to the command bus and address bus to receive command signal CMD and address signal ADDR, respectively. The memory device may further include: a chip select terminal for receiving a chip select signal CS; clock terminals for receiving clock signals CK and CKF; data clock terminals for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI (for data bus transposition function), and DMI (for data mask inversion function); and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0020] Address signals and memory address signals can be supplied externally to the command and address terminals. The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive address signals and supply the decoded row address signal (XADD) to the row decoder 140 (which may be referred to as a row driver), and supply the decoded column address signal (YADD) to the column decoder 145 (which may be referred to as a column driver). The address decoder 110 can also receive the memory address portion of the ADDR input and supply the decoded memory address signal (BADD), and supply the memory address signal to both the row decoder 140 and the column decoder 145.

[0021] Command signal CMD, address signal ADDR, and chip select signal CS can be supplied from the memory controller to the command and address terminals. The command signal can represent various memory commands from the memory controller (e.g., refresh commands, activation (ACT) commands, precharge commands, access commands, etc., which may include read and write commands). The select signal CS can be used to select the memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, commands and addresses can be decoded, and memory operations can be performed. The command signal CMD can be provided as an internal command signal ICMD to the command decoder 115 via the command / address input circuit 105.

[0022] Command decoder 115 may include circuitry that decodes internal command signals ICMD to generate various internal signals and commands for performing memory operations (e.g., row command signals for selecting word lines and column command signals for selecting bit lines). Other examples of memory operations that memory device 100 may perform based on decoding internal command signals ICMD include refresh commands (e.g., re-establishing full charge in individual memory cells stored in memory array 150), activation commands (e.g., activating rows in a particular bank), or precharge commands (e.g., deactivating activated rows in a particular bank). Internal command signals may also include output and input activation commands, such as timing commands CMDCK (…). Figure 1 (Not shown in the text).

[0023] In some embodiments, the command decoder 115 may further include one or more registers 118 for tracking various counts and / or values ​​(e.g., counts of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100), and / or for storing various operating conditions of the memory device 100 to perform certain functions, features, and modes (or test modes). Therefore, in some embodiments, register 118 (or a subset of register 118) may be referred to as a mode register. Alternatively, the memory device 100 may include register 118 as a separate component independent of the command decoder 115. In some embodiments, register 118 may include a multipurpose register (MPR) configured to write dedicated data to and / or read dedicated data from the memory device 100.

[0024] When a read command is issued to a memory bank with open rows and the column address is supplied in a timely manner as part of the read command, read data can be read from a memory cell in memory array 150 specified by the row address (which may have been provided as part of an activation command to identify the open row) and the column address. The read command can be received by command decoder 115, which can provide internal commands to input / output circuitry 160, such that read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuitry 160 according to the RDQS clock signal. Read data can be provided at a time defined by read delay information RL, which can be programmed in memory device 100, for example, in a mode register (e.g., register 118). Read delay information RL can be defined based on the clock cycles of the CK clock signal. For example, read delay information RL can be the number of clock cycles of the CK signal after the read command is received by memory device 100 when the associated read data is provided.

[0025] When a write command is issued to a memory bank with open rows and the column address is supplied in a timely manner as part of the write command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the input / output circuit 160, such that the write data can be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data can be written to the memory cell specified by the row address and column address. The write data can be supplied to the data terminals at a time defined by the write delay information WL. The write delay information WL can be programmed in the memory device 100, for example, in a mode register (e.g., register 118). The write delay information WL can be defined based on the clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0026] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0027] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ can be supplied together with the power supply potential VSS to the input / output circuit 160. In an embodiment of the invention, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of the invention, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used in the input / output circuit 160 so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0028] External clock signals and complementary external clock signals can be supplied to the clock terminal and data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. The complementary clock signals can simultaneously have transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0029] The input buffer included in clock input circuit 120 can receive external clock signals. For example, when enabled by the CKE signal from command decoder 115, the input buffer can receive CK and CKF signals as well as WCK and WCKF signals. Clock input circuit 120 can receive external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115.

[0030] For example, the internal clock circuit 130 may include a clock path ( Figure 1 (Not shown in the diagram), it receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. The internal clock circuit 130 can further provide input / output (IO) clock signals. The IO clock signal can be supplied to the input / output circuit 160 and can be used as a timing signal to determine the output timing for reading data and the input timing for writing data. The IO clock signal can be provided at multiple clock frequencies, allowing data to be output from and input to the memory device 100 at different data rates. A higher clock frequency may be desirable when high memory speed is required. A lower clock frequency may be desirable when lower power consumption is desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0031] The memory device 100 can be connected to any of a plurality of electronic devices, or components thereof, capable of temporarily or permanently storing information using the memory. For example, the host device of the memory device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a plurality of other products. In one embodiment, the host device can be directly connected to the memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a network connection or via an intermediary device).

[0032] In some embodiments, when memory device 100 is performing a refresh operation on memory array 150—for example, in response to receiving a refresh command from a host device—memory device 100 receives an ACT command from a host device coupled to memory device 100. The ACT command includes address information (e.g., XADD, YADD, BADD) that allows memory device 100 to identify a specific word line included in a segment of the memory bank targeted by the ACT command. Subsequently, memory device 100 may determine whether to activate the specific word line based on the currently ongoing refresh operation on the memory bank. In some examples, memory device 100 determines that the specific word line can be safely activated and subsequent commands (e.g., read / write commands) executed for the word line can be performed without risking corruption of the data currently being refreshed on the memory bank. Therefore, memory device 100 may continue to activate the specific word line and generate a signal indicating that the word line is activated (e.g., an indicator signal). In other examples, memory device 100 may determine that the specific word line can be unsafely activated due to the risk of corrupting the data being refreshed. In such examples, memory device 100 generates a signal indicating that the specific word line is not activated.

[0033] Figure 2A A block diagram illustrating the storage body of a memory cell in a memory device (e.g., memory device 100, memory device 300) according to an embodiment of the present invention. Figure 2A Description of storage unit 260, which may be used as a reference. Figure 1 Examples of aspects of the memory bank of the described memory array 150 may be included. Furthermore, the memory bank 260 may be configured to include multiple segments of memory cells (e.g., segments individually identified as S0 to S11). The memory bank 260 also includes gaps 265 (also individually identified as 265a to 265d) located between adjacent segments. In some embodiments, a sense amplifier (e.g., referring to...) Figure 1The described SAMP is located in individual gaps 265, and therefore gaps 265 can be referred to as sense amplifier gaps. In this way, the memory bank 260 can be divided into segments, and individual segments are coupled to corresponding gaps 265 (e.g., sense amplifiers located in gaps 265). Thus, a segment (e.g., memory cells within a segment) can be considered as sharing a sense amplifier.

[0034] Figure 2B A block diagram illustrating a segment (e.g., segment S10) of a memory bank 260 according to an embodiment of the present invention. The segment includes a set of word lines (R0 to Ri-1) depicted extending horizontally. Furthermore, the segment includes a set of bit lines (not shown) generally in a vertical direction relative to the word lines, such that memory cells can be arranged at the intersections of the word lines and bit lines.

[0035] Return to view Figure 2A When the memory device (e.g., the control circuitry 306 of the memory device 300) performs a refresh operation on the memory bank 260, the memory device can utilize an internal counter (e.g., a reference counter). Figure 1 The described register 118 is used to track which segments (and / or which word lines within individual segments) have been refreshed and which segments remain pending refresh. For example, if the memory device performs a refresh operation on segment S4, then before moving to the next segment (e.g., segment S5), the memory device may use an internal counter to iterate through each of the word lines (e.g., R0 to Ri-1) within segment S4 until the memory device has completed refresh operations on all segments within memory bank 260.

[0036] Furthermore, since a refresh operation involves sensing (e.g., using a SAMP) and recovering data from memory cells coupled to the word line being refreshed, the memory device can decouple (e.g., isolate, reserve, or otherwise prevent activation or selection by the memory device's column addressing scheme) the bit lines associated with the word line undergoing a refresh operation—for example, the bit lines associated with the segment S4 currently being refreshed. In some embodiments, multiple segments within the memory may be configured to share a set of bit lines (e.g., local bit lines).

[0037] For example, memory bank 260 describes segments S2 through S6 as sharing a set of bit lines. Therefore, when the memory device performs a refresh operation on segment S4 and disconnects the bit lines associated with segment S4 during the refresh operation, activating a row in any of segments S2, S3, S5, and S6 (and selecting and / or activating a column associated with said segment) will corrupt the data refreshed for segment S4. Therefore, when the memory device refreshes segment S4 (or any of segments S2 through S6), since two word lines (e.g., one from segment S4 and the other from segment S5) are coupled to the shared bit lines between segments S4 and S5, activating any row in segments S2, S3, S5, and S6 to perform a memory operation on said row will corrupt the data refreshed for segment S4. Therefore, if the memory device determines that the introduced ACT command is for a word line in a segment sharing bit lines, the memory device may determine not to execute the introduced ACT command.

[0038] However, memory bank 260 specifies that other segments (e.g., segments S0, S1, and S7 through S11) do not share the set of bit lines associated with segments S2 through S6. Therefore, activating a row in any of segments S0, S1, and S7 through S11 and selecting and / or activating columns associated with other segments will not pose a risk of data corruption for the data being refreshed for segment S4. In some embodiments, the memory device may check that the column selection (CS) device configured to activate the set of bit lines associated with segments S2 through S6 was not activated (e.g., floated, uncoupled, deactivated, or otherwise disabled) before executing an ACT command introduced for other segments (e.g., segments S0, S1, and S7 through S11). In this way, if the memory device determines that an ACT command introduced for another segment is executed and subsequent commands for said segment are executed, the memory device ensures that the data being refreshed (e.g., in segment S4) is not at risk of data corruption. In some embodiments, the column selection scheme of the memory device may be segmented so that only a portion of a segment within the memory can be activated (or selected) at a time. For example, columns (bit lines) associated with the first half of a segment (e.g., segments S0 to S5) may be selected at a time, but the second half of the segment (e.g., segments S6 to S11) may not be selected, or vice versa, to prevent the risk of data corruption.

[0039] Due to various proprietary reasons, the details of the internal implementation of refresh operations can be hidden from the host device coupled to the memory device. For example, the memory device may be configured to perform refresh operations in a specific order within the memory—e.g., based on the bit pattern of the data stored in each segment. In other instances, the memory device may combine the performance of refresh operations with other special operations—e.g., error checking and cleanup operations. Therefore, the host device may not know how to proceed with refresh operations after issuing a refresh command to the memory device. However, the present invention allows the host device to issue an ACT command during a period of time (e.g., tRFC) after issuing a refresh command (without knowing which addresses would be accepted), during which time the host device is otherwise prohibited from issuing any commands to the memory array. Subsequently, the host device may monitor one or more predetermined pins of the memory device (e.g., by parameters determined in a data table) for a predetermined period of time to be notified whether the ACT command (e.g., whether the row specified by the ACT command has been activated) has been accepted (by an indicator signal).

[0040] In some embodiments, the memory device may configure one or more existing pins to provide such notifications to the host device—for example, to transmit indicator signals to the host device. For instance, the memory device may configure an alert pin (ALERT_n) and / or certain data pins or terminals (e.g., DQ terminals) to transmit indicator signals to the host device. In other instances, the memory device may include one or more pins (RFUs) reserved for future use, which may be configured to transmit indicator signals to the host device. Since the datasheet specifies that the host device monitors the indicator signals during a predetermined time period, the memory device may be configured to transmit indicator signals via one or more pins during the predetermined time period. If the host device receives an indicator signal indicating that an ACT command has been accepted (e.g., a word line included in an ACT command has been activated), the host device may issue one or more commands for the activated word line.

[0041] While the foregoing examples describe and illustrate a memory device performing a refresh operation in response to receiving a refresh command from a host device, the present invention is not limited thereto. For example, the memory device may initiate a refresh operation on its own (e.g., self-refresh, automatic refresh) without receiving an external command, and the present invention facilitates the memory device accommodating access commands during such self-initiated refresh operations. Furthermore, the present invention is not limited to DRAM technology and can be applied to various memory technologies that require periodic restoration of data written to memory cells—for example, refresh for DRAM technology.

[0042] Figure 3A block diagram of a system 301 having a memory device 300 configured according to an embodiment of the present invention. The memory device 300 may be a reference. Figures 1 to 2B Examples of aspects of the described memory device (e.g., memory device 100) or include said aspects. As shown, memory device 300 includes main memory 302 (e.g., DRAM, NAND flash, NOR flash, FeRAM, PCM, etc.) and control circuitry 306 operatively coupled to host device 308 (e.g., upstream central processing unit (CPU), memory controller). Control circuitry 306 may include references Figures 1 to 2B The various components described herein. For example, the control circuit system 306 may include aspects such as command / address input circuitry 105, address decoder 110, command decoder 115, column decoder 140, row decoder 145, etc. Furthermore, the control circuit system 306 may perform the functions described above. Figure 2A and 2B The various operations described.

[0043] Main memory 302 includes a plurality of memory cells 320, each comprising a plurality of memory cells. Memory cells 320 may be individual memory dies, memory planes within a single memory die, stacks of memory dies vertically connected to through-silicon vias (TSVs), etc. For example, in one embodiment, each of the memory cells 320 may be formed from a semiconductor die and disposed within a single device package along with other memory cell dies. In other embodiments, the plurality of memory cells 320 may be co-located on a single die and / or distributed across multiple device packages. In some embodiments, memory cells 320 may further be subdivided into memory regions 328 (e.g., memory banks, memory rows, channels, blocks, pages, etc.).

[0044] Memory cells may include, for example, floating gates, charge traps, phase-changing, capacitive, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to store data persistently or semi-persistently. Main memory 302 and / or individual memory cells 320 may also include other circuit components, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc., for accessing and / or programming (e.g., writing) memory cells and other functions, such as processing information and / or communicating with control circuitry 306 or host device 308. While a certain number of memory cells, rows, columns, areas, and memory units are shown in the illustrated embodiments for illustrative purposes, the number of memory cells, rows, columns, areas, and memory units may vary, and in other embodiments, the proportions may be larger or smaller than those shown in the illustrated examples. For example, in some embodiments, memory device 300 may include only one memory cell 320. Alternatively, the memory device 300 may include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory cells 320. Although the memory cells 320 are... Figure 3 The present invention is shown to include four memory regions 328, but in other embodiments, each memory unit 320 may include one, two, three, eight or more (e.g., 16, 32, 64, 100, 128, 256 or more) memory regions.

[0045] In one embodiment, the control circuitry 306 may be located on the same die as the main memory 302 (e.g., including command / address / clock input circuitry, decoders, voltage and timing generators, input / output circuitry, etc.). In another embodiment, the control circuitry 306 may be a microcontroller, a special-purpose logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a control circuitry system on the memory die, etc.), or other suitable processor. In one embodiment, the control circuitry 306 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines for controlling the operation of the memory device 300, including managing the main memory 302 and handling communication between the memory device 300 and the host device 308. In some embodiments, the control circuitry 306 may include embedded memory having memory registers for storing, for example, memory addresses, row counters, bank counters, memory pointers, acquired data, etc. In another embodiment of the invention, the memory device 300 may not include control circuitry and may rely virtually on external control (e.g., provided by the host device 308 or by a processor or controller separate from the memory device 300).

[0046] The host device 308 may be any one of a plurality of electronic devices, or a component thereof, capable of temporarily or permanently storing information using memory. For example, the host device 308 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device 308 may be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a plurality of other products. In one embodiment, the host device 308 may be directly connected to the memory device 300, but in other embodiments, the host device 308 may be indirectly connected to the memory device (e.g., via a network connection or via an intermediary device).

[0047] In operation, the control circuitry 306 can directly write to or otherwise program (e.g., erase) the various memory regions of the main memory 302. The control circuitry 306 communicates with the host device 308 via a host device bus or interface 310. In some embodiments, the host device 308 and the control circuitry 306 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 308 and the control circuitry 306 can communicate via a serial interface, such as a serially connected SCSI (SAS), serial AT accessory (SATA) interface, peripheral component interconnect high speed (PCIe), or other suitable interface (e.g., a parallel interface). The host device 308 can send various requests (in the form of packets or packet streams, for example) to the control circuitry 306. Requests may include commands for reading, writing, erasing, returning information, and / or performing specific operations (e.g., refresh operations, TRIM operations, precharge operations, activation operations, wear leveling operations, garbage collection operations, etc.).

[0048] In some embodiments, the memory device 300 includes a bank of memory cells. The bank may include multiple segments, each having a set of word lines. Furthermore, the memory device 300 may include circuitry (e.g., control circuitry 306) configured to: receive an activation (ACT) command for a first segment of the plurality of segments while performing a refresh operation on the bank; determine, in response to receiving the ACT command, whether a first word line of the first segment's set of word lines is activated; and generate a signal indicating whether the first word line is activated. In some embodiments, a host device 308 is configured to monitor the signal for a predetermined time period while transmitting the ACT command to the memory device. Furthermore, if the signal indicates that the first word line is activated, the host device 308 may be configured to transmit an access command for the first word line.

[0049] Figure 4The flowchart 400 illustrates a method for operating a memory device (e.g., memory device 100) according to an embodiment of the present invention. Flowchart 400 may be a memory device (e.g., control circuitry 306) as shown in the reference diagram. Figures 1 to 3 An instance of or including the aspects of the method described and performed.

[0050] The method includes receiving an activation (ACT) command for a first segment of a plurality of segments (block 410) at a memory device having memory cells at the same time as performing a refresh operation on the memory bank. According to one aspect of the invention, this can be achieved through... (See reference...) Figures 1 to 3 The described control circuit system 306 executes the features of the receiving frame 410.

[0051] The method further includes determining, in response to receiving an ACT command, whether to activate a first word line (box 415) of a set of word lines in the first segment. According to one aspect of the invention, this can be achieved through, as referenced... Figures 1 to 3 The described control circuit system 306 performs the features of the determination block 415.

[0052] The method further includes generating a signal indicating whether the first word line has been activated (box 420). According to one aspect of the invention, this can be achieved through, as referenced... Figures 1 to 3 The described control circuit system 306 performs the features of generating block 420.

[0053] In some embodiments, the memory device performs a refresh operation in response to receiving a refresh command before receiving an ACT command. In some embodiments, the method may further include determining that the refresh operation is for a second segment of a plurality of segments, the second segment being different from the first segment. In some embodiments, the method may further include activating a first word line of the first segment in response to determining that the refresh operation is for the second segment, and generating a signal indicating that the first word line of the first segment has been activated.

[0054] In some embodiments, the method may further include performing an operation in response to an access command for the first word line if the memory device determines that a first word line of the first segment is activated. In some embodiments, the method may further include configuring at least one of a warning pin, a data pin, or a pin of the memory device for transmitting a signal to a host device coupled to the memory device. In some embodiments, the method may further include transmitting a signal to the host device coupled to the memory device for a predetermined time period after receiving an ACT command.

[0055] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods described can be combined.

[0056] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0057] The devices, including memory devices, discussed herein can be formed on semiconductor substrates or dies, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0058] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed such that portions of the functionality are implemented in different physical locations.

[0059] As used herein, the word "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates a list including endpoints, such that a list of at least one of A, B, or C means A or B or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0060] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. Generally, it should be understood that various other devices, systems, and methods besides the specific embodiments disclosed herein are within the scope of the invention.

Claims

1. A device for memory operations, comprising: At least one bank of memory cells, wherein each bank includes multiple segments, each having a set of word lines; and The circuit system is configured as follows: While performing a refresh operation on the same memory bank of at least one memory bank of the memory cell, an activation ACT command is received for the first segment of the plurality of segments; In response to receiving the ACT command, based on whether the refresh operation is for the first segment, determine whether to activate the first word line of the group of word lines in the first segment; as well as A signal is generated indicating whether the first word line has been activated.

2. The device of claim 1, wherein the ongoing refresh operation is based on a refresh command received prior to receiving the ACT command.

3. The device according to claim 1, wherein the circuit system is further configured to: The refresh operation is determined to be performed on the second segment of the plurality of segments, the second segment being different from the first segment.

4. The device according to claim 3, wherein the circuit system is further configured to: In response to determining that the refresh operation will be performed on the second segment, the first word line of the first segment is activated; and A signal is generated indicating that the first word line of the first segment has been activated.

5. The device of claim 3, wherein the first segment is not coupled to a bit line associated with the second segment during the refresh operation.

6. The device of claim 3, wherein each memory bank includes a third segment of the plurality of segments, the third segment being different from the first segment and the second segment, and coupled to a bit line associated with the second segment during the refresh operation.

7. The device according to claim 1, wherein the circuit system is further configured to: If the circuit system determines that the first word line of the first segment is activated, then an operation is performed in response to an access command for the first word line.

8. The device of claim 1, wherein the device includes at least one of a warning pin, a data pin, or a pin, and the circuitry is further configured to: The warning pin, the data pin, or at least one of the pins is configured to transmit the signal to a host device coupled to the device.

9. The device according to claim 1, wherein the circuit system is further configured to: In response to receiving the ACT command, the signal is transmitted to a host device coupled to the device within a predetermined time period.

10. The device of claim 1, wherein the memory cell of each storage bank comprises a dynamic random access memory (DRAM) cell.

11. A method for memory operations, comprising: An activation ACT command for a first segment of a plurality of segments is received at a memory device having at least one memory bank of memory cells, while a refresh operation is performed on the same memory bank of the at least one memory bank of the memory cells, each memory bank of the at least one memory bank including the plurality of segments each having a set of word lines. In response to receiving the ACT command, based on whether the refresh operation is for the first segment, determine whether to activate the first word line of the group of word lines in the first segment; as well as A signal is generated indicating whether the first word line has been activated.

12. The method of claim 11, wherein the memory device performs the refresh operation in response to a refresh command received prior to receiving the ACT command.

13. The method of claim 11, further comprising: It is determined that the refresh operation is applied to the second segment of the plurality of segments, which is different from the first segment.

14. The method of claim 13, further comprising: In response to determining that the refresh operation is for the second segment, the first word line of the first segment is activated; and A signal is generated indicating that the first word line of the first segment has been activated.

15. The method of claim 11, further comprising: If the memory device determines that the first word line of the first segment is activated, then an operation is performed in response to an access command for the first word line.

16. The method of claim 11, further comprising: At least one of the warning pin, data pin, or pin of the memory device is configured to transmit the signal to a host device coupled to the memory device.

17. The method of claim 11, further comprising: After receiving the ACT command, the signal is transmitted to the host device coupled to the memory device within a predetermined time period.

18. A system for memory operations, comprising: Main unit; as well as A memory device coupled to the host device, the memory device comprising: At least one bank of memory cells, each bank having multiple segments each having a set of word lines; and The circuit system is configured as follows: While performing a refresh operation on the same memory bank of at least one memory bank of the memory cell, an activation ACT command is received for the first segment of the plurality of segments; In response to receiving the ACT command, based on whether the refresh operation is applied to the first segment, determine whether to activate the first word line of the group of word lines in the first segment; and A signal is generated indicating whether the first word line has been activated.

19. The system of claim 18, wherein the host device is configured to: After the ACT command is transmitted to the memory device, the signal is monitored for a predetermined time period.

20. The system of claim 18, wherein the host device is configured to: If the signal indicates that the first word line has been activated, then an access command for the first word line is transmitted.

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