Method and system for facilitating dynamic hardware resource allocation in an active switch

Abstract

Embodiments of the present disclosure relate to methods and systems for facilitating dynamic hardware resource allocation in an active switch. A dynamic resource allocation system in a switch is provided. During operation, the system may represent a first subset of hardware elements of the switch to an operating unit of the switch, the first subset being assigned to the operating unit as a logical element. The system may then determine a request for dynamically reallocating the hardware elements to the operating unit. Accordingly, the system may determine whether reallocation of the hardware elements is feasible in the switch. If reallocation of the hardware elements is feasible, the system may allocate a second subset of the hardware elements to the operating unit during runtime of the switch. The system may then merge the second subset of the hardware elements into the logical element.

Description

Technical Field

[0001] The present disclosure relates to communication networks. More particularly, the present disclosure relates to methods and systems for dynamically allocating hardware resources in an active switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 An exemplary network with a switch supporting dynamic hardware resource allocation based on resource virtualization according to an embodiment of the present application is illustrated.

[0003] Figure 2A An exemplary process of dynamically increasing memory resources allocated to an operation unit of a switch according to an embodiment of the present application is illustrated.

[0004] Figure 2B An exemplary process of dynamically reducing memory resources allocated to an operation unit of a switch according to an embodiment of the present application is illustrated.

[0005] Figure 3A An exemplary process of managing counter resources of a switch according to an embodiment of the present application is illustrated.

[0006] Figure 3B An exemplary process of dynamically increasing counter resources allocated to an operation unit of a switch according to an embodiment of the present application is illustrated.

[0007] Figure 3C An exemplary process of dynamically reducing counter resources allocated to an operation unit of a switch according to an embodiment of the present application is illustrated.

[0008] Figure 4A A flow chart illustrating a process in which a switch dynamically increases memory resources allocated to an operation unit of the switch according to an embodiment of the present application is presented.

[0009] Figure 4B A flow chart illustrating a process in which a switch dynamically reduces memory resources allocated to an operation unit of the switch according to an embodiment of the present application is presented.

[0010] Figure 5A A flowchart illustrating a process in which a switch dynamically increases counter resources allocated to an operation unit of the switch according to an embodiment of the present application is presented.

[0011] Figure 5B A flow chart illustrating a process in which a switch dynamically reduces counter resources allocated to an operation unit of the switch according to an embodiment of the present application is presented.

[0012] Figure 6 An exemplary switch supporting efficient multicast forwarding across overlay tunnels according to an embodiment of the present application is illustrated.

[0013] In the drawings, like reference numerals refer to like drawing elements. DETAILED DESCRIPTION

[0014] The following description is presented so that any person skilled in the art can make and use the invention, and is provided in the context of a specific application and its requirements. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the illustrated embodiments, but is intended to be accorded the widest scope consistent with the claims.

[0015] Overview

[0016] The Internet is a delivery medium for various applications running on physical and virtual devices. This application has brought about an increasing demand for services. Therefore, equipment vendors compete to build switches with multiple capabilities. Therefore, a switch may include multiple operating units to support its capabilities. The resulting complexity of the switch may increase the difficulty of efficiently allocating hardware resources to specific operating units. Typically, the corresponding operating unit may be equipped with a static and predefined set of hardware resources. However, during the operation time of the switch (i.e., when the switch is in an active state), the operating unit may exhaust its allocated resources. On the contrary, another operating unit may not fully utilize its allocated resources.

[0017] One embodiment of the present invention provides a system that can facilitate dynamic resource allocation in a switch. During operation, the system can represent to an operating unit of the switch a first subset of hardware elements of the switch, the first subset being allocated to the operating unit as a logical element. The system can then determine a request to dynamically reallocate the hardware elements to the operating unit. Thus, the system can determine whether reallocation of the hardware elements is feasible in the switch. If reallocation of the hardware elements is feasible, the system can allocate a second subset of the hardware elements to the operating unit during runtime of the switch. The system can then merge the second subset of the hardware elements into the logical element.

[0018] In a variation on this embodiment, the hardware elements of the switch may comprise a collection of ternary content addressable memory (TCAM) cells. The logical elements may then be logical TCAM cells presented to the operating unit.

[0019] In a variation on this embodiment, the hardware element of the switch comprises a collection of memory segments of a central memory of the switch, and wherein the logical element is a logical memory segment presented to the operating unit.

[0020] In a variation on this embodiment, the hardware element of the switch may comprise a set of counter groups of hardware-based counters. The logical element may then be a logical counter group presented to the operating unit.

[0021] In yet another variation, the hardware element of the switch may also include a set of memory counter groups maintained in a central memory of the switch. The system may then refresh the current values ​​of the corresponding counters in the counter group to the corresponding memory counters. Here, the counters may be represented as logical counters in a logical counter group.

[0022] In yet another variation, the system may maintain an accumulation counter for the logical counter. The system may then allocate a second subset of hardware elements by adding the respective values ​​of the counter and the corresponding memory counter to the accumulation counter. The system may then reassociate the logical counter to a new counter in the second subset of hardware elements.

[0023] In a variation on this embodiment, the reallocation of the hardware elements includes adding or reducing the first subset of hardware elements to the second subset of hardware elements. The system can then determine the target hardware elements for the first subset of hardware elements based on the selection policy, and generate the second subset of hardware elements from the first subset of hardware elements.

[0024] In yet another variation, the system may determine whether reallocation of the hardware element is feasible by determining whether the target hardware element can accommodate valid data from the first subset of the hardware elements.

[0025] In a variation on this embodiment, the system may indicate in a register of the switch that the first subset of hardware elements belongs to the logical element. The system may then merge the second subset of hardware elements into the logical element by updating the register to indicate that the second subset of hardware elements belongs to the logical element.

[0026] In a variation on this embodiment, the system can determine whether dynamic reallocation of the third subset of hardware elements assigned to the second operating unit is required due to the allocation of the second subset of hardware elements to the operating unit. If dynamic reallocation to the second operating unit is required, the system can dynamically allocate a fourth subset of hardware elements to the second operating unit.

[0027] In a variation on this embodiment, the system may receive a command indicating a request for dynamic reallocation of hardware elements for operating units. The system may then determine reallocation operations and parameters for the dynamic reallocation.

[0028] Embodiments described herein solve the problem of efficiently allocating hardware resources to corresponding operation units of a switch by (i) maintaining the hardware resources of a switch as a global pool that can be allocated to different operation units, and (ii) dynamically allocating hardware resources from the global pool to the operation units based on an allocation policy. The operation units can operate on the allocated resources without making any changes to the operation units.

[0029] Using the prior art, the hardware resources of the switch (such as application specific integrated circuit (ASIC) resources) are pre-allocated to the operation unit based on static allocation. Examples of hardware resources of the switch include, but are not limited to, random access memory (RAM), hash tables, counter groups, and ternary content addressable memory (TCAM) units. The operation unit can be any hardware and / or software module of the switch that can facilitate the specific capabilities of the switch. For example, the operation unit can facilitate the operation of specific layers of the network protocol stack, such as Layer 2 (e.g., Ethernet processing and forwarding) and Layer 3 (Internet Protocol (IP) processing, routing, and forwarding). The operation unit can also facilitate specialized operations of the switch, such as policy-based forwarding and overlay tunneling.

[0030] The operation unit of the switch may be equipped with hardware resources that are exhausted during runtime. On the other hand, the hardware resources of another operation unit may still be underutilized. For example, a large number of media access control (MAC) addresses may be learned by the switch during operation. Therefore, the TCAM units assigned to the layer 2 operation unit may be overutilized. However, the switch may deploy a small number of policies, so the TCAM units assigned to the policy operation unit may still be underutilized. However, due to static pre-allocation, the switch may not be able to provide more TCAM units to the layer 2 operation unit, or may not be able to use the underutilized TCAM units assigned to the policy operation unit. Therefore, the operation of the switch may become very inefficient. In addition, even for the same operation unit, one type of hardware resources may be exhausted, while another type of hardware resources may still be underutilized. Static pre-allocation of hardware resources may also prevent different types of hardware resources from being adjusted based on current needs.

[0031] To solve this problem, the hardware resources of the switch can be organized in a global pool that can be assigned to different operating units. When allocating hardware resources to operating units, the switch can store identifiers of the hardware resources in registers associated with resource configurations (e.g., configuration registers that can specify which physical resources belong to which logical entity). The switch can then represent the allocated hardware resources as corresponding logical entities. A logical entity can include hardware resources indicated by a register. This allows the switch to determine which hardware resources correspond to the logical entities of an operating unit.

[0032] For example, when a switch assigns a set of TCAM cells to an operating unit, the switch may store an identifier of the TCAM cell in a register (e.g., a TCAM configuration register). The system may then represent the set of TCAM cells as a logical TCAM cell. Similarly, when a switch assigns a set of counter groups to an operating unit, the switch may represent the set of counter groups as a logical counter group. However, the operating unit may perceive the logical TCAM cell and the logical counter group as a physical TCAM cell and a physical counter group, respectively. Therefore, the operating unit may use the logical representation without making any changes to the operating unit.

[0033] To facilitate the logical representation, the switch may maintain a mapping between a corresponding address or index of a physical unit and a corresponding logical address. The physical address space of a TCAM unit may be mapped to the logical address space of a logical TCAM unit. A logical TCAM unit may span multiple physical TCAM units. The capacity (or size) of a logical TCAM unit may be the sum of the corresponding capacities of the physical TCAM units assigned to the operation unit. The corresponding address (or index) of the corresponding physical TCAM unit may be mapped to the corresponding logical address. The operation unit may perform a corresponding operation based on the logical address. The switch may then determine the corresponding physical address and perform the operation on the location identified by the physical address.

[0034] Assume that the switch has allocated two TCAM units to the operation unit. Each TCAM unit can support n entries (i.e., n addresses or indexes) that store x (e.g., a multiple of 32) bits. Then, the logical address space may include 2n addresses. The 2n addresses of the two TCAM units can be mapped to the 2n addresses of the logical address space based on the allocation strategy. Depending on the allocation, sequential addresses in the logical address space can be mapped to sequential or non-sequential addresses in the same or different physical TCAM units. The logical representation allows the switch to dynamically merge or remove the underlying physical TCAM units. For example, if a new TCAM unit with n entries is dynamically allocated to the operation unit, the new TCAM unit is merged into the logical TCAM unit, and the corresponding logical address space is updated to merge 3n addresses. In the same way, if not needed, the switch can remove the TCAM unit from the logical TCAM unit and adjust the logical address space accordingly.

[0035] In addition, other hardware resources can be allocated to the operation unit accordingly. For example, if the switch allocates a TCAM unit with 2n entries to the operation unit, the switch can also dynamically allocate a counter group including 2n counters. The allocated counter group can be represented as a logical counter group with 2n logical counters. Each logical counter can correspond to a physical counter in one of the counter groups. The corresponding physical counter can have y bits. In some embodiments, if the counter reaches a refresh value, the switch can refresh the current value from the counter and merge the physical counter value into the memory (e.g., central memory or static RAM (SRAM)) of the switch. The refresh value can represent a counter value that cannot be increased for subsequent events. Assume that the counter indicates the total number of bytes received by the port. When receiving a packet with multiple bytes that cannot be added to the counter due to the limitation imposed by y number of bits, the switch can determine that the counter has reached its refresh value.

[0036] The counter in the memory may be referred to as a memory counter. The switch may specify a specific location with z bits in the memory for maintaining the memory counter. The memory counter may be initialized with an initial value (e.g., value 0). Whenever the switch refreshes the counter, the switch may add the value of the counter to the current value of the memory counter and reset the counter. Since the counter may be dynamically assigned, a counter group currently assigned to one operating unit may be reallocated to another operating unit. In order to store the value of the reallocated counter group, the switch may maintain an accumulation counter (e.g., a software-based counter) for the corresponding logical counter. For each reallocation, the switch may first add the current value represented by the memory counter and the corresponding physical counter to the accumulation counter. When storing the value in the accumulation counter, the switch may reallocate the counter group and its corresponding memory counter.

[0037] The switch can maintain a mapping between a logical counter and a corresponding physical counter. A register in the switch can indicate which counter groups belong to which logical counter group. In some embodiments, a register associated with a counter group can indicate the location in the memory of a bit representing a corresponding memory counter associated with the counter group (e.g., by maintaining a bitmap). Since each physical counter is assigned a corresponding set of bits in the memory for the memory counter, the mapping can indirectly merge the memory counters based on the location indicated by the register. Therefore, in order to obtain the value of the logical counter, the switch can obtain the value from the physical counter based on the mapping. The switch can also obtain the value from the memory counter based on the location indicated by the bitmap in the register. Subsequently, the switch can add the obtained value to the value of the cumulative counter to determine the logical counter value.

[0038] In the present disclosure, the term "switch" is used in a general sense, and it may refer to any standalone switch or fabric switch operating in any network layer. "Switch" should not be interpreted as limiting embodiments of the present invention to Layer 2 networks. Any device that can forward traffic to an external device or another switch may be referred to as a "switch." Any physical or virtual device (e.g., a virtual machine / switch operating on a computing device) that can forward traffic to a terminal device may be referred to as a "switch." Examples of "switches" include, but are not limited to, Layer 2 switches, Layer 3 routers, routing switches, components of a Gen-Z network, or a fabric switch comprising multiple similar or heterogeneous smaller physical and / or virtual switches.

[0039] The term "packet" refers to a group of bits that can be transported together across a network. "Packet" should not be interpreted as limiting embodiments of the present invention to layer 3 networks. "Packet" may be replaced by other terms referring to a group of bits, such as "message", "frame", "cell", "datagram" or "transaction".

[0040] Network Architecture

[0041] Figure 1 FIG. 1 illustrates an exemplary network having a switch supporting dynamic hardware resource allocation based on resource virtualization according to an embodiment of the present application. Figure 1 As illustrated, network 100 includes switches 102, 104, 106, and 108. In some embodiments, network 100 is a Gen-Z network, and the corresponding switches of network 100 (such as switch 102) are Gen-Z components. Gen-Z networks can be memory semantic structures that can be used to communicate with devices in a computing environment. By unifying communication paths and simplifying software through simple memory semantics, Gen-Z components can facilitate high-performance solutions for complex systems. In this scenario, communication between switches in network 100 is based on memory semantic structures. In some other embodiments, network 100 is an Ethernet and / or IP network, and the corresponding switches of network 100 (such as switch 102) are Ethernet switches and / or IP routers. In this scenario, communication between switches in network 100 is based on Ethernet and / or IP.

[0042] Using existing techniques, hardware resources (such as ASIC resources) of the switch 104 are pre-allocated to operation units such as the operation unit 110 based on static allocation. The hardware resources of the switch 104 may include a central memory 140 (e.g., an SRAM of the switch 104), a plurality of TCAM units 122, 124, and 126, and a plurality of counter groups 132, 134, and 136. The memory 140 may include a plurality of memory segments 142, 144, and 146. The operation unit 110 may be any hardware and / or software module of the switch 104 that may facilitate specific capabilities of the switch 104. For example, the operation unit 110 may facilitate operations of specific layers of a network protocol stack, such as Layer 2 and Layer 3. The operation unit 110 may also facilitate specialized operations of the switch 104, such as policy-based forwarding and overlay tunneling.

[0043] Assume that the TCAM units 122 and 126 and the counter groups 132 and 136 are statically pre-allocated to the operation unit 110. If the operation unit 110 is a layer 2 processing engine of the switch 104, the MAC addresses learned at the switch 110 may be stored in a layer 2 forwarding table (or MAC address table) maintained in the TCAM units 122 and 126. Therefore, the large number of MAC addresses learned at the switch 104 may over-use the TCAM units 122 and 126. However, due to the static pre-allocation, the switch 104 may not be able to provide more TCAM units to the operation unit 110, or may not be able to use the underutilized TCAM units allocated to another unit. Therefore, the operation of the switch 104 may become inefficient. In addition, even for the operation unit 110, the TCAM units 122 and 126 may be exhausted, while the counter group 136 may remain underutilized. Static pre-allocation of hardware resources may also prevent the adjustment of different hardware resources based on current needs.

[0044] To address this issue, the hardware resources of the switch 104 can be organized in a global pool that can be allocated to different operating units. For example, TCAM units 122, 124, and 126 can be organized in TCAM pool 120. Similarly, counter groups 132, 134, and 136 can be organized in counter pool 130. The corresponding physical counters (such as counter 164 in counter group 132) can have y bits. The switch 104 can be equipped with a dynamic allocation system 150, which can allocate the hardware resources of the switch 104 to the operating units 110 during runtime (i.e., when the switch 104 is actively operating and forwarding packets in the network 100). The system 150 can program and configure the underlying hardware resources (e.g., configuration ASIC) for the dynamic allocation of hardware resources.

[0045] During initiation (e.g., a boot or power cycle process), the system 150 may assign the TCAM cells 122 and 126 to the operating unit 110. The switch 150 may store identifiers of the TCAM cells 122 and 126 in a TCAM configuration register, which may specify which physical TCAM cells are assigned to which logical TCAM cells. For example, the register may indicate that the TCAM cells 122 and 126 are assigned to the logical TCAM cell 128. In this way, the system 150 may represent the TCAM cells 122 and 126 as the logical TCAM cell 128 based on the entries in the register. Similarly, the system 150 may assign the counter groups 132 and 136 to the operating unit 110. The system 150 may represent the counter groups 132 and 136 as the logical counter group 138. In the same manner, the system 150 may assign the memory segments 142 and 146 to the operating unit 110. The system 150 may represent the memory segments 142 and 146 as the logical memory segments 148.

[0046] However, the operation unit 110 may perceive the logical TCAM cell 128, the logical counter group 138, and the logical memory segment 148 as a physical TCAM cell, a physical counter group, and a physical memory segment, respectively. Therefore, the operation unit 110 may use the logical representation without making any changes to the operation unit 110. To facilitate the logical representation of the logical TCAM cell 128, the logical counter group 138, and the logical memory segment 148, the system 150 may maintain a mapping between the logical entities and the underlying physical entities. For example, the physical address space of the TCAM cells 122 and 126 may be mapped to the logical address space 150 of the logical TCAM cell 128. The capacity of the logical TCAM cell 128 may be the sum of the corresponding capacities of the TCAM cells 122 and 126.

[0047] The respective addresses (or indices) of the TCAM cells 122 and 126 may be mapped to corresponding logical addresses in the logical address space 150. For example, the address 156 of the TCAM cell 122 and the address 158 of the TCAM cell 126 may be mapped to the logical addresses 152 and 154, respectively. The operation unit 110 may perform operations (e.g., add, remove, and update entries) based on the corresponding logical addresses, such as the logical address 152. By looking up the logical address 152 in the mapping, the system 150 may determine the physical address 156. The switch 104 may then perform the operation on the location identified by the physical address 156.

[0048] Assume that each of the TCAM cells 122 and 126 can support n entries (i.e., n addresses or indices), each of which stores x (e.g., a multiple of 32) bits. Then, the logical address space 150 can include 2n addresses. The 2n addresses of the TCAM cells 122 and 126 can be mapped to the 2n addresses of the logical address space 150 based on the allocation policy. Depending on the allocation, the sequential addresses 152 and 154 can be mapped to sequential or non-sequential addresses in the same or different TCAM cells. The logical TCAM cell 128 allows the system 150 to dynamically merge or remove underlying physical TCAM cells.

[0049] For example, a TCAM unit 124 that can support m entries can be dynamically allocated to an operation unit 110. Then, the TCAM unit 124 can be merged into the logical TCAM unit 128. Therefore, the logical address space 150 is updated to merge 2n+m logical addresses. In the same manner, if not needed, the system 150 can remove the TCAM unit 126 from the logical TCAM unit 128 and adjust the logical address space 150. Therefore, the logical address space 150 is updated to represent n+m logical addresses.

[0050] In addition, if the system 150 allocates TCAM units 122 and 126 having 2n entries to the operation unit 110, the system 150 can also dynamically allocate counter groups 132 and 136 including 2n counters. The counter groups 132 and 136 can be represented as a logical counter group 138 having 2n logical counters. Each logical counter can correspond to a physical counter in the counter group 132 or 136. For example, the logical counter 162 can be mapped to the underlying physical counter 164 in the counter group 132. Therefore, if the operation unit 110 increases the value of the logical counter 162, the system 150 can determine the underlying physical counter 164. The switch 104 can then merge the increment into the physical counter 164.

[0051] Similar to the allocation of TCAM cells, the system 150 can allocate memory segments 142 and 146 to the operation unit 110, which can be separate memory modules or specific portions of the memory 140 represented by corresponding memory ranges. If the capacity of the memory segments 142 and 146 is 2q and q bytes, the capacity of the logical memory segment 148 can be 3q bytes. The corresponding memory location of the logical memory segment 148 can be identified by a logical memory address. The system 150 can maintain a mapping that maps the corresponding memory location of the memory segment 148 to the corresponding physical memory location in the memory segment 142 or 146. When the operation unit 110 performs an operation on the logical memory segment 148 based on the logical address (e.g., read from or write to the logical memory segment 148), the system 150 can obtain the corresponding physical address from the mapping and perform the operation in the physical memory location.

[0052] After the initial allocation, the system 150 can increase or decrease the capacity of the logical TCAM cells 128, logical counter groups 138, and logical memory segments 148. Reducing a logical entity can include deleting the logical unit. The system 150 can provide a set of commands that a user can execute to increase or decrease the logical TCAM cells 128, logical counter groups 138, and logical memory segments 148. For example, a command can be for a logical entity (e.g., a logical TCAM cell or a logical counter group) that can perform an operation (increase, decrease, or delete). The command can receive a set of parameters from the user, such as a target capacity. The system 150 can then perform the operation indicated by the command.

[0053] In other words, the user may not specify which physical element will be allocated for the command. Instead, the user may specify whether to increase or decrease the logical entity and the target capacity. The system 150 may then increase or decrease the logical entity to the target capacity (i.e., dynamically reallocate hardware resources) as needed based on the user command without disrupting the service on the switch 104. In this way, the system 150 may determine the operations and parameters associated with dynamic reallocation.

[0054] Figure 2AAn exemplary process of dynamically increasing memory resources allocated to an operating unit of a switch according to an embodiment of the present application is illustrated. It is assumed that in addition to TCAM units 122, 124, and 126, TCAM pool 120 may also include TCAM units 202, 204, and 206. The TCAM units of TCAM pool 120 may have different capacities (or sizes). For example, TCAM units 122, 124, 126, and 204 may support n entries, TCAM unit 202 may support m entries, and TCAM unit 206 may support p entries. Each entry in a TCAM unit may support x bits (e.g., a multiple of 32). In some embodiments, the values ​​of n, m, and p may be 2048, 1024, and 4096, respectively. System 150 may allocate TCAM units 122 and 126 to operating unit 110 as logical TCAM unit 128. Similarly, system 150 may allocate TCAM unit 204 to operating unit 210 as logical TCAM unit 228. Thus, logical TCAM cells 128 and 228 may represent 2n and n entries, respectively.

[0055] After the initial allocation, the system 150 can increase or decrease the respective capacities of the logical TCAM cells 128 and 228. During operation, the user may determine that the logical TCAM cell 128 may need to accommodate more entries for the operating unit 110. The user may then issue a command to the system 150 to dynamically increase the capacity of the logical TCAM cell 128 to a new target capacity (e.g., to accommodate 2n+m entries). The system 150 may then determine which available TCAM cells in the TCAM pool 120 can meet the target capacity requirements. Subsequently, the system 150 may select a target TCAM cell in such a way that the logical TCAM cell 128 can accommodate the new target capacity. The system 150 may then accommodate the target TCAM cell into the logical TCAM cell 128.

[0056] In some embodiments, the system 150 may deploy a selection strategy for selecting a target TCAM cell. Examples of selection strategies may include, but are not limited to, efficient fit selection, incremental fit selection, first available selection, and random selection. For efficient fit selection, the system 150 may select a target TCAM cell (or cells) with the smallest capacity that can accommodate the target capacity with the smallest residual capacity (e.g., a capacity greater than the target capacity). The system 150 may then determine whether the selection requires data transfer based on whether the target TCAM cell replaces the currently allocated TCAM cell.

[0057] The system 150 may determine that the available TCAM cells 124, 202, and 206 have capacities n, m, and p, respectively. If 2n+m=p, the system 150 may select TCAM cell 206 as the target TCAM cell. Since TCAM cell 206 may replace the currently allocated TCAM cells 122 and 126, the system 150 may determine that a data transfer is required. The system 150 may then transfer valid entries from TCAM cells 122 and 126 to TCAM cell 206, merge TCAM cell 206 into logical TCAM cell 128, and release TCAM cells 122 and 126 for subsequent allocation (indicated by dashed arrows). To merge TCAM cell 206 into logical TCAM cell 128, the system 150 may update the TCAM configuration register.

[0058] On the other hand, for incremental fit selection, system 150 may select the target TCAM cell(s) with the smallest capacity that can accommodate the incremental capacity with the smallest residual capacity. System 150 may then determine whether the selection requires data transfer based on whether the current entry requires redistribution. Figure 2A In the example of , system 150 may select TCAM cell 202 as the target TCAM cell (indicated by the dashed arrow). Since TCAM cell 202 may provide more redistribution of current entries, system 150 may determine that data transfer is required.

[0059] Therefore, the system 150 can merge the TCAM cell 202 into the logical TCAM cell 128 and redistribute the existing TCAM entries of the TCAM cells 122 and 126 into the allocated TCAM cells 122, 126, and 202 (indicated by the dashed arrows). The redistribution can facilitate the insertion of entries or updates to entries without reorganizing the current TCAM entries. Otherwise, if one of the TCAM cells 122 and 126 becomes highly utilized (e.g., becomes full), the movement of a large number of TCAM entries to the TCAM cell 202 may become inefficient.

[0060] It should be noted that in order to move data from a TCAM cell 122 to another TCAM cell 202, the system 150 may not select any random location in the TCAM 202. The entries in the TCAM cells are stored based on their respective priorities or rankings. The system 150 may move data in such a way that the priorities are preserved at the TCAM cells 202. The ranking (or priority) of the entries in the TCAM cells indicates which entry should be selected if multiple entries match. Typically, entries with lower ranking numbers have higher priority than entries with higher ranking numbers. In some embodiments, higher priority entries may be stored before lower priority entries (e.g., at lower index values). The entries may then be looked up in the TCAM cells in such a way that earlier matches are selected for processing.

[0061] For example, if the operation unit 110 forwards a layer 3 packet based on the longest prefix match, the entries in the logical TCAM unit 128 can be stored to the IP address. Assume that the two entries in the logical TCAM unit 128 (e.g., TCAM unit 122) include {Rank 0, 192.168.0.2} and {Rank 100, 192.168.*.*}. If a packet with an IP destination address of 192.168.0.2 arrives at the switch 104, the destination address can match both entries. However, the first entry can be selected to forward the packet because the lower ranking value can indicate a higher priority. Therefore, if the two entries are moved from the TCAM unit 122 to the TCAM unit 202, the system 150 can maintain the TCAM unit 202 of the corresponding priority.

[0062] Figure 2B An exemplary process of dynamically reducing memory resources allocated to an operating unit of a switch according to an embodiment of the present application is illustrated. During operation, a user may determine that a logical TCAM unit 128 can operate with fewer entries of an operating unit 110. The user may then issue a command to the system 150 to dynamically reduce the capacity of the logical TCAM unit 128 to a new target capacity (e.g., from 2n entries to m entries). The system 150 may then mark the released (multiple) TCAM units as unavailable so that the released (multiple) TCAM units may be reallocated to another operating unit. The system 150 may remove TCAM units from the logical TCAM unit 128 based on user commands without interrupting the service at the switch 104.

[0063] The system 150 can ensure that the remaining TCAM cells (or new target TCAM cells) can accommodate valid entries in the (multiple) TCAM cells to be disassociated from the logical TCAM cells. For efficient fit selection, the system 150 can determine that the unassigned TCAM cell 202 has a capacity of m entries. The system 150 can then determine whether the TCAM cell 202 can accommodate valid entries in the TCAM cells 122 and 126. If the TCAM cell 202 cannot accommodate valid entries, the system 150 can fall back to another allocation strategy or provide an error message to the user. Otherwise, the system 150 can allocate the TCAM cell 202 to the operating unit 110 and merge the TCAM cell 202 into the logical TCAM cell 128.

[0064] The system 150 may then move the corresponding valid entries from the TCAM cells 122 and 126 (i.e., the TCAM cells 122 and 126 are decrement TCAM units) to the TCAM cell 202 (indicated by dashed lines). When the TCAM cells 122 and 126 become empty, the system 150 may disassociate the TCAM cells 122 and 126 from the logical TCAM cell 128. On the other hand, for incremental fit selection, the system 150 may select one of the TCAM cells 122 and 126 that can support at least m entries. If the capacity of the TCAM cells 122 and 126 is greater than the target capacity (e.g., n>m), the system 150 may determine which TCAM cell can accommodate the valid entries of the other TCAM cell.

[0065] If neither TCAM cell 122 nor 126 can accommodate a valid entry of the other TCAM cell, the system 150 may fall back to another allocation strategy or provide an error message to the user. On the other hand, if both TCAM cells 122 and 126 can, the system 150 may select one of the TCAM cells 122 and 126 with the smallest residual capacity. Assume that the system 150 has selected TCAM cell 126 for removal (i.e., TCAM cell 126 is a decrementing TCAM cell). The system 150 may then move the corresponding valid entry from TCAM cell 126 to TCAM cell 122 (indicated by a dashed line). When TCAM cell 126 becomes empty, the system 150 may disassociate TCAM cell 126 from logical TCAM cell 128, thereby making TCAM cell 126 available for subsequent allocation.

[0066] Both selection processes include moving valid entries to the target TCAM cells. To facilitate data movement, the system 150 may copy entries from the source TCAM cell (e.g., TCAM cell 126) to new entry locations in the target TCAM cell (e.g., TCAM cell 202 or 122). The system 150 may then enable the new entry in the target TCAM cell and disable the old entry in the TCAM cell selected for removal. The system 150 may then remove the old entry. In some embodiments, the system 150 may perform the reallocation as an atomic operation by updating a register that specifies which TCAM cells belong to the logical TCAM cell 128. For example, the system 150 may deploy a lock on the logical TCAM cell 128 to prevent the creation of new entries in the logical TCAM cell 128 during the movement of data from one TCAM cell to another.

[0067] The system 150 may allocate other hardware resources, such as a counter group, to the operating units 110 and 210 . Figure 3A An exemplary process of managing counter resources of a switch according to an embodiment of the present application is illustrated. It is assumed that in addition to counter groups 132, 134, and 136, counter pool 130 may also include counter groups 302, 304, and 306. In some embodiments, the corresponding counter groups may be based on counter RAMs. A specific number of bits (e.g., y bits, which may be a multiple of 32) at a specific location of the counter RAM may be allocated as counters. The counter groups of counter pool 130 may have different capacities (or sizes). For example, counter groups 122, 124, 126, and 304 may support a entries, counter group unit 302 may support b entries, and counter group 306 may support c entries.

[0068] In some embodiments, the values ​​of a, b, and c may be n, m, and p, respectively. In general, if the system 150 assigns a TCAM unit having 2n entries to the operation unit 110, the system 150 may also dynamically assign a counter group including 2n counters. Thus, the system 150 may assign counter groups 132 and 136 to the operation unit 110 as a logical counter group 138. For example, if each of the counter groups 132 and 136 includes 2048 counters, the logical counter group 138 may include 4096 counters. Similarly, the system 150 may assign counter group 304 to the operation unit 210 as a logical counter group 338. Thus, the logical counter groups 138 and 338 may represent 2a and a entries, respectively.

[0069] It should be noted that the number of counters assigned to an operating unit (i.e., the number of counters in the corresponding logical counter group) may not correspond to the number of entries in the logical TCAM unit of the operating unit. The correspondence between the numbers depends on how many TCAM entries require counters. The operating units 110 and 210 may not be aware of the virtualization of the logical counter groups 138 and 338. Therefore, the operating units 110 and 210 can access the logical counter groups 138 and 338, respectively, without considering the underlying physical counter groups. For example, the operating unit 110 can operate without considering that the logical counter group 138 is implemented on two different physical counter groups 132 and 136. This allows the system 150 to associate and disassociate the physical counter group with the logical counter group 138 during runtime without interrupting the business.

[0070] Each logical counter in logical counter group 138 may correspond to a physical counter in counter group 132 or 136. For example, logical counter 320 of logical counter group 138 may correspond to counter 322 of counter group 132. The corresponding physical counter may have y bits. In some embodiments, system 150 may maintain memory counter groups for corresponding physical counter groups. For example, system 150 may maintain memory counter groups 311, 312, 313, 314, 315, and 316 in memory 140 for counter groups 132, 134, 136, 302, 304, and 306, respectively. If counter 322 reaches a refresh value, system 150 may refresh the current value from counter 322 and merge the counter value into memory counter 324 in memory counter group 311. For example, if counter 322 indicates the total number of bytes received by a port of switch 104, system 150 may determine that counter 322 has reached a refresh value if counter 322 cannot be incremented to count the number of bytes in a new packet without counter 322 wrapping around.

[0071] The system 150 may also periodically refresh the value of the counter 322 to the memory counter 324. The system 150 may specify a specific location with z bits in the specific location in the memory 140, which may include at least 2y bits, to maintain the memory counter 324. The memory counter 324 may be initialized with an initial value (e.g., a value of 0). Whenever the system 150 refreshes the counter 322, the system 150 may add the value of the counter 322 to the current value of the memory counter 324 and reset the counter 322 (e.g., to a value of 0). Since the counters may be dynamically assigned, the counter group 132 currently assigned to the operating unit 110 may be reallocated to another operating unit.

[0072] To store the values ​​of the reallocated counter groups 132, the system 150 may maintain cumulative counters (e.g., software-based counters) for the corresponding logical counters. To reallocate the counter groups 132, the system 150 may merge the current values ​​of the corresponding counters and their corresponding memory counters into the cumulative counters. For example, the system 150 may add the corresponding current values ​​of the memory counter 324 and the counter 322 to the corresponding cumulative counter 326. The system 150 may repeat the process for the corresponding counters of the counter groups 132. When storing the counter and memory counter values ​​in the corresponding cumulative counters, the system 150 may reallocate the counter groups 132 and their corresponding memory counters.

[0073] The system 150 can maintain a mapping between the logical counters 320 and the counters 322. Registers in the switch 104 can indicate which counter groups belong to which logical counter group. In some embodiments, the registers associated with the counter groups 132 can indicate the locations of the bits representing the corresponding memory counters associated with the counter groups 132 in the memory 140 (e.g., by maintaining a bitmap). In other words, the registers can indicate the locations of the bits representing the memory counters 324 in the memory 140. Since each physical counter is assigned a corresponding set of bits in the memory 140 for the memory counters, the mapping can indirectly merge the memory counters 324 based on the locations indicated by the registers.

[0074] Thus, to obtain the value of the logical counter 320, the system 150 may obtain the value from the counter 322 based on the mapping. The system 150 may also obtain the value from the memory counter 324 based on the location indicated by the register. Subsequently, the system 150 may add the obtained value to the value of the cumulative counter 326 to determine the logical counter value. Thus, the corresponding logical counter value 330 may be the sum of the cumulative counter value 332, the memory counter value 334, and the physical counter value 336.

[0075] Figure 3B An exemplary process of dynamically increasing counter resources assigned to an operating unit of a switch according to an embodiment of the present application is illustrated. During operation, a user may determine that a logical counter group 138 may need to accommodate more counters for an operating unit 110. The user may then issue a command to the system 150 to dynamically increase the capacity of the logical counter group 138 to a new target capacity (e.g., accommodating 2a+b entries). The system 150 may then determine which available counter groups in the counter pool 130 can meet the target capacity requirements. Subsequently, the system 150 may select a target counter group in such a way that the logical counter group 138 can accommodate the new target capacity. The system 150 may then accommodate the target counter group into the logical counter group 138.

[0076] In some embodiments, the system 150 may deploy a selection strategy for selecting a target counter group. Examples of selection strategies may include, but are not limited to, efficient fit selection, incremental fit selection, first available selection, and random selection. For efficient fit selection, the system 150 may select a target counter group (or groups) with the smallest capacity that can accommodate the target capacity with the smallest residual capacity. The system 150 may then determine whether the selection requires data transmission based on whether the target counter group replaces the currently allocated counter group. Subsequently, the system 150 may determine that the available counter groups 134, 302, and 306 have capacities a, b, and c, respectively. If 2a+b=c, the system 150 may select counter group 306 as the target counter group.

[0077] Since the counter group 306 can replace the currently allocated counter groups 132 and 136, the system 150 can determine that a data transfer is required. The system 150 can then merge the counter group 306 into the logical counter group 138 and release the counter groups 132 and 136 for subsequent allocation (indicated by the dashed arrows). The system 150 can perform the reallocation as an atomic operation by updating the register that specifies which physical counter groups belong to the logical counter group 138. In this way, the system 150 can then map the corresponding logical counters in the logical counter group 138 to the physical counters in the counter group 306. In order to merge the counter group 306 into the logical counter group 138, the system 150 can add the values ​​from the corresponding counters and the corresponding memory counters to the cumulative counter.

[0078] For example, the system 150 may add the values ​​from the counter 322 and the memory counter 324 to the current value of the cumulative counter 326 associated with the logical counter 320. The system 150 may deploy a lock on the logical counter group 138 during the reallocation process for maintaining consistency. The system 150 may then map the logical counter 320 to the counter 342 of the counter group 306. Since the counter 342 is associated with the memory counter 344, the mapping also indirectly merges the memory counter 344. For any subsequent event, the counter 342 may be increased, and the sum of the increased value and the value of the cumulative counter 326 may represent the value of the logical counter 320. Therefore, the total value of the logical counter 320 may be the sum of the corresponding values ​​of the cumulative counter 326, the memory counter 344, and the counter 342. In this way, the counter values ​​accumulated by the counter 322 and the memory counter 324 are saved by the cumulative counter 326 of the logical counter 320.

[0079] On the other hand, for the incremental fit selection, the system 150 may select the counter group with the smallest capacity that can accommodate the incremental capacity with the smallest residual capacity. The system 150 may then determine whether the selection requires data transfer based on whether the current counters need to be redistributed. Figure 2A In the example of , the system 150 can select the counter group 302 as the target counter group (indicated by the dashed arrow). Therefore, the number of logical counters in the logical counter group 138 can be increased to 2a+b. The system 150 can initiate b new accumulation counters for the logical counter group 138 for any subsequent reallocation.

[0080] In some embodiments, for each reallocation of counter groups, the system 150 can evaluate how to efficiently distribute physical counter groups for the corresponding counter groups of the switch 104. For example, the system 150 can iteratively apply the efficient fit selection. Assume that the counter group 306 is currently assigned to the logical counter group 338. Therefore, the system 150 may not be able to assign the counter group 306 to the logical counter group 338 to increase the number of logical counters in the logical counter group 138 to 2a+b based on the efficient fit selection. In other words, regardless of the selection strategy, the system 150 can only consider the currently unassigned counter groups for reallocation.

[0081] However, if the system 150 releases the counter group 306 from the logical counter group 338 (e.g., due to an update based on a user command), the system 150 can re-evaluate the allocation of the counter group to each logical counter group. During the re-evaluation process, the system 150 can determine that allocating the counter group 306 to the logical counter group 138 to 2a+b can meet the efficient fit. Therefore, the system 150 can merge the counter group 306 into the logical counter group 138 and release the counter groups 132 and 136 for subsequent allocation. In the same manner, when the system 150 releases a TCAM cell due to reallocation, the system 150 can iteratively apply the selection strategy to the logical TCAM cell.

[0082] Figure 3CAn exemplary process of dynamically reducing counter resources assigned to an operating unit of a switch according to an embodiment of the present application is illustrated. During operation, a user may determine that a logical counter group 138 may be operated with a smaller number of counters of an operating unit 110. The user may then issue a command to the system 150 to dynamically reduce the capacity of the logical counter group 138 to a new target capacity (e.g., from 2a counters to b counters). The system 150 may then mark the released (multiple) counter groups as unavailable so that the released (multiple) counter groups may be reallocated to another operating unit. The system 150 may remove counter groups from the logical counter group 138 based on user commands without interrupting the business at the switch 104.

[0083] For efficient fit selection, the system 150 may select a target counter group (or groups) with the smallest capacity that can accommodate the target capacity with the smallest residual capacity. The system 150 may then determine whether the selection requires data transfer based on whether the target counter group replaces the currently allocated counter group. Subsequently, the system 150 may determine that the available counter groups 134, 302, and 306 have capacities a, b, and c, respectively. Since the target capacity is b counters, the system 150 may select counter group 302 as the target counter group.

[0084] Since the counter group 302 can replace the currently allocated counter groups 132 and 136 (i.e., the counter groups 132 and 136 are decrement counter groups), the system 150 can determine that data transfer is required. The system 150 can then merge the counter group 302 into the logical counter group 138 and release the counter groups 132 and 136 for subsequent allocation (indicated by the dotted arrows). The system 150 can perform the reallocation as an atomic operation. In order to merge the counter group 302 into the logical counter group 138, the system 150 can add the values ​​from the corresponding counters and the corresponding memory counters to the accumulation counter. For example, the system 150 can add the values ​​from the counter 322 and the memory counter 324 to the current value of the accumulation counter 326 associated with the logical counter 320. Then, the system 150 can map the logical counter 320 to the corresponding counter of the counter group 302. In this way, the counter values ​​accumulated by the counter 322 and the memory counter 324 are saved by the accumulation counter 326 of the logical counter 320.

[0085] On the other hand, for incremental fit selection, system 150 can select one of counter groups 132 and 136 that can support at least b entries. If the capacity of counter groups 132 and 136 is greater than the target capacity (e.g., a>b), system 150 can determine which counter group can accommodate valid entries of the other counter group. If neither counter group 132 nor 136 can accommodate valid counters of the other counter group, system 150 can fall back to another allocation strategy or provide an error message to the user. On the other hand, if both counter groups 132 and 136 can, system 150 can select one of counter groups 132 and 136 with the smallest residual capacity.

[0086] Assume that the system 150 has selected the counter group 132 (that is, the counter group 132 is a decrement counter group) for removal. The system 150 can determine the sum of the corresponding effective counter value from the counter group 132 and the corresponding memory counter value from the memory counter group 311. The system 150 can then store the sum in the cumulative counter of the associated logical counter. For example, the system 150 can then determine the sum of the value of the counter 322 and the value of the memory counter 324, and store the sum in the cumulative counter 326 of the logical counter 320. Subsequently, the system 150 can map the logical counters of the counters that have been mapped to the counter group 132 to the new counters of the counter group 136. The system 150 can perform the reallocation of the logical counters as an atomic operation by writing in the registers that specify which physical counters belong to the logical counter group 138. In this way, the system 150 can reduce the logical counter group 138 without interrupting the business in the switch 104.

[0087] operate

[0088] Figure 4A A flow chart illustrating a process of dynamically increasing memory resources allocated to an operating unit of a switch according to an embodiment of the present application is presented. During operation, a dynamic allocation system of the switch may obtain an increase instruction from a user (operation 402) and determine a selection strategy for the increase instruction (operation 404). The system may then select a target TCAM unit for the increase based on the selection strategy (operation 406) and merge the TCAM unit into a logical TCAM unit (operation 408). The system may check whether data transfer is required (operation 410).

[0089] If data transfer is required, the system may copy the old entry from the source TCAM cell to the new location in the target TCAM cell and enable the new entry (operation 412). The system may then disable the old entry and remove the old entry (operation 414). Subsequently, the system may generate an entry for the logical TCAM cell by updating the corresponding mapping (operation 416). The system may determine whether the transfer has been completed (operation 418). If not, the system may continue to copy the entry to the new location in the target TCAM cell and disable the old entry in the current TCAM cell (operation 412). If the transfer is completed, the system may remove the old TCAM cell(s) from the logical TCAM cell and mark it as available (operation 420).

[0090] Figure 4B A flow chart illustrating a process of dynamically reducing memory resources allocated to an operating unit of a switch according to an embodiment of the present application is presented. During operation, a dynamic allocation system of the switch may obtain a reduction instruction from a user (operation 452) and determine a selection strategy for the reduction instruction (operation 454). The system may then select a target TCAM unit and a decrement TCAM unit based on the selection strategy (operation 456). Subsequently, the system may determine whether data transfer is required (operation 458). If data transfer is not required, the system may mark the instruction as non-executable (issue an error message to the user) (operation 462).

[0091] If data transfer is required, the system may copy the old entry from the decrement TCAM cell to the new location in the target TCAM cell and enable the new entry (operation 462). The system may then disable the old entry and remove the old entry (operation 464). Subsequently, the system may generate an entry for the logical TCAM cell by updating the corresponding mapping (operation 466). The system may determine whether the TCAM cell is empty (operation 468). If the TCAM cell is not empty, the system may continue to copy the entry to the new location in the target TCAM cell and disable the old entry in the current TCAM cell (operation 462). If the transfer is completed, the system may remove the decrement TCAM cell from the logical TCAM cell and mark it as available (operation 470).

[0092] Figure 5AA flow chart illustrating a process in which a switch dynamically reduces counter resources allocated to an operating unit of the switch according to an embodiment of the present application is presented. During operation, a dynamic allocation system of the switch may obtain an increase instruction from a user (operation 502) and determine a selection strategy for the increase instruction (operation 504). The system may then select a target counter group for increase based on the selection strategy (operation 506) and determine a memory counter group associated with the selected counter group (operation 508). Subsequently, the system may merge the counter group and the memory counter group into a logical counter group (operation 510) and initialize the cumulative counter to the logical counter group (operation 512).

[0093] The system may check whether data transfer is required (operation 514). The system may then determine the current counter values ​​of the corresponding counter and the corresponding memory counter (operation 516), and add the current counter value to the cumulative counter (operation 518). The system may determine whether the transfer has been completed (operation 520). If not, the system may continue to determine the current counter values ​​of the corresponding counter and the corresponding memory counter (operation 516). If the transfer is completed, the system may reset the counter values ​​in the counter group and the memory counter group (operation 522). Subsequently, the system may disassociate the counter group and the memory counter group from the logical counter group (operation 524).

[0094] Figure 5B A flow chart illustrating a process of dynamically reducing counter resources allocated to an operating unit of a switch according to an embodiment of the present application is presented. During operation, a dynamic allocation system of the switch may obtain a reduction instruction from a user (operation 552) and determine a selection strategy for the reduction instruction (operation 554). The system may then select a target counter group and a decrement counter group based on the selection strategy (operation 556). Subsequently, the system may determine a memory counter group associated with the decrement counter group (operation 558) and identify an accumulation counter associated with the logic counter group (operation 560).

[0095] The system may then determine the current counter values ​​of the corresponding counter and the corresponding memory counter (operation 562), and add the current counter value to the cumulative counter (operation 564). The system may determine whether the transfer has been completed (operation 566). If not, the system may continue to determine the current counter values ​​of the corresponding counter and the corresponding memory counter (operation 562). If the transfer is completed, the system may reset the counter values ​​in the counter group and the memory counter group (operation 568). Subsequently, the system may disassociate the counter group and the memory counter group from the logical counter group (operation 570).

[0096] Exemplary switch system

[0097] Figure 6 An exemplary switch supporting efficient multicast forwarding across overlay tunnels according to an embodiment of the present application is illustrated. In this example, the switch 600 includes a plurality of communication ports 602, a packet processor 610, a dynamic allocation logic block 630, and a storage device 650. The switch 600 may also include switch hardware (e.g., processing hardware of the switch 600, such as its application-specific integrated circuit (ASIC) chip) including a TCAM pool 662, a counter pool 664, and a memory (e.g., SRAM). The packet processor 610 extracts and processes header information from a received packet. The packet processor 610 may identify a switch identifier (e.g., a media access control (MAC) address and / or an IP address) associated with the switch 600 in a header of the packet.

[0098] The communication port 602 may include an inter-switch communication channel for communicating with other switches and / or user equipment. The communication channel may be implemented via a conventional communication port and based on any open or proprietary format. The communication port 602 may include one or more Ethernet ports that may receive frames encapsulated in an Ethernet header. The communication port 602 may also include one or more IP ports that may receive IP packets. The IP port may receive IP packets and may be configured with an IP address. The packet processor 610 may process Ethernet frames and / or IP packets.

[0099] The switch 600 may maintain a database 652 (e.g., in a storage device 650). The database 652 may be a relational database and may run on one or more DBMS instances. The dynamic allocation logic block 630 may facilitate the operation of the system 150. The TCAM logic block 632 may organize the TCAM cells of the switch 600 into a TCAM pool 662 and dynamically allocate the TCAM cells to the operating units of the switch 600. In addition, the TCAM logic block 632 may represent the allocated TCAM cells to the operating units as logical TCAM cells. The TCAM logic block 632 may also dynamically increase / decrease the capacity of the logical TCAM cells during the runtime of the switch 600 without interrupting the service.

[0100] Similarly, the counter logic block 634 can organize the counter groups (e.g., counter RAM sets) of the switch 600 into counter pools 664 and dynamically allocate the counter groups to the operation units. The counter logic block 634 can also maintain memory counter groups for the corresponding counter groups in the memory 666 and refresh the counter values ​​to the corresponding memory counters. In addition, the counter logic block 634 can indicate the allocated counter groups to the operation units as logical counter groups.

[0101] The counter logic block 634 can also dynamically increase / decrease the capacity of the logical counter group during the run time of the switch 600 without interrupting the service. The counter logic block 634 can also maintain an accumulation counter for the corresponding logical counter of the logical counter block (e.g., at the software level). The counter logic block 634 can merge the value of the counter and its corresponding memory counter into the accumulation counter.

[0102] The data structures and codes described in this detailed description are generally stored on a computer-readable storage medium, which can be any device or medium that can store code and / or data for use by a computer system. Computer-readable storage media include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices (such as disks, tapes, CDs (compact disks), DVDs (digital versatile disks or digital video disks)), or other media that can store computer-readable media now known or later developed.

[0103] The methods and processes described in the detailed description section can be implemented as code and / or data, which can be stored in the above-mentioned computer-readable storage medium. When a computer system reads and executes the code and / or data stored on the computer-readable storage medium, the computer system executes the methods and processes implemented as data structures and codes and stored in the computer-readable storage medium.

[0104] The methods and processes described herein may be performed by and / or included in hardware modules or devices. These modules or devices may include, but are not limited to, application specific integrated circuit (ASIC) chips, field programmable gate arrays (FPGAs), dedicated or shared processors that execute a specific software module or piece of code at a specific time, and / or other programmable logic devices currently known or developed in the future. When the hardware modules or devices are activated, they execute the methods and processes included therein.

[0105] The foregoing descriptions of the embodiments of the present invention are presented for the purpose of illustration and description only. They are not intended to be exhaustive or to limit the present disclosure. Therefore, many modifications and variations will be apparent to those skilled in the art. The scope of the present invention is defined by the appended claims.

Claims

1. A method for facilitating dynamic resource allocation in a switch, comprising: for an operation unit of the switch, representing a first subset of hardware elements of the switch assigned to the operation unit as logical elements within the switch, wherein the operation unit facilitates an ability in the switch to perform operations of the switch in a network using the hardware elements assigned to the operation unit; determining, during runtime of the switch, a request to dynamically reassign the hardware element to the operating unit; determining whether the reallocation of the hardware elements is feasible in the switch; In response to the reallocation of the hardware elements being feasible, allocating a second subset of the hardware elements to the operating unit during runtime of the switch; as well as merging the second subset of the hardware elements into the logic element; determining whether dynamic reallocation of a third subset of hardware elements allocated to a second operating unit is required as a result of said allocation of said second subset of hardware elements to said operating unit; as well as In response to determining that dynamic reallocation of the second operating unit is required, a fourth subset of the hardware elements is dynamically allocated to the second operating unit.

2. The method of claim 1, wherein the hardware elements of the switch include a set of ternary content addressable memory (TCAM) cells, and wherein the logic elements are logical TCAM cells presented to the operation unit.

3. The method of claim 1, wherein the hardware element of the switch comprises a collection of memory segments of a central memory of the switch, and wherein the logical element is a logical memory segment presented to the operating unit.

4. The method of claim 1, wherein the hardware element of the switch comprises a set of counter groups of hardware-based counters, and wherein the logical element is a logical counter group presented to the operation unit.

5. The method of claim 4, wherein the hardware element of the switch further comprises a set of memory counter groups maintained in a central memory of the switch; and The method further comprises: Current values ​​of corresponding counters in a counter group are refreshed to corresponding memory counters, wherein the counters are represented as logical counters in the logical counter group.

6. The method according to claim 5, further comprising: Maintaining an accumulation counter for the logic counter; and Wherein allocating the second subset of the hardware elements comprises: adding respective values ​​of the counter and the corresponding memory counter to the cumulative counter; as well as The logical counter is reassociated to a new counter in the second subset of the hardware elements.

7. The method of claim 1, wherein the reallocation of the hardware elements comprises: adding or reducing the first subset of the hardware elements to the second subset of the hardware elements; The method further comprises: determining a target hardware element for the first subset of the hardware elements based on a selection policy; as well as The second subset of the hardware elements is generated from the first subset of the hardware elements.

8. The method of claim 7, wherein determining whether the reallocation of the hardware elements is feasible comprises: A determination is made as to whether the target hardware element can accommodate valid data from the first subset of the hardware elements.

9. The method according to claim 1, further comprising: indicating, in a register of the switch, that the first subset of the hardware elements belongs to the logical element; and Wherein merging the second subset of the hardware elements into the logic element comprises: updating the register to indicate that the second subset of the hardware elements belongs to the logic element.

10. The method according to claim 1, further comprising: receiving a command indicating the request for dynamic reallocation of the hardware element for the operating unit; as well as A reallocation operation and parameters for the dynamic reallocation are determined.

11. A computer system comprising: processor; Storage devices; as well as a memory coupled to the processor and storing instructions that, when executed by the processor, cause the processor to perform a method for facilitating dynamic resource allocation in a switch, the method comprising: for an operation unit of the switch, representing a first subset of hardware elements of the switch assigned to the operation unit as logical elements within the switch, wherein the operation unit facilitates an ability in the switch to perform operations of the switch in a network using the hardware elements assigned to the operation unit; determining, during runtime of the switch, a request to dynamically reassign the hardware element to the operating unit; determining whether the reallocation of the hardware elements is feasible in the switch; In response to the reallocation of the hardware elements being feasible, allocating a second subset of the hardware elements to the operating unit during runtime of the switch; and merging the second subset of the hardware elements into the logic element; determining whether dynamic reallocation of a third subset of hardware elements allocated to a second operating unit is required as a result of said allocation of said second subset of hardware elements to said operating unit; and In response to determining that dynamic reallocation of the second operating unit is required, a fourth subset of the hardware elements is dynamically allocated to the second operating unit.

12. The computer system of claim 11, wherein the hardware elements of the switch include a collection of ternary content addressable memory (TCAM) cells, and wherein the logic elements are logical TCAM cells presented to the operation unit.

13. The computer system of claim 11, wherein the hardware element of the switch comprises a collection of memory segments of a central memory of the switch, and wherein the logical element is a logical memory segment presented to the operating unit.

14. The computer system of claim 11, wherein the hardware element of the switch comprises a collection of counter groups of hardware-based counters, and wherein the logical element is a logical counter group presented to the operation unit.

15. The computer system of claim 14, wherein the hardware element of the switch further comprises a set of memory counter groups maintained in a central memory of the switch; and The method further comprises: Current values ​​of corresponding counters in a counter group are refreshed to corresponding memory counters, wherein the counters are represented as logical counters in the logical counter group.

16. The computer system of claim 15, wherein the method further comprises maintaining an accumulation counter for the logical counter; and Wherein allocating the second subset of the hardware elements comprises: adding respective values ​​of the counter and the corresponding memory counter to the cumulative counter; as well as The logical counter is reassociated to a new counter in the second subset of the hardware elements.

17. The computer system of claim 11, wherein the reallocation of the hardware elements comprises: adding or reducing the first subset of the hardware elements to the second subset of the hardware elements; The method further comprises: determining a target hardware element for the first subset of the hardware elements based on a selection policy; as well as The second subset of the hardware elements is generated from the first subset of the hardware elements.

18. The computer system of claim 17, wherein determining whether the reallocation of the hardware element is feasible comprises: A determination is made as to whether the target hardware element can accommodate valid data from the first subset of the hardware elements.

19. The computer system of claim 11, wherein the method further comprises: indicating, in a register of the switch, that the first subset of the hardware elements belongs to the logical element; and Wherein merging the second subset of the hardware elements into the logic element comprises: updating the register to indicate that the second subset of the hardware elements belongs to the logic element.

20. The computer system of claim 11, wherein the method further comprises: receiving a command indicating the request for dynamic reallocation of the hardware element for the operating unit; as well as A reallocation operation and parameters for the dynamic reallocation are determined.

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