Solid-state imaging device and distance measuring system

Abstract

The object of the present invention is to provide a solid-state imaging device and a distance measurement system capable of detecting high-frequency pulsed light. The solid-state imaging device includes: a plurality of pixels, each pixel having a light-receiving element for converting received light into an electrical signal; a driving unit for driving the plurality of pixels while offsetting the operating timing of the light-receiving element; and a time measurement unit for measuring, based on an input electrical signal, the duration until light emitted from a light source is received by the light-receiving element after being reflected by an object, the time measurement unit being configured such that an electrical signal is input from each of the plurality of pixels.

Description

Technical Field

[0001] This disclosure relates to a solid-state imaging apparatus having a light-receiving element and a distance measurement system using the solid-state imaging apparatus. Background Technology

[0002] In recent years, distance image sensors that measure distance using Time-of-Flight (ToF) technology have attracted attention. For example, a pixel array configured to planarize multiple SPAD (Single-Photon Avalanche Diode) pixels using CMOS (Complementary Metal-Oxide-Semiconductor) semiconductor integrated circuit technology can be used as a distance image sensor. In the SPAD pixel, avalanche amplification occurs when a photon enters a PN junction region with a high electric field, where the voltage is much larger than the applied breakdown voltage. By detecting the instantaneous current flow time at this moment, distance can be determined with high precision (see, for example, Patent Documents 1 and 2).

[0003] [List of Citations]

[0004] [Patent Literature]

[0005] [Patent Document 1]

[0006] Japanese Patent Publication No. 2013-48278

[0007] [Patent Document 2]

[0008] Japanese Patent Publication No. 2015-41746 Summary of the Invention

[0009] [Technical Issues]

[0010] However, SPAD pixels cannot detect light after avalanche amplification ends until the SPAD pixels are reset. Therefore, SPAD pixels have a problem in detecting high-frequency pulsed light.

[0011] The purpose of this disclosure is to provide a solid-state imaging device and a distance measurement system capable of detecting high-frequency pulsed light.

[0012] [Solution to the problem]

[0013] A solid-state imaging apparatus according to one aspect of the present disclosure includes: a plurality of pixels, each pixel having a light-receiving element that converts received light into an electrical signal; a driving unit configured to drive the plurality of pixels by offsetting the operating timing of the light-receiving element; and a time measuring unit configured to input an electrical signal from each of the plurality of pixels and to measure, based on the input of the electrical signal, the time for light emitted from a light source to be reflected by an object and received by the light-receiving element.

[0014] A distance measurement system according to one aspect of the present disclosure includes: a light source adapted to emit light onto an object; a solid-state imaging device having a plurality of pixels, each pixel having a light receiving element that converts received light into an electrical signal; a driving unit adapted to drive the plurality of pixels by offsetting the operating timing of the light receiving element; and a time measuring unit configured to input an electrical signal from each of the plurality of pixels and adapted to measure, based on the input of the electrical signal, the time it takes for light emitted from the light source to be reflected by the object and received by the light receiving element. Attached Figure Description

[0015] [ Figure 1A [Illustrated diagram] is a schematic diagram depicting an example of the configuration of a distance measurement system according to an embodiment of the present disclosure.

[0016] [ Figure 1B [ ] is a block diagram describing an example of the circuit configuration of a distance measurement system according to an embodiment of the present disclosure.

[0017] [ Figure 2 [Illustration] is a schematic diagram illustrating a configuration example of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0018] [ Figure 3 [Illustration 1] is a plan view depicting an example of the configuration of a group of pixels included in a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0019] [ Figure 4 [ ] is a cross-sectional view depicting an example of the configuration of a group of pixels included in a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0020] [ Figure 5 [ ] is a block diagram illustrating an example of the circuit configuration of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0021] [ Figure 6 [ ] is a block diagram illustrating an example of the configuration of the pixel circuit of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0022] [ Figure 7 [ ] is a circuit diagram depicting an example of the configuration of a decoder disposed in a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0023] [ Figure 8 [ ] is a circuit diagram illustrating an example of the configuration of a detection circuit provided in a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0024] [ Figure 9 [ ] is a circuit diagram depicting an example of the configuration of a selection circuit provided in a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0025] [ Figure 10[ ] is a timing diagram illustrating an example of the operation of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0026] [ Figure 11 [Illustration 1] is a plan view depicting an example of the configuration of a group of pixels included in a solid-state imaging apparatus according to a modified embodiment of the present disclosure.

[0027] [ Figure 12 [ ] is a cross-sectional view depicting an example of the configuration of a pixel group included in a solid-state imaging apparatus according to a modified example 1 of the present disclosure.

[0028] [ Figure 13 [ ] is a plan view depicting an example of the configuration of pixel groups included in a solid-state imaging apparatus according to a modified embodiment 2 of the present disclosure.

[0029] [ Figure 14 [ ] is a cross-sectional view depicting an example of the configuration of pixel groups included in a solid-state imaging apparatus according to a modified embodiment 2 of the present disclosure.

[0030] [ Figure 15 [ ] is a plan view depicting an example of the configuration of pixel groups included in a solid-state imaging apparatus according to a variation 3 of the present disclosure.

[0031] [ Figure 16 [ ] is a cross-sectional view depicting an example of the configuration of pixel groups included in a solid-state imaging apparatus according to a variation 3 of the present disclosure.

[0032] [ Figure 17 [Illustration] is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0033] [ Figure 18 [This is an example diagram illustrating the installation location of the vehicle exterior information detection unit and the imaging unit.] Detailed Implementation

[0034] The following is a detailed description of the modes (implementations) for carrying out this disclosure, with reference to the accompanying drawings. The descriptions given below are merely specific examples of this disclosure, and this disclosure is not limited to the embodiments given below.

[0035] Distance Measurement System

[0036] The distance measurement system according to embodiments of this disclosure is a system for measuring the distance to an object using structured light technology. Furthermore, the distance measurement system according to this embodiment can also be used as a system for acquiring three-dimensional (3D) images, and in this case, it can be referred to as a three-dimensional image acquisition system. In structured light technology, distance is measured by identifying the coordinates of a point image and by pattern matching of which light source (i.e., point light source) the point image was projected from.

[0037] [System Configuration]

[0038] Figure 1A This is a schematic diagram illustrating an example of the configuration of the distance measurement system according to this embodiment. Figure 1B This is a block diagram illustrating an example of the circuit configuration of the distance measurement system according to this embodiment.

[0039] The distance measurement system 9 according to this embodiment includes a light source 91 that emits light toward an object 8. The light source 91 includes a surface-emitting semiconductor laser, such as a vertical resonator surface-emitting laser. The distance measurement system 9 includes a solid-state imaging device 1 according to this embodiment (described in detail later). A plurality of pixels 20 included in the solid-state imaging device 1 serve as light receivers in the distance measurement system 9. The light source 91 irradiates the object 8 with a high-frequency laser. Figure 1A and Figure 1B As shown, the distance measurement system 9 according to this embodiment includes not only a light source 91 and a plurality of pixels 20, but also a control unit 31, a laser control unit 33, a distance measurement processing unit 35, a light source-side optical device 93, and an imaging device-side optical device 94.

[0040] The control unit 31, laser control unit 33, distance measurement processing unit 35, and multiple pixels 20 will be described in detail later. The control unit 31 drives the light source 91 via the laser control unit 33 and controls the multiple pixels 20 and the distance measurement processing unit 35. More specifically, the control unit 31 controls the light source 91, the multiple pixels 20, and the distance measurement processing unit 35 by synchronizing these units.

[0041] In the distance measurement system 9 according to this embodiment, a high-frequency laser beam emitted from a light source 91 is irradiated onto an object 8 (i.e., the target to be measured) via a light source-side optics 93. The emitted beam is reflected by the object 8. The beam reflected by the object 8 passes through an imaging device-side optics 94 and enters multiple pixels 20. The distance measurement processing unit 35 measures the distance between the solid-state imaging device 1 and the object 8 using TOF (Time-of-Flight) technology. The distance information measured by the distance measurement processing unit 35 is provided to an application processor 700 external to the distance measurement system 9. The application processor 700 performs given processing on the input distance information.

[0042] <Schematic configuration of solid-state imaging device>

[0043] Next, we will use... Figures 2 to 4 A schematic configuration of the solid-state imaging apparatus 1 according to this embodiment is described. Figure 2 This is a schematic diagram depicting an example of a planar configuration of a solid-state imaging device 1.

[0044] Figure 3It is a plan view depicting an example of the configuration of the pixel group 2 included in the solid-state imaging device 1.

[0045] Figure 4 It describes along Figure 3 A cross-sectional view of a configuration instance of pixel group 2 cut by line LL.

[0046] like Figure 2 As shown, the solid-state imaging device 1 according to this embodiment includes a sensor chip 10a and a logic chip 10b. Figure 2 (Not shown in the image). A pixel region A1, a peripheral region A2, and a pad region A3 are provided on the sensor chip 10a. A logic chip 10b is arranged on the lower surface of the sensor chip 10a (the surface opposite to the light-entering surface). The pixel region A1 is, for example, a rectangular region extending from the center of the sensor chip 10a towards its edge. The peripheral region A2 is an annular region that surrounds the pixel region A1. The pad region A3 is an annular region that surrounds the peripheral region A2 and is located on the outermost periphery of the sensor chip 10a.

[0047] Pixel region A1 has multiple pixels 20 arranged in an array pattern. All pixels 20 in pixel region A1 have the same structure. Figure 2 In the image, pixel 20 is represented by a white rectangle. Furthermore, in... Figure 2 In this context, reference numerals "20a, 20b, 20c, and 20d" are assigned to only four of the multiple pixels 20 for ease of understanding. Hereinafter, without distinguishing between pixels 20a, 20b, 20c, and 20d, or between all pixels 20 located in pixel region A1, they will be collectively referred to as pixel 20.

[0048] The solid-state imaging device 1 includes multiple pixel groups 2, each pixel group 2 having multiple pixels 20 (four pixels in this embodiment). Figure 2 In this context, reference numeral "2" is only assigned to those pixel groups 20a, 20b, 20c, and 20d that have multiple pixel groups 2.

[0049] like Figure 2 As shown, the pad region A3 extends from the upper edge of the sensor chip 10a to the wiring layer 102a. Figure 2 Not shown in the image; see reference. Figure 4 ), and the wiring holes of the guide electrode pads (not shown) are arranged in a straight line. Figure 2 In the diagram, the pad opening 101 is represented by a white rectangle. Furthermore, in... Figure 2For ease of understanding, reference numerals are assigned to only one of the plurality of pad openings 101. A wiring electrode pad is provided at the bottom of each pad opening 101. This electrode pad is used to connect to wiring in the wiring layer 102a or other external devices (e.g., chips). Additionally, the wiring layer near the bonding surface between the sensor chip 10a and the logic chip 10b can also be used as an electrode pad.

[0050] Each of the wiring layer 102a formed in the sensor chip 10a and the wiring layer 102b formed in the logic chip 10b ( Figure 2 Not shown in the image; see reference. Figure 4 The wiring includes an insulating film and multiple wiring layers, and the multiple wiring layers and electrode pads include, for example, metals such as copper (Cu) or aluminum (Al). The wiring formed in pixel region A1 and surrounding region A2 includes the same material as the multiple wiring layers and electrode pads formed in wiring layers 102a and 102b.

[0051] like Figure 2 As shown, a surrounding region A2 is provided between pixel region A1 and pad region A3. The surrounding region A2 includes an n-type semiconductor region and a p-type semiconductor region. Furthermore, the p-type semiconductor region is connected to a wiring (not shown) formed in the surrounding region A2 via a contact (not shown). The wiring is grounded (GND). A trench (not shown) is formed between pixel region A1 and surrounding region A2. The trench is provided to reliably separate pixel region A1 from surrounding region A2.

[0052] Although described later, the light receiving element 21 ( Figure 2 Not shown in the image; see reference. Figure 3 and Figure 4 A photodiode, including an avalanche photonic diode, is disposed in pixel 20. A high voltage is applied between the cathode and anode of the light-receiving element 21. Furthermore, the surrounding region A2 is connected to GND. Therefore, a high electric field region exists in the area between pixel region A1 and surrounding region A2 due to the high voltage applied to the anode of the light-receiving element 21, which may lead to breakdown. A possible solution to avoid breakdown is to widen the region (separation region) between pixel region A1 and surrounding region A2. However, if the separation region is widened, the size of the sensor chip 10a becomes larger. Therefore, in this embodiment, a trench is formed to prevent such damage and the enlargement of the sensor chip 10a. This trench allows breakdown to be prevented without widening the separation region.

[0053] like Figure 3As shown, pixel group 2 has four pixels 20a, 20b, 20c, and 20d arranged in an array pattern. Pixels 20a, 20b, 20c, and 20d are arranged adjacent to each other. Pixel group 2 has a first light-shielding portion 22 and a second light-shielding portion 23. The first light-shielding portion 22 is configured to surround the outer periphery of pixel group 2. The second light-shielding portion 23 is disposed in the boundary portions of the plurality of pixels 20a, 20b, 20c, and 20d. The first light-shielding portion 22 and the second light-shielding portion 23 include a metallic material such as W (tungsten), Al (aluminum), or Cu (copper) or other materials such as polycrystalline silicon. The first light-shielding portion 22 prevents leakage of light reflected by object 8. Figure 3 (Not depicted in Figure 1); adjacent pixel groups 2 are formed. Furthermore, the second light-shielding portion 23 prevents light reflected from the object 8 from leaking into adjacent pixels 20.

[0054] Each of pixels 20a, 20b, 20c, and 20d has a light-receiving element 21 that converts received light into an electrical signal. The light-receiving element 21 is, for example, an avalanche photodiode (APD) that multiplies carriers using a high electric field region. The APD has Geiger mode and linear mode. In Geiger mode, the APD operates at a bias voltage higher than its breakdown voltage. In linear mode, the APD operates at a bias voltage close to and slightly higher than its breakdown voltage. The avalanche photodiode in Geiger mode is also referred to as a single-photon avalanche diode (SPAD). A SPAD is a device that can detect a single photon of each pixel 20 by multiplying the carriers generated by photoelectric conversion in a PN junction region having a high electric field provided for each pixel 20. In this embodiment, for example, the light-receiving element 21 includes a SPAD as an APD. This allows the light-receiving element 21 to improve light detection accuracy. The configuration of the pixels 20 will be described in detail later.

[0055] like Figure 4 As shown, logic chip 10b is connected to and arranged on the lower surface of sensor chip 10a. Peripheral circuitry (described in detail later) is formed on logic chip 10b to process signals input from pixel 20 and supply power to pixel circuitry (described in detail later) disposed in pixel 20. Figure 4 In the example shown, sensor chip 10a and logic chip 10b are electrically connected such that some of the wiring layers formed in pixel region A1 on the bonding surface side between sensor chip 10a and logic chip 10b are directly bonded together.

[0056] (Pixel configuration)

[0057] The following is a detailed description of the configuration of the pixels included in the solid-state imaging apparatus 1 according to this embodiment. The solid-state imaging apparatus 1 includes back-illuminated pixels 20. That is, a sensor chip 10a is disposed on the rear surface side of the solid-state imaging apparatus 1, and a logic chip 10b is disposed on the front surface side of the solid-state imaging apparatus 1. Pixels 20 are stacked on top of an on-chip lens (not shown) into which light enters. A wiring layer 102a is stacked on top of the pixels 20. The logic chip 10b is stacked on top of the wiring layer 102a, and the wiring layer 102b is placed face-to-face with the wiring layer 102a.

[0058] Light enters the pixel 20 from the on-chip lens side. In the case of a back-illuminated pixel 20, the pixel circuitry for driving the pixel 20 is formed, for example, in wiring layers 102a and 102b disposed on the logic chip 10b. Furthermore, the peripheral circuitry for driving the pixel circuitry is formed, for example, in wiring layer 102b disposed on the logic chip 10b. Additionally, the circuitry can be arranged on the same substrate by arranging the circuitry in a region outside the pixel region.

[0059] The solid-state imaging device 1 according to this embodiment can be applied to... Figure 4 The diagram shows the rear illumination pixel 20 and the front illumination pixel arranged below the on-chip lens. The following description of the pixels included in the solid-state imaging device 1 will be given with reference to an example of the back illumination pixel 20.

[0060] like Figure 4 As shown, pixel 20 has a light-receiving element 21 including a SPAD. The light-receiving element 21 has an n-type semiconductor region 211 with an n-type conductivity type (first conductivity type). The light-receiving element 21 has a p-type semiconductor region 212 formed below the n-type semiconductor region 211 and having a p-type conductivity type (second conductivity type). The n-type semiconductor region 211 and the p-type semiconductor region 212 are formed in the well layer 213.

[0061] The well layer 213 can be a semiconductor region with an n-type conductivity or a p-type conductivity. Furthermore, the well layer 213 is prone to depletion; for example, when the well layer 213 is 1 × 10⁻⁶... 14 In the case of low-concentration n-type or p-type semiconductor regions, or even smaller orders of magnitude, the depletion of the well layer 213 makes it possible to improve the detection efficiency, known as PDE (photon detection efficiency).

[0062] The n-type semiconductor region 211 comprises, for example, Si (silicon) and is a semiconductor region with a high impurity concentration and an n-type conductivity type. The p-type semiconductor region 212 comprises, for example, Si (silicon) and is a semiconductor region with a high impurity concentration and a p-type conductivity type. A pn ​​junction is formed at the interface between the p-type semiconductor region 212 and the n-type semiconductor region 211. The p-type semiconductor region 212 has a carrier multiplication region that multiplies the carriers that enter due to the entry of the light to be detected by avalanche multiplication. The p-type semiconductor region 212 can be depleted. The depletion of the p-type semiconductor region 212 makes it possible to improve the PDE.

[0063] The n-type semiconductor region 211 serves as the cathode of the light-receiving element 21. The n-type semiconductor region 211 is connected to the pixel circuit via contact 214 and wiring. Figure 4 (Not shown in the image). The anode 215 of the light-receiving element 21 paired with the cathode is formed in the same layer as the n-type semiconductor region 211 to surround the n-type semiconductor region 211 (see reference). Figure 3 An anode 215 is formed between an n-type semiconductor region 211 and an oxide film 218 formed on the sidewall of each of the first and second light-shielding portions 22 and 23. The anode 215 is connected to a power supply (not shown) disposed in an external circuit via a contact 216 and wiring.

[0064] Not only the first light-shielding portion 22 and the oxide film 218, but also the second light-shielding portion 23 and the oxide film 218 serve as separation regions for separating the pixels 20 from each other. A hole accumulation region 217 is formed between the oxide film 218 and the well layer 213. The hole accumulation region 217 is formed below the anode 215. The hole accumulation region 217 is electrically connected to the anode 215. For example, the hole accumulation region 217 can be formed as a p-type semiconductor region. The hole accumulation region 217 can be formed by ion implantation, solid-phase diffusion, induction by a fixed charge film, or other means.

[0065] Cavity accumulation region 217 is formed in the part where different materials come into contact. Figure 4 In the example shown, the materials included in the oxide film 218 are different from those included in the well layer 213. Therefore, if the oxide film 218 and the well layer 213 are in contact, there is a possibility that dark current may occur at the interface between them. Therefore, by forming a hole accumulation region 217 between the oxide film 218 and the well layer 213, dark current can be suppressed.

[0066] In the case of using a light-receiving element 21 including an APD in a back-illuminated solid-state imaging device, an on-chip lens (not shown) is stacked, for example, below the well layer 213 (on the side opposite to the side forming the n-type semiconductor region 211). A hole accumulation region may be formed at the interface with the well layer 213 on the side forming the on-chip lens.

[0067] Meanwhile, in the case of using a light-receiving element 21 including an APD in a front-illuminated solid-state imaging device, for example, the silicon substrate is arranged below the well layer 213 (on the side opposite to the side where the n-type semiconductor region 211 is formed). Therefore, in the case of using a light-receiving element 21 including an APD in a front-illuminated solid-state imaging device, a pixel configuration in which no hole accumulation region is formed can be adopted. Needless to say, even when the light-receiving element 21 including an APD is used in a front-illuminated solid-state imaging device, the hole accumulation region 217 can be formed below the well layer 213.

[0068] That is, the hole accumulation region 217 can be formed on a surface other than the upper surface of the well layer 213 (the surface on which the n-type semiconductor region 211 is formed). Optionally, the hole accumulation region 217 can be formed on a surface other than the upper or lower surface of the well layer 213.

[0069] The first light-shielding portion 22, the second light-shielding portion 23, and the oxide film 218 are formed between adjacent pixels 20 to separate the light-receiving elements 21 formed in the pixels 20 from each other. That is, the first light-shielding portion 22, the second light-shielding portion 23, and the oxide film 218 are formed such that the multiplication regions are formed in a one-to-one correspondence with the light-receiving elements 21. The first light-shielding portion 22, the second light-shielding portion 23, and the oxide film 218 are formed in a two-dimensional grid pattern so as to completely surround the periphery of each n-type semiconductor region 211 (i.e., the multiplication region) (see reference). Figure 3 The first light-shielding portion 22, the second light-shielding portion 23, and the oxide film 218 are formed to penetrate the well layer 213 from the upper surface side to the lower surface side in the stacking direction. The first light-shielding portion 22, the second light-shielding portion 23, and the oxide film 218 can be configured to not only completely penetrate the well layer 213 from the upper surface side to the lower surface side, but also, for example, to only partially penetrate the well layer 213 from the upper surface side to the lower surface side and be inserted in the middle of the substrate.

[0070] like Figure 3 As shown, pixels 20a, 20b, 20c, and 20d in pixel group 3 are separated by a second light-shielding portion 23 formed in a grid pattern and an oxide film 218. An anode 215 is formed inside the second light-shielding portion 23. A well layer 213 is formed between the anode 215 and the n-type semiconductor region 211. The n-type semiconductor region 211 is formed at the center of the light-receiving element 21.

[0071] Although the hole accumulation region 217 is not visible when viewed from above, it is formed inside the second light-shielding portion 23. In other words, the hole accumulation region 217 is formed in the same region as the anode 215.

[0072] When viewed from above, the shape of the n-type semiconductor region 211 is not limited to a rectangle, and can also be circular. The n-type semiconductor region 211 is formed as follows... Figure 3 In the case of the rectangular shape shown, a large area can be ensured as a multiplication region (n-type semiconductor region 211), which can improve the detection efficiency known as PDE. When the n-type semiconductor region 211 is formed into a circular shape, the electric field concentration at the edge portion of the n-type semiconductor region 211 can be suppressed, thereby reducing unwanted edge breakdown.

[0073] As described above, by forming a hole accumulation region 217 at the interface, electrons generated at the interface can be captured, thus suppressing dark current (DCR). Furthermore, in this embodiment, pixel 20 captures electrons by accumulating holes in the hole accumulation region 217. However, pixel 20 can also be configured to capture holes by accumulating electrons. Even when pixel 20 is configured to capture holes, DCR can still be suppressed.

[0074] Furthermore, the solid-state imaging device 1 can reduce at least one of electrical crosstalk and optical crosstalk by including a first light-shielding part 22, a second light-shielding part 23, an oxide film 218, and a hole accumulation region 217. In addition, by providing the hole accumulation region 217 on the side of the pixel 20, a lateral electric field is formed, which facilitates the recovery of charge carriers in the high electric field region and can improve the PDE.

[0075] <Circuit Configuration of Solid State Imaging Device>

[0076] Next, we will refer to Figures 2 to 4 And by using Figures 5 to 9 A description is given of the peripheral circuitry and pixel circuitry included in the solid-state imaging apparatus 1 according to this embodiment.

[0077] like Figure 5 As shown, the solid-state imaging device 1 includes a control unit 31, whose integrated control includes peripheral circuitry and pixel circuitry within the solid-state imaging device 1. The control unit 31 includes, for example, a central processing unit (CPU). The solid-state imaging device 1 includes a laser control unit 33, a pixel driving unit (an example of a driving unit) 26, and a distance measurement processing unit 35, all connected to the control unit 31.

[0078] The control unit 31 is configured to output a light emission control signal Slc to the laser control unit 33 and the distance measurement processing unit 35. Furthermore, the control unit 31 is configured to output a distance measurement start signal Srs to the pixel driving unit 26. The control unit 31 synchronizes the light emission control signal Slc with the distance measurement start signal Srs and outputs these signals to the laser control unit 33, the distance measurement processing unit 35, and the pixel driving unit 26.

[0079] The pixel driving unit 26 included in the solid-state imaging device 1 is configured to drive pixels 20a, 20b, 20c, and 20d by respectively offsetting the operating timing of light-receiving elements 21 disposed in pixels 20a, 20b, 20c, and 20d. The pixel driving unit 26 has a gate-on signal generation unit (example of a signal generation unit) 261, which generates gate control signals Sg1 and Sg2 (examples of signals) in response to an input of a distance measurement start signal Srs (example of a synchronization signal) synchronized with a light emission control signal Slc that controls the emission of light from the light source 91. Furthermore, the pixel driving unit 26 has a decoder 262, which is controlled by the signals generated by the gate-on signal generation unit 261 to output control signals Ssc1, Ssc2, Ssc3, and Ssc4 to control the switching element 25 (described in detail later).

[0080] The distance measurement processing unit 35 included in the solid-state imaging device 1 is configured such that an electrical signal obtained from each of pixels 20a, 20b, 20c, and 20d through photoelectric conversion by the light receiving element 21 is input, and the distance measurement processing unit 35 includes: a time measurement unit 351, which measures the time up to the emission of light from the light source 91 based on the input of the electrical signal (in... Figure 5 (Not shown in the image; refer to Figure 1) This is from object 8 ( Figure 5 (Not depicted in the image; refer to Figure 1) and received by the light receiving element 21. The time measurement unit 351 includes, for example, a time-to-digital converter, which converts time information of an analog signal based on an electrical signal output from the light receiving element 21 into time information of a digital signal. A light emission control signal Slc is input to the time measurement unit 351. The time measurement unit 351 measures the time it takes for light emitted from the light source 91 to be reflected by the object 8 and received by the light receiving element 21 in response to the input of the light emission control signal Slc as a trigger. Furthermore, the time measurement unit 351 terminates the time measurement in response to the input of a detection signal from the detection circuit 24 (described in detail later) via the selection circuit 34, based on the electrical signal output from the light receiving element 21 as a trigger.

[0081] The distance measurement processing unit 35 included in the solid-state imaging device 1 has a distance calculation unit 352, which calculates the distance to the object 8 based on time information output from the time measurement unit 351. The distance measurement processing unit 35 is configured to measure the distance between the solid-state imaging device 1 and the object 8 using Time-of-Flight (ToF) technology. Specifically, time information including the time of flight of light ΔT is input from the time measurement unit 351 to the distance calculation unit 352. The time of flight of light ΔT corresponds to the time until the light emitted from the light source 91 is reflected by the object 8 and received by the light receiving element 21. The time measurement unit 351 obtains the time of flight of light ΔT by calculating the difference (te-ts) between the measured time ts of the time until the light emitted from the light source 91 is reflected by the object 8 and received by the light receiving element 21 and the time te at the end of the measurement. The distance calculation unit 352 calculates the distance D between the solid-state imaging device 1 and the object 8 using the formula (1) given below. It should be noted that “c” in formula (1) represents the speed of light.

[0082] D=(c / 2)×(te-ts)…(1)

[0083] The laser control unit 33 emits a laser beam toward the object 8 in response to the input of the emission control signal Slc, which serves as a trigger. The gate conduction signal generation unit 261 outputs gate control signals Sg1 and Sg2 to the decoder 262 based on the input of the distance measurement start signal Srs, which serves as a trigger. Furthermore, as will be explained in detail later, the pixel 20 starts the light detection operation of the light receiving element 21 based on the output of the gate control signals Sg1 and Sg2, which serve as triggers. In addition, the distance measurement processing unit 35 starts measuring the time when the light emitted from the light source 91 is reflected by the object 8 and received by the light receiving element 21 in response to the input of the emission control signal Slc, which serves as a trigger. This allows the solid-state imaging device 1 to synchronize the start of the output of the laser beam from the light source 91 with the start of the reception of the light through the light receiving element 21 and the start of the time measurement by the distance measurement processing unit 35.

[0084] Each of pixels 20a, 20b, 20c, and 20d has a switching element 25 connected between the cathode of an avalanche photonic diode included in the light receiving element 21 and a power supply Ve. The pixel driving unit 26 generates control signals Ssc1, Ssc2, Ssc3, and Ssc4 to control the switching element 25 to turn on and off. In this embodiment, a decoder 262 provided in the pixel driving unit 26 generates the control signals Ssc1, Ssc2, Ssc3, and Ssc4. The switching element 25 and the decoder 262 will be described in detail later.

[0085] Each of pixels 20a, 20b, 20c, and 20d has a detection circuit 24, to which an electrical signal output from the light-receiving element 21 is input. The detection circuit 24 may include, for example, an inverter circuit. The detection circuit 24 will be described in detail later.

[0086] The solid-state imaging device 1 includes a selection circuit 34 connected between the detection circuit 24 and the time measurement unit 351. Under the control of the control unit 31, the selection circuit 34 outputs the output signal of the detection circuit 24 provided in any one of the pixels 20a, 20b, 20c, and 20d to the time measurement unit 351. The selection circuit 34 will be described in detail later.

[0087] The control unit 31, laser control unit 33, gate conduction signal generation unit 261, and distance measurement processing unit 35 are formed in the surrounding area A2 and the pad area A3 and are included in the peripheral circuit. Furthermore, the decoder 262, switching element 25, detection circuit 24, selection circuit 34, and power supply circuit 27 are also included. Figure 5 Not shown in the image; see reference. Figure 6 The pixel group 2, which will be described later, is formed in pixel region A1 and included in the pixel circuitry. A decoder 262, a switching element 25, a detection circuit 24, and a selection circuit 34 are provided for each pixel group 2.

[0088] like Figure 6 As shown, the switching element 25 included in each of pixels 20a, 20b, 20c, and 20d includes a P-type transistor. The gate of the switching element 25 is connected to the output terminal of the decoder 262. More specifically, the gate of the switching element 25 in pixel 20a is connected to the output terminal of the decoder 262, from which a control signal Ssc1 is output. The gate of the switching element 25 in pixel 20b is connected to the output terminal of the decoder 262, from which a control signal Ssc12 is output. The gate of the switching element 25 in pixel 20c is connected to the output terminal of the decoder 262, from which a control signal Ssc3 is output. The gate of the switching element 25 in pixel 20d is connected to the output terminal of the decoder 262, from which a control signal Ssc4 is output.

[0089] Therefore, when control signal Ssc1 is at a low voltage level, the switch element 25 in pixel 20a is turned on (ON), and when control signal Ssc1 is at a high voltage level, switch element 25 is turned off (OFF). When control signal Ssc2 is at a low voltage level, switch element 25 in pixel 20b is turned on (ON), and when control signal Ssc2 is at a high voltage level, switch element 25 is turned off (OFF). When control signal Ssc3 is at a low voltage level, switch element 25 in pixel 20c is turned on (ON), and when control signal Ssc3 is at a high voltage level, switch element 25 is turned off (OFF). When control signal Ssc4 is at a low voltage level, switch element 25 in pixel 20d is turned on (ON), and when control signal Ssc4 is at a high voltage level, switch element 25 is turned off (OFF). Decoder 262 is configured to set the voltage of any one of control signals Ssc1, Ssc2, Ssc3, and Ssc4 to a low level and set the remaining voltage to a high level. Therefore, the pixel driving unit 26 can drive the pixel group 2, so that any one of the pixels 20a, 20b, 20c, and 20d set in the pixel group 2 is turned on, while the other pixels are not turned on.

[0090] The switching element 25 disposed in pixel 20a has a source connected to the power supply circuit 27 (described in detail later) and a drain connected to the cathode of the light receiving element 21 disposed in pixel 20a. The switching element 25 disposed in pixel 20b has a source connected to the power supply circuit 27 and a drain connected to the cathode of the light receiving element 21 disposed in pixel 20b. The switching element 25 disposed in pixel 20c has a source connected to the power supply circuit 27 and a drain connected to the cathode of the light receiving element 21 disposed in pixel 20c. The switching element 25 disposed in pixel 20d has a source connected to the power supply circuit 27 and a drain connected to the cathode of the light receiving element 21 disposed in pixel 20d.

[0091] The detection circuit 24 in pixel 20a has an input terminal and an output terminal. The input terminal is connected to the drain of the switching element 25 and the cathode of the light receiving element 21 in pixel 20a. The output terminal is connected to the selection circuit 34. The detection circuit 24 in pixel 20b has an input terminal and an output terminal. The input terminal is connected to the drain of the switching element 25 and the cathode of the light receiving element 21 in pixel 20b. The output terminal is connected to the selection circuit 34. The detection circuit 24 in pixel 20c has an input terminal and an output terminal. The input terminal is connected to the drain of the switching element 25 and the cathode of the light receiving element 21 in pixel 20c. The output terminal is connected to the selection circuit 34. The detection circuit 24 in pixel 20d has an input terminal and an output terminal. The input terminal is connected to the drain of the switching element 25 and the cathode of the light receiving element 21 in pixel 20d. The output terminal is connected to the selection circuit 34.

[0092] like Figure 6 As shown, pixel group 2 has a power supply circuit 27 connected to light receiving element 21 via switching element 25. Power supply circuit 27 has a current mirror circuit 271 and a constant current source 272. The constant current source 272 provides a constant current to the current mirror circuit 271. The current mirror circuit 271 has a P-type transistor 271a connected to the constant current source 272 and four P-type transistors 271b connected to the P-type transistor 271a.

[0093] A constant current source 272 and a P-type transistor 271a are connected in series between the power supply Ve and ground (GND). The source of the P-type transistor 271a is connected to the output terminal of the constant current source 272, and the drain is connected to the power supply Ve. The gate of the P-type transistor 271a is connected to the source of the P-type transistor 271a and to the gate of each of the four P-type transistors 271b.

[0094] The source of the P-type transistor 271b in pixel 20a is connected to the power supply Ve, and its drain is connected to the source of the switching element 25 in pixel 20a. The source of the P-type transistor 271b in pixel 20b is connected to the power supply Ve, and its drain is connected to the source of the switching element 25 in pixel 20b. The source of the P-type transistor 271b in pixel 20c is connected to the power supply Ve, and its drain is connected to the source of the switching element 25 in pixel 20c. The source of the P-type transistor 271b in pixel 20d is connected to the power supply Ve, and its drain is connected to the source of the switching element 25 in pixel 20d.

[0095] The four P-type transistors 271b have the same transistor size. The P-type transistor 271a is formed to allow it to deliver the desired current to each of the four P-type transistors 271b. This allows the current mirror circuit 271 to deliver the same and desired current to the light receiving elements 21 disposed in pixels 20a, 20b, 20c, and 20d, respectively.

[0096] The anode of the light-receiving element 21 in each of pixels 20a, 20b, 20c, and 20d is connected to a power supply Vbd. The power supply Vbd is configured to output, for example, a voltage of -20V. For example, the power supply Ve is configured to output a voltage of +3V to +5V. Therefore, when the switching element 25 is turned on, a voltage of -20V is applied to the anode of the light-receiving element 21, and a voltage of +3V to +5V is applied to its cathode. This results in a voltage higher than the breakdown voltage being applied to the light-receiving element 21. If the light-receiving element 21 receives light in this state, avalanche amplification occurs, causing current to flow. The current flow through the light-receiving element 21 reduces the cathode voltage of the light-receiving element 21.

[0097] When the switching element 25 is not conducting, or before current flows through the photoreceiving element 21, a voltage approximately the same as the output voltage of the power supply Ve is input to the input terminal of the detection circuit 24. Therefore, the detection circuit 24 outputs a low-level voltage. Simultaneously, when the cathode voltage level drops below 0V due to current flowing through the photoreceiving element 21, the detection circuit 24 outputs a high-level voltage.

[0098] The output terminals of the four detection circuits 24 are connected to the selection circuit 34. Therefore, the output signals of the four detection circuits 24 are input to the selection circuit 34. A selection signal is input from the control unit 31 to the selection circuit 34. Based on the selection signal, the selection circuit 34 outputs any one of the output signals of the four detection circuits 24 to the distance measurement processing unit 35.

[0099] This will be done by using Figure 7 Provide a description of the specific configuration of decoder 262.

[0100] like Figure 7 As shown, the decoder 262 has inverter gates 262a and 262b disposed on its input side and NAND gates 262c, 262d, 262e, and 262f disposed on its output side. The input terminals of inverter gates 262a and 262b are used as input terminals of the decoder 262. A gate control signal Sg1 is input to the input terminal of inverter gate 262a. A gate control signal Sg2 is input to the input terminal of inverter gate 262b.

[0101] The input terminal of inverter gate 262a is connected to one of the input terminals of each of NAND gates 262e and 262f. The output terminal of inverter gate 262a is connected to one of the input terminals of each of NAND gates 262c and 262d. The input terminal of inverter gate 262b is connected to the other input terminal of each of NAND gates 262d and 262f. The output terminal of inverter gate 262b is connected to the other input terminal of each of NAND gates 262c and 262e.

[0102] The output terminals of NAND gates 262c, 262d, 262e, and 262f are used as output terminals of decoder 262. For example, output control signal Ssc1 is output from the output terminal of NAND gate 262c. For example, output control signal Ssc2 is output from the output terminal of NAND gate 262d. For example, output control signal Ssc3 is output from the output terminal of NAND gate 262e. For example, output control signal Ssc4 is output from the output terminal of NAND gate 262f.

[0103] When both gate control signals Sg1 and Sg2 are at low voltage levels, control signal Ssc1 is at a low voltage level, and control signals Ssc2, Ssc3, and Ssc4 are at high voltage levels. This only drives the settings at pixel 20a (reference). Figure 6 Switching element 25 in the circuit is turned on and the remaining switching element 25 (reference) is turned on. Figure 6 When the gate control signal Sg1 is at a low voltage level and the gate control signal Sg2 is at a high voltage level, the control signal Ssc2 is at a low voltage level, and the control signals Ssc1, Ssc3, and Ssc4 are at a high voltage level. Therefore, only the switching element 25 in pixel 20b is turned on, and the remaining switching elements 25 are turned off. When the gate control signal Sg1 is at a high voltage level and the gate control signal Sg2 is at a low voltage level, the control signal Ssc3 is at a low voltage level, and the control signals Ssc1, Ssc2, and Ssc4 are at a high voltage level. Therefore, only the switching element 25 in pixel 20c is turned on, and the remaining switching elements 25 are turned off. When both the gate control signals Sg1 and Sg2 are at a high voltage level, the control signal Ssc4 is at a low voltage level, and the control signals Ssc1, Ssc2, and Ssc3 are at a high voltage level. Therefore, only the switching element 25 in pixel 20d is turned on, and the remaining switching elements 25 are turned off.

[0104] As described above, the decoder 262 can control any one of the four switching elements 25 to be turned on, while the remaining switching elements 25 are turned off. The pixel driving unit 26 operates synchronously with the laser control unit 33, and therefore, the voltage levels of the gate control signals Sg1 and Sg2 can be changed synchronously with the output of the laser from the light source 91. This allows the decoder 262 to sequentially switch the voltage levels of the control signals Ssc1, Ssc2, and Ssc4 synchronously with the output of the laser beam from the light source 91. Therefore, the solid-state imaging device 1 can sequentially enable the light receiving elements 21 respectively disposed in pixels 20a, 20b, 20c, and 20d to detect light.

[0105] Next, the specific structure of the detection circuit 24 will be explained.

[0106] like Figure 8 As shown, the detection circuit 24 has a P-type transistor 241 and an N-type transistor 242 connected in series between the power supply VDD and ground. The gates of the P-type transistor 241 and the N-type transistor 242 are connected to each other. The connection between the gates of the P-type transistor 241 and the N-type transistor 242 serves as the input terminal of the detection circuit 24. The source of the P-type transistor 241 is connected to the power supply VDD. The source of the N-type transistor 242 is grounded. The drains of the P-type transistor 241 and the N-type transistor 242 are connected to each other. The connection between the drains of the P-type transistor 241 and the N-type transistor 242 serves as the output terminal of the detection circuit 24.

[0107] This configuration allows the detection circuit 24 to output a high-voltage signal when a low-voltage signal is input, and a low-voltage signal when a high-voltage signal is input. As described above, when the light-receiving element 21 does not receive light, the cathode voltage of the light-receiving element 21 is approximately the same as the output voltage of the power supply Ve and is at a high level (e.g., 3V to 5V). Therefore, when the light-receiving element 21 does not receive light, the detection circuit 24 outputs a detection signal at a low voltage level. Simultaneously, when the light-receiving element 21 receives light, the cathode voltage of the light-receiving element 21 is approximately the same as the output voltage of the power supply Vbd and is at a low level (e.g., -20V). Therefore, when the light-receiving element 21 receives light, the detection circuit 24 outputs a detection signal at a high voltage level.

[0108] Next, the specific structure of the selection circuit 34 will be described. The selection circuit 34 has logic circuitry connected to each detection circuit 24. For example... Figure 9 As shown, the logic circuit is, for example, a logic AND circuit. That is, the selection circuit 34 has as many elements as the detection circuit 24. Figure 9 The OR circuit shown is an example of logic and circuits 341.

[0109] The OR circuit 341 has two P-type transistors 341a and 341b and one N-type transistor 341c connected in series between the power supply VDD and the reference potential VSS, which is at the same voltage level as ground. The gate of the P-type transistor 341a is used as one of the input terminals of the OR circuit 341 and is connected, for example, to the output terminal of the detection circuit 24. The gate of the P-type transistor 341b is used as the other input terminal of the OR circuit 341 and is connected, for example, to the control unit 31. The source of the P-type transistor 341a is connected to the power supply VDD. The drain of the P-type transistor 341a is connected to the source of the P-type transistor 341b. The source of the N-type transistor 341c is connected to the reference potential VSS. The drains of the N-type transistor 341c and the P-type transistor 341b are connected to each other.

[0110] OR circuit 341 has an N-type transistor 341d, which is connected between the drain of N-type transistor 341c and P-type transistor 341b and the reference potential VSS. The gate of N-type transistor 341d is connected to the gate of P-type transistor 341b.

[0111] OR circuit 341 has a P-type transistor 341e and an N-type transistor 341f connected between a power supply VDD and a reference potential VSS. The gates of the P-type transistor 341e and the N-type transistor 341f are interconnected. The connection between the gates of the P-type transistor 341e and the N-type transistor 341f is connected to the connection between the drain of the N-type transistor 341c and the drain of the P-type transistor 341b. The source of the P-type transistor 341e is connected to the power supply VDD. The source of the N-type transistor 341f is connected to the reference potential VSS. The drains of the P-type transistor 341e and the N-type transistor 341f are interconnected. The connection between the drains of the P-type transistor 341e and the N-type transistor 341f serves as the output terminal of OR circuit 341.

[0112] When a high-level selection signal is input from the control unit 31, the OR circuit 341 outputs a signal equal to the voltage level of the power supply VDD. Conversely, when a low-level selection signal is input from the control unit 31, the OR circuit 341 outputs the same signal as the detection signal input from the detection circuit 24. Therefore, the selection circuit 34 can select one of the detection signals from the four detection circuits 24 based on the selection signal input from the control unit 31 and output that detection signal to the distance measurement processing unit 35.

[0113] Operation of Solid State Imaging Devices

[0114] Next, we will refer to Figure 5 and Figure 6 And by using Figure 10Here is a description of the operation of the solid-state imaging apparatus 1 according to this embodiment. Figure 10 This is a timing diagram illustrating an example of the operation of solid-state imaging device 1. Figure 10 The term "laser" in this context refers to the emission pattern of the laser beam output from light source 91. The high level of the emission pattern indicates the duration of laser beam emission. Figure 10 In this context, "Ssc1, Ssc2, Ssc3, Ssc4" represent the control signals Ssc1, Ssc2, Ssc3, and Ssc4 output from the decoder 262.

[0115] Figure 10 In this context, "SPADa" represents the cathode voltage waveform of the light receiving element 21 located in pixel 20a. Figure 10 In this context, "SPADb" represents the cathode voltage waveform of the light receiving element 21 located in pixel 20b. Figure 10 In this context, "SPADc" refers to the cathode voltage waveform of the light receiving element 21 located in pixel 20c. Figure 10 In this context, "SPADd" refers to the cathode voltage waveform of the light receiving element 21 located in pixel 20d. Figure 10 In the text, "detection circuit a" refers to the detection signal voltage waveform of the detection circuit 24 set in pixel 20a. Figure 10 In the text, "detection circuit b" refers to the detection signal voltage waveform of the detection circuit 24 set in pixel 20b. Figure 10 The “detection circuit c” in the text refers to the detection signal voltage waveform of the detection circuit 24 set in pixel 20c. Figure 10 In the text, "detection circuit d" refers to the detection signal voltage waveform of the detection circuit 24 set in pixel 20d. Figure 10 The term "selection circuit" refers to the output signal of selection circuit 34.

[0116] like Figure 10 As shown, at time t1, the control signal Ssc1 output from the decoder 262 synchronously becomes a high voltage level with the start of the output of the laser beam from the light source 91. This causes the switching element 25 located in pixel 20a to turn on. Then, the laser beam reflected from object 8 is received by the light receiving element 21 located in pixel 20a, and current begins to flow through the light receiving element 21, causing the cathode voltage of the light receiving element 21 to decrease.

[0117] Within a predetermined time period after time t1, when the cathode voltage of the light-receiving element 21 located in pixel 20a at time t2 reaches, for example, 0 volts (more precisely, a voltage lower than the threshold voltage of the transistor contained in the detection circuit 24), the detection signal of the detection circuit 24 located in pixel 20a changes from a low voltage level to a high voltage level. When a given time period has elapsed from time t2, the cathode voltage of the light-receiving element 21 drops below the power supply voltage Vbd, which is the breakdown voltage, thus stopping avalanche amplification. After avalanche amplification in the light-receiving element 21 has stopped, the cathode voltage of the light-receiving element 21 begins to return to the initial voltage of the power supply Ve (recharging operation).

[0118] When the detection signal of the detection circuit 24 in pixel 20a becomes high, the selection circuit 34, under the control of the control unit 31, selects the detection signal of the detection circuit 24 in pixel 20a and outputs the signal to the time measurement unit 351 (reference) in the distance measurement processing unit 35. Figure 5 ).

[0119] The output of the laser beam from light source 91 begins at time t3 after the recharging operation starts in the light receiving element 21 located in pixel 20a. Control signal Ssc1 output from decoder 262 becomes a low voltage level, and control signal Ssc2 synchronously becomes a high voltage level in sync with the laser beam output. Consequently, the switching element 25 located in pixel 20a is de-conducted, and the switching element 25 located in the non-conducting pixel 20b becomes conducted. Thereafter, current begins to flow through the light receiving element 21 located in pixel 20b, receiving the laser beam reflected from object 8, which reduces the cathode voltage of the light receiving element 21.

[0120] When the cathode voltage of the light-receiving element 21 in pixel 20b reaches, for example, 0 volts (more precisely, below the threshold voltage of the transistor included in the detection circuit 24) at time t4 within a given time period after time t3, the detection signal of the detection circuit 24 in pixel 20b changes from a low voltage level to a high voltage level. When a given time period has elapsed since time t4, the cathode voltage of the light-receiving element 21 drops below the power supply voltage Vbd, which is the breakdown voltage, thus stopping avalanche amplification. After avalanche amplification in the light-receiving element 21 has stopped, the cathode voltage of the light-receiving element 21 begins to return to the initial voltage of the power supply Ve (recharging operation). When the charging operation of the light-receiving element 21 in pixel 20b begins, the light-receiving element 21 in pixel 20a continues its charging operation.

[0121] When the detection signal of the detection circuit 24 in pixel 20b becomes high, the selection circuit 34, under the control of the control unit 31, replaces the detection signal of the detection circuit 24 in pixel 20a, selects the detection signal of the detection circuit 24 in pixel 20b, and outputs it to the time measurement unit 351 in the distance measurement processing unit 35.

[0122] At time t5 after the recharging operation begins in the light-receiving element 21 located in pixel 20b, a laser beam begins to be output from the light source 91. The control signal Ssc2 output from the decoder 262 becomes a low voltage level, and the control signal Ssc3 becomes a high voltage level synchronously with the output of the laser beam. As a result, the switching element 25 located in pixel 20b is not turned on, and the switching element 25 located in the non-conducting pixel 20c is turned on. Thereafter, current begins to flow through the light-receiving element 21 receiving the laser beam reflected by the object 8, which reduces the cathode voltage of the light-receiving element 21.

[0123] When the cathode voltage of the light-receiving element 21 in pixel 20c reaches, for example, 0 volts (more precisely, below the threshold voltage of the transistor included in the detection circuit 24) at time t6 within a given time period after time t5, the detection signal of the detection circuit 24 in pixel 20c changes from a low voltage level to a high voltage level. When a given time period has elapsed since time t6, the cathode voltage of the light-receiving element 21 drops below the power supply voltage Vbd, which is the breakdown voltage, thus stopping avalanche amplification. After avalanche amplification in the light-receiving element 21 has stopped, the cathode voltage of the light-receiving element 21 begins to return to the initial voltage of the power supply Ve (recharge operation). When the recharge operation of the light-receiving element 21 in pixel 20c begins, the light-receiving elements 21 in pixel 20a and pixel 20b continue their respective recharge operations.

[0124] When the detection signal of the detection circuit 24 in pixel 20c becomes high, the selection circuit 34, under the control of the control unit 31, replaces the detection signal of the detection circuit 24 in pixel 20b, selects the detection signal of the detection circuit 24 in pixel 20c, and outputs the signal to the time measurement unit 351 in the distance measurement processing unit 35.

[0125] During a specified period after time t6, at time t7, if the cathode voltage of the light receiving element 21 provided in pixel 20a reaches or exceeds the threshold voltage of the transistor in the detection circuit 24 provided in pixel 20a, then the detection signal output from the detection circuit 24 changes from a low voltage level to a high voltage level.

[0126] After a given time t7 following the detection signal output from the detection circuit 24 in pixel 20a becoming a low voltage level, a laser beam is output from the light source 91 at time t8. The control signal Ssc3 output from the decoder 262 becomes a low voltage level, and the control signal Ssc4 becomes a high voltage level synchronously with the laser beam output. Consequently, the switching element 25 in pixel 20c is de-conducted, and the switching element 25 in the non-conducting pixel 20d becomes conducted. Thereafter, the laser beam reflected from the object 8 is received by the light receiving element 21 in pixel 20d, and current begins to flow through the light receiving element 21, which reduces the cathode voltage of the light receiving element 21.

[0127] When the cathode voltage of the light-receiving element 21 in pixel 20d reaches, for example, 0 volts (more precisely, below the threshold voltage of the transistor included in the detection circuit 24) at time t9 within a given time period after time t8, the detection signal of the detection circuit 24 in pixel 20d changes from a low voltage level to a high voltage level. As a given time period elapses from time t9, the cathode voltage of the light-receiving element 21 drops below the power supply voltage Vbd, which is the breakdown voltage, thus stopping avalanche amplification. After avalanche amplification in the light-receiving element 21 has stopped, the cathode voltage of the light-receiving element 21 begins to return to the initial voltage of the power supply Ve (recharging operation). When the charging operation of the light-receiving element 21 in pixel 20c begins, the light-receiving elements 21 in pixel 20a, pixel 20b, and pixel 20c continue their charging operations.

[0128] When the detection signal of the detection circuit 24 provided in pixel 20d becomes high, under the control of the control unit 31, the selection circuit 34 replaces the detection signal of the detection circuit 24 provided in pixel 20c, selects the detection signal of the detection circuit 24 provided in pixel 20d, and outputs it to the time measurement unit 351 provided in the distance measurement processing unit 35.

[0129] When the cathode voltage of the light-receiving element 21 in pixel 20b reaches a voltage equal to or higher than the threshold voltage of the transistor included in the detection circuit 24 in pixel 20b within a given time period after time t9 at time t10, the detection signal output from the detection circuit 24 changes from a low voltage level to a high voltage level. Furthermore, the light-receiving element 21 in pixel 20a ends its recharging operation at time t10.

[0130] When the cathode voltage of the light-receiving element 21 in pixel 20c reaches a voltage equal to or higher than the threshold voltage of the transistor included in the detection circuit 24 in pixel 20c within a given time period after time t10, the detection signal output from the detection circuit 24 changes from a high voltage level to a low voltage level. Furthermore, the light-receiving element 21 in pixel 20b ends its recharging operation at time t11.

[0131] When the cathode voltage of the light-receiving element 21 in pixel 20d reaches a voltage equal to or higher than the threshold voltage of the transistor included in the detection circuit 24 in pixel 20d within a given time period after time t11 at time t12, the detection signal output from the detection circuit 24 changes from a high voltage level to a low voltage level. Furthermore, the light-receiving element 21 in pixel 20c ends its recharging operation at time t12. Additionally, when a given time period has elapsed from time t12, the light-receiving element 21 in pixel 20d ends its recharging operation. The solid-state imaging device 1 repeats the operation from time t1 to time t12. However, it should be noted that after the recharging operation of the light-receiving element 21 in pixel 20c begins, the control signal Ssc4 output from the decoder 262 becomes a low voltage level, and the control signal Ssc1 becomes a high voltage level synchronously with the first output of the laser beam from the light source 91.

[0132] Incidentally, the time period during which the light receiving element 21 performs its recharging operation is the time period during which the light receiving element 21 cannot receive light. Here, if we focus on, for example, the light receiving element 21 located in pixel 20a, the recharging operation time period of the light receiving element 21 located in pixel 20a ranges from a given time slightly earlier than time t3 to time t10. Therefore, at times t3, t5, and t8, the light receiving element 21 cannot receive the laser beam emitted onto and reflected from the object 8. Therefore, in conventional solid-state imaging devices... Figure 10 In the timing operation shown, the solid-state imaging device cannot receive only one of the four laser beams emitted. Therefore, conventional solid-state imaging devices cannot receive high-frequency laser beams and have limitations on increasing the laser beam frequency. Consequently, conventional solid-state imaging devices cannot achieve sufficient frame rates and suffer from time-consuming distance measurements.

[0133] Conversely, the solid-state imaging device 1 according to this embodiment is configured to drive pixels 20a, 20b, 20c, and 20d in the pixel group 2 by timing the operation of these pixels. Furthermore, in the solid-state imaging device 1, pixels 20a, 20b, 20c, and 20d in the pixel group 2 are connected to a single-measurement unit 351. This allows the solid-state imaging device 1 to input detection signals indicating timing offsets from detection circuits 24 respectively provided in pixels 20a, 20b, 20c, and 20d to the time measurement unit 351. This enables the solid-state imaging device 1 to detect high-frequency pulsed light. This allows the solid-state imaging device 1 to achieve a sufficient frame rate and reduce the time required for distance measurement.

[0134] (Variation Example 1)

[0135] Next, by using Figure 11 and Figure 12 A description of a solid-state imaging apparatus according to a modified example 1 of this embodiment will be given. The solid-state imaging apparatus according to this modified example is characterized in that, unlike the solid-state imaging apparatus 1 according to the above embodiment, it does not include a second light-shielding portion 23. It should be noted that components having the same operation and function as those in the solid-state imaging apparatus 1 according to the above embodiment will be indicated by the same reference numerals, and their descriptions will be omitted.

[0136] like Figure 11 As shown, the solid-state imaging device according to this modification includes a pixel group 4 having a plurality of pixels 20a, 20b, 20c, and 20d (four pixels in this embodiment). Pixels 20a, 20b, 20c, and 20d are arranged adjacent to each other. Figure 11 and Figure 12 As shown, pixel group 4 has a first light-shielding portion (an example of a light-shielding portion) 22 configured to surround the outer periphery of pixel group 4, and no light-shielding portion is provided between adjacent pixels in pixels 20a, 20b, 20c and 20d. That is, no light-shielding portion is provided between pixels 20a and 20b, between pixels 20a and 20c and between pixels 20b and 20d.

[0137] Hole accumulation region 217 is disposed between pixels 20a and 20b, between pixels 20a and 20c, and between pixels 20b and 20d. Pixels 20a, 20b, 20c, and 20d are separated by hole accumulation region 217.

[0138] Since no light-shielding portions are provided between adjacent pixels in pixels 20a, 20b, 20c, and 20d, the solid-state imaging apparatus according to this modification does not require any grooves. Therefore, the aperture ratio of pixels 20a, 20b, 20c, and 20d can be increased, thereby improving sensitivity. Furthermore, in the solid-state imaging apparatus according to this modification, when any one of pixels 20a, 20b, 20c, and 20d is active, the remaining pixels are inactive. Therefore, compared to conventional solid-state imaging apparatuses, the solid-state imaging apparatus according to this modification is less susceptible to light leakage caused by the absence of light-shielding portions between adjacent pixels in pixels 20a, 20b, 20c, and 20d.

[0139] Since the solid-state imaging apparatus according to this modification is similar in circuit configuration and operation to the solid-state imaging apparatus 1 according to the above embodiment, its description will be omitted. Furthermore, since the configuration of the distance measurement system according to this modification is similar to the distance measurement system according to the above embodiment, its description will also be omitted.

[0140] As described above, the solid-state imaging device and distance measurement system according to this modification provide similar beneficial effects to those of the solid-state imaging device 1 and distance measurement system according to the above embodiments.

[0141] (Variation Example 2)

[0142] Next, by using Figure 13 and Figure 14 A description of a solid-state imaging apparatus according to a modified embodiment 2 will be given below. The solid-state imaging apparatus according to this modified embodiment is characterized in that the first light-shielding portion 22 and the second light-shielding portion 23 are not formed to penetrate the well layer 213 from the upper surface side to the lower surface side in the stacking direction, and unlike the solid-state imaging apparatus 1 according to the above embodiment, the corresponding cathodes of the plurality of pixels disposed in the pixel group are shared. It should be noted that components having the same operation and function as those in the solid-state imaging apparatus 1 according to the above embodiment will be indicated by the same reference numerals, and their descriptions will be omitted.

[0143] like Figure 12 As shown, the solid-state imaging apparatus according to this modification includes a pixel group 5 having a plurality of pixels 50a, 50b, 50c and 50d (four pixels in this embodiment). Pixels 50a, 50b, 50c and 50d are arranged adjacent to each other.

[0144] like Figure 14As shown, the first light-shielding portion 52 and the second light-shielding portion 53 disposed in the pixel group 5 are not formed to penetrate the well layer 213 from the upper surface side to the lower surface side in the stacking direction. The first light-shielding portion 52, the second light-shielding portion 53 and the oxide film 518 penetrate only a portion of the well layer 213 from the upper surface side to the lower surface side and are inserted through the middle of the substrate. The oxide film 518 is formed to also cover the lower surface side of the first light-shielding portion 52 and the second light-shielding portion 53.

[0145] The hole accumulation region 517 is formed to cover not only the well layer 213 disposed in each of pixels 50a, 50b, 50c, and 50d, but also the first light-shielding portion 52, the second light-shielding portion 53, and the oxide film 518. The anode 515 is formed in the same layer as the n-type semiconductor region 211 disposed in each of pixels 50a, 50b, 50c, and 50d. The anode 515 is formed to cover not only the well layer 213 disposed in each of pixels 50a, 50b, 50c, and 50d, but also the first light-shielding portion 52, the second light-shielding portion 53, and the oxide film 518, and surrounds the hole accumulation region 517.

[0146] Since the solid-state imaging apparatus according to this modification is similar in circuit configuration and operation to the solid-state imaging apparatus 1 according to the above embodiment, its description will be omitted. Furthermore, since the configuration of the distance measurement system according to this modification is similar to the distance measurement system according to the above embodiment, its description will also be omitted.

[0147] Even though the first light-shielding part 52, the second light-shielding part 53 and the oxide film 518 do not penetrate the trap layer 213 and the anode 515 is shared by pixels 50a, 50b, 50c and 50d, the solid-state imaging device and distance measurement system according to this variant provide similar advantageous effects to the solid-state imaging device 1 and distance measurement system according to the above embodiment.

[0148] (Variation Example 3)

[0149] Next, we will use... Figure 15 and Figure 16 This describes a solid-state imaging apparatus according to Modification 3 of this embodiment. The solid-state imaging apparatus according to this modification is characterized in that it has the characteristics of the solid-state imaging apparatuses according to Modifications 1 and 2 of the above embodiments. It should be noted that components having the same operation and function as the solid-state imaging apparatuses according to Modifications 1 and 2 of the above embodiments will be represented by the same reference numerals, and their descriptions will be omitted.

[0150] like Figure 15 As shown, the solid-state imaging apparatus according to this modification includes a pixel group 6 having a plurality of pixels 60a, 60b, 60c, and 60d (four pixels in this embodiment). Pixels 60a, 60b, 60c, and 60d are arranged adjacent to each other. Figure 15 and Figure 16 As shown, pixel group 6 has a first light-shielding portion (an example of a light-shielding portion) 52 configured to surround the outer periphery of pixel group 6, and no light-shielding portion is provided between adjacent pixels in pixels 60a, 60b, 60c and 60d. That is, no light-shielding portion is provided between pixels 60a and 60b, between pixels 60a and 60c and between pixels 60b and 60d.

[0151] Hole accumulation region 517 is disposed between pixels 60a and 60b, between pixels 60a and 60c, and between pixels 60b and 60d. Pixels 60a, 60b, 60c, and 60d are separated by hole accumulation region 517.

[0152] like Figure 16 As shown, the first light-shielding portion 52 disposed in pixel group 6 is not formed to penetrate the well layer 213 from the upper surface side to the lower surface side in the stacking direction. The first light-shielding portion 52 and the oxide film 518 penetrate only a portion of the well layer 213 from the upper surface side to the lower surface side and are inserted through the middle of the substrate. The oxide film 518 is formed to also cover the lower surface side of the first light-shielding portion 52.

[0153] The hole accumulation region 517 is formed to cover not only the well layer 213 disposed in each of pixels 60a, 60b, 60c, and 60d, but also the first light-shielding portion 52 and the oxide film 518. The anode 515 is formed in the same layer as the n-type semiconductor region 211 disposed in each of pixels 60a, 60b, 60c, and 60d. The anode 515 is formed to cover not only the well layer 213 disposed in each of pixels 60a, 60b, 60c, and 60d, but also the first light-shielding portion 52 and the oxide film 518, and surrounds the hole accumulation region 517.

[0154] Since the solid-state imaging apparatus according to this modification is similar in circuit configuration and operation to the solid-state imaging apparatus 1 according to the above embodiment, its description will be omitted. Furthermore, since the configuration of the distance measurement system according to this modification is similar to the distance measurement system according to the above embodiment, its description will also be omitted.

[0155] The solid-state imaging device and distance measurement system according to this modification provide similar advantages to those of the solid-state imaging device and distance measurement system according to the above embodiments and modifications 1 and 2.

[0156] This disclosure is not limited to the above-described embodiments, and can be modified in various ways.

[0157] Although the pixel group has four pixels in the above embodiments and variations, this disclosure is not limited thereto. The pixel group may have two, three, five or more pixels.

[0158] Although the solid-state imaging device according to the above embodiments and various modifications has a selection circuit 34, the selection circuit 34 may not be provided, and the detection circuit 24 provided in each pixel may be directly connected to the time measurement unit 351.

[0159] Although the solid-state imaging apparatus according to the above embodiments and various modifications is configured to control the switching element 25 using the decoder 262, this disclosure is not limited thereto. For example, the pixel driving unit may have a signal generation unit that generates a control signal for controlling the switching element disposed in each pixel in response to an input of a synchronization signal synchronized with a light emission control signal that controls the emission of light from a light source. That is, the pixel driving unit 26 may be configured such that the gate conduction signal generation unit 261 generates control signals Ssc1, Ssc2, Ssc3, and Ssc4 and outputs these signals to the switching element 25. In this case, the solid-state imaging apparatus can individually control the switching element 25 to be turned on and off, which provides similar advantageous effects to the solid-state imaging apparatus according to the above embodiments.

[0160] <Example applied to moving objects>

[0161] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body (such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal transport vehicles, airplanes, drones, ships, or robots).

[0162] Figure 17 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0163] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 17 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an onboard information detection unit 12040, and an integrated control unit 12050. Furthermore, as examples of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an onboard network interface (I / F) 12053 are shown.

[0164] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0165] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0166] The exterior information detection unit 12030 detects exterior information, including information from outside the vehicle, which is part of the vehicle control system 12000. For example, an imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives these captured images. Furthermore, the exterior information detection unit 12030 can also perform processing based on the received images, such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0167] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0168] The vehicle information detection unit 12040 detects information about the interior of the vehicle. The vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0169] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained from the external information detection unit 12030 or the on-board information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0170] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about external or in-vehicle information obtained by the external information detection unit 12030 or the in-vehicle information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive autonomously without relying on the driver's operation.

[0171] Additionally, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on information about the outside of the vehicle obtained by the external vehicle information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicle detected by the external vehicle information detection unit 12030.

[0172] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 17 In this example, audio speaker 12061, display unit 12062, and instrument panel 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0173] Figure 18 This is an illustration depicting an example of the mounting position of the imaging unit 12031.

[0174] exist Figure 18 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0175] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, installed on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the windshield inside the vehicle. Imaging unit 12101 installed on the front nose inside the vehicle and imaging unit 12105 installed on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 installed on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 installed on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0176] Incidentally, Figure 18 Examples of the imaging ranges of imaging units 12101 to 12104 are described. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0177] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0178] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to stay ahead of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control for autonomous driving can be executed, enabling the vehicle to drive autonomously without relying on driver operation.

[0179] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0180] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 such that an icon representing the pedestrian is displayed at a desired location.

[0181] Examples of vehicle control systems to which the technology of this disclosure can be applied have been described above. The technology of this disclosure can be applied to the imaging unit 12031 of those components.

[0182] Although the present disclosure has been described above by way of examples of embodiments, the present disclosure is not limited to the above embodiments and can be modified in various ways. It should be noted that the beneficial effects described in this specification are merely illustrative. The beneficial effects of the present disclosure are not limited to those described in this specification. The present disclosure may have beneficial effects other than those described in this specification.

[0183] Furthermore, this disclosure may have the following configurations: (1)

[0185] A solid-state imaging device, comprising:

[0186] Multiple pixels, each pixel having a light-receiving element that converts received light into electrical signals;

[0187] A driving unit is used to drive multiple pixels by means of the operating timing of a deflection light receiving element; and

[0188] The time measurement unit is configured to input an electrical signal from each of the multiple pixels, and the time measurement unit is adapted to measure the time until the light emitted from the light source is reflected by the object and received by the light receiving element based on the input of the electrical signal. (2)

[0190] According to the solid-state imaging device described in (1), wherein,

[0191] The optical receiving element includes an avalanche photonic diode, which multiplies the charge carriers by using a high electric field region. (3)

[0193] According to the solid-state imaging device described in (2), wherein,

[0194] Each of the multiple pixels has a switching element connected between the cathode of the avalanche photonic diode and a power supply; and

[0195] The drive unit generates control signals to control the on and off states of the switching elements. (4)

[0197] According to the solid-state imaging device described in (3), wherein,

[0198] The drive unit has:

[0199] The signal generation unit generates a signal in response to an input of a synchronization signal that is synchronized with a light emission control signal that controls light emission from a light source.

[0200] The decoder outputs a control signal under the control of the signal generated by the signal generation unit. (5)

[0202] According to the solid-state imaging device described in (3), wherein,

[0203] The drive unit has a signal generation unit that generates a control signal in response to an input of a synchronization signal that is synchronized with a light emission control signal that controls light emission from a light source. (6)

[0205] The solid-state imaging apparatus according to any one of (1) to (5), wherein,

[0206] Each of the multiple pixels has a detection circuit, and an electrical signal is input to the detection circuit. (7)

[0208] According to the solid-state imaging device described in (6), wherein,

[0209] The detection circuit is an inverter circuit. (8)

[0211] The solid-state imaging device according to (6) or (7) includes:

[0212] The selection circuit is connected between the detection circuit and the time measurement unit. (9)

[0214] According to the solid-state imaging device described in (8), wherein,

[0215] The selection circuit has logic circuitry connected to each detection circuit. (10)

[0217] According to the solid-state imaging device described in (9), wherein,

[0218] Logic circuits are logic and circuits. (11)

[0220] The solid-state imaging apparatus according to any one of (1) to (10), wherein,

[0221] The time measurement unit is a time-to-digital converter that converts time information from analog signals based on electrical signals into time information from digital signals. (12)

[0223] The solid-state imaging apparatus according to any one of (1) to (11) comprises:

[0224] The distance calculation unit is adapted to calculate the distance to the object based on the time information output from the time measurement unit. (13)

[0226] The solid-state imaging apparatus according to any one of (1) to (12), wherein,

[0227] Multiple pixels are arranged to be adjacent to each other. (14)

[0229] The solid-state imaging device according to (13) includes:

[0230] A pixel group having multiple pixels, where,

[0231] The pixel group has:

[0232] The first light-shielding part is configured to surround the outer periphery of the pixel group, and

[0233] The second light-shielding part is set in the boundary of multiple pixels. (15)

[0235] The solid-state imaging device according to (13) includes:

[0236] A pixel group having multiple pixels, where,

[0237] The pixel group has a light-shielding portion configured to surround the outer periphery of the pixel group, and

[0238] No light-blocking elements are set between adjacent pixels in multiple pixels. (16)

[0240] A distance measurement system, comprising:

[0241] A light source, suitable for emitting light onto an object; and

[0242] A solid-state imaging device has multiple pixels, each pixel having a light-receiving element that converts received light into an electrical signal; a driving unit configured to drive the multiple pixels by offsetting the operating timing of the light-receiving element; and a time measuring unit configured to input an electrical signal from each of the multiple pixels, and the time measuring unit is adapted to measure the time until light emitted from the light source is reflected by the object and received by the light-receiving element based on the input of the electrical signal. (17)

[0244] According to the distance measurement system described in (16), wherein,

[0245] The light receiving element is an avalanche photonic diode element that multiplies the charge carriers by using a high electric field region.

[0246] [List of Reference Numbers]

[0247] 1: Solid-state imaging device

[0248] 2, 3, 4, 5, 6: Pixel groups

[0249] 8: Object

[0250] 9: Distance Measurement System

[0251] 10a: Sensor chip

[0252] 10b: Logic chip

[0253] 20, 20a, 20b, 20c, 20d, 50a, 50b, 50c, 50d, 60a, 60b, 60c, 60d: pixels

[0254] 21: Optical receiving element

[0255] 22, 52: First shading section

[0256] 23, 53: Second shading section

[0257] 24: Detection Circuit

[0258] 25: Switching elements

[0259] 26: Pixel Driver Unit

[0260] 27: Power supply circuit

[0261] 31: Control Department

[0262] 33: Laser Control Department

[0263] 34: Selection Circuit

[0264] 35: Distance Measurement and Processing Department

[0265] 91: Light source

[0266] 93: Optical components on the light source side

[0267] 94: Optical components on the imaging device side

[0268] 101: Pad opening

[0269] 102a: Wiring layer

[0270] 102b: Wiring layer

[0271] 211: n-type semiconductor region

[0272] 212: p-type semiconductor region

[0273] 213: Trap layer

[0274] 214, 216: Contact elements

[0275] 215, 515: Negative electrode

[0276] 217, 517: Hole accumulation areas

[0277] 218, 518: Oxide film

[0278] 241, 271a, 271b, 341e: P-type transistors

[0279] 242: N-type transistor

[0280] 261: Gate On Signal Generation Unit

[0281] 262: Decoder

[0282] 262a, 262b: Inverter gates

[0283] 262c, 262d, 262e, 262f: NAND gates

[0284] 271: Current Mirror Circuit

[0285] 272: Constant Current Source

[0286] 341: OR circuit

[0287] 341c, 341d, 341f: N-type transistors

[0288] 351: Time Measurement Department

[0289] 352: Distance Calculation Department

[0290] 700: Application Processor

[0291] A1: Pixel area

[0292] A2: Surrounding area

[0293] A3: Pad area.

Claims

1. A solid-state imaging device, comprising: Multiple pixels, each pixel having a light-receiving element that converts received light into electrical signals; The driving unit is used to drive the plurality of pixels by offsetting the operation timing of the light receiving element; A time measurement unit is configured to input the electrical signal from each of the plurality of pixels, and the time measurement unit is adapted to measure, based on the input of the electrical signal, the time until the light emitted from the light source is reflected by the object and received by the light receiving element. The distance calculation unit is adapted to calculate the distance to the object based on time information output from the time measurement unit. The plurality of pixels are arranged adjacent to each other, each of the plurality of pixels has a detection circuit, and the electrical signal is input to the detection circuit. A selection circuit is connected between the detection circuit and the time measurement unit. The solid-state imaging device includes a pixel group having the plurality of pixels, wherein, The pixel group has: The first light-shielding portion is configured to surround the outer periphery of the pixel group. The second light-shielding part is disposed in the boundary portion of the plurality of pixels. An oxide film is formed on the sidewall of each of the first and second light-shielding portions, and Hole accumulation regions are formed between the oxide film and the trap layer. The time measurement unit is a time-to-digital converter that converts the time information of an analog signal based on the electrical signal into the time information of a digital signal. The light receiving element includes an avalanche photonic diode, which multiplies the charge carriers by using a high electric field region. Each of the plurality of pixels has a switching element connected between the cathode of the avalanche photonic diode and a power supply; and The driving unit generates control signals to control the on and off states of the switching element. The driving unit includes a signal generation unit that generates the control signal in response to an input of a synchronization signal that is synchronized with a light emission control signal that controls light emission from the light source.

2. The solid-state imaging device according to claim 1, wherein, The drive unit also has: The decoder outputs the control signal under the control of the signal generated by the signal generation unit.

3. The solid-state imaging device according to claim 1, wherein, The detection circuit is an inverter circuit.

4. The solid-state imaging device according to claim 1, wherein, The selection circuit has logic circuitry connected to each detection circuit.

5. The solid-state imaging device according to claim 4, wherein, The logic circuit is a logic AND circuit.

6. A distance measurement system, comprising: A light source, suitable for emitting light onto an object; as well as The solid-state imaging device according to claim 1.

Images