Execution method, device and system associated with a storage unit

Abstract

The present invention discloses operating a memory cell using a low-power DC source. The low-power DC source provides power less than that required to operate the memory cell. In one embodiment, charge from the low-power source is stored on a charge storage device during a first time interval. During a second time interval, the charge storage device is used as a second power source to operate the memory cell. A portion of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval.

Description

[0001] Priority Claim

[0002] This patent application claims priority to the pending provisional Indian patent application with application number 202141020222, titled "Method for Reading OTP / EFuse Storage from a Current-Limited Power Supply", filed on May 3, 2021, and to the U.S. patent application with application number 17 / 643,823, filed on December 11, 2021. The entire contents of both are incorporated herein by reference. Technical Field

[0003] Embodiments of the present application generally relate to power supply circuits, and more particularly, to operating memory cells using a low-power DC power supply. Background Art

[0004] In the related art, it is well known that a direct-current (DC) power supply is commonly used as the power supply for an electronic circuit. Examples of DC power supplies include conventional batteries, power supplies that obtain regulated or unregulated power from an alternating current (AC) or DC power supply, and the like.

[0005] The power provided by the DC power supply can be used to operate a memory cell. Operating a memory cell means successfully performing basic access operations such as reading and / or writing and / or programming to / from the memory cell. At least to perform such operations, each memory cell is designed to operate at a specific power level (voltage and / or current intensity) for the corresponding (read, write, program, etc.) operations.

[0006] There are often environments where it is necessary to use a low-power DC power supply to operate a memory cell. A low-power DC power supply refers to a DC power supply that provides a voltage less than the minimum voltage required for the operation of the memory cell, or has a maximum current limit less than the (maximum) current consumed by the memory cell during read / write / program access to the memory cell, or both (i.e., has a voltage and current less than the voltage and current required by the memory cell). Summary of the Invention

[0007] Certain aspects of the present application are directed to operating a memory cell using a low-power direct current (DC) power supply.

[0008] Some embodiments of the present application provide an execution method associated with a storage unit. The method includes: storing charges from a first power supply on a charge storage device within a first time interval, where the power provided by the first power supply is less than the power required to operate the storage unit; and using the charge storage device as a second power supply to operate the storage unit within a second time interval; where a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval.

[0009] In some embodiments, the charge storage device is a capacitor. The storage unit is designed to be operated by a power supply providing a first voltage, and a second voltage provided by the first power supply is less than the first voltage. The storage causes the second voltage to be amplified to provide an amplified voltage greater than or equal to the first voltage. Wherein, the storage causes the capacitor to be charged to the amplified voltage within the first time interval.

[0010] In some embodiments, the method further includes: reading a first bit from the storage unit during a first read duration and reading a second bit from the storage unit during a second read duration, where the first read duration is separated from the second read duration by an idle duration, and the idle duration includes the first time interval, and the first read duration includes the second time interval.

[0011] In some embodiments, the first time interval and the second time interval do not overlap at all. Wherein, the amplified voltage is greater than the first voltage, and the method further includes: obtaining the first voltage from the amplified voltage.

[0012] In some embodiments, the storage unit is a non-volatile one-time programmable (OTP) storage unit for storing configuration parameters, where the configuration parameters include the first bit and the second bit.

[0013] In some embodiments, the first time interval is longer than the second time interval.

[0014] In some embodiments, the amplified voltage represents the maximum safe voltage to which the capacitor can be charged.

[0015] In some embodiments, the configuration parameters are used to configure one or more circuit blocks of a device, and the method is executed in the device. Wherein, the device includes: the one or more circuit blocks for performing desired operations; the storage unit; a digital unit for performing the reading of the first bit and the reading of the second bit; a charge pump coupled to the first power supply, and the charge pump performs the storage.

[0016] In some embodiments, the method further includes: receiving one or more data bits; and programming each location in the storage unit with the one or more data bits during the second time interval.

[0017] Some embodiments of the present application further provide a device, including: a charge storage unit; and a charge pump, wherein an input of the charge pump is coupled to a first power supply, and an output node of the charge pump is coupled to the charge storage unit; wherein: the power provided by the first power supply is less than the power required to operate the storage unit, and the charge pump is designed to store charge from the first power supply on the charge storage device during a first time interval, use the charge storage device as a second power supply, and operate the storage unit during a second time interval, and a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval.

[0018] In some embodiments, the charge storage device is a capacitor, and the device further includes the storage unit, wherein: the storage unit is designed to be operated by a power supply providing a first voltage, a second voltage provided by the first power supply is less than the first voltage, and the charge pump is designed to amplify the second voltage to an amplified voltage during charging the capacitor, so that the capacitor is charged to the amplified voltage during the first time interval, wherein the amplified voltage is greater than or equal to the first voltage.

[0019] In some embodiments, the device further includes: a digital unit, configured to read a first bit from the storage unit during a first read duration and read a second bit from the storage unit during a second read duration, wherein the first read duration is separated from the second read duration by an idle duration, and the idle duration includes the first time interval, and the first read duration includes the second time interval.

[0020] In some embodiments, the first time interval and the second time interval do not overlap at all, and the amplified voltage is greater than the first voltage. The device further includes: a resistor and a first transistor, which are serially coupled between the output node and an internal node of the device, and the capacitor is coupled between the internal node and a first constant reference potential; and a second transistor, which is coupled between the internal node and a power supply terminal of the storage unit.

[0021] In some embodiments, a first end of the resistor is coupled to the output node, a first current terminal of the first transistor is coupled to a second end of the resistor, a second current terminal of the first transistor is coupled to the internal node, and a control terminal of the first transistor is coupled to a first reference voltage, the magnitude of the first reference voltage being equal to the sum of a threshold voltage of the first transistor and a maximum voltage to which the capacitor is to be charged.

[0022] In some embodiments, a first current terminal of the second transistor is coupled to the internal node, a second current terminal of the second transistor is coupled to a power supply terminal of the storage unit, and a control terminal of the second transistor is coupled to a second reference voltage, the magnitude of the second reference voltage being equal to the sum of an amplitude of the first voltage and a threshold voltage of the second transistor.

[0023] In some embodiments, the device further includes a reference voltage generator for generating the first reference voltage and the second reference voltage.

[0024] In some embodiments, the device further includes a core functional block, the core functional block including a circuit for implementing a low dropout regulator (LDO) for generating a regulated power supply voltage from a low power supply, the regulated power supply voltage being an output of the device.

[0025] Some embodiments of the present application further provide a system, including: a power terminal coupled to a first power supply; and a power supply unit coupled to receive power from the power terminal, the power supply unit including a first linear regulator and a first DC-DC converter, the first DC-DC converter representing a third power supply coupled to the power terminal, the first linear regulator being coupled to the third power supply to generate a first lower power supply voltage, wherein the first linear regulator includes: a core functional block including a circuit for generating the first lower power supply voltage; a charge storage unit; and a charge pump, wherein an input of the charge pump is coupled to the third power supply, an output node of the charge pump is coupled to the charge storage unit; wherein: the power provided by the third power supply is less than the power required to operate the storage unit, the charge pump is designed to store charge from the power terminal on the charge storage device during a first time interval, use the charge storage device as a second power supply to operate the storage unit during a second time interval, and a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval.

[0026] In some embodiments, the system further includes: an antenna; a first duplexer coupled to the antenna; and a first transceiver, wherein the first lower supply voltage is used to power a noise-sensitive block in the first transceiver, the first transceiver includes a transmitter section and a receiver section, the transmitter section and the receiver section are each coupled to the first duplexer, the first transceiver transmits communication signals to a wireless medium via the first duplexer and the antenna, and the first transceiver also receives communication signals from the wireless medium via the first duplexer and the antenna; wherein: the charge storage device is a capacitor, the first linear voltage regulator further includes the storage unit, the storage unit is designed to be operated by a power supply providing a first voltage, a second voltage provided by the third power supply is less than the first voltage, the charge pump is designed to amplify the second voltage to an amplified voltage during storing charge on the capacitor, so that the capacitor is charged to the amplified voltage within the first time interval, wherein the amplified voltage is greater than or equal to the first voltage.

[0027] In some embodiments, the system is a Base Transceiver Station (BTS) system, and the BTS system further includes: a combiner coupled to the antenna; a plurality of duplexers, each of the plurality of duplexers being coupled to the combiner, the plurality of duplexers including the first duplexer; and a plurality of transceivers, including the first transceiver, each of the plurality of transceivers including a transmitter section and a receiver section, being coupled at one end to a respective one of the plurality of duplexers and at the other end to a Base Station Controller (BSC), wherein each of the plurality of transceivers is configured to transmit an information signal received from the base station controller to the wireless medium via a respective one of the plurality of duplexers, the combiner, and the antenna, and to forward an information signal received from the wireless medium to the base station controller via a respective one of the plurality of duplexers, the combiner, and the antenna; wherein the power supply unit includes: a plurality of DC-DC converters coupled to receive the power from the power terminal and generate respective supply voltages including the second voltage, the plurality of DC-DC converters including a first DC-DC converter, wherein the second voltage is used to power a noise-insensitive block in the first transceiver; a plurality of linear regulators coupled to receive a supply voltage from a respective one of the DC-DC converters and generate respective lower supply voltages, the plurality of linear regulators including the first linear regulator, wherein the first linear regulator is coupled to receive the second voltage from the first DC-DC converter to generate the first lower supply voltage; wherein: the supply voltages generated by one or more of the DC-DC converters are used to power noise-insensitive blocks in the plurality of transceivers, and wherein the supply voltages generated by one or more of the linear regulators are used to power noise-sensitive blocks in the plurality of transceivers, and at least a second linear regulator among the plurality of linear regulators is implemented in a similar manner to the first linear regulator, wherein the first linear regulator further includes: a digital unit configured to read a first bit from the storage unit during a first read duration and a second bit from the storage unit during a second read duration, wherein the first read duration is separated from the second read duration by an idle duration, wherein the idle duration includes the first time interval, and the first read duration includes the second time interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Example embodiments of the present application will be described with reference to the drawings briefly described below.

[0029] Figure 1 A block diagram of an example device in which several aspects of the present application can be implemented is shown.

[0030] Figure 2 A timing diagram of a read operation from a storage unit according to the prior art is shown.

[0031] Figure 3 A flowchart showing a way to read data from a storage cell using a low - power power supply in an embodiment of the present application.

[0032] Figure 4 A schematic diagram showing implementation details of a data retrieval block designed to read data from a storage cell using a low - power source in an embodiment of the present application.

[0033] Figure 5 A schematic diagram showing a read operation from a storage cell in an embodiment of the present application.

[0034] Figure 6 A block diagram of a system of a device that can be implemented in accordance with several aspects of the present application in an embodiment of the present application.

[0035] In the drawings, like reference numerals generally represent identical, functionally similar, and / or structurally similar elements. The figure in which an element first appears is indicated by the left - most digit in the corresponding reference numeral. Detailed Description of the Invention

[0036] 1. Overview

[0037] According to one aspect of the present application, a low - power source is used to operate a storage cell. The power provided by the low - power source is less than the power required to operate the storage cell. During a first time interval, charge from the low - power power supply is stored on a charge - storage device. During a second time interval, the charge - storage device is used as a second power supply to operate the storage cell. A part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval.

[0038] The following describes several aspects of the present application with reference to examples for illustration. However, those skilled in the art will recognize that the present application can be implemented without one or more specific details or using other methods, components, materials, etc. In other cases, well - known structures, materials, or operations are not shown in detail to avoid obscuring the features of the present application. Additionally, the described features / aspects can be practiced in various combinations, although only some combinations are described here for the sake of brevity.

[0039] 2. Example Device

[0040] Figure 1A block diagram of an example device that can implement several aspects of the present application is shown. Device 100 is shown as including a power-on detector 110, a power regulation circuit 120, a core function block 130, a digital unit 140, and a storage unit 150. Device 100 can be implemented in part or in whole in the form of an integrated circuit (IC) or in discrete form. A low-power DC source (not shown) provides a voltage 101 (Vin) to device 100. In Figure 1 , 4 and 6 examples, the low-power DC source is a low-voltage source, and the voltage Vin (101) is less than the power supply voltage required to power the storage unit 150 and operate the storage unit 150 for reading and programming. However, it should be noted that the techniques described herein can be applied to environments or devices powered by a power source whose maximum current limit is less than the (maximum) current consumed by the storage unit (or a general load) during read / write / programming access to the storage unit, or less than the voltage and current required by the storage unit, as also described above.

[0041] In addition, a description of a read operation from a one-time programmable (OTP) memory is provided below. However, when the storage unit has similar limiting conditions as described herein, the techniques described below can also be applied to environments that require reading or writing to a volatile memory, or (multiple) programming of the content of a non-volatile memory. For those skilled in the art, any modifications to the techniques described herein in such other environments will be obvious after reading the disclosure provided herein.

[0042] The core function block 130 is designed to perform one or more desired operations to obtain a desired function from device 100. As an example, the core function block 130 can include circuits required to implement a linear voltage regulator (including low dropout / LDO) or a switching voltage regulator function in device 100, and device 100 is a linear / LDO or switching voltage regulator. The core function block 130 can be designed to generate a regulated power supply voltage 131 (Vreg). Depending on the specific implementation of the core function block 130, Vreg can be greater than, less than, or equal to the voltage Vin. To achieve the correct and desired operation of the core function block 130, it may be necessary to first configure one or more circuits / sections within the core function block 130. For example, before the normal operation of device 100, one or more "trim bits" (configuration bits) for setting / initializing a reference voltage, current limit, oscillator programming, etc. within the core function block 130 may be required. The trim bits typically close or open corresponding switches within the core function block 130 to affect the configuration.

[0043] Upon power - on of device 100 from DC source 101 (Vin), power - on detector 110 generates a power - on signal on path 112. Signal 112 can be in the form of a pulse with an appropriate pulse width. Power - on detector 110 provides power - on signal 112 to power - regulation circuit 120 and can be implemented in a known manner.

[0044] Storage unit 150 represents a non - volatile memory and stores data bits required to configure one or more circuits / sections within core function block 130. This configuration is typically performed only once, i.e., when device 100 is powered on, although it can also be performed after the start of normal operation of core function block 130. Storage unit 150 can be implemented as any non - volatile memory type, such as flash memory, UV erasable programmable read - only memory (EPROM), electrically erasable programmable read - only memory (EEPROM), one - time programmable memory (OTP), and uses technologies such as electronic fuse (eFUSE) technology, gate - oxide breakdown antifuse technology, etc. In an embodiment of the present application, storage unit 150 is an OTP memory. Storage unit 150 receives a power supply voltage from power - regulation circuit 120 on path 125, which will be described in detail in the following section.

[0045] Digital unit 140 is designed to read configuration data from storage unit 150 via path 145 and use this configuration data to configure the corresponding part of core function block 130 via path 134. The techniques described herein for reading storage unit 150 can also be applied to programming storage unit 150. Accordingly, digital unit 140 is shown connected to path 141, on which digital unit 140 can receive configuration bits from an external device (not shown) and program the bits in storage unit 140. Digital unit 140 also receives power supply voltage 125 from power - regulation circuit 120. However, in other embodiments, digital unit 140 can receive a different power supply voltage, e.g., from another charge pump (not shown).

[0046] The power regulation circuit 120 receives an input voltage Vin(101) from a low-power DC source, which means the voltage is unidirectional. The low-power source can be, for example, a battery (not shown) or a DC power supply (regulated or unregulated, also not shown). The input voltage Vin is less than the minimum voltage required for the operation of the storage unit 150. The term "operation or operating" of the storage unit 150 is used herein to include reading from the storage unit 150, writing to the storage unit 150, and programming the storage unit 150. Additionally or alternatively, the low-power source providing Vin has a maximum current limit that is less than the current consumed or required to operate the storage unit 150. It should be noted here that when in the standby state, i.e., when the storage unit 150 is only powered on and not accessed, the storage unit 150 may not require a large current, but any of the above operations require a large current otherwise. The power regulation circuit 120 receives a power-on signal 112 and starts operating to generate a power supply voltage 125.

[0047] Optionally, although it may be possible to generate a voltage large enough from Vin for the operation of the storage unit 150 (and other blocks such as the digital unit 140) by employing appropriate circuitry, it may not be possible to implement a circuit that does not require a larger component size (and thus does not result in an increased implementation area penalty) to provide the current required for the operation of the storage unit 150 (whether or not additional current is required for one or more other components of the device 100 such as the digital unit 140).

[0048] According to one aspect of the present application, the combination of the power regulation circuit 120 and the digital unit 140 is designed to be able to read data bits from the storage unit 150 using the low-power source Vin. Additionally, compared to the case where the above requirements of the storage unit 150, especially the current requirement, do not exist, the power regulation circuit 120 can be implemented with a minimum or no implementation area penalty.

[0049] Furthermore, although the environment described herein is for providing the reading of configuration bits from an OTP memory that is used to configure the operation of a circuit such as a voltage regulator, several aspects of the present application can equally well be applied to other environments where similar constraints as those described above regarding the low-power source are presented. Examples of such other environments include those (implemented using the core functional block 130) that require reading the startup code of a computing unit, reading the encryption key of a security device, etc., and these examples will be obvious to those skilled in the relevant art after reading the present disclosure.

[0050] The manner in which the combination of the power regulation circuit 120 and the digital unit 140 is used to read data bits from the storage unit 150 will be described below in conjunction with the flow chart. The combination of the power regulation circuit 120 and the digital unit 140 is referred to herein as the "data retrieval block 190".

[0051] Certain features of the present application can be better understood and appreciated by comparing with the conventional techniques for reading OTP memories. Therefore, reference is made next to Figure 2 Briefly illustrate an example of the prior art.

[0052] Figure 2 A timing diagram of the prior / conventional art for reading data from an OTP memory is shown. Signals 210 (NR) and strobe 220 represent the read signal and the strobe signal for reading data from the OTP memory, respectively. Voltage 205 is generated or obtained from a high-power source and can provide the voltage required for the OTP memory as well as the maximum read current. For the sake of brevity, Figure 2 the contents of the address lines and data lines during the OTP memory read are not shown. In Figure 2 it is assumed that 4 data bits are to be read from the OTP memory.

[0053] Upon power-up, voltage 205 is generated at a magnitude of (Vr) volts, which is the magnitude required for the OTP memory. NR 210 is the read signal and is asserted for the entire duration of the read of the 4 bits shown. As shown in example intervals 221 and 222, strobe 220 is active and inactive. When active (e.g., interval 221), data (assumed to be one-bit wide) is read. Prior to the next read, strobe 220 is inactive for a shorter duration (e.g., interval 222). Bits 0, 1, 2, and 3 are shown as being read continuously. When the strobe is active ( Figure 2 logic high in

[0054] As described above, there are several environments (such as Figure 1 the environment ofFigure 1 In the example of Figure 1 , Vin(101) can be as low as 1.1 volts (V), and the memory cell 150 requires a supply voltage of 1.8 V and a current of up to 200 microamps for a reliable read operation. Although a charge pump can be implemented to generate a higher voltage (e.g., 2.2 V (2X) or 3.3 V (3X)) from Vin, which has a constant voltage of 1.8 V, it needs to continuously supply at least 200 uA until all configuration bits from the memory cell 150 are read. This requirement may translate into an unacceptably large implementation area for the charge pump, which may be undesirable, especially when the OTP memory typically only needs to be read once, i.e., when the device 100 is powered on. Additionally, when other blocks of the device 100, such as the digital unit 140, also need to operate at a voltage higher than Vin, the current requirement of the charge pump further increases (e.g., increases to 300 uA continuously), which translates into a further increase in the implementation area, which may be undesirable.

[0055] As described below, various aspects of the present application enable reading a memory cell using a low-power source while avoiding the above-mentioned drawbacks.

[0056] 3. Reading the memory using a low-power source

[0057] Figure 3 A flowchart illustrating the manner in which a data retrieval block reads data from a memory using a low-power source is shown. The flowchart is described with reference to Figure 1 and the associated data retrieval block 190 for illustrative purposes only. However, the various features can be implemented in other environments and using other components. Additionally, for illustrative purposes only, the steps are described in a particular order. Alternative embodiments can also be implemented in other environments and using other components and different step orders without departing from the scope and spirit of several aspects of the present invention, which will be apparent to those skilled in the relevant art by reading the disclosure provided herein. The flowchart begins at step 301, where control immediately transfers to step 310. Figure 1

[0058] In step 310, the data retrieval block 190 stores charge from a first power source on a charge storage device during a first time interval. The first power source is a low-power DC power source. Then control transfers to step 320.

[0059] In step 320, the data retrieval block 190 operates the memory cell during a second time interval using the charge storage device as a second power source. A portion of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval. In other words, the time intervals do not completely overlap on the time scale.

[0060] Then, control returns to step 310, where data retrieval block 190 stores the charge from the first power supply on the charge storage device again. The remaining steps can be repeated, and other data bits can be read.

[0061] Since at least part of the first interval and the second interval do not overlap, data retrieval block 190 can read the storage unit 150 from the low-power DC source.

[0062] Next, the operation of the above steps will be described with reference to an exemplary implementation of data retrieval block 190.

[0063] 4. Data Retrieval Block

[0064] Figure 4 A schematic diagram showing the implementation details of data retrieval block 190 in an embodiment of the present application is shown. For ease of reference, the storage unit 150 is also shown. Figure 1 of Figure 4 The power regulation circuit 120 and the digital unit 140 of data retrieval block 190 are shown in more detail in. The internal details of the digital unit 140 are not shown because the digital unit 140 can be implemented in a known manner. The power regulation circuit 120 is shown to include charge pumps 410 and 420, resistor 430, N-type Metal Oxide Semiconductor transistor (NMOS) 440, NMOS 450, charge storage device 460, control block 470, and reference voltage generator 480.

[0065] The control block 470 receives the power-on signal 112 and sends signals via path 471 to charge pumps 410 and 420 and voltage reference generator 480 to start operation.

[0066] Each of charge pumps 410 and 420 represents a voltage multiplier circuit. The combination of charge pumps 410 and 420 is operated to store the charge from the low-power DC source providing Vin on capacitor 460, as further described below. In Figure 4 the embodiment of, two charge pumps 410 and 420 are used. Charge pump 410 is a 2x (2 times) voltage multiplier, and its output is provided to charge pump 420. Charge pump 420 is a 4x (4 times) voltage multiplier, and its output is provided to path 423. Vin(101) is configured as the input of charge pump 410. The two charge pumps are jointly used to generate a voltage on path 423, the amplitude of which is eight times (8x) that of Vin. Although not shown for simplicity, the control block 470 can generate one or more clock signals, which can operate the switches within each charge pump so that the capacitors in the charge pumps are operated to perform voltage multiplication in a known manner.

[0067] Accordingly, a combination of two charge pumps is operated to “amplify” (i.e., multiply the voltage) Vin to produce a “higher voltage” on path 423. The magnitude of the voltage 423 is at least equal to (or at least slightly greater than) the supply voltage (125) required by the memory cell 150. However, a voltage greater than the supply voltage 125 simplifies the design of the charge pumps 410 and 420 and at the same time speeds up the reading of the desired data bits from the memory cell 150. Generally speaking, the larger the value of the voltage 423, the higher the value of the operating current (required by the memory cell 150) that can be provided, the shorter the total time required to read the desired number of data bits from the memory cell 150, and the smaller the size required for the capacitors and / or switches in the charge pumps, as further described below with reference to Figure 5 In the example of Figure 4 , in addition to the memory cell 150, the voltage 423 is also supplied to the digital unit 140. The magnitude of the voltage 423 is only limited by the maximum safe voltage that can be applied across the charge storage device 460.

[0068] The use of two charge pumps with a voltage multiplication factor as described above is for illustrative purposes only. A single charge pump can be used instead of two charge pumps and can be implemented with other integer or fractional voltage multiplication factors, including factor 1. When voltage amplification is not required (i.e., Vin is already greater than or equal to the supply voltage required by the memory cell 150), the charge pump can have a multiplication factor of 1 and simply transfer charge to the capacitor 460. The control block 470 can be implemented such that the multiplication factor can be selected, although the details are not shown as they are obvious to those skilled in the relevant art.

[0069] The node 423 is connected to the drain of the NMOS 440 through the resistor 430. As Figure 4 shown, the source of the NMOS 440 is connected to the drain of the NMOS 450. The resistor 430 has a resistance value selected to limit the charging current for charging the charge storage device 460. It is noted here that there may be other circuits / blocks (not shown) in the device 100 that can operate directly from the voltage 423. Therefore, the capacitor 460 draws a large current, which will cause a significant drop in the voltage 423, which may affect such other circuits. The charge storage device 460 is connected between the connection point of the source of the NMOS 440 and the drain of the NMOS 450 and the ground 499. The charge storage device 460 can be implemented as a capacitor or a supercapacitor / ultracapacitor and can use any of several techniques available for implementing charge storage devices. In the Figure 4 embodiment, the charge storage device 460 is a capacitor. The source of the NMOS 450 provides the supply voltage 125, and the supply voltage 125 is connected to the power supply terminals of each of the memory cell 150 and the digital unit 140.

[0070] The gate terminals of each of NMOS 440 and NMOS 450 are connected to the output of reference voltage generator 480. The reference voltage generator 480 receives voltage 423 and signal 471 as inputs. In response to signal 471 being valid during power-on, the reference voltage generator 480 generates reference voltages Vref1 (484) and Vref2 (485), the values of which are respectively based on the maximum safe voltage that can be applied across capacitor 460 (without damage) and the magnitude of the required power supply voltage 125. In Figure 4 the example embodiment of, the maximum safe voltage is 5.5V. However, depending on the technology used to implement capacitor 460, such a safe voltage can be greater than or less than 5.5V. Specifically, the value of Vref1 is equal to the sum of Vt1 (the threshold voltage of NMOS 440) and the maximum safe voltage to which capacitor 460 can be charged during a charging cycle. The value of Vref2 is equal to the sum of Vt2 (the threshold voltage of NMOS 450) and the magnitude of the power supply voltage 125. The lowest voltage to which capacitor 460 can be discharged during a discharging phase can be greater than or equal to the desired power supply voltage 125. The charging and discharging phases of capacitor 460 will be described further below. The charging phase corresponds to the first time interval referred to above with reference to Figure 3 and the discharging phase corresponds to Figure 3 the second time interval referred to above.

[0071] In Figure 4 the example of, Vin is 1.1V, so voltage 423 is 8.8V. The power supply voltage 125 required by the storage unit 150 is 1.8V. In Figure 4 the example of, the digital unit 140 also requires a power supply voltage of 1.8V. The maximum voltage to which capacitor 460 is charged during the charging phase is equal to 5.5V. The lowest voltage to which capacitor 460 is discharged during the discharging phase is equal to the power supply voltage 125 of 1.8V. Accordingly, Vref1 is equal to 5.5V + Vt1 and Vref2 is equal to 1.8V + Vt2, thereby maintaining the power supply voltage 125 at a constant 1.8V as required. It should be noted here that although voltage 145 was labeled as 8.8V above, there may be some voltage drop (1 or 2 volts) in voltage 125 if there are other circuits / blocks (not shown) powered by voltage 125. However, such a voltage drop is Figure 1 , 4 and 6 background is acceptable because capacitor 460 only needs to be charged to 5.5V. The operation of data retrieval block 190 shown in Figure 4 and Figure 5 will be described below in conjunction with Figure 4 the operation of the data retrieval block 190 shown.

[0072] Figure 5 A timing diagram illustrating the operation of the data retrieval block 190 is shown, where the digital unit 140 is shown reading two data bits, bit 0 and bit 1. However, the same operation is used to read all the configuration bits in the storage unit 150. Vh(530) represents the maximum voltage to which the capacitor 460 is charged during the charging phase, and V1(540) represents the minimum voltage to which the capacitor 460 is discharged during the discharging phase. Vtank(520) represents the voltage of the capacitor 460. Vdd(550) represents the desired value of the power supply voltage 125 and is equal to Vl(540) in the example, but for clarity, Vl(540) is shown separately. However, generally, Vl(540) can be greater than or equal to the voltage 125. The time interval t51 - t52 represents the discharging phase of the capacitor 460, and the time interval t52 - t53 represents the charging phase. The time interval t53 - t54 represents the next discharging phase. Similar to Figure 2 the read signal (NR) of the NR 210 in Figure 5 is not shown in

[0073] In Figure 5 the first interval and the second interval mentioned above with respect to the Figure 3 flowchart are completely non - overlapping (in the time domain, the duration t51 - t52 does not overlap with the duration t52 - t53), and are consecutive (i.e., the second interval immediately follows the first interval, and there is no gap or overlap between the first interval and the second interval). However, in another embodiment, there is a gap between these intervals. In Figure 5 the example of

[0074] the operation power regulation circuit 120 is operated to charge the capacitor 460 to Vh(530) during the charging phase, so that the charge pumps 410 and 420 operate normally and generate a higher voltage at the node 423. Then, the digital unit 140 reads one or more data bits during the discharging phase (although in Figure 5In the case of only indicating the reading of a single bit, during the discharge phase, charge pumps 410 and 420 may not operate and thus are turned off (under the control of control block 470). During the discharge phase t51 - t52, the voltage Vh at the end of the immediately preceding charging phase or the corresponding charge on capacitor 460 is used to provide the read current required for the memory cell 150 (and digital unit 140) when reading bit 0. In the example, depending on whether bit 0 is logic high or logic low, currents of 50 μA or 200 μA are respectively drawn from capacitor 460 for reading the bit. Thus, capacitor 460 is shown to be discharged to Vl (540) before t52. At t52, the next charging phase begins and charges capacitor 460 to Vh (530) before t53. The duration t52 - t53 is an idle duration during which the memory cell 150 is idle or standby, i.e., not being accessed for reading. During the idle period, the memory cell 150 can also be turned off by control block 470, although such control is not shown in Figure 4 The interval t53 - t54 is the next discharge interval, and digital unit 140 reads another bit (bit 1). The charging and discharging intervals can be repeated until digital unit 140 has read all the data bits required for configuring the core functional block 130 ( Figure 1 ).

[0075] The required capacitance value of capacitor 460 depends on several factors, such as the difference between Vh and V1, the maximum read current (200 μA in the example), how many bits are read during the discharge phase, the magnitude of the power supply voltage 125, and the interval between two reads ( Figure 5 t52 - t53 in). In the described example, when Vh is 5.5 V and the power supply voltage 125 is 1.8 V, in order to provide a maximum read current of 200 μA for memory cell 150 within a read duration of 2 microseconds (e.g., Figure 5 t51 - t52 or t53 - t54 in), the minimum required value of the capacitance is [200 μA * 2 μs / (5.5 - 1.8)], i.e., approximately 108 picofarads (pF). Assuming that an additional current of 100 μA is required for other components of device 100 (including digital unit 140) powered by power supply voltage 125 (1.8 V), the minimum required value of the capacitance is approximately 162 pF. For the above capacitance values, capacitor 460 can be implemented as a high - density gate - oxide capacitor, thus only requiring a very small implementation area.

[0076] From the above description, it can be understood that allowing a sufficiently long interval between data reads (e.g., Figure 5In t52 - t53), and by operating charge pumps 410 and 420 to supplement the charge on capacitor 460 between data reads, the average current required from the charge pumps for reading memory cell 150 is greatly reduced. Thus, charge pumps 410 and 420 can be implemented using a smaller - sized capacitor (e.g., using metal - insulator - metal (MIM) capacitor technology). In one embodiment, a 10% read duty cycle (the ratio of intervals t53 - t54 and interval t52 - t54) is employed, and charge pumps 410 and 420 together only need to provide 1 / 10 of the maximum read current (200 uA in the example), i.e., an average of 20 uA in the steady state, thus simplifying the design and relaxing the current specification requirements for the charge pumps. In one embodiment, charge pumps 410 and 420 operate continuously, or at least for the duration required to configure core functional block 130. Synchronization is not required between the start of the read interval (e.g., t51 and t53) and the end of the charging phase (e.g., t51 and t53) because the read intervals (e.g., t51 - t52 and t53 - t54) are far enough apart in time such that the average load current drawn from the charge pumps is low enough to maintain the supply voltage 125 at the desired level of 1.8 V. However, the interval between two read operations can be reduced, thus increasing the average current drawn from the charge pumps (and capacitor 460). And in this case, the start of the read interval can be synchronized with the end of the charging phase of capacitor 460 to ensure that voltage 125 does not drop below the desired level during the read operation.

[0077] It should be noted here that although in the Figure 5 example the first interval and the second interval are consecutive and completely non - overlapping, the first interval and the second interval can generally overlap partially (but not completely). Alternatively, a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval. Thus, in an alternative embodiment, a part of the charging phase of capacitor 460 can overlap with the discharging phase of reading data from memory 150. In such an embodiment, the change in voltage Vtank(520) can have a different slope, as Figure 5 indicated by marker 560 in

[0078] Although the above techniques are considered applicable to reading data from a storage unit, substantially similar or identical techniques can also be applicable to writing to or reading from a volatile memory, or programming a non-volatile memory. In such cases, the read operation is replaced by a write operation or a programming operation. Accordingly, the digital unit 140 can interact with an external system to receive data through path 141 and write / program the received data into the storage unit 150. Depending on the write / programming specifications (including voltage and current), Figure 5 the specific durations and voltage levels of the charging and discharging phases may vary.

[0079] The device 100 implemented as described above can be incorporated into a larger device or system briefly described below.

[0080] 5. Device / System

[0081] Figure 6 is a block diagram showing implementation details of a system in an embodiment of the present application, which incorporates the device 100 implemented as a linear voltage regulator as described in detail above. Figure 6 The system can be deployed in a Base Transceiver Station (BTS) (eNodeB in LTE - Long Term Evolution) of a cellular phone system and is referred to herein as the BTS system 600. Generally speaking, the BTS system 600 facilitates wireless communication between User Equipment (UE), which can be a mobile station (such as a mobile phone) or a fixed user equipment (such as a computer with an Internet connection). The BTS system 600 can be implemented according to technologies and standards such as Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), 3rd Generation (3G), 4th Generation (4G), Long Term Evolution, 5th Generation (5G), etc. The BTS system 600 is shown to include transceivers 610A to 610N, duplexers 620A to 620N, a combiner 630, an antenna 640, a battery pack 650, and a power supply 660. The specific components / blocks of the BTS system 600 are shown by way of illustration only. However, as is well known in the relevant art, generally the BTS system 600 can include more components / blocks, such as a temperature sensor, a maintenance and configuration block, etc.

[0082] Each of transceivers 610A to 610N operates to transmit to / receive from a wireless user equipment a communication signal via a corresponding duplexer 620A - 620N, a combiner 630, and an antenna 640. Each transceiver includes a transmitter section and a receiver section. Thus, transceiver 610A is shown as including a transmitter section and a receiver section, the transmitter section including a transmit baseband block 611, a transmit radio frequency (RF) block 612, and a power amplifier 613, and the receiver section including a low - noise amplifier (LNA) 616, a receive RF block 615, and a receive baseband block 614.

[0083] The transmit baseband block 611 receives an information signal (e.g., representing voice, data) (which in turn receives a communication signal from another user equipment (wireless or fixed) in the network downstream of the BSC) from the base station controller (BSC) via the corresponding path shown in bus 699, processes the signal according to corresponding technologies and protocols to perform modulation, channel coding, and other operations, and forwards the processed signal to the transmit RF block 612. The transmit RF block 612 may perform operations such as up - conversion to RF and forwards the RF signal to the power amplifier 613. The power amplifier 613 amplifies the received RF signal and transmits the power - amplified signal to the corresponding wireless user equipment via the duplexer 620A, the combiner 630, and the antenna 640.

[0084] The LNA 616 receives an RF signal from the wireless user equipment via the duplexer 620A, the combiner 630, and the antenna 640, amplifies the RF signal, and forwards the amplified RF signal to the receive RF block 615. The receive RF block 615 down - converts the RF signal to baseband frequency and forwards the baseband signal to the receive baseband block 614. The receive baseband block 614 may perform operations such as demodulation, error correction, etc. on the baseband signal to obtain an information signal (e.g., data, voice) and forwards the information signal to the BSC via the corresponding path in bus 699.

[0085] The clock 617 generates one or more clocks required to enable the operation of the digital units in the transceiver 610. For example, the transmit baseband block 611 and the receive baseband block 614 may internally include one or more processors that require clocks to enable their operation.

[0086] Figure 6 The operations of the transmitters, receivers, and clocks of the other transceivers are similar to those described above for transceiver 610A and include corresponding transmitter blocks and receiver blocks.

[0087] Each of the duplexers 620A to 620N is capable of sending and receiving corresponding transmit and receive signals (i.e., two-way (duplex) communication) on a single path between the respective duplexer and the combiner 630. Each of the duplexers 620A to 620N can be implemented with two band-pass filters connected in parallel, where one filter provides a path between the respective transmitter and the combiner 630, and the other filter provides a path between the combiner 630 and the respective receiver.

[0088] The combiner 630 combines the signals from / to the transceivers 610A to 610N so that all signals can be sent and received using a single antenna 640.

[0089] The antenna 640 operates to receive wireless signals carrying information via a wireless medium between the transceiver and the wireless user equipment, and to send wireless signals carrying information to the wireless medium.

[0090] The battery pack 650 houses batteries and provides power for the operation of the blocks / units in the BTS system 600.

[0091] The power supply 660 receives power (e.g., at a voltage of 12 volts) from the battery pack 650, and includes a plurality of DC-DC converters 661A to 661M, and a plurality of linear regulators (e.g., implemented as LDOs) 662A to 662L. The DC-DC converters 661A - 661M generate various voltages (each DC-DC converter generates a corresponding voltage, e.g., 0.7V, 1.2V, 2.0V, 3.6V, etc.) for powering one or more blocks / components of the above BTS system 600. Specifically, the voltages generated by the DC-DC converters can be used to power the blocks and components in the transceivers 610A to 610N that are less sensitive to noise (e.g., the transmit and receive baseband blocks). Thus, the power supply voltage 491C is shown as being generated by the DC-DC converter 661A and being provided to the (transmit and receive baseband blocks) of the transceiver 610. The power supply voltage 691C can correspond to Figure 1 the voltage 101 (Vin). For clarity and conciseness, Figure 6 only one power connection directly from the DC-DC converter is shown in

[0092] Each of the LDOs 662A - 662L is connected to receive the output voltage of the corresponding DC-DC converter 661A - 661M, and generates a corresponding lower voltage according to the needs of some components / blocks of the transceiver. Thus, the LDO 662A can correspond to Figure 1 the device / linear regulator 100 of Figure 1The voltage 131 (Vreg) corresponds to the voltage 691B. The voltage generated by the LDO is used to power the noise-sensitive blocks and components in the transceivers 610A to 610N, such as the transmit RF block (e.g., 612), the receive RF block (e.g., 615), the LNA (e.g., 616), and the clock (e.g., 617) included in the transceivers. For clarity and brevity, Figure 6 only two power connections 491A and 491B (from LDO 662A and LDO 662L respectively) are shown in

[0093] One or more of the LDOs 662A - 662 - L are implemented as the linear voltage regulator / device 100 described in detail above.

[0094] It should be noted here that the linear voltage regulator 100 can also be used in other systems, such as a separate transmitter and receiver, mobile phones, etc.

[0095] 7. Conclusion

[0096] Throughout the specification, references to "one embodiment" ("one embodiment" and "an embodiment") or similar language mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the present application. Thus, the phrases "in one embodiment" ("in one embodiment" and "in an embodiment") and similar language that appear throughout the specification may, but do not necessarily, all refer to the same embodiment.

[0097] Although in Figure 1 、 4 and the illustration of 6, the ends / nodes are shown as having direct connections to (i.e., "connected to") various other ends, it should be understood that additional components (suitable for a particular environment) may also be present in the path, and thus the connections can be considered "electrically coupled" to the same connected ends.

[0098] It should be understood that the specific types of transistors mentioned above (e.g., NMOS, PMOS, etc.) are for illustration only. However, by reading the disclosure provided herein, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art. For example, an NMOS transistor can be replaced with a PMOS (P-type metal oxide semiconductor) transistor while interchanging the connections to the power and ground terminals.

[0099] Therefore, in the present application, the power supply terminal and the ground terminal are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (providing a current path when turned on and an open circuit path when turned off) are referred to as current terminals, and the gate (base) is referred to as a control terminal.

[0100] Although various embodiments of the present application have been described above, it should be understood that they are presented only by way of example and not limitation. Therefore, the breadth and scope of the present application should not be limited by any of the above-described embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. An execution method associated with a storage unit, the method comprising: Storing charge from a first power supply on a charge storage device within a first time interval, wherein the power provided by the first power supply is less than the power required to operate the storage unit; Using the charge storage device as a second power supply to operate the storage unit within a second time interval; wherein a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval; and Reading a first bit from the storage unit during a first read duration and reading a second bit from the storage unit during a second read duration, wherein the first read duration is separated from the second read duration by an idle duration, wherein the idle duration includes the first time interval and the first read duration includes the second time interval.

2. The method according to claim 1, wherein, the charge storage device is a capacitor, the storage unit is designed to be operated by a power supply providing a first voltage, a second voltage provided by the first power supply is less than the first voltage, the storage causes the second voltage to be amplified to provide an amplified voltage greater than or equal to the first voltage, wherein the storage causes the capacitor to be charged to the amplified voltage within the first time interval.

3. The method according to claim 2, wherein, the first time interval and the second time interval do not overlap at all, wherein the amplified voltage is greater than the first voltage, the method further comprising: Obtaining the first voltage from the amplified voltage.

4. The method according to claim 3, wherein, the storage unit is a non-volatile one-time programmable OTP storage unit for storing configuration parameters, wherein the configuration parameters include the first bit and the second bit.

5. The method according to claim 4, wherein, the first time interval is longer than the second time interval.

6. The method according to claim 5, wherein, the amplified voltage represents the maximum safe voltage to which the capacitor can be charged.

7. The method according to claim 6, wherein, the configuration parameters are used to configure one or more circuit blocks of a device, the method is executed in the device, wherein the device includes: the one or more circuit blocks for performing desired operations; the storage unit; a digital unit for performing the reading of the first bit and the reading of the second bit; a charge pump, which is coupled to the first power supply, and the charge pump performs the storage.

8. The method according to claim 3, further comprising: Receiving one or more data bits; and During the second time interval, programming each location in the storage unit with the one or more data bits.

9. A device, comprising: A charge storage device; A charge pump, wherein an input of the charge pump is coupled to a first power supply and an output node of the charge pump is coupled to the charge storage device; wherein: The power provided by the first power supply is less than the power required to operate a storage unit, The charge pump is designed to store charge from the first power supply on the charge storage device during a first time interval, use the charge storage device as a second power supply to operate the storage unit during a second time interval, a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval; and a digital unit, configured to read a first bit from the storage unit during a first read duration and read a second bit from the storage unit during a second read duration, wherein the first read duration is separated from the second read duration by an idle duration, wherein the idle duration includes the first time interval and the first read duration includes the second time interval.

10. The apparatus according to claim 9, wherein, the charge storage device is a capacitor, and the apparatus further includes the storage unit, wherein: the storage unit is designed to be operated by a power supply providing a first voltage, a second voltage provided by the first power supply is less than the first voltage, the charge pump is designed to amplify the second voltage to an amplified voltage during storing charge on the capacitor, so that the capacitor is charged to the amplified voltage during the first time interval, wherein the amplified voltage is greater than or equal to the first voltage.

11. The apparatus according to claim 10, wherein, the first time interval and the second time interval do not overlap at all, wherein the amplified voltage is greater than the first voltage, and the apparatus further includes: a resistor and a first transistor, the resistor and the first transistor are serially coupled between the output node and an internal node of the apparatus, wherein the capacitor is coupled between the internal node and a first constant reference potential; and a second transistor, which is coupled between the internal node and a power supply terminal of the storage unit.

12. The apparatus according to claim 11, wherein, a first end of the resistor is coupled to the output node, a first current terminal of the first transistor is coupled to a second end of the resistor, a second current terminal of the first transistor is coupled to the internal node, and a control terminal of the first transistor is coupled to a first reference voltage, the magnitude of the first reference voltage is equal to the sum of the threshold voltage of the first transistor and the maximum voltage to which the capacitor is to be charged.

13. The apparatus according to claim 12, wherein, a first current terminal of the second transistor is coupled to the internal node, a second current terminal of the second transistor is coupled to the power supply terminal of the storage unit, a control terminal of the second transistor is coupled to a second reference voltage, the magnitude of the second reference voltage is equal to the sum of the amplitude of the first voltage and the threshold voltage of the second transistor.

14. The apparatus according to claim 13, further includes a reference voltage generator for generating the first reference voltage and the second reference voltage.

15. The device according to claim 14 further includes a core functional block, the core functional block includes a circuit for implementing a low dropout regulator (LDO), the LDO is used to generate a regulated power supply voltage from a low-power power supply, and the regulated power supply voltage is the output of the device.

16. A system, comprising: a power terminal coupled to a first power supply; and a power supply unit, which is coupled to receive power from the power terminal, the power supply unit includes a first linear regulator and a first DC-DC converter, the first DC-DC converter represents a third power supply coupled to the power terminal, and the first linear regulator is coupled to the third power supply to generate a first lower power supply voltage, wherein, the first linear regulator includes: a core functional block, the core functional block includes a circuit for generating the first lower power supply voltage; a charge storage device; a charge pump, wherein an input of the charge pump is coupled to the third power supply, and an output node of the charge pump is coupled to the charge storage device; wherein: the power provided by the third power supply is less than the power required to operate the storage unit, the charge pump is designed to store charge from the power terminal on the charge storage device within a first time interval, use the charge storage device as a second power supply to operate the storage unit within a second time interval, a part of one of the first time interval and the second time interval does not overlap with the other of the first time interval and the second time interval; and a digital unit, for reading a first bit from the storage unit during a first read duration and reading a second bit from the storage unit during a second read duration, wherein the first read duration is separated from the second read duration by an idle duration, wherein, the idle duration includes the first time interval, and the first read duration includes the second time interval.

17. The system according to claim 16 further comprises: an antenna; a first duplexer coupled to the antenna; and a first transceiver, wherein the first lower power supply voltage is used to supply power to a noise-sensitive block in the first transceiver, the first transceiver includes a transmitter section and a receiver section, the transmitter section and the receiver section are each coupled to the first duplexer, the first transceiver transmits a communication signal to a wireless medium via the first duplexer and the antenna, and the first transceiver also receives a communication signal from the wireless medium via the first duplexer and the antenna; wherein: the charge storage device is a capacitor, and the first linear regulator further includes the storage unit, the storage unit is designed to be operated by a power supply providing a first voltage, a second voltage provided by the third power supply is less than the first voltage, the charge pump is designed to amplify the second voltage to an amplified voltage during the period of storing charge on the capacitor, so that the capacitor is charged to the amplified voltage within the first time interval, wherein the amplified voltage is greater than or equal to the first voltage.

18. The system according to claim 17, wherein, The system is a Base Transceiver Station (BTS) system, and the BTS system further includes: A combiner coupled to the antenna; A plurality of duplexers, each of the plurality of duplexers being coupled to the combiner, the plurality of duplexers including the first duplexer; and A plurality of transceivers, including the first transceiver, each of the plurality of transceivers including a transmitter section and a receiver section, coupled at one end to a corresponding one of the plurality of duplexers and at the other end to a Base Station Controller (BSC), wherein each of the plurality of transceivers is configured to transmit an information signal received from the base station controller into the wireless medium via a corresponding one of the plurality of duplexers, the combiner, and the antenna, and to forward an information signal received from the wireless medium to the base station controller via a corresponding one of the plurality of duplexers, the combiner, and the antenna; Wherein the power supply unit includes: A plurality of DC-DC converters coupled to receive the power from the power terminal and generate corresponding supply voltages including the second voltage, the plurality of DC-DC converters including a first DC-DC converter, wherein the second voltage is used to power a noise-insensitive block in the first transceiver; A plurality of linear regulators coupled to receive a supply voltage from a corresponding one of the DC-DC converters and generate corresponding lower supply voltages, the plurality of linear regulators including the first linear regulator, wherein the first linear regulator is coupled to receive the second voltage from the first DC-DC converter to generate the first lower supply voltage; wherein: The supply voltages generated by one or more of the DC-DC converters are used to power noise-insensitive blocks in the plurality of transceivers, and the supply voltages generated by one or more of the linear regulators are used to power noise-sensitive blocks in the plurality of transceivers, The implementation of at least a second linear regulator among the plurality of linear regulators is similar to that of the first linear regulator.

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