Transistor gate structure and method of forming the same

Abstract

This application relates to transistor gate structures and methods of forming the same. In one embodiment, a device includes a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including an n-type work function metal, the n-type work function metal being different than the p-type work function metal; and a fill layer on the second work function tuning layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically to transistor gate structures and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a transistor gate structure is provided, the transistor gate structure comprising: a channel region; a gate dielectric layer located on the channel region; a first work function tuning layer located on the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal; a barrier layer located on the first work function tuning layer; a second work function tuning layer located on the barrier layer, the second work function tuning layer comprising an n-type work function metal, the n-type work function metal being different from the p-type work function metal; and a fill layer located on the second work function tuning layer.

[0005] According to another aspect of this disclosure, a transistor gate structure is provided, comprising: a first transistor, the first transistor including: a first channel region; a first gate dielectric layer located on the first channel region; a p-type work function tuning layer located on the first gate dielectric layer; a barrier layer located on the p-type work function tuning layer; a first n-type work function tuning layer located on the barrier layer, the first n-type work function tuning layer comprising a metal, the concentration of metal residue contained in the upper part of the barrier layer being greater than the concentration of metal residue contained in the lower part of the barrier layer, the upper part of the barrier layer being close to the first n-type work function tuning layer, and the lower part of the barrier layer being close to the p-type work function tuning layer; and a first fill layer located on the first n-type work function tuning layer. The transistor gate structure further includes: a second transistor, the second transistor including: a second channel region; a second gate dielectric layer located on the second channel region; a second n-type work function tuning layer located on the second gate dielectric layer, the second n-type work function tuning layer comprising the metal; and a second fill layer located on the second n-type work function tuning layer.

[0006] According to another aspect of this disclosure, a method for forming a transistor gate structure is provided, the method comprising: depositing a gate dielectric layer having a first portion and a second portion, the first portion being deposited on a first channel region and the second portion being deposited on a second channel region; forming a first work function tuning layer on the first portion of the gate dielectric layer; forming a barrier layer on the first work function tuning layer; and depositing a second work function tuning layer on the barrier layer and on the second portion of the gate dielectric layer, the barrier layer suppressing modification of the first work function of the first work function tuning layer during the deposition of the second work function tuning layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanostructured FET) is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22BThis is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 23A and Figure 23B This is a view of a nanostructured FET according to some other embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0013] According to various embodiments, the gate electrode is formed with multiple work function tuning layers. A barrier layer is formed on the lower work function tuning layer, and an upper work function tuning layer is deposited on the barrier layer. The barrier layer can be thin enough not to significantly modify the work function of the gate electrode, and modifications to the lower work function tuning layer are suppressed (e.g., substantially prevented or at least reduced) during the deposition of the upper work function tuning layer. Therefore, the threshold voltage of the resulting device can be tuned more accurately.

[0014] Embodiments of dies incorporating nanostructured FETs (field effect transistors) have been described in a specific context. However, various embodiments may be applied to dies incorporating other types of transistors (e.g., fin field effect transistors, planar transistors, etc.) instead of or in combination with nanostructured FETs.

[0015] Figure 1 Examples of nanostructured FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1 This is a 3D view, in which some features of the nanostructure FET are omitted for clarity. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), etc.

[0016] The nanostructured FET includes nanostructures 66 (e.g., nanosheets, nanowires, etc.) on a substrate 50 (e.g., a semiconductor substrate) above fins 62, wherein the nanostructures 66 serve as channel regions for the nanostructured FET. The nanostructures 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70 (e.g., shallow trench isolation (STI) regions) are disposed between adjacent fins 62, and the fins 62 may protrude above the isolation regions 70 between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as independent of the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fins 62 is illustrated as a single continuous material with respect to the substrate 50, the bottom portion of the fins 62 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 62 refers to the portion extending above the isolation regions 70 between adjacent isolation regions 70.

[0017] Gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 124 is located above gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62, on opposite sides of gate dielectric 122 and gate electrode 124. These epitaxial source / drain regions 98 can be shared between fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by joining these epitaxial source / drain regions 98 through epitaxial growth, or by coupling these epitaxial source / drain regions 98 to the same source / drain contact.

[0018] Figure 1Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section B-B' is along the longitudinal axis of the fin 62 and in a direction, for example, the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nanostructure FET. These reference cross sections are referenced in subsequent figures for clarity.

[0019] Some of the embodiments discussed herein are discussed in the context of forming nanostructured FETs using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in fin field-effect transistors (FinFETs). For example, a FinFET may include fins on a substrate, where these fins serve as the channel region of the FinFET. Similarly, a planar FET may include a substrate, where portions of the substrate serve as the channel region of the planar FET.

[0020] Figures 2 to 22B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 21A and Figure 22A It shows Figure 1 The reference section A-A' is shown in the figure. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 20B , Figure 21B and Figure 22B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 9C and Figure 9D It shows Figure 1 The reference section C-C' shown in the figure.

[0021] exist Figure 2 The diagram provides a substrate 50 for forming a nanostructured FET. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc.), which can be doped (e.g., doped with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0022] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as N-type metal-oxide-semiconductor (NMOS) transistors, for example, n-type nanostructure FETs, and the p-type region 50P can be used to form p-type devices such as P-type metal-oxide-semiconductor (PMOS) transistors, for example, p-type nanostructure FETs. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] The substrate 50 can be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation can be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities can be implanted into the substrate 50. The conductivity type of the impurity can be opposite to the conductivity type of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region can extend below the source / drain regions in the nanostructured FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region can be approximately 10. 18 cm -3 To about 10 19 cm -3 Within the range.

[0024] A multilayer stack 52 is formed on the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. Each semiconductor material can be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0025] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed, and the second semiconductor layer 56 is patterned to form channel regions for a nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity (compared to etching the second semiconductor layer 56), such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0026] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-xThe second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The first and second semiconductor materials can have high etch selectivity relative to each other, such that the first semiconductor layer 54 can be removed without removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 can be removed without removing the first semiconductor layer 54 in the p-type region 50P.

[0027] Each layer of the multilayer stack 52 can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form the channel region for a nanostructured FET in an n-type region 50N and a p-type region 50P, the first semiconductor layer 54 can have a first thickness and the second semiconductor layer 56 can have a second thickness, wherein the second thickness is about 30% to about 60% smaller than the first thickness. Forming the second semiconductor layer 56 to a smaller thickness allows the channel region to be formed at a greater density.

[0028] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fins 62 are semiconductor strips patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 comprise the remainder of the first semiconductor layer 54 and the remainder of the second semiconductor layer 56, respectively. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0029] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have smaller spacing, for example, than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used as masks to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0030] The widths of fins 62 and nanostructures 64, 66 can each range from about 8 nm to about 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than those in another region (e.g., p-type region 50P).

[0031] exist Figure 4 In this embodiment, STI regions 70 are formed on substrate 50 and between adjacent fins 62. The STI regions 70 are arranged to surround at least a portion of the fins 62, such that at least a portion of the nanostructures 64, 66 protrudes from between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI regions 70 separate features of adjacent devices.

[0032] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although the individual STI regions 70 are illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Afterward, a filling material, such as those previously described, can be formed on top of the lining.

[0033] Then, a removal process is applied to the insulating material to remove excess insulating material on the nanostructures 64, 66. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, combinations thereof, can be used. In embodiments where the mask remains on the nanostructures 64, 66, the planarization process can expose or remove the mask. After the planarization process, the top surface of the insulating material is coplanar with the top surface of the mask (if present) or the nanostructures 64, 66 (within the range of process variations). Thus, the top surface of the mask (if present) or the nanostructures 64, 66 is exposed through the insulating material. In the illustrated embodiment, no mask is retained on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 70 can be formed into a flat, convex, and / or concave shape through appropriate etching. Acceptable etching processes can be used to recess the insulating material, such as material-selective etching processes for the insulating material (e.g., selectively etching the STI region 70 at a faster rate than etching the material for fins 62 and nanostructures 64, 66). For example, oxide removal can be performed using diluted hydrofluoric acid (dHF).

[0034] The processes described above are merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structure may include the alternating semiconductor materials described previously, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing the epitaxial structure, the material to be epitaxially grown can be in-situ doped during growth, which can avoid prior and / or subsequent implantation; however, in-situ doping and implantation doping can also be used together.

[0035] Furthermore, suitable wells (not shown separately) may be formed in the substrate 50, fins 62, and / or nanostructures 64, 66. The conductivity type of the well may be opposite to the conductivity type of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well may be formed in the n-type region 50N, and an n-type well may be formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0036] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as a photoresist (not shown separately). For example, a photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist can be patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region at a concentration of about 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0037] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region, at a concentration of approximately 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0038] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments of epitaxial growth of fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation; however, in-situ doping and implantation doping can also be used together.

[0039] exist Figure 5In this process, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed from dielectric materials such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown using acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited on the dummy gate layer 74. The dummy gate layer 74 can be formed from conductive or non-conductive materials, such as amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), metals, metal nitrides, metal silicides, metal oxides, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed of one or more materials with high etch selectivity (compared to etch insulating materials such as STI region 70 and / or dummy dielectric layer 72). The mask layer 76 can be formed of a dielectric material such as silicon nitride or silicon oxynitride. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and STI region 70, such that the dummy dielectric layer 72 is over the STI region 70 and extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and nanostructures 64, 66.

[0040] exist Figure 6 In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 using any acceptable etching technique to form dummy gate 84. The pattern of mask 86 may optionally be further transferred to dummy dielectric layer 72 using acceptable etching techniques to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66, which will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of nanostructures 66, which will be patterned to form channel regions 68. The pattern of mask 86 can be used to physically separate adjacent dummy gates 84. Furthermore, the longitudinal direction of dummy gate 84 may be substantially perpendicular to the longitudinal direction of fin 62 (within process variations). Mask 86 may optionally be removed after patterning, for example, by acceptable etching techniques.

[0041] Figures 7A to 22B Various additional steps in manufacturing the embodiment device are shown. Figures 7A to 13B as well as Figures 20A to 22B Features in either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structure of the n-type region 50N and the p-type region 50P are described in the text corresponding to each figure. Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A Features in the p-type region 50P are shown. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B The characteristics of the n-type region 50N are shown.

[0042] exist Figure 7A and Figure 7B In this embodiment, gate spacers 90 are formed on nanostructures 64 and 66, on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching that dielectric material(s). Acceptable dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, each gate spacer 90 includes multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-yThe first spacer layer 90A may be formed from a silicon carbonitride composition similar to or different from that of the second spacer layer 90B. An acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s) may have portions remaining on the sidewalls of the dummy gate 84 during etching (thus forming the gate spacer 90). As will be described in more detail later, the dielectric material(s) may also have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 during etching (thus forming the fin spacer 92, see...). Figure 9C and Figure 9D After etching, the fin spacer 92 / gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0043] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments for different device types, similar to the implantation previously described for wells, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity described above, and the p-type impurity can be any p-type impurity described above. During implantation, the channel region 68 remains covered by the dummy gate 84, ensuring that the channel region 68 is essentially free of impurities implanted to form the LDD region. The impurity concentration in the LDD region can be approximately 10. 15 cm -3 To about 10 19 cm -3 Within the scope. Annealing can be used to repair implant damage and activate implanted impurities.

[0044] Note that the previous disclosures generally described the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0045] exist Figure 8A and Figure 8B In the illustrated embodiment, source / drain recesses 94 are formed in nanostructures 64, 66. In this embodiment, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of substrate 50 without etching substrate 50; the fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is arranged below the top surface of STI region 70; and so on. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using anisotropic etching processes (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.). During the etching process used to form the source / drain recesses 94, gate spacer 90 and dummy gate 84 jointly mask portions of fin 62 and / or nanostructures 64, 66. A single etching process can be used to etch each of the nanostructures 64 and 66, or multiple etching processes can be used to etch the nanostructures 64 and 66. A time-controlled etching process can be used to stop the etching of the source / drain recess 94 after it has reached the desired depth.

[0046] Optionally, internal spacers 96 are formed on the sidewalls of the remaining portion of the first nanostructure 64 (e.g., those sidewalls exposed by the source / drain recesses 94). As will be described in more detail later, source / drain regions are then formed in the source / drain recesses 94, and the first nanostructure 64 is subsequently replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent subsequent etching processes (e.g., etching processes for the subsequent removal of the first nanostructure 64) from damaging the subsequently formed source / drain regions.

[0047] As an example of forming the internal spacer 96, the source / drain recesses 94 can be extended laterally. Specifically, portions of the sidewalls of the first nanostructure 64 exposed by the source / drain recesses 94 can be recessed. Although the sidewalls of the first nanostructure 64 are illustrated as straight, these sidewalls can be concave or convex. The sidewalls can be recessed by an acceptable etching process, such as an etching process selective for the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than etching the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas (e.g., hydrogen fluoride (HF) gas). In some embodiments, the same etching process can be performed sequentially to form the source / drain recesses 94 and to recess the sidewalls of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material can be silicon nitride or silicon oxynitride, however any suitable material can be used, such as a low dielectric constant (low-k) material with a k-value less than about 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer sidewalls of the internal spacer 96 are illustrated as flush with the sidewalls of the gate spacer 90, the outer sidewalls of the internal spacer 96 can extend beyond or recess from the sidewalls of the gate spacer 90. In other words, the internal spacer 96 can partially fill, completely fill, or overfill the sidewall recesses. Furthermore, although the sidewalls of the inner spacer 96 are shown as straight, the sidewalls of the inner spacer 96 may be concave or convex.

[0048] exist Figure 9A and Figure 9BIn this process, epitaxial source / drain regions 98 are formed in the source / drain recesses 94. The epitaxial source / drain regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and its corresponding channel region 68) is arranged between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 by an appropriate lateral distance, and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the first nanostructure 64 by an appropriate lateral distance, such that the epitaxial source / drain regions 98 are not short-circuited with the gate of the subsequently formed nanostructure FET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel regions 68, thereby improving performance.

[0049] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain region 98 in the n-type region 50N is then epitaxially grown in the source / drain recess 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N may be referred to as the "n-type source / drain region". The surface of the epitaxial source / drain region 98 in the n-type region 50N may protrude above the surfaces of the corresponding fins 62 and nanostructures 64, 66, and may have small facets.

[0050] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain region 98 in the p-type region 50P is then epitaxially grown in the source / drain recess 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material that applies compressive strain to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P may be referred to as the "p-type source / drain region". The surface of the epitaxial source / drain region 98 in the p-type region 50P may protrude above the surfaces of the corresponding fins 62 and nanostructures 64, 66, and may have small facets.

[0051] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration in the source / drain regions can be approximately 10. 19cm -3 To about 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0052] As a result of the epitaxial process used to form the epitaxial source / drain region 98, the upper surface of the epitaxial source / drain region has small planes that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, such as Figure 9C As shown, these small planes cause adjacent epitaxial source / drain regions 98 to merge. In some embodiments, such as Figure 9D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 98 remain separated. In the illustrated embodiment, the spacer etching for forming the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover portions of the sidewalls of fins 62 and / or nanostructures 64, 66 that extend above the STI region 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching for forming the gate spacer 90 is adjusted not to form fin spacers, so as to allow the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0053] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, each epitaxial source / drain region 98 may include a liner layer 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the liner layer 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the liner layer 98A may have a lower impurity concentration than the main layer 98B, and the finishing layer 98C may have a higher impurity concentration than the liner layer 98A but a lower impurity concentration than the main layer 98B. In an embodiment where the epitaxial source / drain region 98 includes three semiconductor material layers, a liner layer 98A may be grown in the source / drain recess 94, a main layer 98B may be grown on the liner layer 98A, and a trimming layer 98C may be grown on the main layer 98B.

[0054] exist Figure 10A and Figure 10BIn this configuration, a first-layer dielectric (ILD) 104 is deposited over the epitaxial source / drain region 98, gate spacer 90, mask 86 (if present), or dummy gate 84. The first ILD 104 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phospho-silicate gases (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0055] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have high etch selectivity (compared to etching the first ILD 104). The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0056] exist Figure 11A and Figure 11B In this process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or the dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the gate spacer 90, the first ILD 104, CESL 102, and the mask 86 (if present) or the dummy gate 84 are coplanar (within the range of process variations). Therefore, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0057] exist Figure 12A and Figure 12BIn the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 106. A portion of the dummy dielectric 82 in the recess 106 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 at a faster rate than for the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may serve as an etch stop layer while the dummy gate 84 is etched. The dummy dielectric 82 is then removed. Each recess 106 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between an adjacent pair of epitaxial source / drain regions 98.

[0058] The remaining portion of the first nanostructure 64 is then removed to extend the recess 106, thereby forming an opening 108 in the region 50I between the second nanostructures 66. The remaining portion of the first nanostructure 64 can be removed by an acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate faster than that for the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructure 66. Figures 14A to 19B As shown more clearly in (described in more detail later), the remainder of the second nanostructure 66 may have rounded corners.

[0059] exist Figure 13A and Figure 13B In the recess 106, a gate dielectric layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers used to replace the gate, and each layer encloses all (e.g., four) sides of the second nanostructure 66.

[0060] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the second nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the gate spacer 90 and the first ILD 104. The gate dielectric layer 112 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may include dielectric materials with a k-value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figure 13A and Figure 13B A single-layer gate dielectric layer 112 is shown, but as will be described in more detail later, the gate dielectric layer 112 may include an interface layer and a main layer.

[0061] The gate electrode layer 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in Figure 13A and Figure 13B The diagram shows a single gate electrode layer 114, but as will be described in more detail later, the gate electrode layer 114 may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0062] The formation of the gate dielectric layer 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 112 in each region is formed of the same material, and the formation of the gate electrode layer 114 can occur simultaneously, such that the gate electrode layer 114 in each region is formed of the same material. In some embodiments, the gate dielectric layer 112 in each region can be formed by different processes, such that these gate dielectric layers 112 can be different materials and / or have different numbers of layers, and / or the gate electrode layer 114 in each region can be formed by different processes, such that these gate electrode layers 114 can be different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. In the following description, at least a portion of the gate electrode layer 114 in the n-type region 50N and at least a portion of the gate electrode layer 114 in the p-type region 50P are formed separately.

[0063] Figures 14A to 19B The process of forming a gate dielectric layer 112 and a gate electrode layer 114 for replacing the gate in the recess 106 is shown. A comparison with... Figure 13A Features similar to those in region 50R. When forming the alternative gate layer, a first work function tuning layer 114A is formed in the first region (e.g., p-type region 50P) (see...). Figure 17A ) and barrier layer 114B (see Figure 17A Then, a second work function tuning layer 114C is formed in both the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N) (see...). Figure 18A and Figure 18B Because the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N) include different numbers and types of work function tuning layers, the devices formed in these regions have different threshold voltages. Furthermore, in the first region (e.g., p-type region 50P), a barrier layer 114B is disposed between the first work function tuning layer 114A and the second work function tuning layer 114C. During the deposition of the second work function tuning layer 114C, the barrier layer 114B protects the underlying first work function tuning layer 114A so that the work function of the first work function tuning layer 114A is not modified due to metal diffusion into the first work function tuning layer 114A. Therefore, the threshold voltage of the resulting device can be tuned more accurately.

[0064] exist Figure 14A and Figure 14B In this configuration, the gate dielectric layer 112 is deposited in the recess 106 of both the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N). The gate dielectric layer 112 may also be deposited on the top surface of the first ILD 104 and the gate spacer 90 (see [link to ILD configuration]). Figure 13B The gate dielectric layer 112 can be formed by methods such as molecular-beam deposition (MBD), ALD, and PECVD. The gate dielectric layer 112 surrounds all (e.g., four) sides of the second nanostructure 66. In the illustrated embodiment, the gate dielectric layer 112 is multilayered, including an interface layer 112A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 112B (or more generally, a second gate dielectric layer). The interface layer 112A may be formed of silicon oxide, while the high-k dielectric layer 112B may be formed of hafnium oxide.

[0065] exist Figure 15A and Figure 15BIn this process, a first work function tuning layer 114A is deposited on a gate dielectric layer 112 in both a first region (e.g., p-type region 50P) and a second region (e.g., n-type region 50N). As will be described in more detail later, the first work function tuning layer 114A is patterned to remove a portion of the first work function tuning layer 114A in the second region (e.g., n-type region 50N), while retaining a portion of the first work function tuning layer 114A in the first region (e.g., p-type region 50P). When the first work function tuning layer 114A is removed from the second region (e.g., n-type region 50N) but retained in the first region (e.g., p-type region 50P), it may be referred to as a "p-type work function tuning layer". The first work function tuning layer 114A includes any acceptable material for tuning the work function of the device to a desired amount for the application of the device to be formed, and the first work function tuning layer 114A can be deposited using any acceptable deposition process. For example, when the first work function tuning layer 114A is a p-type work function tuning layer, it can be formed of a p-type work function metal (PWFM) such as titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, and it can be deposited by ALD, CVD, or PVD. Although the first work function tuning layer 114A is shown as a single layer, it can be multilayered. For example, the first work function tuning layer 114A may include a titanium nitride (TiN) layer and a tantalum nitride (TaN) layer.

[0066] In the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N), the first work function tuning layer 114A fills the remaining portion of region 50I located between the second nanostructures 66 (e.g., fills the opening 108, see below). Figure 14A and Figure 14BSpecifically, a first work function tuning layer 114A is deposited on the gate dielectric layer 112 until it is thick enough to merge and bond together. In some embodiments, an interface 116 is formed by contact between adjacent portions of the first work function tuning layer 114A (e.g., those around the second nanostructure 66). As a result, the opening 108 is completely filled with one or more dielectric materials of the gate dielectric layer 112 and the work function metal of the first work function tuning layer 114A, such that no barrier layer (described in more detail later) can be formed in the opening 108. By not depositing a barrier layer in the opening 108, ease of fabrication can be improved, especially in advanced semiconductor nodes with small feature sizes, as it can be difficult to deposit barrier layer material in small spaces. In the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N), portions of the gate dielectric layer 112 surround each of the second nanostructure 66, and portions of the first work function tuning layer 114A fill the regions between the portions of the gate dielectric layer 112. In some embodiments, the first work function tuning layer 114A is formed to have approximately to approximately The thickness is within the range of [specific parameters]. The first work function tuning layer 114A is formed with a thickness less than approximately [specific value]. The thickness may not allow the portions of the first work function tuning layer 114A to merge. The first work function tuning layer 114A is formed to have a thickness greater than approximately... The thickness of the material may have a negative impact on the threshold voltage of the resulting device.

[0067] exist Figure 16A and Figure 16B A barrier layer 114B is deposited on the first work function tuning layer 114A. As will be described in more detail later, a second work function tuning layer is formed on the barrier layer 114B, and the second work function tuning layer may be formed of an easily diffusing metal. The barrier layer 114B is formed of a barrier material resistant to metal diffusion, thereby suppressing (e.g., substantially preventing or at least reducing) modification of the work function of the first work function tuning layer 114A. In some embodiments, forming the second work function tuning layer includes depositing aluminum, and the barrier layer 114B is formed of a barrier material resistant to aluminum diffusion, thereby suppressing aluminum diffusion into the first work function tuning layer 114A. Suitable barrier materials include amorphous silicon or fluorine-free tungsten, which can be deposited by CVD or ALD, etc., as described in more detail later.

[0068] The barrier layer 114B is formed to have a thickness sufficient to suppress modification of the work function of the first work function tuning layer 114A during subsequent processing. In some embodiments, the barrier layer 114B is formed to have approximately to approximately The thickness is within the range of [specific range]. The barrier layer 114B is formed to have a thickness less than approximately [specific value]. The thickness may be insufficient to protect the first work function tuning layer 114A. The barrier layer 114B is formed to have a thickness greater than approximately [missing information]. The thickness of the barrier layer 114B may have a negative impact on the threshold voltage of the resulting device. The barrier layer 114B can have a smaller thickness than the first work function tuning layer 114A.

[0069] In some embodiments, the barrier layer 114B is formed of amorphous silicon, which is deposited via a CVD process. Specifically, the barrier layer 114B may be formed by placing a substrate 50 in a deposition chamber and providing a silicon source precursor into the deposition chamber. Acceptable silicon source precursors include binary silicon-hydrogen compound silanes, such as silane (SiH4) and disilane (Si2H6). The CVD process can be performed at a temperature ranging from about 275°C to about 500°C and a pressure ranging from about 3 Torr to about 45 Torr, for example, by maintaining the deposition chamber at such temperature and pressure. The CVD process can be performed for a duration ranging from about 0.2 seconds to about 990 seconds, for example, by holding the silicon source precursor in the deposition chamber for such a duration. Performing the CVD process using parameters within these ranges allows the barrier layer 114B to be formed to the desired thickness (previously described) and quality. Performing the CVD process using parameters outside these ranges may not allow the barrier layer 114B to be formed to the desired thickness or quality.

[0070] In some embodiments, the barrier layer 114B is formed of fluorine-free tungsten, which is deposited via an ALD process. Specifically, the barrier layer 114B may be formed by placing a substrate 50 in a deposition chamber and cyclically supplying the deposition chamber with various source precursors. The fluorine-free tungsten is tungsten that does not contain fluorine and is deposited using a fluorine-free tungsten source precursor, such as a fluorine-free tungsten source precursor. Depositing tungsten with a fluorine-free tungsten source precursor avoids the generation of undesirable corrosive fluorine byproducts during deposition. A first pulse of the ALD cycle is performed by supplying the fluorine-free tungsten source precursor into the deposition chamber. Acceptable fluorine-free tungsten source precursors include tungsten chloride, such as tungsten chloride (V) (WCl5), etc. This first pulse can be performed at a temperature ranging from about 250°C to about 550°C and a pressure ranging from about 0.1 Torr to about 60 Torr, for example, by maintaining the deposition chamber at such temperature and pressure. The first pulse can be performed for a duration ranging from about 0.1 seconds to about 300 seconds, for example, by holding the fluorine-free tungsten source precursor in the deposition chamber for such a duration. The fluorine-free tungsten source precursor is then removed from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas into the deposition chamber. A second pulse of the ALD cycle is performed by supplying a hydrogen source precursor to the deposition chamber. Acceptable hydrogen source precursors include hydrogen (H2), etc. The second pulse can be performed at a temperature ranging from about 250°C to about 550°C and a pressure ranging from about 0.1 Torr to about 60 Torr, for example, by maintaining the deposition chamber at such temperature and pressure. The second pulse can be performed for a duration ranging from about 0.1 seconds to about 300 seconds, for example, by holding the hydrogen source precursor in the deposition chamber for such a duration. The hydrogen source precursor is then removed from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas into the deposition chamber. Each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of fluorine-free tungsten. The ALD cycle is repeated until the barrier layer 114B achieves the desired thickness (as previously described). The ALD cycle can be repeated from approximately 1 to approximately 500 times. Performing the ALD process using parameters within these ranges allows the barrier layer 114B to be formed with the desired thickness (as previously described) and quality. Performing the ALD process using parameters outside these ranges may fail to form the barrier layer 114B with the desired thickness or quality.

[0071] In the illustrated embodiment, the barrier layer 114B is a multilayer (one or more) barrier material, including a first barrier sublayer 114B1 and a second barrier sublayer 114B2. Such a barrier layer 114B is formed by the following steps: depositing the first barrier sublayer 114B1, and then depositing the second barrier sublayer 114B2 on top of the first barrier sublayer 114B1. In some embodiments, after the deposition of the first barrier sublayer 114B1 and before the deposition of the second barrier sublayer 114B2, the upper portion of the first barrier sublayer 114B1 is oxidized, thereby forming a third barrier sublayer 114B3 between the first barrier sublayer 114B1 and the second barrier sublayer 114B2. The upper portion of the first barrier sublayer 114B1 can be oxidized by exposing the first barrier sublayer 114B1 to an oxygen-containing environment. The oxygen-containing environment can be the same processing chamber as where the first barrier sublayer 114B1 was deposited, or it can be a different processing chamber. Therefore, the material of the third barrier sublayer 114B3 is an oxide of the barrier material of the first barrier sublayer 114B1. For example, when the first barrier sublayer 114B1 is formed of amorphous silicon, the third barrier sublayer 114B3 is formed of silicon oxide. The first barrier sublayer 114B1 and the second barrier sublayer 114B2 can be formed of the same barrier material, or they can include different barrier materials. Continuing with the previous example, when the first barrier sublayer 114B1 is formed of amorphous silicon, the second barrier sublayer 114B2 can also be formed of amorphous silicon, or the second barrier sublayer 114B2 can be formed of another barrier material such as fluorine-free tungsten. When the first barrier sublayer 114B1 and the second barrier sublayer 114B2 are formed of the same barrier material, depositing the second barrier sublayer 114B2 may include depositing more of the barrier material of the first barrier sublayer 114B1. The third barrier sublayer 114B3 can be thinner, for example, thinner than the first barrier sublayer 114B1 and the second barrier sublayer 114B2. For example, the thickness of the third barrier sublayer 114B3 can be from about 20% to about 75% of the total thickness of the barrier layers 114B. When the third barrier sublayer 114B3 is formed of oxide and is relatively thin, it can be referred to as a "thin oxide". As described in more detail later, including a third barrier sublayer 114B3 (e.g., a thin oxide) in the barrier layer 114B can help the barrier layer 114B further resist metal diffusion. In another embodiment (hereinafter referred to as...) Figure 23A and 23B (As described), barrier layer 114B is a single continuous layer of barrier material that does not include the intermediate thin oxide sublayer.

[0072] exist Figure 17A and Figure 17BIn this process, portions of the barrier layer 114B and the first work function tuning layer 114A are removed from the second region (e.g., n-type region 50N). Removing these portions of the barrier layer 114B and the first work function tuning layer 114A from the second region (e.g., n-type region 50N) extends the recess 106 in the second region (e.g., n-type region 50N) to re-expose the gate dielectric layer 112 and reform the opening 108 in the second region (e.g., n-type region 50N). This removal can be performed using acceptable photolithography and etching techniques. The etching can include any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0073] In some embodiments, a first etching is performed to remove portions of the barrier layer 114B, and a second etching is performed to remove portions of the first work function tuning layer 114A. The first etching may be selective for the barrier layer 114B (e.g., selectively etching the material of the barrier layer 114B at a faster rate than etching the material of the first work function tuning layer 114A). For example, when the barrier layer 114B is formed of amorphous silicon, it can be removed by wet etching using dilute hydrofluoric acid (dHF). The second etching may be selective for the first work function tuning layer 114A (e.g., selectively etching the material of the first work function tuning layer 114A at a faster rate than etching the material of the gate dielectric layer 112). For example, when the first work function tuning layer 114A is formed of titanium nitride, it can be removed by wet etching using ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). In other embodiments, a single etching is performed to remove portions of both the barrier layer 114B and the first work function tuning layer 114A.

[0074] exist Figure 18A and Figure 18BIn this configuration, a second work function tuning layer 114C is deposited on a barrier layer 114B in a first region (e.g., p-type region 50P) and on a gate dielectric layer 112 in a second region (e.g., n-type region 50N). As will be described in more detail later, an n-type device is formed having a second work function tuning layer 114C in the second region (e.g., n-type region 50N), and a p-type device is formed having a first work function tuning layer 114A and a second work function tuning layer 114C in the first region (e.g., p-type region 50P). When the second work function tuning layer 114C is the only work function tuning layer in the second region (e.g., n-type region 50N), it may be referred to as an "n-type work function tuning layer". The second work function tuning layer 114C includes any acceptable material for tuning the work function of the device to a desired amount for the application of the device to be formed, and the second work function tuning layer 114C can be deposited using any acceptable deposition process. For example, when the second work function tuning layer 114C is an n-type work function tuning layer, it can be formed of an n-type work function metal (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or combinations thereof, and can be deposited by ALD, CVD, or PVD. Although the second work function tuning layer 114C is shown as a single layer, it can be multilayered. For example, the second work function tuning layer 114C may include a titanium aluminum nitride (TiAlN) layer and a titanium nitride (TiN) layer.

[0075] In embodiments where the second work function tuning layer 114C is an n-type work function tuning layer, the second work function tuning layer 114C may include a metallic element (e.g., aluminum) suitable for tuning the threshold voltage of an n-type device, and this metallic element may also readily diffuse. For example, when the second work function tuning layer 114C includes aluminum, an aluminum-containing precursor such as triethylaluminum (TEA) (Al2(C2H5)6) or trimethylaluminum (TMA) (Al2(CH3)6) can be used to deposit the second work function tuning layer 114C via ALD or CVD. During deposition, aluminum dissociates from the aluminum-containing precursor to form the material of the second work function tuning layer 114C, but aluminum may also dissociate from the aluminum-containing precursor and diffuse into the barrier layer 114B. Similarly, the second work function tuning layer 114C can also be deposited via PVD, in which case sputtered aluminum ions may diffuse into the barrier layer 114B. The barrier layer 114B is formed of a barrier material resistant to metal diffusion, thereby inhibiting the diffusion of metal elements (e.g., aluminum) into the underlying first work function tuning layer 114A. Therefore, the deposition of the second work function tuning layer 114C may form a residue 120 of metal elements (e.g., aluminum) in the barrier layer 114B, wherein the concentration of residue 120 is greater in the upper portion of the barrier layer 114B than in the lower portion. The upper portion of the barrier layer 114B is a portion that is remote from the gate dielectric layer 112 and the first work function tuning layer 114A, and close to the second work function tuning layer 114C. The lower portion of the barrier layer 114B is a portion that is close to the gate dielectric layer 112 and the first work function tuning layer 114A, and remote from the second work function tuning layer 114C. The concentration of residue 120 can be reduced in the barrier layer 114B along a direction extending from the upper part of the barrier layer 114B to the lower part of the barrier layer 114B. In some embodiments, there is no residue 120 in the lower part of the barrier layer 114B. Oxides can be particularly resistant to the diffusion of some metals (e.g., aluminum) that readily combine with oxygen, and thus can be particularly effective in suppressing the diffusion of metals to the underlying first work function tuning layer 114A when the barrier layer 114B includes a third barrier sublayer 114B3 (e.g., a thin oxide). For example, when the barrier layer 114B is a multilayer (one or more) barrier material, the second barrier sublayer 114B2 may include residue 120, while the first barrier sublayer 114B1 does not contain residue 120.

[0076] In the second region (e.g., n-type region 50N), the second work function tuning layer 114C fills the remaining portion of region 50I located between the second nanostructures 66 (e.g., fills the openings 108, see...). Figure 17BSpecifically, a second work function tuning layer 114C is deposited on the gate dielectric layer 112 until it is thick enough to merge and bond together. In some embodiments, an interface 118 is formed by the contact of adjacent portions of the second work function tuning layer 114C (e.g., those around the second nanostructure 66). As a result, the opening 108 in the second region (e.g., n-type region 50N) is completely filled with one or more dielectric materials of the gate dielectric layer 112 and the work function metal of the second work function tuning layer 114C, such that no adhesive layer can be formed in the opening 108 (described in more detail later). By not depositing an adhesive layer in the opening 108, ease of fabrication can be improved, especially in advanced semiconductor nodes with small feature sizes, as it can be difficult to deposit adhesive layer material in small spaces. In the second region (e.g., n-type region 50N), portions of the gate dielectric layer 112 surround each second nanostructure 66, and portions of the second work function tuning layer 114C fill the regions between the portions of the gate dielectric layer 112. In some embodiments, the second work function tuning layer 114C is formed to have approximately to approximately The thickness is within the range of [specific parameters]. The second work function tuning layer 114C is formed with a thickness less than approximately [specific value]. The thickness of the second work function tuning layer 114C may not allow the portions to merge. The second work function tuning layer 114C is formed to have a thickness greater than approximately... The thickness of the barrier layer 114B may have a negative impact on the threshold voltage of the resulting device. The barrier layer 114B may have a smaller thickness than the second work function tuning layer 114C.

[0077] The material of the first work function tuning layer 114A is different from the material of the second work function tuning layer 114C. As described above, the first work function tuning layer 114A can be formed of p-type work function metal (PWFM), and the second work function tuning layer 114C can be formed of n-type work function metal (NWFM). PWFM and NWFM are different. Furthermore, one or more materials of the barrier layer 114B are different from the materials of the first work function tuning layer 114A and the second work function tuning layer 114C.

[0078] exist Figure 19A and 19B In this process, a filler layer 114E is deposited on the second work function tuning layer 114C. Optionally, an adhesive layer 114D is formed between the filler layer 114E and the second work function tuning layer 114C. After formation, the gate electrode layer 114 includes a first work function tuning layer 114A, a barrier layer 114B, a second work function tuning layer 114C, an adhesive layer 114D, and a filler layer 114E.

[0079] The adhesive layer 114D comprises any acceptable material for promoting adhesion and preventing diffusion. For example, the adhesive layer 114D may be formed of a metal or a metal nitride, such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, etc., which may be deposited by ALD, CVD, PVD, etc.

[0080] The filler layer 114E comprises any acceptable low-resistivity material. For example, the filler layer 114E can be formed of metals such as tungsten, aluminum, cobalt, ruthenium, or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The filler layer 114E fills the remaining portion of the recess 106.

[0081] Although the barrier layer 114B is used to protect the first work function tuning layer 114A during processing, it may not significantly affect the electrical characteristics of the resulting device and may remain within a portion of the gate electrode layer 114 in the first region (e.g., p-type region 50P). For example, the barrier layer 114B may be thin enough not to significantly modify the work function of the gate electrode layer 114. In the first region (e.g., p-type region 50P), the barrier layer 114B is disposed between portions of the first work function tuning layer 114A and the second work function tuning layer 114C and physically separates them. Conversely, the second region (e.g., n-type region 50N) lacks both the first work function tuning layer 114A and the barrier layer 114B, such that the second work function tuning layer 114C and the gate dielectric layer 112 in the second region (e.g., n-type region 50N) are not separated by the barrier layer but are physically in contact. Therefore, in the second region (e.g., n-type region 50N), the material of the second work function tuning layer 114C can be continuously extended between the gate dielectric layer 112 and the adhesive layer 114D.

[0082] exist Figure 20A and Figure 20B In this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114 (these excess portions are above the top surfaces of the first ILD 104 and the gate separator 90), thereby forming the gate dielectric 122 and the gate electrode 124. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be utilized. The gate dielectric layer 112 has a portion remaining in the recess 106 when planarized (thus forming the gate dielectric 122). The gate electrode layer 114 has a portion remaining in the recess 106 when planarized (thus forming the gate electrode 124). Gate separator 90; CESL 102; First ILD 104; Gate dielectric 122 (e.g., interface layer 112A and high-k dielectric layer 112B, see Figure 19A and Figure 19B); and gate electrode 124 (e.g., first work function tuning layer 114A, barrier layer 114B, second work function tuning layer 114C, adhesive layer 114D, and filler layer 114E, see Figure 19A and Figure 19B The top surfaces of the gate dielectric 122 and gate electrode 124 are coplanar (within the range of process variations). The gate dielectric 122 and gate electrode 124 form the replacement gate of the resulting nanoFET. Each pair of corresponding gate dielectric 122 and gate electrode 124 can be collectively referred to as a “gate structure”. These gate structures each extend along the top surface, sidewalls, and bottom surface of the channel region 68 of the second nanostructure 66.

[0083] exist Figure 21A and Figure 21B In this configuration, the second ILD 134 is deposited over the gate separator 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, which can be deposited by any suitable method such as CVD or PECVD.

[0084] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity (compared to etching the second ILD 134).

[0085] exist Figure 22A and Figure 22B In this configuration, a gate contact 142 and a source / drain contact 144 are formed to contact the gate electrode 124 and the epitaxial source / drain region 98, respectively. The gate contact 142 is physically and electrically coupled to the gate electrode 124. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 98.

[0086] As an example of forming the gate contact 142 and the source / drain contact 144, the opening for the gate contact 142 is formed through the second ILD 134 and ESL 132, and the opening for the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in these openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) may be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 in the openings. The gate contact 142 and the source / drain contact 144 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in different cross sections to avoid short circuits.

[0087] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be: a silicide region formed of metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide silicon region formed of both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process (e.g., ALD, CVD, PVD, etc.). After the thermal annealing process, a cleaning process (e.g., wet cleaning) can be performed to remove any residual metal from the openings for the source / drain contacts 144, for example, from the surface of the metal-semiconductor alloy region 146. One or more materials of the source / drain contacts 144 can then be formed on the metal-semiconductor alloy region 146.

[0088] Figure 23A and Figure 23BThis is a view of a nanostructured FET according to some other embodiments. This embodiment is similar to... Figure 19A and Figure 19B In this embodiment, the difference is that the barrier layer 114B is a single, continuous layer of barrier material. For example, the barrier layer 114B can be a single, continuous layer of amorphous silicon or fluorine-free tungsten. In this embodiment, the variation in the concentration of residue 120 within the barrier layer 114B can be more gradual. For example, in Figure 19A and Figure 19B In one embodiment, the concentration of residue 120 can decrease abruptly at the third barrier sublayer 114B3, but... Figure 23A and Figure 23B In one embodiment, the concentration of residue 120 can be continuously reduced in the barrier layer 114B.

[0089] The embodiment offers several advantages. Including a second work function tuning layer 114C in both the first region (e.g., p-type region 50P) and the second region (e.g., n-type region 50N) allows tuning of the work function of the gate electrode 124 in both regions. A barrier layer 114B formed between the first work function tuning layer 114A and the second work function tuning layer 114C protects the first work function tuning layer 114A from metal diffusion during the deposition of the second work function tuning layer 114C, especially when the second work function tuning layer 114C is formed of a easily diffusing metal (e.g., aluminum). Therefore, the barrier layer 114B helps suppress modifications to the work function of the first work function tuning layer 114A during the deposition of the second work function tuning layer 114C. Consequently, the threshold voltage of the resulting device in the n-type region 50N and the p-type region 50P can be tuned more accurately.

[0090] In one embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer comprising an n-type work function metal, the n-type work function metal being different from the p-type work function metal; and a fill layer on the second work function tuning layer. In some embodiments of the device, the n-type work function metal comprises a metal element, and the barrier layer is a single continuous layer of barrier material having a lower portion adjacent to the first work function tuning layer and an upper portion adjacent to the second work function tuning layer, the upper portion of the barrier layer containing a higher concentration of residual metal element than the lower portion of the barrier layer. In some embodiments of the device, the n-type work function metal comprises a metal element, and the barrier layer comprises: a first layer; a second layer, located on the first layer, wherein the concentration of the metal element residue contained in the second layer is greater than the concentration of the metal element residue contained in the first layer; and an oxide layer, located between the first layer and the second layer, wherein the oxide layer is thinner than the first layer and the second layer. In some embodiments of the device, the first layer comprises a first barrier material, the oxide layer comprises an oxide of the first barrier material, and the second layer comprises a second barrier material, the second barrier material being different from the first barrier material. In some embodiments of the device, the first layer comprises a barrier material, the oxide layer comprises an oxide of the barrier material, and the second layer comprises a barrier material. In some embodiments of the device, the barrier layer comprises amorphous silicon. In some embodiments of the device, the barrier layer comprises fluorine-free tungsten. In some embodiments of the device, the thickness of the barrier layer is... to Within the range.

[0091] In one embodiment, a device includes: a first transistor comprising: a first channel region; a first gate dielectric layer on the first channel region; a p-type work function tuning layer on the first gate dielectric layer; a barrier layer on the p-type work function tuning layer; a first n-type work function tuning layer on the barrier layer, the first n-type work function tuning layer comprising a metal, wherein the concentration of the metal residue contained in the upper portion of the barrier layer is greater than the concentration of the metal residue contained in the lower portion of the barrier layer, the upper portion of the barrier layer is adjacent to the first n-type work function tuning layer, and the lower portion of the barrier layer is adjacent to the p-type work function tuning layer; and a first fill layer on the first n-type work function tuning layer; and a second transistor comprising: a second channel region; a second gate dielectric layer on the second channel region; a second n-type work function tuning layer on the second gate dielectric layer, the second n-type work function tuning layer comprising the metal; and a second fill layer on the second n-type work function tuning layer. In some embodiments of the device, the barrier layer comprises a single continuous layer of barrier material located between the p-type work function tuning layer and the first n-type work function tuning layer. In some embodiments of the device, the barrier layer comprises multiple layers of barrier material located between the p-type work function tuning layer and the first n-type work function tuning layer. In some embodiments of the device, the metal is aluminum.

[0092] In one embodiment, a method includes: depositing a gate dielectric layer having a first portion and a second portion, the first portion being deposited on a first channel region and the second portion being deposited on a second channel region; forming a first work function tuning layer on the first portion of the gate dielectric layer; forming a barrier layer on the first work function tuning layer; and depositing a second work function tuning layer on the barrier layer and on the second portion of the gate dielectric layer, the barrier layer suppressing modification of the first work function of the first work function tuning layer during the deposition of the second work function tuning layer. In some embodiments of the method, depositing the barrier layer includes depositing amorphous silicon via a CVD process performed using silane at a temperature of 275°C to 500°C and at a pressure of 3 Torr to 45 Torr, the barrier layer being deposited having to The thickness. In some embodiments of the method, the step of depositing the barrier layer includes depositing fluorine-free tungsten by an ALD process performed using tungsten chloride (V) and hydrogen at a temperature of 250°C to 550°C and at a pressure of 0.1 Torr to 60 Torr, wherein the barrier layer is deposited to have to The thickness. In some embodiments of the method, depositing the second work function tuning layer includes depositing metal, and a barrier layer inhibits the diffusion of the metal into the first work function tuning layer during the deposition of the second work function tuning layer. In some embodiments of the method, forming the first work function tuning layer includes depositing the first work function tuning layer on a first portion and a second portion of the gate dielectric layer, and wherein forming the barrier layer includes: depositing a barrier layer on the first work function tuning layer; and removing the barrier layer and portions of the first work function tuning layer to expose the second portion of the gate dielectric layer. In some embodiments of the method, depositing the barrier layer includes depositing a single continuous layer of barrier material. In some embodiments of the method, depositing the barrier layer includes: depositing a first barrier material; oxidizing the upper portion of the first barrier material; and depositing a second barrier material on the first barrier material after oxidizing the upper portion of the first barrier material. In some embodiments of the method, depositing the barrier layer includes: depositing a barrier material; oxidizing the upper portion of the barrier material; and depositing more barrier material after oxidizing the upper portion of the barrier material.

[0093] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0094] Example 1. A transistor gate structure, comprising:

[0095] Channel area;

[0096] A gate dielectric layer is located on the channel region;

[0097] A first work function tuning layer is located on the gate dielectric layer, and the first work function tuning layer contains a p-type work function metal.

[0098] A blocking layer is located on the first work function tuning layer;

[0099] A second work function tuning layer is located on the blocking layer. The second work function tuning layer comprises an n-type work function metal, which is different from the p-type work function metal.

[0100] A filling layer is located on the second work function tuning layer.

[0101] Example 2. The transistor gate structure according to Example 1, wherein the n-type work function metal comprises a metal element, and the barrier layer is a single continuous layer of barrier material having a lower portion near the first work function tuning layer and an upper portion near the second work function tuning layer, wherein the concentration of the metal element residue contained in the upper portion of the barrier layer is greater than the concentration of the metal element residue contained in the lower portion of the barrier layer.

[0102] Example 3. The transistor gate structure according to Example 1, wherein the n-type work function metal comprises a metal element, and the barrier layer comprises:

[0103] First layer;

[0104] A second layer, located on top of the first layer, wherein the concentration of the metal element residue contained in the second layer is greater than the concentration of the metal element residue contained in the first layer; and

[0105] An oxide layer is located between the first layer and the second layer, and the oxide layer is thinner than the first layer and the second layer.

[0106] Example 4. The transistor gate structure according to Example 3, wherein the first layer includes a first barrier material, the oxide layer includes an oxide of the first barrier material, and the second layer includes a second barrier material, the second barrier material being different from the first barrier material.

[0107] Example 5. The transistor gate structure according to Example 3, wherein the first layer comprises a barrier material, the oxide layer comprises an oxide of the barrier material, and the second layer comprises the barrier material.

[0108] Example 6. The transistor gate structure according to Example 1, wherein the barrier layer comprises amorphous silicon.

[0109] Example 7. The transistor gate structure according to Example 1, wherein the barrier layer comprises fluorine-free tungsten.

[0110] Example 8. The transistor gate structure according to Example 1, wherein the thickness of the barrier layer is in to Within the range.

[0111] Example 9. A transistor gate structure, comprising:

[0112] A first transistor, the first transistor comprising:

[0113] First trench area;

[0114] A first gate dielectric layer is located on the first channel region;

[0115] The p-type work function tuning layer is located on the first gate dielectric layer;

[0116] A blocking layer is located on the p-type work function tuning layer;

[0117] A first n-type work function tuning layer is located on the barrier layer. The first n-type work function tuning layer contains a metal. The concentration of the metal residue contained in the upper part of the barrier layer is greater than the concentration of the metal residue contained in the lower part of the barrier layer. The upper part of the barrier layer is close to the first n-type work function tuning layer, and the lower part of the barrier layer is close to the p-type work function tuning layer.

[0118] A first filling layer is located on the first n-type work function tuning layer; and

[0119] The second transistor includes:

[0120] Second trench area;

[0121] A second gate dielectric layer is located on the second channel region;

[0122] A second n-type work function tuning layer is located on the second gate dielectric layer, and the second n-type work function tuning layer includes the metal; and

[0123] The second filling layer is located on the second n-type work function tuning layer.

[0124] Example 10. The transistor gate structure of claim 9, wherein the barrier layer comprises a single continuous layer of barrier material located between the p-type work function tuning layer and the first n-type work function tuning layer.

[0125] Example 11. The transistor gate structure according to claim 9, wherein the blocking layer comprises multiple layers of blocking material located between the p-type work function tuning layer and the first n-type work function tuning layer.

[0126] Example 12. The transistor gate structure according to Example 9, wherein the metal is aluminum.

[0127] Example 13. A method comprising:

[0128] A gate dielectric layer is deposited, the gate dielectric layer having a first portion and a second portion, the first portion being deposited on a first channel region and the second portion being deposited on a second channel region;

[0129] A first work function tuning layer is formed on the first portion of the gate dielectric layer;

[0130] A blocking layer is formed on the first work function tuning layer; and

[0131] A second work function tuning layer is deposited on the barrier layer and on the second portion of the gate dielectric layer, the barrier layer suppressing modification of the first work function of the first work function tuning layer during the deposition of the second work function tuning layer.

[0132] Example 14. The method according to Example 13, wherein depositing the barrier layer comprises depositing amorphous silicon via a CVD process, the CVD process being performed using silane, the CVD process being performed at a temperature of 275°C to 500°C, the CVD process being performed at a pressure of 3 Torr to 45 Torr, and the barrier layer being deposited having to The thickness.

[0133] Example 15. The method according to Example 13, wherein the step of depositing the barrier layer includes depositing fluorine-free tungsten by an ALD process, the ALD process being performed using tungsten chloride (V) and hydrogen, the ALD process being performed at a temperature of 250°C to 550°C, the ALD process being performed at a pressure of 0.1 Torr to 60 Torr, and the barrier layer being deposited having to The thickness.

[0134] Example 16. The method according to Example 13, wherein depositing the second work function tuning layer includes depositing metal, and the barrier layer inhibits the diffusion of the metal into the first work function tuning layer during the deposition of the second work function tuning layer.

[0135] Example 17. The method according to Example 13, wherein forming the first work function tuning layer includes depositing the first work function tuning layer on the first portion and the second portion of the gate dielectric layer, and wherein forming the barrier layer includes:

[0136] Deposit the barrier layer on the first work function tuning layer; and

[0137] Remove portions of the blocking layer and the first work function tuning layer to expose the second portion of the gate dielectric layer.

[0138] Example 18. The method according to Example 17, wherein depositing the barrier layer comprises depositing a single continuous layer of barrier material.

[0139] Example 19. The method according to Example 17, wherein depositing the barrier layer comprises:

[0140] Deposit the first barrier material;

[0141] Oxidize the upper part of the first barrier material; and

[0142] After oxidizing the upper part of the first barrier material, a second barrier material is deposited on the first barrier material.

[0143] Example 20. The method according to Example 17, wherein depositing the barrier layer comprises:

[0144] Deposition barrier materials;

[0145] Oxidize the upper part of the barrier material; and

[0146] After oxidizing the upper part of the barrier material, more of the barrier material is deposited.

Claims

1. A transistor gate structure, comprising: Nanostructures; A gate dielectric layer is located on the nanostructure; A first work function tuning layer is located on the gate dielectric layer. The first work function tuning layer contains a p-type work function metal. The first work function tuning layer and the gate dielectric layer completely fill the region between the nanostructure. A blocking layer is located on the first work function tuning layer; A second work function tuning layer is located on the blocking layer. The second work function tuning layer comprises an n-type work function metal, which is different from the p-type work function metal. A filling layer is located on the second work function tuning layer.

2. The transistor gate structure according to claim 1, wherein, The n-type work function metal comprises a metal element, and the barrier layer is a single continuous layer of barrier material having a lower portion near the first work function tuning layer and an upper portion near the second work function tuning layer, wherein the concentration of the metal element residue contained in the upper portion of the barrier layer is greater than the concentration of the metal element residue contained in the lower portion of the barrier layer.

3. The transistor gate structure according to claim 1, wherein, The n-type work function metal comprises metallic elements, and the barrier layer comprises: First layer; A second layer, located on top of the first layer, wherein the concentration of the metal element residue contained in the second layer is greater than the concentration of the metal element residue contained in the first layer; and An oxide layer is located between the first layer and the second layer, and the oxide layer is thinner than the first layer and the second layer.

4. The transistor gate structure according to claim 3, wherein, The first layer includes a first barrier material, the oxide layer includes an oxide of the first barrier material, and the second layer includes a second barrier material that is different from the first barrier material.

5. The transistor gate structure according to claim 3, wherein, The first layer includes a barrier material, the oxide layer includes an oxide of the barrier material, and the second layer includes the barrier material.

6. The transistor gate structure according to claim 1, wherein, The barrier layer comprises amorphous silicon.

7. The transistor gate structure according to claim 1, wherein, The barrier layer comprises fluorine-free tungsten.

8. The transistor gate structure according to claim 1, wherein, The thickness of the barrier layer is in the range of 7 Å to 40 Å.

9. A transistor gate structure, comprising: A first transistor, the first transistor comprising: The first channel region includes nanostructures; A first gate dielectric layer is located on the nanostructure; A p-type work function tuning layer is located on the first gate dielectric layer, and the p-type work function tuning layer and the first gate dielectric layer completely fill the region between the nanostructure; A blocking layer is located on the p-type work function tuning layer; A first n-type work function tuning layer is located on the barrier layer. The first n-type work function tuning layer contains a metal. The concentration of the metal residue contained in the upper part of the barrier layer is greater than the concentration of the metal residue contained in the lower part of the barrier layer. The upper part of the barrier layer is close to the first n-type work function tuning layer, and the lower part of the barrier layer is close to the p-type work function tuning layer. A first filling layer is located on the first n-type work function tuning layer; and The second transistor includes: The second channel region includes nanostructures; A second gate dielectric layer is located on the nanostructure; A second n-type work function tuning layer is located on the second gate dielectric layer, and the second n-type work function tuning layer includes the metal; and The second filling layer is located on the second n-type work function tuning layer.

10. The transistor gate structure according to claim 9, wherein, The barrier layer comprises a single continuous layer of barrier material located between the p-type work function tuning layer and the first n-type work function tuning layer.

11. The transistor gate structure according to claim 9, wherein, The barrier layer comprises multiple layers of barrier material located between the p-type work function tuning layer and the first n-type work function tuning layer.

12. The transistor gate structure according to claim 9, wherein, The metal is aluminum.

13. A method for forming a transistor gate structure, comprising: A gate dielectric layer is deposited, the gate dielectric layer having a first portion and a second portion, the first portion being deposited on a nanostructure in a first channel region, and the second portion being deposited on a nanostructure in a second channel region. A first p-type work function tuning layer is deposited on the first portion of the gate dielectric layer, wherein the first p-type work function tuning layer and the first portion of the gate dielectric layer completely fill the region between the nanostructures of the first channel region. A barrier layer is deposited on the first p-type work function tuning layer; as well as A second n-type work function tuning layer is deposited on the barrier layer and on the second portion of the gate dielectric layer, the barrier layer suppressing modification of the first p-type work function of the first p-type work function tuning layer during the deposition of the second n-type work function tuning layer.

14. The method according to claim 13, wherein, Depositing the barrier layer includes depositing amorphous silicon via a CVD process performed using silane at a temperature of 275 °C to 500 °C and at a pressure of 3 Torr to 45 Torr, wherein the barrier layer is deposited to have a thickness of 7 Å to 40 Å.

15. The method according to claim 13, wherein, The step of depositing the barrier layer includes depositing fluorine-free tungsten by an ALD process, the ALD process being performed using tungsten chloride (V) and hydrogen, the ALD process being performed at a temperature of 250°C to 550°C, the ALD process being performed at a pressure of 0.1 Torr to 60 Torr, and the barrier layer being deposited to have a thickness of 7 Å to 40 Å.

16. The method according to claim 13, wherein, Depositing the second n-type work function tuning layer includes depositing metal, and the barrier layer inhibits the diffusion of the metal into the first p-type work function tuning layer during the deposition of the second n-type work function tuning layer.

17. The method according to claim 13, wherein, Forming the first p-type work function tuning layer includes depositing the first p-type work function tuning layer on the first and second portions of the gate dielectric layer, and wherein forming the barrier layer includes: Deposit the barrier layer on the first p-type work function tuning layer; and Remove portions of the blocking layer and the first p-type work function tuning layer to expose the second portion of the gate dielectric layer.

18. The method according to claim 17, wherein, Depositing the barrier layer involves depositing a single, continuous layer of barrier material.

19. The method of claim 17, wherein, Depositing the barrier layer includes: Deposit the first barrier material; Oxidize the upper part of the first barrier material; and After oxidizing the upper part of the first barrier material, a second barrier material is deposited on the first barrier material.

20. The method of claim 17, wherein, Depositing the barrier layer includes: Deposition barrier materials; Oxidize the upper part of the barrier material; and After oxidizing the upper part of the barrier material, more of the barrier material is deposited.

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