Display device

Abstract

In the TFT layer, a semiconductor layer, a first interlayer insulating film, a first wiring layer, a second interlayer insulating film, a second wiring layer, a third interlayer insulating film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film are sequentially stacked. A fourth interlayer insulating film (20a) is provided between the third wiring layer and the fourth wiring layer. The fourth interlayer insulating film (20a) is configured to cover at least one end on the display region side of the first side frame wiring (18h) and the second side frame wiring (18i) exposed from the first slit (Sa) formed on the first planarization film and the second planarization film (22a) in a region where the first side frame wiring (18h) and the second side frame wiring (18i) of the third wiring layer face each other in a top view.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In recent years, as a display device to replace a liquid crystal display device, a self-luminous organic EL display device using an organic electroluminescence (hereinafter also referred to as "EL") element has attracted attention. This organic EL display device includes, for example: a substrate; a thin film transistor (hereinafter also referred to as "TFT") layer provided on the substrate; an organic EL element layer provided on the TFT layer; and a sealing film provided so as to cover the organic EL element layer. Here, the organic EL element layer includes, for example, a plurality of organic EL elements arranged in a matrix. In addition, the sealing film includes a first inorganic sealing film provided so as to cover the organic EL element layer, an organic sealing film provided on the first inorganic sealing film, and a second inorganic sealing film provided on the first inorganic sealing film so as to cover the organic sealing film. Further, the organic EL element includes a first electrode provided on the TFT layer, an organic EL layer provided on the first electrode, and a second electrode provided on the organic EL layer.

[0003] For example, in Patent Document 1, a display device including a thin film sealing layer covering an organic light emitting element is disclosed. The thin film sealing layer has a laminated structure in which an inorganic film layer formed by a method such as CVD (chemical vapor deposition) and an organic film layer formed by a method such as an inkjet method are alternately arranged.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-86415 Summary of the Invention

[0007] Technical Problem to be Solved by the Present Invention

[0008] However, as in the display device disclosed in the above-mentioned Patent Document 1, in the case of forming an organic sealing film by an inkjet method, a barrier wall for blocking the ink that becomes the organic sealing film needs to be provided in a frame shape in the border area around the display area where a plurality of organic EL elements are arranged. In addition, in order to supply current to the organic EL elements, a second border wiring is provided in the border area of the organic EL display device. This border wiring is electrically connected to the power supply line constituting the TFT layer, and is connected to the first border wiring to which a high power supply voltage (ELVDD) is input and to the second electrode, and a low power supply voltage (ELVSS) is input. These first border wiring and second border wiring are arranged to cross the barrier wall in a state of being adjacent to each other around the display area and reach the terminal portion at the end of the border area. Here, a planarization film is provided on the first border wiring and the second border wiring, and a first electrode is provided on the planarization film. When the barrier wall and the planarization film are formed of the same material on the same layer, a resist pattern for patterning the first electrode metal film is formed thicker at the lower part of the side wall of the barrier wall. In this way, an unnecessary metal film remains between the first border wiring and the second border wiring, and therefore, there is a risk of short circuit between the first border wiring and the second border wiring.

[0009] The present invention has been completed in view of this point, and its object is to suppress short circuits between border wirings.

[0010] Solution to the problem

[0011] In order to achieve the above object, the display device according to the present invention is characterized in that it includes: a substrate substrate; a thin film transistor layer disposed on the substrate substrate, which is sequentially stacked with a semiconductor layer, a first interlayer insulating film, a first wiring layer, a second interlayer insulating film, a second wiring layer, a third interlayer insulating film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; a light emitting element layer disposed on the thin film transistor layer, which is sequentially stacked with a plurality of first electrodes, a common edge cover, a plurality of light emitting layers, and a common second electrode corresponding to a plurality of sub-pixels constituting a display area; a sealing film disposed to cover the light emitting element layer, which is sequentially stacked with a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a first barrier rib disposed in a frame area around the display area to surround the display area and overlapping with a peripheral end portion of the organic sealing film, separated from the first planarization film and the second planarization film across a first slit formed to penetrate the first planarization film and the second planarization film; a second barrier rib disposed in the frame area to surround the first barrier rib, separated from the first barrier rib across a second slit formed to penetrate the first planarization film and the second planarization film; a power supply line disposed in the display area as the fourth wiring layer, electrically connected to each of the first electrodes via a thin film transistor; a first frame wiring disposed in the frame area as the third wiring layer, electrically connected to the power supply line; a second frame wiring disposed in the frame area as the third wiring layer, electrically connected to the second electrode; and a first conductive layer disposed in the frame area on the same layer with the same material as the first electrode, overlapping with the second frame wiring across the first slit, electrically connecting the second frame wiring and the second electrode. A fourth interlayer insulating film is disposed between the third wiring layer and the fourth wiring layer, and the fourth interlayer insulating film is disposed to cover at least one end portion on the display area side of the first frame wiring and the second frame wiring exposed from the first slit in a region where the first frame wiring and the second frame wiring are opposite in a top view.

[0012] Advantages of the Invention

[0013] According to the present invention, the fourth interlayer insulating film disposed between the third wiring layer and the fourth wiring layer covers at least one end portion on the display area side of the first frame wiring and the second frame wiring exposed from the first slit in a region where the first frame wiring and the second frame wiring are opposite in a top view, so that short circuits between the frame wirings can be suppressed. Description of the Drawings

[0014] Figure 1It is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.

[0015] Figure 2 It is a plan view of a display area of an organic EL display device according to a first embodiment of the present invention.

[0016] Figure 3 It is along Figure 1 A cross-sectional view of a display area of the organic EL display device taken along line III-III in

[0017] Figure 4 It is an equivalent circuit diagram of a TFT layer constituting an organic EL display device according to a first embodiment of the present invention.

[0018] Figure 5 It is a cross-sectional view of an organic EL layer constituting an organic EL display device according to a first embodiment of the present invention.

[0019] Figure 6 It is along Figure 1 A cross-sectional view of a frame area of the organic EL display device taken along line VI-VI in

[0020] Figure 7 It is along Figure 1 A cross-sectional view of a frame area of the organic EL display device taken along line VII-VII in

[0021] Figure 8 It is a plan view of enlarging the area A in Figure 1

[0022] Figure 9 It is a plan view of a modification 1 of an organic EL display device according to a first embodiment of the present invention, and is a figure corresponding to Figure 8

[0023] Figure 10 It is a plan view of a modification 2 of an organic EL display device according to a first embodiment of the present invention, and is a figure corresponding to Figure 8

[0024] Figure 11 It is a plan view of a modification 3 of an organic EL display device according to a first embodiment of the present invention, and is a figure corresponding to Figure 8

[0025] Figure 12 It is a plan view of a modification 4 of an organic EL display device according to a first embodiment of the present invention, and is a figure corresponding to Figure 8

[0026] Figure 13 ​​​​​It is a top view of a terminal portion in a frame region of an organic EL display device according to a first embodiment of the present invention.

[0027] Figure 14 It is a Figure 13 cross-sectional view of a terminal portion in a frame region of an organic EL display device along line XIV-XIV.

[0028] Figure 15 It is a top view of a terminal portion in a frame region of a modified example 5 of an organic EL display device according to the first embodiment of the present invention.

[0029] Figure 16 It is a Figure 15 cross-sectional view of a terminal portion in a frame region of a modified example 5 of an organic EL display device along line XVI-XVI.

[0030] Figure 17 It is a top view of a terminal portion in a frame region of a modified example 6 of an organic EL display device according to the first embodiment of the present invention.

[0031] Figure 18 It is a Figure 17 cross-sectional view of a terminal portion in a frame region of a modified example 6 of an organic EL display device along line XVIII-XVIII.

[0032] Figure 19 It is a cross-sectional view of a frame region of an organic EL display device according to a second embodiment of the present invention, and is a figure corresponding to Figure 6 .

[0033] Figure 20 It is a cross-sectional view of a frame region of an organic EL display device according to a second embodiment of the present invention, and is a figure corresponding to Figure 7 .

[0034] Figure 21 It is a cross-sectional view of a frame region of a modified example of an organic EL display device according to a second embodiment of the present invention, and is a figure corresponding to Figure 20 . Detailed Embodiments

[0035] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. And the present invention is not limited to the following embodiments.

[0036] 《First Embodiment》

[0037] Figures 1 to 18 A first embodiment of a display device according to the present invention is shown. And in the following embodiments, as a display device having a light-emitting element layer, an organic EL display device having an organic EL element layer is exemplified. Here,Figure 1 is a top view showing a schematic configuration of the organic EL display device 50a of the present embodiment. In addition, Figure 2 is a top view of the display area D of the organic EL display device 50a. In addition, Figure 3 is along Figure 1 a cross-sectional view of the display area D of the organic EL display device 50a taken along line III-III in Figure 4 is an equivalent circuit diagram of the TFT layer 30 constituting the organic EL display device 50a. In addition, Figure 5 is a cross-sectional view of the organic EL layer 33 constituting the organic EL display device 50a. In addition, Figure 6 and Figure 7 are cross-sectional views of the frame area F of the organic EL display device 50a taken along lines VI-VI and VII-VII in Figure 1 . Figure 8 is a top view of magnifying the area A in Figure 1 . In addition, Figures 9 to 12 is a top view of modification examples 1 to 4 of the organic EL display device 50a, corresponding to the figure of Figure 8 . In addition, Figure 13 is a top view of the terminal portion T of the frame area F of the organic EL display device 50a. In addition, Figure 14 is a cross-sectional view of the terminal portion T of the frame area F of the organic EL display device 50a taken along line XIV-XIV in Figure 13 .

[0038] As shown in Figure 1 , the organic EL display device 50a includes, for example: a display area D, which is provided in a rectangular shape and displays an image; and a frame area F, which is provided in a rectangular frame shape around the display area D. And, in the present embodiment, a rectangular display area D is illustrated, but the rectangular shape also includes, for example, a shape with an arc-shaped side, a shape with an arc-shaped corner, a shape with a cut in a part of the side, etc., a substantially rectangular shape.

[0039] As shown in Figure 2 , a plurality of sub-pixels P are arranged in a matrix in the display area D. In addition, in the display area D, as shown in Figure 2 , for example, a sub-pixel P having a red light-emitting area Lr for red display, a sub-pixel P having a green light-emitting area Lg for green display, and a sub-pixel P having a blue light-emitting area Lb for blue display are arranged adjacent to each other. And, in the display area D, for example, one pixel is constituted by three adjacent sub-pixels P having a red light-emitting area Lr, a green light-emitting area Lg, and a blue light-emitting area Lb.

[0040] In the Figure 1In the upper right end portion, the terminal portion T is arranged to extend in one direction (the longitudinal direction in the figure). Further, in the frame region F, as Figure 1 shown, between the display region D and the terminal portion T, a bent portion B that can be bent, for example, 180° (U-shaped) with the longitudinal direction in the figure as the axis of bending is arranged to extend in one direction (the longitudinal direction in the figure). Further, as will be described later, on the terminal portion T, a plurality of terminals C are arranged along the extending direction of the terminal portion T (refer to Figure 13 ). Further, as Figure 1 and Figure 6 shown, in the frame region F, a groove G that is substantially C-shaped in plan view is arranged to penetrate through the first planarization film 19a and the second planarization film 22a in the first planarization film 19a and the second planarization film 22a to be described later. Here, as Figure 1 shown, the groove G is arranged to be substantially C-shaped with an opening on the terminal portion T side in plan view.

[0041] As Figure 3 shown, the organic EL display device 50a includes: a resin substrate layer 10 provided as a base substrate, a TFT layer 30 provided on the resin substrate layer 10, an organic EL element layer 35 provided as a light-emitting element layer on the TFT layer 30, and a sealing film 40 provided on the organic EL element layer 35.

[0042] The resin substrate layer 10 is made of, for example, polyimide resin or the like.

[0043] As Figure 3 shown, the TFT layer 30 includes an undercoat film 11 provided on the resin substrate layer 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b (refer to Figure 4 ), a plurality of third TFTs 9c, and a plurality of capacitors 9d. Further, as Figure 3 shown, the TFT layer 30 includes a first planarization film 19a, a fourth interlayer insulating film 20a, and a second planarization film 22a sequentially provided on each of the first TFTs 9a, each of the second TFTs 9b, each of the third TFTs 9c, and each of the capacitors 9d.

[0044] As Figure 3As shown, in the TFT layer 30, a semiconductor layer 12a and 12b, a first interlayer insulating film 13, gate electrodes 14a and 14b, and a lower conductive layer 14c (first wiring layer), a second interlayer insulating film 15, an upper conductive layer 16a (second wiring layer), a third interlayer insulating film 17, source electrodes 18a and 18c, and drain electrodes 18b and 18d (third wiring layer), a first planarization film 19a, a fourth interlayer insulating film 20a, a power line 21a, and a relay layer 21b (fourth wiring layer), and a second planarization film 22a are sequentially stacked on the resin substrate layer 10. Here, the first wiring layer to the fourth wiring layer are formed of, for example, a single-layer metal film such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), or a stacked metal film such as Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, Cu / Ti. In addition, the first wiring layer and the second wiring layer are preferably formed of the same material as each other. For example, they are formed of a molybdenum film having a thickness of about 200 nm. In addition, the third wiring layer and the fourth wiring layer are preferably formed of the same material as each other. For example, they are formed of a stacked metal film such as Ti / Al / Ti having a thickness of about 600 nm that can be etched with the same etching solution and etching gas. And, the third wiring layer and the fourth wiring layer are formed thicker than the first wiring layer and the second wiring layer.

[0045] And, in the present embodiment, a stacked structure in which the fourth interlayer insulating film 20a is provided on the first planarization film 19a is illustrated, but the fourth interlayer insulating film 20a may also be provided between the source electrodes 18a and 18c and the drain electrodes 18b and 18d (third wiring layer) and the first planarization film 19a. Here, when the fourth interlayer insulating film 20a is disposed on the first planarization film 19a, for example, when patterning the fourth wiring layer by dry etching, etching of the surface of the first planarization film 19a is suppressed, and contamination in the chamber can be suppressed. In addition, when the fourth interlayer insulating film is disposed between the third wiring layer and the first planarization film 19a, the fourth interlayer insulating film becomes a protective film for the third wiring layer when patterning the fourth wiring layer.

[0046] In the TFT layer 30, in the display area D, as Figure 2 and Figure 4 shown, a plurality of gate lines 14d are provided so as to extend parallel to each other in the horizontal direction in the figure. In addition, in the TFT layer 30, in the display area D, as Figure 2 and Figure 4 shown, a plurality of light emission control lines 14e are provided so as to extend parallel to each other in the horizontal direction in the figure. And, as Figure 2As shown, each light emission control line 14e is arranged adjacent to each gate line 14d. Further, in the TFT layer 30, in the display area D, as Figure 2 and Figure 4 shown, a plurality of source lines 18f are arranged so as to extend parallel to each other in the vertical direction in the figure. Further, as Figure 1 shown, in the TFT layer 30, in the display area D, the power supply line 21a is arranged in a lattice shape. Further, as Figure 4 shown, in the TFT layer 30, in each sub-pixel P, a first TFT 9a, a second TFT 9b, a third TFT 9c, and a capacitor 9d are respectively arranged.

[0047] The undercoat film 11 is composed of, for example, a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.

[0048] As Figure 4 shown, the first TFT 9a is electrically connected to the corresponding gate line 14d, source line 18f, and second TFT 9b in each sub-pixel P. Further, as Figure 3 shown, the first TFT 9a includes a semiconductor layer 12a, a first interlayer insulating film 13, a gate electrode 14a, a second interlayer insulating film 15, a third interlayer insulating film 17, and a source electrode 18a and a drain electrode 18b which are sequentially arranged on the undercoat film 11. Here, as Figure 3 shown, the semiconductor layer 12a is arranged in an island shape on the undercoat film 11 and has a channel region, a source region, and a drain region, as will be described later. Further, the semiconductor layer 12a and the semiconductor layer 12b described later are formed of, for example, a low-temperature polycrystalline silicon film or an oxide semiconductor film such as In-Ga-Zn-O. Further, as Figure 3 shown, the first interlayer insulating film 13 is arranged so as to cover the semiconductor layer 12a to serve as a gate insulating film. Further, as Figure 3 shown, the gate electrode 14a is arranged on the first interlayer insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. Further, as Figure 3 shown, the second interlayer insulating film 15 and the third interlayer insulating film 17 are sequentially arranged so as to cover the gate electrode 14a. Further, as Figure 3 shown, the source electrode 18a and the drain electrode 18b are arranged so as to be separated from each other on the third interlayer insulating film 17. Further, as Figure 3As shown, the source electrode 18a and the drain electrode 18b are electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively, through the respective contact holes formed in the stacked film of the gate insulating film 13, the second interlayer insulating film 15, and the third interlayer insulating film 17. Further, the first interlayer insulating film 13, the second interlayer insulating film 15, the third interlayer insulating film 17, and the fourth interlayer insulating film 20a described later are each formed of a single-layer film or a stacked film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.

[0049] As Figure 4 shown, the second TFT 9b is electrically connected to the corresponding first TFT 9a, the power supply line 21a, and the third TFT 9c in each sub-pixel P. Further, the second TFT 9b has substantially the same structure as the first TFT 9a and the third TFT 9c described later.

[0050] As Figure 4 shown, the third TFT 9c is electrically connected to the corresponding second TFT 9b, the power supply line 21a, and the light emission control line 14e in each sub-pixel P. Further, as Figure 3 shown, the third TFT 9c includes a semiconductor layer 12b, a first interlayer insulating film 13, a gate electrode 14b, a second interlayer insulating film 15, a third interlayer insulating film 17, and a source electrode 18c and a drain electrode 18d, which are sequentially provided on the undercoat film 11. Here, as Figure 3 shown, the semiconductor layer 12b is provided in an island shape on the undercoat film 11 and has a channel region, a source region, and a drain region, similarly to the semiconductor layer 12a. Further, as Figure 3 shown, the first interlayer insulating film 13 is provided so as to cover the semiconductor layer 12b to serve as a gate insulating film. Further, as Figure 3 shown, the gate electrode 14b is provided on the first interlayer insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. Further, as Figure 3 shown, the second interlayer insulating film 15 and the third interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14b. Further, as Figure 3 shown, the source electrode 18c and the drain electrode 18d are provided so as to be separated from each other on the third interlayer insulating film 17. Further, as Figure 3 shown, the source electrode 18c and the drain electrode 18d are electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively, through the respective contact holes formed in the stacked film of the first interlayer insulating film 13, the second interlayer insulating film 15, and the third interlayer insulating film 17.

[0051] Further, in the present embodiment, the top-gate type first TFT 9a, second TFT 9b, and third TFT 9c are illustrated, but the first TFT 9a, second TFT 9b, and third TFT 9c may also be bottom-gate type.

[0052] As Figure 4 shown, the capacitor 9d is electrically connected to the corresponding first TFT 9a and the power supply line 21a in each sub-pixel P. Here, as Figure 3 shown, the capacitor 9d includes: a lower conductive layer 14c formed of the same material on the same layer as the gate electrode 14a, etc.; a second interlayer insulating film 15 provided so as to cover the lower conductive layer 14c; and an upper conductive layer 16a provided on the second interlayer insulating film 15 so as to overlap with the lower conductive layer 14c. Further, the upper conductive layer 16a is electrically connected to the power supply line 21a via a contact hole (not shown) formed in the third interlayer insulating film 17, the first planarization film 19a, and the fourth interlayer insulating film 20a.

[0053] The first planarization film 19a, the second planarization film 22a, and the edge mask 32a described later are made of an organic resin material such as polyimide resin or acrylic resin, for example.

[0054] The organic EL element layer 35 is composed of a plurality of organic EL elements arranged in a matrix. As Figure 3 shown, it includes a plurality of first electrodes 31a, edge masks 32a, a plurality of organic EL layers 33, and second electrodes 34 sequentially provided on the TFT layer 30.

[0055] As Figure 3 shown, the plurality of first electrodes 31a are arranged in a matrix on the second planarization film 22a so as to correspond to the plurality of sub-pixels P. Here, as Figure 3 shown, the first electrode 31a is electrically connected to the drain electrode 18d of each third TFT 9c via a contact hole formed in the first planarization film 19a and the fourth interlayer insulating film 20a, and a contact hole formed in the relay layer 21b and the second planarization film 22a. In addition, the first electrode 31a has a function of injecting holes into the organic EL layer 33. Further, in order to improve the efficiency of injecting holes into the organic EL layer 33, it is more preferable that the first electrode 31a is formed of a material having a large work function. Here, as the material constituting the first electrode 31a, for example, metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), tin (Sn), etc. can be cited. In addition, the material constituting the first electrode 31a can also be, for example, astatine (At) / astatine oxide (AtO 2alloys such as. Moreover, the material constituting the first electrode 31a can also be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), etc. In addition, the first electrode 31a can also be formed by laminating multiple layers made of the above materials. And, as a compound material with a large work function, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. can be cited.

[0056] As Figure 3 shown, the edge mask 32a is arranged in a lattice pattern in such a way as to be shared by a plurality of sub-pixels P and to cover the peripheral ends of the respective first electrodes 31a.

[0057] As Figure 3 shown, a plurality of organic EL layers 33 are arranged on the respective first electrodes 31a and are arranged in a matrix corresponding to the plurality of sub-pixels P. Here, as Figure 5 shown, each organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5 sequentially provided on the first electrode 31a.

[0058] The hole injection layer 1 is also called an anode buffer layer and has the function of making the energy levels of the first electrode 31a and the organic EL layer 33 close and improving the hole injection efficiency from the first electrode 31a to the organic EL layer 33. Here, as the material constituting the hole injection layer 1, for example, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylenealkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, etc. can be cited.

[0059] The hole transport layer 2 has the function of improving the hole transport efficiency from the first electrode 31a to the organic EL layer 33. Here, as the material constituting the hole transport layer 2, for example, porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly(p-phenylene vinylene), polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolinone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, etc. can be cited.

[0060] The light-emitting layer 3 is a region where holes and electrons are respectively injected from the first electrode 31a and the second electrode 34 when a voltage is applied between the first electrode 31a and the second electrode 34, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Moreover, examples of the material constituting the light-emitting layer 3 include: metal-oxide cluster compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenyl ethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, distyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly(p-phenylene vinylene), polysilane, etc.

[0061] The electron transport layer 4 has a function of efficiently transporting electrons to the light-emitting layer 3. Here, examples of the material constituting the electron transport layer 4 include, as organic compounds: oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenzoquinone derivatives, fluorenone derivatives, silole derivatives, metal-oxide cluster compounds (metal oxynoid compounds), etc.

[0062] The electron injection layer 5 has a function of making the energy levels of the second electrode 34 and the organic EL layer 33 closer and improving the efficiency of injecting electrons from the second electrode 34 into the organic EL layer 33. Through this function, the driving voltage of each organic EL element constituting the organic EL element layer 35 can be reduced. Also, the electron injection layer 5 is also called a cathode buffer layer. Here, examples of the material constituting the electron injection layer 5 include inorganic base compounds such as lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), barium fluoride (BaF 2 ), etc., and aluminum oxide (Al 2 O 3 ), strontium oxide (SrO), etc.

[0063] As Figure 3As shown, the second electrode 34 is provided to cover each organic EL layer 33 and the edge cover 32a, such that they are shared by a plurality of sub-pixels P. In addition, the second electrode 34 has a function of injecting electrons into the organic EL layer 33. Further, in order to improve the electron injection efficiency into the organic EL layer 33, the second electrode 34 is more preferably made of a material with a small work function. Here, examples of the material constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), lithium fluoride (LiF), etc. In addition, the second electrode 34 may also be formed of alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO 2 ), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc. In addition, the second electrode 34 may also be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), etc. In addition, the second electrode 34 may also be formed by laminating a plurality of layers made of the above materials. And, examples of the material with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0064] As Figure 3 shown, the sealing film 40 includes a first inorganic sealing film 36, an organic sealing film 37, and a second inorganic sealing film 38 that are provided to cover the second electrode 34 and are sequentially laminated on the second electrode 34, and has a function of protecting each organic EL layer 33 of the organic EL element layer 35 from the influence of moisture and oxygen. Here, the first inorganic sealing film 36 and the second inorganic sealing film 38 are made of inorganic insulating films such as silicon nitride films, silicon oxide films, silicon oxynitride films, etc., for example. In addition, the organic sealing film 37 is made of organic resin materials such as acrylic resins, epoxy resins, silicone resins, polyurea resins, parylene resins, polyimide resins, polyamide resins, etc., for example.

[0065] In addition, as Figure 1 shown, the organic EL display device 50a includes, in the border area F: a first barrier wall Wa provided in a frame shape outside the trench G and a second barrier wall Wb provided in a frame shape around the first barrier wall Wa.

[0066] As Figure 6 and Figure 7As shown, the first barrier wall Wa includes a lower resin layer 22b formed of the same material as the second planarization film 22a on the same layer, and an upper resin layer 32b formed of the same material as the edge cover 32a on the same layer. In addition, as Figure 6 and Figure 7 shown, the first barrier wall Wa is provided so as to be separated from the first planarization film 19a and the second planarization film 22a of the display region D with the first slit Sa therebetween, and the first slit Sa is formed in a frame shape so as to penetrate the first planarization film 19a and the second planarization film 22a on the first planarization film 19a and the second planarization film 22a. Further, the first barrier wall Wa is provided so as to overlap with the peripheral end portion of the organic sealing film 37 of the sealing film 40, and is configured to suppress the diffusion of the ink of the organic sealing film 37 of the sealing film 40.

[0067] As Figure 6 and Figure 7 shown, the second barrier wall Wb includes a lower resin layer 19b formed of the same material as the first planarization film 19a on the same layer, a middle resin layer 22c formed of the same material as the second planarization film 22a on the same layer, and an upper resin layer 32c formed of the same material as the edge cover 32a on the same layer. In addition, as Figure 6 and Figure 7 shown, the second barrier wall Wb is provided so as to be separated from the first barrier wall Wa with the second slit Sb therebetween, and the second slit Sb is formed in a frame shape so as to penetrate the first planarization film 19a (lower resin layer 19b) and the second planarization film 22a (middle resin layer 22c) on the first planarization film 19a (lower resin layer 19b) and the second planarization film 22a (middle resin layer 22c).

[0068] In addition, as Figure 1 shown, the organic EL display device 50a includes a first frame wiring 18h in the frame region F, and the first frame wiring 18h is provided as the above-described third wiring layer, extends wide in the opening portion of the groove G, extends linearly inside the groove G on the display region D side, and extends toward the terminal portion T at both end portions on the side opposite to the display region D. Here, the first frame wiring 18h is configured to be electrically connected to the power supply line 21a on the display region D side in the frame region F, and a high voltage (ELVDD) is input to the terminal portion T.

[0069] In addition, as Figure 1 shown, the organic EL display device 50a includes a second frame wiring 18i in the frame region F, and the second frame wiring 18i is provided in a substantially C shape as the above-described third wiring layer outside the groove G, and both end portions extend toward the terminal portion T. Here, as Figure 6As shown, the second frame wiring 18i is configured to be electrically connected to the second electrode 34 via the first conductive layer 31b formed in the trench G, and a low power supply voltage (ELVSS) is input to the terminal portion T. It should be noted that, as Figure 6 shown, the first conductive layer 31b is provided to be formed of the same material as the first electrode 31a in the same layer, and in the frame region F, it overlaps with the second frame wiring 18i across the first slit Sa to electrically connect the second frame wiring 18i and the second electrode 34.

[0070] In a plan view, in a region where the first frame wiring 18h and the second frame wiring 18i face each other (refer to the region in Figure 1 ), as Figure 8 shown, the fourth interlayer insulating film 20a (the shaded portion in the figure) is provided so as to cover the end portion of the second frame wiring 18i exposed from the first slit Sa and the first frame wiring 18h.

[0071] In addition, in the present embodiment, although the fourth interlayer insulating film 20a covering the end portion of the second frame wiring 18i exposed from the first slit Sa and the entire first frame wiring 18h is illustrated, the fourth interlayer insulating film 20a may also be the following fourth interlayer insulating films 20aa (modification example 1), 20ab (modification example 2), 20ac (modification example 3), 20ad (modification example 4), etc. That is, in a region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view, as long as the fourth interlayer insulating film 20a is provided so as to cover at least one end portion on the display region D side of the first frame wiring 18h and the second frame wiring 18i exposed from the first slit Sa, a short circuit between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0072] (Modification example 1)

[0073] In a region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view, as Figure 9 shown, the fourth interlayer insulating film 20a is provided so as to cover the entire first frame wiring 18h exposed from the first slit Sa.

[0074] (Modification example 2)

[0075] In a region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view, as Figure 10 shown, the fourth interlayer insulating film 20ab is provided so as to cover the end portions on the display region D side of the first frame wiring 18h and the second frame wiring 18i exposed from the first slit Sa. Here, in the fourth interlayer insulating film 20ab, as Figure 10As shown, at the lower part of the side wall of the first slit Sa, since the interval between the first frame wiring 18h and the second frame wiring 18i can be obtained (the two arrowheads in the figure), short - circuiting between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0076] (Modification Example 3)

[0077] In the region where the first frame wiring 18h and the second frame wiring 18i face each other in a top view, as Figure 11 shown, the fourth interlayer insulating film 20ac is provided so as to cover the end portion on the display region D side of the first frame wiring 18h exposed from the first slit Sa. Here, in the fourth interlayer insulating film 20ac, as Figure 11 shown, at the lower part of the side wall of the first slit Sa, since the interval between the first frame wiring 18h and the second frame wiring 18i can be obtained (the two arrowheads in the figure), short - circuiting between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0078] (Modification Example 4)

[0079] In the region where the first frame wiring 18h and the second frame wiring 18i face each other in a top view, as Figure 10 shown, the fourth interlayer insulating film 20ad is provided so as to cover the end portion on the display region D side of the second frame wiring 18i exposed from the first slit Sa. Here, in the fourth interlayer insulating film 20ad, as Figure 12 shown, at the lower part of the side wall of the first slit Sa, since the interval between the first frame wiring 18h and the second frame wiring 18i can be obtained (the two arrowheads in the figure), short - circuiting between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0080] According to Modification Examples 1 to 4, the first planarization film 19a under the second planarization film 22a is not covered by the fourth interlayer insulating films 20aa, 20ab, 20ac, and 20ad, and exhaust gas can be efficiently discharged when forming the first planarization film 19a.

[0081] In addition, in the present embodiment and the above-described modification examples 1 to 4, the fourth interlayer insulating film 20a is illustrated as being provided so as to cover at least one end portion on the display region D side of the first frame wiring 18h and the second frame wiring 18i exposed from the first slit Sa. However, the fourth interlayer insulating film 20a may be provided so as to cover the entire first frame wiring 18h exposed from the second slit Sb, or may be provided so as to cover the end portion on the side opposite to the display region D of the second frame wiring 18i exposed from the second slit Sb. That is, the fourth interlayer insulating film 20a only needs to be provided so as to cover not only at least one end portion on the display region D side of the first frame wiring 18h and the second frame wiring 18i exposed from the first slit Sa, but also at least one end portion on the side opposite to the display region D of the first frame wiring 18h and the second frame wiring 18i exposed from the second slit Sb. Here, the first slit Sa and the second slit Sb may be formed on the laminated film of the first planarization film 19a and the second planarization film 22a, may be formed on the second planarization film 22a covering the first planarization film 19a, or may be formed on the planarization film that exposes the end portion of the second frame wiring 18i and the first frame wiring 18h in the second planarization film 22a covering the first planarization film 19a.

[0082] In addition, as Figure 13 shown, the organic EL display device 50a includes a plurality of terminals C arranged in two columns in the extending direction of the terminal portion T in the terminal portion T of the frame region F.

[0083] As Figure 13 and Figure 14 shown, the terminal C includes: a first terminal electrode 18t, which is provided as the above-described third wiring layer and is electrically connected to the gate line 14d, the light emission control line 14e, the source line 18f, the first frame wiring 18h, the second frame wiring 18i, etc.; and a second terminal electrode 21t, which is provided as the above-described fourth wiring layer and is electrically connected to the first terminal electrode 18t.

[0084] Here, as Figure 13 and Figure 14 shown, a terminal first opening Mta for exposing the contact portion of the first terminal electrode 18t is formed on the first planarization film 19c provided on the first terminal electrode 18t. And the first planarization film 19c is formed of the same material as the first planarization film 19a of the display region D in the same layer.

[0085] In addition, as Figure 13 and Figure 14As shown, a terminal second opening portion Mtb exposing the contact portion of the second terminal electrode 21t is formed on a second planarization film 22d provided on the second terminal electrode 21t. Further, the second planarization film 22d is formed of the same material as the second planarization film 22a in the display region D and is formed on the same layer.

[0086] In addition, as Figure 13 and Figure 14 shown, a terminal third opening portion Mtc is formed on a fourth interlayer insulating film 20a provided between the first planarization film 19c and the second planarization film 22d so as to overlap with the second terminal electrode 21t. It should be noted that, as Figure 3 and Figure 14 shown, the periphery of the terminal third opening portion Mtc is disposed outside the peripheries of the terminal first opening portion Mta and the terminal second opening portion Mtb.

[0087] As Figure 14 shown, the second terminal electrode 21t contacts the first terminal electrode 18t via the terminal first opening portion Mta, and is electrically connected to the counter electrode 61 of the flexible printed circuit (hereinafter also referred to as "FPC") 65 via an anisotropic conductive film (hereinafter also referred to as "ACF") 70. And, as Figure 14 shown, the FPC 65 includes a flexible circuit board main body 60 and a counter electrode 61 provided on the surface of the FPC main body 60.

[0088] In addition, in the present embodiment, in the terminal portion T, an organic EL display device 50a in which the periphery of the terminal third opening portion Mtc is disposed outside the peripheries of the terminal first opening portion Mta and the terminal second opening portion Mtb is illustrated, but it may also be an organic EL display device 50aa (modification example 5) and 50ab (modification example 6) as described below. Here, Figure 15 is a plan view of the terminal portion T of the organic EL display device 50aa which is a modification example 5 of the organic EL display device 50a. In addition, Figure 16 is a cross-sectional view of the terminal portion T of the organic EL display device 50aa along the XVI-XVI line in Figure 15 . In addition, Figure 17 is a plan view of the terminal portion T of the organic EL display device 50ab which is a modification example 6 of the organic EL display device 50a. In addition, Figure 18 is a cross-sectional view of the terminal portion T of the organic EL display device 50ab along the XVIII-XVIII line in Figure 17 .

[0089] (Modification example 5)

[0090] At the end T of the organic EL display device 50aa, as Figure 15 and Figure 16 shown, the terminal C includes a first terminal electrode 18ta corresponding to the above-mentioned first terminal electrode 18t and a second terminal electrode 21ta corresponding to the above-mentioned second terminal electrode 21t.

[0091] Here, as Figure 15 and Figure 16 shown, a terminal first opening Mta that exposes the contact portion of the first terminal electrode 18ta is formed on the first planarization film 19ca provided on the first terminal electrode 18ta. And the first planarization film 19ca is formed of the same material as the first planarization film 19a in the display region D on the same layer.

[0092] In addition, as Figure 15 and Figure 16 shown, a terminal second opening Mtb that exposes the contact portion of the second terminal electrode 21ta is formed on the second planarization film 22da provided on the second terminal electrode 21ta. And the second planarization film 22da is formed of the same material as the second planarization film 22a in the display region D on the same layer. In addition, as Figure 15 and Figure 16 shown, the terminal second opening Mtb is provided outside the terminal first opening Mta so as not to overlap the terminal first opening Mta in a top view.

[0093] In addition, as Figure 15 and Figure 16 shown, a terminal third opening Mtc is formed on the fourth interlayer insulating film 20ae provided between the first planarization film 19ca and the second planarization film 22da so as to include the terminal first opening Mta and the terminal second opening Mtb in a top view.

[0094] As Figure 16 shown, the second terminal electrode 21ta contacts the first terminal electrode 18ta via the terminal first opening Mta and is electrically connected to the opposing electrode 61 of the FPC 65 via the ACF 70. In addition, as Figure 15 shown, the second terminal electrode 21ta is provided to include the terminal third opening Mtc and its periphery in a top view.

[0095] In the organic EL display device 50aa configured as described above, since the film thickness of the ACF 70 is thinner than that of the organic EL display device 50a, contact failure can be suppressed, and thus the yield of the mounting process can be improved.

[0096] (Modification Example 6)

[0097] At the end T of the organic EL display device 50ab, as Figure 17 and Figure 18 shown, the terminal C includes a first terminal electrode 18tb corresponding to the above-mentioned first terminal electrode 18t and a second terminal electrode 21tb corresponding to the above-mentioned second terminal electrode 21t.

[0098] Here, as Figure 17 and Figure 18 shown, a terminal first opening Mta that exposes the contact portion of the first terminal electrode 18ta is formed on the first planarization film 19cb provided on the first terminal electrode 18tb. Moreover, the first planarization film 19cb and the first planarization film 19a in the display region D are formed of the same material on the same layer.

[0099] In addition, as Figure 17 and Figure 18 shown, a terminal second opening Mtb that exposes the contact portion of the second terminal electrode 21ta is formed on the second planarization film 22da provided on the second terminal electrode 21ta. In addition, as Figure 17 and Figure 18 shown, the terminal second opening Mtb is provided outside the terminal first opening Mta so as not to overlap the terminal first opening Mta in a top view. Moreover, the first terminal electrode 18tb has a substantially same structure as the above-mentioned first terminal electrode 18t, and as Figure 17 and Figure 18 shown, it is set to overlap the terminal second opening Mtb in a top view.

[0100] In addition, as Figure 17 and Figure 18 shown, a terminal third opening Mtc is formed on the fourth interlayer insulating film 20ae provided between the first planarization film 19ca and the second planarization film 22da so as to include the terminal first opening Mta and the terminal second opening Mtb in a top view.

[0101] As Figure 18 shown, the second terminal electrode 21tb contacts the first terminal electrode 18tb via the terminal first opening Mta and is electrically connected to the opposing electrode 61 of the FPC 65 via the ACF 70. In addition, as Figure 17 shown, the second terminal electrode 21tb is set to include the terminal third opening Mtc and its periphery in a top view.

[0102] In the organic EL display device 50ab configured as described above, since the film thickness of the ACF 70 is thinner than that of the organic EL display device 50a, poor contact can be suppressed, and thus the yield of the mounting process can be improved. Further, in the organic EL display device 50ab configured as described above, each terminal C is formed by laminating the first terminal electrode 18tb of the relatively thick third wiring layer and the second terminal electrode 21tb of the relatively thick fourth wiring layer. Therefore, rigidity can be ensured even after the glass substrate is peeled off from the resin substrate layer 10, and the yield of the mounting process can be improved.

[0103] In the above-described organic EL display device 50a, in each sub-pixel P, a gate signal is input to the first TFT 9a through the gate line 14d, the first TFT 9a becomes conductive, and a predetermined voltage corresponding to the source signal is written to the gate electrode 14b of the second TFT 9b and the capacitor 9d via the source line 18f. When a light emission control signal is input to the third TFT 9c through the light emission control line 14e, the third TFT 9c becomes conductive, and a current corresponding to the gate voltage of the second TFT 9b is supplied from the power supply line 21a to the organic EL layer 33, so that the light emitting layer 3 of the organic EL layer 33 emits light to perform image display. Further, in the organic EL display device 50a, even when the first TFT 9a becomes non-conductive, the gate voltage of the second TFT 9b is held by the capacitor 9d. Therefore, the light emission of the light emitting layer 3 is maintained in each sub-pixel P until the gate signal of the next frame is input.

[0104] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. The method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer forming step, an organic EL element layer forming step, a sealing film forming step, and a mounting step.

[0105] <TFT layer forming step>

[0106] For example, a bottom coating film 11, a first TFT 9a, a second TFT 9b, a third TFT 9c, a capacitor 9d, a first planarization film 19a, a fourth interlayer insulating film 20a, a power supply line 21a, a second planarization film 22a, etc. are formed on the surface of the resin substrate layer 10 formed on a glass substrate by a known method, thereby forming a TFT layer 30.

[0107] <organic EL element layer forming step>

[0108] On the second planarization film 22a of the TFT layer 30 formed in the above-described TFT layer forming step, a first electrode 31a, an edge mask 32a, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emitting layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 34 are formed by a known method, thereby forming an organic EL element layer 35.

[0109] <Sealing film formation process>

[0110] First, on the surface of the substrate on which the organic EL element layer 35 is formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD method using a mask, thereby forming a first inorganic sealing film 36.

[0111] Next, for example, by an inkjet method, an organic resin material such as an acrylic resin is formed on the surface of the substrate on which the first inorganic sealing film 36 is formed, thereby forming an organic sealing film 37.

[0112] Then, for the substrate on which the organic sealing film 37 is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD method using a mask, thereby forming a second inorganic sealing film 38, and thus a sealing film 40 is formed.

[0113] Then, after a protective sheet (not shown) is pasted on the surface of the substrate on which the sealing film 40 is formed, a laser is irradiated from the glass substrate side of the resin substrate layer 10, thereby peeling the glass substrate from the lower surface of the resin substrate layer 10. Further, a protective sheet (not shown) is pasted on the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled.

[0114] <Mounting process>

[0115] First, for the protective sheet pasted on the surface of the sealing film 40 in the above-mentioned sealing film formation process, the protective sheet is locally removed by irradiating a laser, for example, to expose each terminal C of the terminal portion T.

[0116] Then, the ACF 70 is temporarily fixed on each terminal C of the terminal portion T.

[0117] Further, after the relative electrodes 61 of each terminal C of the terminal portion T and the FPC 65 are aligned so as to overlap via the ACF 70, the FPC 65 is pressed by a crimping tool, and the FPC 65 is mounted on the terminal portion T.

[0118] As described above, the organic EL display device 50a of the present embodiment can be manufactured.

[0119] As described above, in the organic EL display device 50a according to the present embodiment, the fourth interlayer insulating film 20a provided between the first planarization film 19a and the power supply line 21a covers the end portion of the second frame wiring 18i and the first frame wiring 18h exposed from the first slit Sa and the second slit Sb in a region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view. Therefore, even if it is assumed that the metal film of the first electrode 31a remains between the first frame wiring 18h and the second frame wiring 18i at the lower part of each side wall of the first slit Sa and the second slit Sb, since the first frame wiring 18h and the second frame wiring 18i are covered with the fourth interlayer insulating film 20a in the region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view, short circuit between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0120] In addition, in the organic EL display device 50a according to the present embodiment, each terminal C of the terminal portion T is formed by laminating the first terminal electrode 18t of the thicker third wiring layer and the second terminal electrode 21t of the thicker fourth wiring layer. Therefore, rigidity can be ensured even after the glass substrate is peeled off from the resin substrate layer 10, and the yield of the mounting process can be improved.

[0121] <<Second Embodiment>>

[0122] Figures 19 to 21 The second embodiment of the display device of the present invention is shown. Here, Figure 19 and Figure 20 are cross-sectional views of the frame region F of the organic EL display device 50b of the present embodiment, and are equivalent to Figure 6 and Figure 7 in the above-described first embodiment. In addition, Figure 21 is a cross-sectional view of the frame region F of the organic EL display device 50ba which is a modified example of the organic EL display device 50b, and is equivalent to Figure 20 . And in the following respective embodiments, the same reference numerals are assigned to the same parts as Figures 1 to 18 , and detailed description thereof is omitted.

[0123] In the above-described first embodiment, the organic EL display device 50a in which no other metal film is laminated on the first frame wiring 18h and the second frame wiring 18i is exemplified. However, in the present embodiment, the organic EL display device 50b in which other metal films are laminated on the first frame wiring 18h and the second frame wiring 18i is exemplified.

[0124] Similar to the organic EL display device 50a of the above-described first embodiment, the organic EL display device 50b includes a display region D provided in a rectangular shape and a frame region F provided in a frame shape around the display region D.

[0125] The organic EL display device 50b, like the organic EL display device 50a of the above-described first embodiment, includes: a resin substrate layer 10; a TFT layer 30 provided on the resin substrate layer 10; an organic EL element layer 35 as a light-emitting element provided on the TFT layer 30; and a sealing film 40 provided so as to cover the organic EL element layer 35.

[0126] The organic EL display device 50b, like the organic EL display device 50a of the above-described first embodiment, includes, in the border area F: a first barrier wall Wa provided in a frame shape outside the trench G and a second barrier wall Wb provided in a frame shape around the first barrier wall Wa.

[0127] The organic EL display device 50b, like the organic EL display device 50a of the above-described first embodiment, includes, in the border area F, a first border wiring 18h mainly provided in a part of the opening of the trench G and a second border wiring 18i provided substantially in a C shape outside the trench G.

[0128] As Figure 19 shown, a second conductive layer 21c formed of the same material as the power supply line 21a and in the same layer is provided on the second border wiring 18i. Here, as Figure 19 shown, the second conductive layer 21c is provided in the first slit Sa and the second slit Sb as the above-described fourth wiring layer. In addition, as Figure 19 shown, the second conductive layer 21c is in contact with the first conductive layer 31b and the second border wiring 18i. In addition, as Figure 19 shown, a fourth interlayer insulating film 20b corresponding to the fourth interlayer insulating film 20a of the first embodiment is provided so as to cover the end portion on the display area D side of the second border wiring 18i exposed from the first slit Sa and the end portion on the side opposite to the display area D of the second border wiring 18i exposed from the second slit Sb. In addition, as Figure 19 shown, a first opening Ma for exposing the second border wiring 18i is provided in the fourth interlayer insulating film 20b, and the second conductive layer 21c is provided so as to cover all of the second border wiring 18i exposed from the first opening Ma.

[0129] As Figure 20 shown, a third conductive layer 21d and a fourth conductive layer 21e formed of the same material as the power supply line 21a and in the same layer are provided on the first border wiring 18h. Here, as Figure 16 shown, the third conductive layer 21d is provided so as to overlap with the first barrier wall Wa and serves as the above-described fourth wiring layer. In addition, as Figure 20As shown, the fourth interlayer insulating film 20b is provided so as to cover all of the first frame wiring 18h exposed from the first slit Sa and the second slit Sb. Further, as Figure 20 shown, a second opening Mb that overlaps with the first barrier wall Wa and exposes the first frame wiring 18h is provided on the fourth interlayer insulating film 20b. And, as Figure 20 shown, the third conductive layer 21d is provided so as to cover all of the first frame wiring 18h exposed from the second opening Mb, thereby coming into contact with the first frame wiring 18h. Further, in the first planarization film 19a, a third opening Mc that exposes the first frame wiring 18h is provided between the first slit Sa and the display region D. Moreover, as Figure 20 shown, in the third opening Mc, a fourth conductive layer 21e is provided as the above-described fourth wiring layer. And, as Figure 20 shown, the fourth conductive layer 21e is provided so as to cover all of the first frame wiring 18h exposed from the third opening Mc.

[0130] The organic EL display device 50b is configured in the same manner as the organic EL display device 50a of the first embodiment, has flexibility, and in each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 emits light appropriately through the first TFT 9a, the second TFT 9b, and the third TFT 9c, thereby performing image display.

[0131] Further, in the present embodiment, an organic EL display device 50b in which the third conductive layer 21d is provided so as to overlap with the first barrier wall Wa is illustrated, but it may be, as Figure 21 shown, an organic EL display device 50ba in which, in addition to the third conductive layer 21d, a third conductive layer 21da is provided so as to overlap with the second barrier wall Wb. Here, in the organic EL display device 50ba, the first barrier wall Wa and the second barrier wall Wb have the same cross-sectional structure, and the second barrier wall Wb has: a lower resin layer 22ba formed of the same material as the second planarization film 22a in the same layer; an upper resin layer 32c formed of the same material as the edge mask 32a in the same layer. Further, as Figure 21 shown, a second opening Mba that overlaps with the second barrier wall Wb and exposes the first frame wiring 18h is provided on the fourth interlayer insulating film 20ba corresponding to the fourth interlayer insulating film 20b.

[0132] The organic EL display device 50b of the present embodiment can be manufactured by forming the second conductive layer 21c and the third conductive layer 21d when forming the power supply line 21a in the manufacturing method of the organic EL display device 50a of the first embodiment.

[0133] As described above, in the organic EL display device 50b according to the present embodiment, the fourth interlayer insulating film 20b provided between the first planarization film 19a and the power supply line 21a covers the first frame wiring 18h exposed from the first slit Sa and the second slit Sb in a region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view. Therefore, even if it is assumed that the metal film of the first electrode 31a remains between the first frame wiring 18h and the second frame wiring 18i at the lower part of each side wall of the first slit Sa and the second slit Sb, since the first frame wiring 18h and the second frame wiring 18i are covered by the fourth interlayer insulating film 20b in the region where the first frame wiring 18h and the second frame wiring 18i face each other in a plan view, short circuit between the first frame wiring 18h and the second frame wiring 18i can be suppressed.

[0134] In addition, in the organic EL display device 50b according to the present embodiment, the third conductive layer 21d and the fourth conductive layer 21e are stacked on the first frame wiring 18h, and the second conductive layer 21c is stacked on the second frame wiring 18i. Therefore, the wiring resistance of the first frame wiring 18h and the second frame wiring 18i can be reduced.

[0135] 《Other Embodiments》

[0136] In the above-described embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may be, for example, a three-layer stacked structure of a hole injection layer and a hole transport layer, a light-emitting layer, and an electron transport layer and an electron injection layer.

[0137] In addition, in the above-described embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, the first electrode is a cathode, and the second electrode is an anode.

[0138] In addition, in the above-described embodiments, an organic EL display device in which the electrode of the TFT connected to the first electrode is a drain electrode is exemplified. However, the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called a source electrode.

[0139] In addition, in the above-described embodiments, an organic EL display device is exemplified as a display device. However, the present invention can be applied to a display device including a plurality of light-emitting elements driven by current. For example, it can be applied to a display device including a light-emitting element using a quantum dot-containing layer, that is, a QLED (Quantum-dot light emitting diode).

[0140] As described above, the present invention is useful for a flexible display device.

[0141] Description of Reference Numerals

[0142] C terminal

[0143] D display area

[0144] F border area

[0145] Ma first opening

[0146] Mb second opening

[0147] Mc third opening

[0148] Mta terminal first opening

[0149] Mtb terminal second opening

[0150] Mtc terminal third opening

[0151] P sub-pixel

[0152] Sa first slit

[0153] Sb second slit

[0154] T terminal part

[0155] Wa first barrier wall

[0156] Wb second barrier wall

[0157] 9b, 9c TFT

[0158] 10 resin substrate layer (base substrate)

[0159] 12a, 12b semiconductor layer

[0160] 13 first interlayer insulating film

[0161] 14c lower conductive layer (first wiring layer)

[0162] 14d gate line (first wiring layer)

[0163] 14e emission control line (first wiring layer)

[0164] 15 second interlayer insulating film

[0165] 16a upper conductive layer (second wiring layer)

[0166] 17 third interlayer insulating film

[0167] 18f source line (third wiring layer)

[0168] 18h First frame wiring (third wiring layer)

[0169] 18i Second frame wiring (third wiring layer)

[0170] 18t, 18ta, 18tb First terminal electrode

[0171] 19a, 19c, 19ca, 19cb First planarization film

[0172] 20a, 20aa, 20ab, 20ac, 20aa, 20ae, 20b Fourth interlayer insulating film

[0173] 21a Power supply line (fourth wiring layer)

[0174] 21t, 21ta, 21tb Second terminal electrode

[0175] 21c Second conductive layer (fourth wiring layer)

[0176] 21d Third conductive layer (fourth wiring layer)

[0177] 21e Fourth conductive layer (fourth wiring layer)

[0178] 22a, 22d, 22da Second planarization film

[0179] 30 TFT layer

[0180] 31a First electrode

[0181] 31b First conductive layer

[0182] 32a Edge mask

[0183] 33 Organic EL layer (light-emitting layer)

[0184] 34 Second electrode

[0185] 35 Organic EL element layer

[0186] 36 First inorganic sealing film

[0187] 37 Organic sealing film

[0188] 38 Second inorganic sealing film

[0189] 40 Sealing film

[0190] 50a, 50a, 50b, 50b, 50b Organic EL display device

[0191] 61 Counter electrode

[0192] 65 Flexible printed circuit board

[0193] 70 Anisotropic conductive film

Claims

1. A display device, characterized in that, comprising: a base substrate; a thin film transistor layer disposed on the base substrate, and sequentially stacked with a semiconductor layer, a first interlayer insulating film, a first wiring layer, a second interlayer insulating film, a second wiring layer, a third interlayer insulating film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; a light emitting element layer disposed on the thin film transistor layer, and sequentially stacked with a plurality of first electrodes, a common edge mask, a plurality of light emitting layers, and a common second electrode corresponding to a plurality of sub-pixels constituting a display region; a sealing film disposed to cover the light emitting element layer, and sequentially stacked with a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a first barrier rib disposed to surround the display region in a border region around the display region and overlap with a peripheral end portion of the organic sealing film, and separated from the first planarization film and the second planarization film through a first slit formed to penetrate the first planarization film and the second planarization film; a second barrier rib disposed to surround the first barrier rib in the border region, and separated from the first barrier rib through a second slit formed to penetrate the first planarization film and the second planarization film; a power supply line disposed in the display region as the fourth wiring layer, and electrically connected to each of the first electrodes via a thin film transistor; a first border wiring disposed in the border region as the third wiring layer, and electrically connected to the power supply line; a second border wiring disposed in the border region as the third wiring layer, and electrically connected to the second electrode; and a first conductive layer disposed in the same layer as the first electrode with the same material in the border region, overlapping with the second border wiring through the first slit, and electrically connecting the second border wiring and the second electrode, a fourth interlayer insulating film is disposed between the third wiring layer and the fourth wiring layer, the fourth interlayer insulating film is disposed to cover at least one end portion on the display region side of the first border wiring and the second border wiring exposed from the first slit in a region where the first border wiring and the second border wiring face each other in a top view.

2. The display device according to claim 1, characterized in that, the fourth interlayer insulating film is disposed to cover all of the first border wiring exposed from the first slit.

3. The display device according to claim 1, characterized in that, the fourth interlayer insulating film is disposed to cover all of the first border wiring exposed from the second slit.

4. The display device according to claim 1, characterized in that, the fourth interlayer insulating film is disposed to cover the end portion on the display region side of the second border wiring exposed from the first slit.

5. The display device according to claim 1, characterized in that, The fourth interlayer insulating film is provided to cover an end portion of the second frame wiring exposed from the second slit on a side opposite to the display region.

6. The display device according to claim 1, wherein, the fourth interlayer insulating film is provided on the first planarization film.

7. The display device according to claim 1, wherein, in the first slit, the first conductive layer is in contact with the second frame wiring.

8. The display device according to claim 1, wherein, a second conductive layer is provided as the fourth wiring layer in the first slit, and the second conductive layer is in contact with the first conductive layer and the second frame wiring.

9. The display device according to claim 8, wherein, the fourth interlayer insulating film is provided to cover an end portion of the second frame wiring on the display region side exposed from the first slit and an end portion of the second frame wiring on a side opposite to the display region exposed from the second slit.

10. The display device according to claim 9, wherein, a first opening portion for exposing the second frame wiring is provided on the fourth interlayer insulating film, and the second conductive layer is provided to cover all of the second frame wiring exposed from the first opening portion.

11. The display device according to claim 1, wherein, a third conductive layer is provided as the fourth wiring layer so as to overlap with the first barrier wall, and the third conductive layer is in contact with the first frame wiring.

12. The display device according to claim 11, wherein, the fourth interlayer insulating film is provided to cover all of the first frame wiring exposed from the first slit and the second slit.

13. The display device according to claim 11, wherein, a second opening portion is provided in the fourth interlayer insulating film, the second opening portion overlaps with the first barrier wall and exposes the first frame wiring, and the third conductive layer is provided to cover all of the first frame wiring exposed from the second opening portion.

14. The display device according to claim 1, wherein, on the first planarization film, a third opening portion for exposing the first frame wiring is provided between the first slit and the display region, a fourth conductive layer is provided as the fourth wiring layer in the third opening portion, and the fourth conductive layer is provided to cover all of the first frame wiring exposed from the third opening portion.

15. The display device according to claim 1, wherein, a terminal portion in which a plurality of terminals are arranged is provided at an end portion of the frame region, each of the terminals includes a first terminal electrode provided as the third wiring layer and a second terminal electrode provided as the fourth wiring layer, a terminal first opening portion for exposing the first terminal electrode is provided in the first planarization film, the second terminal electrode is in contact with the first terminal electrode via the terminal first opening portion, and a terminal second opening portion for exposing the second terminal electrode is provided in the second planarization film.

16. The display device according to claim 15, wherein, the second terminal electrode is electrically connected to the opposing electrode of the flexible printed circuit board through the second opening of the terminal.

17. The display device according to claim 16, wherein, a third opening of the terminal is provided on the fourth interlayer insulating film so as to overlap with the second terminal electrode, and the periphery of the third opening of the terminal is disposed at a position outside the peripheries of the first opening of the terminal and the second opening of the terminal.

18. The display device according to claim 16, wherein, the second opening of the terminal is provided outside the first opening of the terminal in a top view.

19. The display device according to claim 18, wherein, the first terminal electrode is provided so as to overlap with the second opening of the terminal in a top view.

20. The display device according to any one of claims 1 to 19, wherein, each of the light emitting layers is an organic electroluminescent layer.

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