Current detection chip and packaging structure

Abstract

The application provides a current detection chip and a packaging structure. The current detection chip comprises two or more detection circuit modules, each of which comprises a detection port and a sampling resistor, the detection port being connected to the sampling resistor; the application mode of the sampling resistor is identified according to the potential of the detection port; and the working state of one detection circuit module is reserved when the application mode of the sampling resistor is parallel application. The working state of one detection circuit module is reserved when the application mode of the sampling resistor is parallel application. The current of multiple channels can be detected, the expansibility is high, only a small number of external application components are needed, the power consumption of the chip is reduced, the packaging size is small, and the manufacturing cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of circuit testing, and more particularly to a current detection chip and its packaging structure. Background Technology

[0002] Current sensing chips in current technology typically only provide current sensing for one channel, failing to support customers in detecting multiple currents and exhibiting very limited scalability. Furthermore, current sensing chips in current technology require numerous external application components, resulting in high power consumption. Integrating external application components into the chip would lead to a larger package size and higher manufacturing costs.

[0003] Therefore, how to achieve multi-channel current detection in a smaller volume is a problem that existing technologies need to solve. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a current detection chip and its packaging structure, which makes the chip package small in size and can realize multi-channel current detection.

[0005] To address the aforementioned problems, this invention provides a current detection chip. The current detection chip includes two or more detection circuit modules, each module comprising a detection port and a sampling resistor, the detection port being connected to the sampling resistor; the application mode of the sampling resistor is identified based on the potential of the detection port; when the sampling resistor is used in parallel, the operating state of one detection circuit module is maintained.

[0006] In some embodiments, identifying the application mode of the sampling resistor based on the potential of the detection port includes: acquiring the potential of each detection port; calculating the voltage difference of the corresponding detection ports in each detection circuit module; and identifying the application mode of the sampling resistor as parallel application when the voltage difference between the corresponding detection ports is less than a preset threshold.

[0007] In some embodiments, the detection circuit module further includes: an operational amplifier, wherein a first input terminal of the operational amplifier is electrically connected to a first terminal of the sampling resistor, a second input terminal of the operational amplifier is electrically connected to a second terminal of the sampling resistor, and the output terminal of the operational amplifier serves as the output terminal of the detection circuit module.

[0008] In some embodiments, the current sensing chip is pre-set with at least one common-mode reference voltage.

[0009] In some embodiments, the detection circuit module further includes: a first power resistor, a second power resistor, a third power resistor, and a fourth power resistor; a first end of the first power resistor is connected to a first end of the sampling resistor, and a second end is connected to a first input terminal of the operational amplifier; a first end of the second power resistor is connected to a second end of the sampling resistor, and a second end is connected to a second input terminal of the operational amplifier; a first end of the third power resistor is connected to a second end of the first power resistor, and a second end is connected to the common-mode reference voltage; a first end of the fourth power resistor is connected to a second end of the second power resistor, and a second end is connected to the output terminal of the operational amplifier.

[0010] In some embodiments, the detection port is configured as a multiplexed port and calibrated using internal programming.

[0011] In some embodiments, the output mode of the current detection chip is set to a single-sided output mode or a double-sided output mode.

[0012] In some embodiments, the resistance value of the sampling resistor is 2mΩ ± 0.1%.

[0013] The present invention also provides a packaging structure, including a packaging shell and any of the aforementioned current detection chips, wherein the circuit detection chip is located inside the packaging shell, and the packaging structure further includes pins, which are disposed on the outer wall of the packaging shell, and the pins serve as detection ports of the current detection chip or are electrically connected to the detection ports.

[0014] In some embodiments, the pins are surface mount pins, which can support fully automated wave soldering placement and reel packaging.

[0015] The above technical solution uses multiple detection circuit modules to detect the potential of multiple detection ports connected to the sampling resistor. Based on the potential of the detection ports, the application mode of the sampling resistor is identified, and then the detection circuit modules to be retained are selected based on the identification results. It offers strong scalability and requires only a few external application components to detect multiple currents, thus reducing chip power consumption and minimizing package size and manufacturing costs. Attached Figure Description

[0016] Figure 1 This is a structural diagram of a current detection chip provided in a specific embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the application mode of the identification sampling resistor provided in a specific embodiment of the present invention.

[0018] Figure 3This is a schematic diagram of the sensitivity of the current detection chip provided in a specific embodiment of the present invention at 0.5 times the power supply voltage VCC.

[0019] Figure 4 This is a schematic diagram of the sensitivity of the current detection chip provided in another specific embodiment of the present invention at 0.1 times the power supply voltage VCC.

[0020] Figure 5 This is a packaging structure provided in a specific embodiment of the present invention. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings, illustrates a specific embodiment of the current detection chip and its packaging structure provided by the present invention.

[0022] Figure 1 This is a structural diagram of a current detection chip provided in a specific embodiment of the present invention. The current detection chip B includes: a detection circuit module M1 and a detection circuit module M2. It should be noted that in other specific embodiments, the detection circuit modules are not limited to two. The detection circuit module M1 includes: a detection port 1, a detection port 8, and a first resistor R1, wherein the detection port 1 and the detection port 8 are connected to the first resistor R1. The detection port 1 serves as the first pin of the current detection chip B, and the detection port 8 serves as the eighth pin of the current detection chip B. The first pin and the eighth pin serve as the first input terminal of the current detection chip B, i.e., the input terminal of the detection circuit module M1, and are connected to an external circuit. The detection circuit module M1 samples the current value of the external circuit, and the first resistor R1 serves as the sampling resistor of the external circuit.

[0023] The detection circuit module M2 includes a detection port 4, a detection port 5, and a second resistor R2. Detection ports 4 and 5 are connected to the second resistor R2. Detection port 4 serves as the fourth pin of the current detection chip B, and detection port 5 serves as the fifth pin of the current detection chip B. The fourth and fifth pins serve as the second input terminals of the current detection chip B, i.e., the input terminals of the detection circuit module M2, and are connected to another external circuit. The detection circuit module M2 samples the current value of the external circuit, and the second resistor R2 serves as the sampling resistor of the external circuit.

[0024] The current detection chip B identifies the application mode of the first resistor R1 and the second resistor R1 based on the potentials of detection ports 1, 8, 4, and 5. When the first resistor R1 and the second resistor R1 are used in parallel, the operating state of one detection circuit module is maintained. In this specific embodiment, the resistance values ​​of the first resistor R1 and R2 in the current detection chip are adjusted to 2mΩ ± 0.1%.

[0025] Figure 2 This is a schematic diagram of the application mode identification of the sampling resistor provided by a specific embodiment of the present invention. The step of identifying the application mode of the sampling resistor based on the potential of the detection port includes: step S101, obtaining the potential of each detection port; step S102, calculating the voltage difference of the corresponding detection ports in each detection circuit module; step S103, when the voltage difference between the corresponding detection ports is less than a preset threshold, the application mode of the sampling resistor is identified as parallel application.

[0026] Please continue reading below. Figure 1 The detection circuit module M1 further includes a first operational amplifier A1. The first input terminal a11 of the first operational amplifier A1 is electrically connected to the first terminal r11 of the first resistor R1. The second input terminal a12 of the first operational amplifier A1 is electrically connected to the second terminal r11 of the first resistor R1. The output terminal a13 of the first operational amplifier A1 serves as the output terminal of the detection circuit module M1, i.e., the first output terminal 7 of the current detection chip B. The detection circuit module M2 further includes a second operational amplifier A2. The first input terminal a21 of the second operational amplifier A2 is electrically connected to the first terminal r21 of the second resistor R1. The second input terminal a22 of the second operational amplifier A2 is electrically connected to the second terminal r22 of the second resistor R1. The output terminal a23 of the second operational amplifier A2 serves as the output terminal 6 of the detection circuit module M2, i.e., the second output terminal of the current detection chip B.

[0027] In this specific embodiment, the detection circuit module further includes: a first power resistor, a second power resistor, a third power resistor, and a fourth power resistor; a first end of the first power resistor is connected to a first end of the sampling resistor, and a second end is connected to a first input terminal of the operational amplifier; a first end of the second power resistor is connected to a second end of the sampling resistor, and a second end is connected to a second input terminal of the operational amplifier; a first end of the third power resistor is connected to a second end of the first power resistor, and a second end is connected to the common-mode reference voltage; a first end of the fourth power resistor is connected to a second end of the second power resistor, and a second end is connected to the output terminal of the operational amplifier.

[0028] Please continue reading below. Figure 1 The third resistor R3 is set as the first power resistor of the detection circuit module M1, the seventh resistor R7 is set as the second power resistor of the detection circuit module M1, the fourth resistor R4 is set as the third power resistor of the detection circuit module M1, and the eighth resistor R8 is set as the fourth power resistor of the detection circuit module M1.

[0029] In the detection circuit module M1, the first terminal r11 of the first resistor R1 is connected to detection port 1 of the detection circuit module M1, and the second terminal r12 of the first resistor R1 is connected to detection port 8 of the detection circuit module M1. Detection port 1 and detection port 8 are used to connect to an external circuit, so that the voltage across the first resistor R1 is the same as that across the external circuit, enabling sampling of the external circuit. The first terminal r31 of the third resistor R3 is connected to the first terminal r11 of the first resistor R1. The first terminal r41 of the fourth resistor R4 is connected to the second terminal r32 of the third resistor R3 and connected to the first terminal a11 of the first operational amplifier A1. The first terminal r71 of the seventh resistor R7 is connected to the second terminal r12 of the first resistor R1. The first terminal r81 of the eighth resistor R8 is connected to the second terminal r72 of the seventh resistor R7 and connected to the second terminal a12 of the first operational amplifier A1. The second terminal r82 of the eighth resistor R8 is connected to the third terminal a13 of the first operational amplifier A1. The third terminal a13 of the first operational amplifier A1 is connected to the first output port 7. The first output port 7 serves as the seventh pin of the current detection chip B or is electrically connected to the seventh pin of the current detection chip B as the first output terminal of the current detection chip B, and is used to output the current value of the external circuit detected by the detection circuit module M1.

[0030] Please continue reading below. Figure 1 The sixth resistor R6 is set as the first power resistor of the detection circuit module M2, the tenth resistor R10 is set as the second power resistor of the detection circuit module M2, the fifth resistor R5 is set as the third power resistor of the detection circuit module M2, and the ninth resistor R9 is set as the fourth power resistor of the detection circuit module M2.

[0031] In the detection circuit module M2, the first end r21 of the second resistor R2 is connected to pin 4 of the current detection chip B, and the second end r22 of the second resistor R2 is connected to pin 5 of the current detection chip B. Detection ports 4 and 5 are used to connect to another external circuit, so that the voltage across the second resistor R2 is the same as that across the external circuit, enabling sampling of the external circuit. The first end r61 of the sixth resistor R6 is connected to the second end r52 of the fifth resistor R5 and then to the first end a21 of the second operational amplifier A2. The second end r62 of the sixth resistor R6 is connected to the first end r21 of the second resistor R2. The second end r102 of the tenth resistor R10 is connected to the second end r22 of the second resistor R2. The second end r92 of the ninth resistor R9 is connected to the first end r101 of the tenth resistor R10 and then to the second end a22 of the second operational amplifier A2. The first end r91 of the ninth resistor R9 is connected to the third end a23 of the second operational amplifier A2. The third end a23 of the second operational amplifier A2 is connected to the second output port 6. The second output port 6 serves as the sixth pin of the current detection chip B or is electrically connected to the sixth pin of the current detection chip B as the second output terminal of the current detection chip B, and is used to output the current value of the external circuit detected by the detection circuit module M2.

[0032] The first terminal r51 of the fifth resistor R5 is connected to the second terminal r42 of the fourth resistor R4 and connected to the built-in common-mode voltage VREF, so that the detection circuit module M1 and the detection circuit module M2 are both subjected to the common-mode voltage VREF, avoiding temperature drift or other factors from having different effects on the detection circuit module M1 and the detection circuit module M2, thereby affecting the accuracy of the detection results.

[0033] In this specific embodiment, the current detection chip B further includes internal pin 2, internal pin 3, and a first capacitor C. Internal pin 2 is connected to the first terminal c1 of the first capacitor C and connected to the power supply voltage VCC to start the chip. Internal pin 3 is connected to the second terminal c2 of the first capacitor C and connected to ground. The first capacitor C is used to store charge to prevent the chip from being damaged by excessive instantaneous voltage.

[0034] In this specific embodiment, the resistance value of the second resistor R1 is set to be the same as that of the first resistor R1, and the resistance values ​​of the third resistor R3, the seventh resistor R7, the sixth resistor R6, and the tenth resistor R10 are also set to be the same. The current detection chip B acquires the potentials of detection ports 1, 8, 4, and 5. By calculating the voltage difference between the corresponding detection ports in the detection circuit module M1 and the detection circuit M2, when the voltage difference between the corresponding detection ports is less than a preset threshold, for example, when the voltage difference between detection port 1 and detection port 4, and between detection port 8 and detection port 5 is less than the preset threshold, it is identified that the application mode of the first resistor R1 and the second resistor R1 is parallel application. In this case, the voltage applied across the first resistor R1 and the second resistor R1 by the two external circuits is the same. Since the resistance value of the second resistor R1 is the same as that of the first resistor R1, the current flowing through the second resistor R1 and the first resistor R1 is the same. At this time, the output of one detection circuit module is turned off to reduce power consumption. That is, when the application mode of the first resistor R1 and the second resistor R1 is identified as parallel application, the current detection chip B only retains the working state of detection circuit module M1 or only retains the working state of detection circuit module M2. When the voltage difference between the corresponding detection ports is greater than or equal to the preset threshold, both detection circuit module M1 and detection circuit module M2 operate normally and detect the current value of their respective paths.

[0035] It should be noted that in this invention, multiple resistors can be connected in series as sampling resistors. The resistance value of the first resistor R1 or the second resistor R2 in the detection circuit module M1 and the detection circuit M2 only represents the total resistance value of the sampling resistors in the detection circuit module M1 or the detection circuit M2, and does not limit the number of sampling resistors.

[0036] In some specific embodiments, the detection port in the current detection chip is set as a multiplexed port and internally programmed for calibration, so that one chip port can correspond to the pins of multiple current detection chips. This reduces the number of pins of the current detection chip while also allowing for performance tuning after packaging to improve the yield of the current detection chip.

[0037] In some specific embodiments, the current sensing chip is pre-set with at least one common-mode reference voltage VREF, and different common-mode reference voltages can be set according to the needs of different users through programming.

[0038] In other specific embodiments, the output mode of the current detection chip is set to a single-sided output mode or a double-sided output mode. The single-sided mode detects only unidirectional current, while the double-sided mode can detect current in both positive and negative directions. For example, when the output mode of the current detection chip is set to single-sided mode, a signal is output only when the current flowing through the first resistor R1 and the second resistor R1 flows from the first end to the second end of the first resistor R1 and the second resistor R1, or only when the current flowing through the first resistor R1 and the second resistor R1 flows from the second end to the first end of the first resistor R1 and the second resistor R1. When the output mode of the current detection chip is set to double-sided mode, a signal is also output by the seventh pin of the first output terminal and / or the sixth pin of the second output terminal when the currents flowing through the first resistor R1 and the second resistor R1 are in opposite directions.

[0039] The following description uses the sensitivity of the current detection chip at 0.5 times the power supply voltage VCC and 0.1 times the power supply voltage VCC as examples.

[0040] Figure 3 This is a schematic diagram of the sensitivity of the current detection chip provided in a specific embodiment of the present invention at 0.5 times the power supply voltage VCC. Figure 4 This is a schematic diagram illustrating the sensitivity of a current detection chip provided in a specific embodiment of the present invention at 0.1 times the power supply voltage VCC. For example... Figure 3 and Figure 4 As shown, the horizontal axis represents the current of the circuit under test, and the vertical axis represents the voltage value output by the circuit module under test. +IP MAX For the maximum forward current value, -IP MAX The maximum negative current value is represented by the slope, which is the sensitivity (Sens) of the current sensing chip. VCC is the power supply voltage. Figure 3 As shown, when 0.5 times the power supply voltage VCC is applied, the value at point a in the figure is 0.5VCC + Sens * IP. MAX The value at point b is 0.5VCC - Sens * IP. MAX As shown in the figure, the current detection chip has stable sensitivity. Figure 4 As shown, when 0.1 times the power supply voltage VCC is applied, the value at point a in the figure is 0.1VCC + Sens*IP. MAX The value at point b is 0.1VCC, and the figure shows that the sensitivity of the current detection chip is stable.

[0041] The above technical solution acquires the potentials of detection ports 1, 8, 4, and 5 through detection circuit modules M1 and M2 in the current detection chip B. By calculating the voltage difference between the corresponding detection ports in detection circuit modules M1 and M2, when the voltage difference between the corresponding detection ports is less than a preset threshold, the application mode of the first resistor R1 and the second resistor R1 is identified as parallel application. The current detection chip B retains only the working state of detection circuit module M1 or only the working state of detection circuit module M2, reducing the chip's power consumption. When the voltage difference between the corresponding detection ports is greater than or equal to the preset threshold, both detection circuit modules M1 and M2 operate normally, each detecting the current value of its respective path. This achieves current value detection of multiple circuits in a single current detection chip, reducing manufacturing costs.

[0042] This technical solution also provides a packaging structure for a current detection chip. Figure 5 This is a packaging structure provided by a specific embodiment of the present invention. The packaging structure includes a packaging shell 9 and a current detection chip (not shown). The circuit detection chip is located inside the packaging shell 9, and the structure of the current detection chip is the same as that described above, and will not be repeated. The packaging structure also includes pins 91, 95, 96, 97, and 98, which are disposed on the outer wall of the packaging shell 9. These pins serve as detection ports of the current detection chip or are electrically connected to the detection ports. In some embodiments, pins 91, 95, 96, 97, and 98 are surface mount pins, which can support fully automated wave soldering and tape packaging. Compared with traditional current detection modules limited by the size of printed circuit boards and the complexity of internal auxiliary circuits, the above technical solution uses a semiconductor chip to replace the internal printed circuit board and internal auxiliary circuit components, integrating the function into the semiconductor chip. Furthermore, through semiconductor packaging technology, the length*width*height dimensions of the current detection chip's package structure are reduced to 5.1mm*6.55mm*1.2mm. Compared to the traditional current detection module with length*width*height dimensions of 17.7mmX110mmX118.9mm, the package volume of the current detection chip is reduced, thus reducing manufacturing costs.

[0043] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A current detection chip, characterized in that, include: Two or more detection circuit modules are provided, each detection circuit module including: a detection port and a sampling resistor, wherein the detection port is connected to the sampling resistor; the application mode of the sampling resistor is identified according to the potential of the detection port; when the application mode of the sampling resistor is parallel application, the working state of one detection circuit module is maintained.

2. The current detection chip according to claim 1, characterized in that, The step of identifying the application mode of the sampling resistor based on the potential of the detection port includes: acquiring the potential of each detection port; calculating the voltage difference of the corresponding detection ports in each detection circuit module; and identifying the application mode of the sampling resistor as parallel application when the voltage difference between the corresponding detection ports is less than a preset threshold.

3. The current detection chip according to claim 1, characterized in that, The detection circuit module further includes an operational amplifier, wherein the first input terminal of the operational amplifier is electrically connected to the first terminal of the sampling resistor, the second input terminal of the operational amplifier is electrically connected to the second terminal of the sampling resistor, and the output terminal of the operational amplifier serves as the output terminal of the detection circuit module.

4. The current detection chip according to claim 3, characterized in that, The current sensing chip is pre-set with at least one common-mode reference voltage.

5. The current detection chip according to claim 4, characterized in that, The detection circuit module further includes: a first power resistor, a second power resistor, a third power resistor, and a fourth power resistor; a first end of the first power resistor is connected to a first end of the sampling resistor, and a second end of the first power resistor is connected to a first input terminal of the operational amplifier; a first end of the second power resistor is connected to a second end of the sampling resistor, and a second end of the second power resistor is connected to a second input terminal of the operational amplifier; a first end of the third power resistor is connected to a second end of the first power resistor, and a second end of the third power resistor is connected to the common-mode reference voltage; a first end of the fourth power resistor is connected to a second end of the second power resistor, and a second end of the fourth power resistor is connected to the output terminal of the operational amplifier.

6. The current detection chip according to claim 1, characterized in that, The detection port is configured as a multiplexed port and calibrated using internal programming.

7. The current detection chip according to claim 1, characterized in that, The output mode of the current detection chip is set to either single-sided output mode or double-sided output mode.

8. The current detection chip according to any one of claims 1 to 7, characterized in that, The resistance value of the sampling resistor is 2mΩ±0.1%.

9. A packaging structure, characterized in that, The package includes a housing and a current detection chip as described in any one of claims 1 to 8. The current detection chip is located inside the housing. The package structure also includes pins, which are disposed on the outer wall of the housing. The pins serve as detection ports of the current detection chip or are electrically connected to the detection ports.

10. The packaging structure according to claim 9, characterized in that, The pins are surface mount pins, which can support fully automated wave soldering placement and reel packaging.

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