A method for determining parameter value and a chip

Abstract

The embodiment of the present application discloses a method and chip for determining parameter values, which are widely used to improve signal quality. The method includes: a first chip obtains N reference values ​​of a forward equalizer parameter of a second chip, N is an integer greater than 1, and the forward equalizer parameter is a parameter for the forward equalizer of the second chip to adjust the transmitted signal; the first chip determines a first optional value set from the N reference values, the first optional value set includes M optional values, M is an integer greater than or equal to 1 and less than N; the first chip obtains M signal quality information according to the M optional values, each signal quality information in the M signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to the corresponding optional value in the M optional values; the first chip determines a target value according to the M signal quality information, and the target value is used for the forward equalizer of the second chip to adjust the transmitted signal; the first chip sends the target value to the second chip.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a method and chip for determining parameter values. Background Art

[0002] With the advancement of electronics technology, serial interfaces have replaced parallel interfaces due to their fast transmission speeds, low power consumption, and strong anti-interference properties, becoming the mainstream technology in the high-speed transmission field. A serial interface consists of a serializer and a deserializer, collectively referred to as SerDes. The serializer, located at the transmitting end, converts parallel signals into serial signals; the deserializer, located at the receiving end, converts serial signals into parallel signals. To reduce the loss incurred by the serial signal (hereinafter referred to as "signal") as it travels from the serializer at the transmitting end to the deserializer at the receiving end, as well as the impact of intersymbol interference (ISI) on the signal, a common implementation method is to implement a feed-forward equalizer (FFE) at the transmitting end to compensate for channel damage to the signal. The quality of the signal received at the receiving end is directly affected by the settings of the forward equalizer parameters.

[0003] In traditional technology, the values ​​of the forward equalizer parameters are set by technical experts based on their own experience in limited transmission scenarios. However, the actual signal transmission scenarios are more complex (for example, the signal is transmitted over different link lengths or environments). Therefore, this method cannot ensure that the signal quality remains at a high level in different scenarios, and its application scope is limited. Summary of the Invention

[0004] The embodiments of the present application provide a method and chip for determining parameter values, which are used to improve signal quality and expand the scope of application.

[0005] In a first aspect, a method for determining a parameter value is provided, which can be applied to a first chip. Specifically, the method includes the following steps: the first chip obtains N reference values ​​of a forward equalizer parameter of a second chip. Wherein, N is an integer greater than 1. The forward equalizer parameter is a parameter used by the forward equalizer of the second chip to adjust the transmitted signal, for example, including one or more of a main-cursor setting parameter, a forward symbol setting parameter, and a backward symbol setting parameter. The first chip determines a first optional value set from the N reference values, and the first optional value set includes M optional values, where M is an integer greater than or equal to 1 and less than N. The first chip obtains M signal quality information based on the M optional values, and each signal quality information in the M signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values. For example, the signal quality information may include one or more of information related to the eye diagram, a signal-to-noise ratio (SNR), and a bit error rate (BER). The information related to the eye diagram may include the width, height, and area of ​​the eye diagram. The first chip determines a target value based on the M signal quality information and sends the target value to the second chip. After receiving the target value, the second chip uses its forward equalizer to adjust the transmitted signal. After the adjustment, the signal quality of the signal sent by the second chip is higher. Compared with the traditional method of determining the value of the forward equalizer parameter based on experience, this parameter value determination method can be applied to various different transmission scenarios, has a wider range of applications, and can achieve better forward equalization effects and improve the quality of the transmitted signal. In addition, the first chip selects M optional values ​​from N reference values ​​to obtain its signal quality information, rather than obtaining signal quality information for all N reference values. Therefore, the efficiency of determining the target value of the forward equalization reference is higher.

[0006] As a possible design, the first chip determines a first set of optional values ​​from the N reference values, including: the first chip arranges the N reference values ​​in ascending order or descending order, and uniformly selects the M optional values ​​from the arranged N reference values ​​to obtain the first set of optional values. To a certain extent, the higher the value of M, the higher the probability that the determined target value can achieve high signal quality. In practical applications, the value of M needs to be pre-determined based on the size of N to achieve a relative balance between efficiency and quality in target value determination.

[0007] As a possible design, the first chip determines a first set of selectable values, which can be considered a first round of screening. Subsequently, the first chip can perform the following steps to perform a second round of screening to select a more optimal target value and improve signal quality. Specifically, the second round of screening includes the following steps: the first chip determines a second set of selectable values ​​from the N reference values. The second set of selectable values ​​includes selectable values ​​in the first set of selectable values ​​whose signal quality information meets a first preset condition, and S reference values ​​surrounding the selectable values ​​that meet the first preset condition. The N reference values ​​include the S reference values. The first preset condition may be, for example, that the signal quality indicated by the signal quality information is the best, or ranked in the top n, where n is greater than or equal to 1. The S reference values ​​surrounding the selectable value that meets the first preset condition are the S selectable values ​​adjacent to the selectable value whose signal quality information meets the first preset condition, after sorting the Nth reference value in descending order or in ascending order. The first chip obtains S pieces of signal quality information based on the S reference values. Each piece of the S signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding reference value among the S reference values. The first chip determines the target value based on the signal quality information corresponding to the optional values ​​that meet the first preset condition and the S signal quality information included in the second optional value set. Since the signal quality information will show a certain pattern as the reference value increases or decreases, that is, the signal quality information has a maximum value (maximum value or minimum value), the reference values ​​around the reference value corresponding to the maximum value will roughly show an increasing or decreasing trend as the distance from the reference value increases. Therefore, through the first round of screening, that is, the signal quality meets the first preset condition, the area where the maximum value may appear can be roughly determined. Then, by obtaining the optional values ​​within this area for a second round of screening, the maximum value can be determined more accurately, so that the signal quality received by the second chip from the first chip is the best.

[0008] As a possible design, the first chip can also determine the target value based on the M signal quality information in the following implementation method: the first chip determines the optional value corresponding to the signal quality information with the best signal quality indicated in the M signal quality information as the target value to ensure the signal quality sent by the second chip.

[0009] As a possible design, the forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter. Accordingly, the first chip obtains N reference values ​​of the forward equalizer parameters of the second chip, including: the first chip obtains N1 reference values ​​of the first forward equalizer parameters of the second chip and N2 reference values ​​of the second forward equalizer parameters, wherein the N1 and the N2 are both integers greater than 1. The first chip determines a first optional value set from the N reference values, including: the first chip determines a first optional value set from the N1 reference values ​​and the N2 reference values, the first optional value set including M optional values, and M is an integer greater than or equal to 1 and less than N1*N2. Please refer to the above for the subsequent steps, which will not be repeated here. Of course, the forward equalization parameters can also include three or more parameters, which are not specifically limited in the embodiments of the present application.

[0010] As a possible design, the first chip can obtain N reference values ​​of the forward equalizer parameters of the second chip in the following manner: the first chip sends a first adjustment instruction to the second chip until receiving an adjustment response from the second chip, the first adjustment instruction is used by the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step size based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value. The first chip obtains the N reference values ​​of the forward equalizer parameter based on the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size, and the preset value. In other words, the first chip can achieve the purpose of determining N reference values ​​by interacting with the second chip to ensure the accuracy of the reference values.

[0011] As a possible design, before the first chip sends a first adjustment instruction to the second chip, the method also includes: the first chip sends a second adjustment instruction to the second chip, and the second adjustment instruction is used to adjust the forward equalizer parameters of the second chip to the preset value, so that the second chip can accurately adjust according to the first adjustment instruction.

[0012] As one possible design, after determining the M optional values, the first chip may send third adjustment instructions corresponding to the M optional values ​​to the second chip, so that the second chip adjusts the forward equalizer parameters to the optional values ​​according to the third adjustment instructions. The second chip receives the signal sent by the second chip when the forward equalizer parameters are adjusted to the M optional values, and obtains signal quality information corresponding to the signal. In another possible design, the first chip may also obtain the corresponding signal quality information before determining the M optional values. For related details, please refer to the following and will not be repeated here.

[0013] As a possible design, the first chip sending the target value to the second chip includes: the first chip sending a fourth adjustment instruction to the second chip, so that the second chip adjusts the forward equalizer parameters to the target value according to the fourth adjustment instruction, and sends a signal.

[0014] In a second aspect, a device for determining a parameter value is provided, which is applied to a first chip, and the device includes: a first acquisition unit, used to obtain N reference values ​​of a forward equalizer parameter of a second chip, where N is an integer greater than 1, and the forward equalizer parameter is a parameter used by the forward equalizer of the second chip to adjust the transmitted signal; a first determination unit, used to determine a first optional value set from the N reference values, the first optional value set including M optional values, where M is an integer greater than or equal to 1 and less than N; a second acquisition unit, used to obtain M signal quality information based on the M optional values, each signal quality information in the M signal quality information indicating the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values; a second determination unit, used to determine a target value based on the M signal quality information, the target value being used for the forward equalizer of the second chip to adjust the transmitted signal; and a sending unit, used to send the target value to the second chip.

[0015] As a possible design, the first determination unit is used to arrange the N reference values ​​in order from small to large or from large to small, and evenly select the M optional values ​​from the arranged N reference values ​​to obtain the first optional value set.

[0016] As a possible design, the second determination unit is used to determine a second optional value set from the N reference values, the second optional value set including the optional values ​​in the first optional value set whose signal quality information meets the first preset condition and S reference values ​​around the optional values ​​that meet the first preset condition, and the N reference values ​​include the S reference values; obtain S pieces of signal quality information based on the S reference values, each piece of the S signal quality information indicating the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding reference value in the S reference values; determine the target value based on the signal quality information corresponding to the optional value that meets the first preset condition included in the second optional value set and the S pieces of signal quality information.

[0017] As a possible design, the second determination unit is used to determine the optional value corresponding to the signal quality information with the best signal quality indicated in the M signal quality information as the target value.

[0018] As a possible design, the forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter; the first acquisition unit is used to obtain N1 reference values ​​of the first forward equalizer parameter and N2 reference values ​​of the second forward equalizer parameter of the second chip, wherein the N1 and the N2 are both integers greater than 1; the first determination unit is used to determine a first optional value set from the N1 reference values ​​and the N2 reference values, the first optional value set including M optional values, wherein M is an integer greater than or equal to 1 and less than N1*N2.

[0019] As a possible design, the first acquisition unit is used to send a first adjustment instruction to the second chip until an adjustment response is received from the second chip, wherein the first adjustment instruction is used for the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step size based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value; the N reference values ​​of the forward equalizer parameter are obtained based on the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size, and the preset value.

[0020] As a possible design, the sending unit is further used to send a second adjustment instruction to the second chip before sending the first adjustment instruction to the second chip, and the second adjustment instruction is used to adjust the forward equalizer parameters of the second chip to the preset value.

[0021] As a possible design, the second acquisition unit is used to send third adjustment instructions corresponding to the M optional values ​​to the second chip, and the third adjustment instructions are used to adjust the forward equalizer parameters of the second chip to the optional values, and receive the signal sent by the second chip when the forward equalizer parameters are adjusted to the M optional values; and obtain signal quality information corresponding to the signal.

[0022] As a possible design, the sending unit is used to send a fourth adjustment instruction to the second chip, and the fourth adjustment instruction is used to adjust the forward equalizer parameters of the second chip to the target value.

[0023] As a possible design, the forward equalizer parameters include at least one of the following parameters: a front symbol setting parameter, a rear symbol setting parameter, and a main symbol setting parameter.

[0024] In a third aspect, a first chip is provided, comprising a control circuit and an interface circuit; wherein the interface circuit is used to obtain N reference values ​​of a forward equalizer parameter of a second chip, where N is an integer greater than 1, and the forward equalizer parameter is a parameter used by the forward equalizer of the second chip to adjust the transmitted signal; the control circuit is used to determine a first optional value set from the N reference values, where the first optional value set includes M optional values, where M is an integer greater than or equal to 1 and less than N; M signal quality information is obtained based on the M optional values, where each signal quality information in the M signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values; a target value is determined based on the M signal quality information, where the target value is used by the forward equalizer of the second chip to adjust the transmitted signal; and the interface circuit is further used to send the target value to the second chip.

[0025] As a possible design, the control circuit determines the first set of optional values ​​from the N reference values, including: the control circuit arranges the N reference values ​​in order from small to large or from large to small, and evenly selects the M optional values ​​from the arranged N reference values ​​to obtain the first set of optional values.

[0026] As a possible design, the control circuit determines the target value based on the M signal quality information, including: the control circuit determines a second optional value set from the N reference values, the second optional value set including the optional values ​​in the first optional value set whose signal quality information meets the first preset condition and S reference values ​​around the optional values ​​that meet the first preset condition, and the N reference values ​​include the S reference values; the control circuit obtains S signal quality information based on the S reference values, each signal quality information in the S signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to the corresponding reference value in the S reference values; the control circuit determines the target value based on the signal quality information corresponding to the optional value that meets the first preset condition included in the second optional value set and the S signal quality information.

[0027] As a possible design, the control circuit determines the target value based on the M signal quality information, including: the control circuit determines the optional value corresponding to the signal quality information indicating the best signal quality among the M signal quality information as the target value.

[0028] As a possible design, the forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter;

[0029] The interface circuit obtains N reference values ​​of the forward equalizer parameters of the second chip, including: the interface circuit obtains N1 reference values ​​of the first forward equalizer parameter and N2 reference values ​​of the second forward equalizer parameter of the second chip, wherein the N1 and the N2 are both integers greater than 1; the control circuit determines a first optional value set from the N reference values, including: the control circuit determines a first optional value set from the N1 reference values ​​and the N2 reference values, the first optional value set including M optional values, wherein M is an integer greater than or equal to 1 and less than N1*N2.

[0030] As a possible design, the interface circuit obtains N reference values ​​of the forward equalizer parameters of the second chip, including: the interface circuit sends a first adjustment instruction to the second chip until receiving an adjustment response from the second chip, the first adjustment instruction is used by the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step size based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value; the interface circuit obtains the N reference values ​​of the forward equalizer parameter based on the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size, and the preset value.

[0031] As a possible design, the interface circuit is further used to send a second adjustment instruction to the second chip before sending the first adjustment instruction to the second chip, and the second adjustment instruction is used to adjust the forward equalizer parameters of the second chip to the preset value.

[0032] As a possible design, the control circuit obtains M signal quality information based on the M optional values, including: the control circuit sends third adjustment instructions corresponding to the M optional values ​​to the second chip, the third adjustment instructions being used to adjust the forward equalizer parameters of the second chip to the optional values, and receiving the signal sent by the second chip when the forward equalizer parameters are adjusted to the M optional values; the control circuit obtains the signal quality information corresponding to the signal.

[0033] As a possible design, the interface circuit sending the target value to the second chip includes: the interface circuit sending a fourth adjustment instruction to the second chip, and the fourth adjustment instruction is used to adjust the forward equalizer parameters of the second chip to the target value.

[0034] As a possible design, the forward equalizer parameters include at least one of the following parameters: a front symbol setting parameter, a rear symbol setting parameter, and a main symbol setting parameter.

[0035] In a fourth aspect, a device for determining a parameter value is provided, which is applied to a first chip. The device includes a processor and a memory, wherein the memory is used to store a program that supports the device in executing the parameter value determination method provided in the first aspect, and to store data involved in implementing the parameter value determination method provided in the first aspect. The processor is configured to execute the program stored in the memory. The device may also include a communication bus for establishing a connection between the processor and the memory.

[0036] In a fifth aspect, a computer-readable storage medium is provided, characterized in that it includes instructions, programs or codes, which, when executed on a computer, enable the computer to execute the parameter value determination method as described in the first aspect above.

[0037] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the method for determining the parameter value described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A hardware architecture diagram of a system 10 to which the parameter value determination method provided in an embodiment of the present application may be applied;

[0039] Figure 2 A flow chart of a method for determining parameter values ​​provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of a device 300 for determining a parameter value provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of the structure of a device 400 provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of the structure of a device 500 provided in an embodiment of the present application;

[0043] Figure 6 A schematic structural diagram of a first chip 600 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In traditional technologies, the values ​​of the forward equalizer parameters of the transmitter's forward equalizer are determined based on human experience, making it difficult to guarantee the signal quality of the SerDes and unsuitable for various complex signal transmission scenarios.

[0045] In order to overcome this technical problem, the embodiments of the present application provide a method and device for determining parameter values, thereby achieving the purpose of improving the signal transmission quality of SerDes.

[0046] See also Figure 1 , which is a hardware architecture diagram of a system 10 to which the parameter value determination method provided in the embodiment of the present application may be applied. Figure 1 In the embodiment, system 10 includes chip 11 and chip 12. Chip 11 and chip 12 can both be interface chips and can be connected via a medium such as a cable or a backplane. Chip 11 and chip 12 can belong to the same device or different devices, such as a switch, a router, or a network adapter.

[0047] Chip 11 includes a transmitter 111 and a receiver 112, and chip 12 includes a transmitter 121 and a receiver 122. Transmitter 111 communicates with receiver 122, and transmitter 121 communicates with receiver 112. Signals transmitted between chip 11 and chip 12 may comply with the Institute of Electrical and Electronics Engineers (IEEE) 802.3 protocol or the Ethernet Alliance protocol.

[0048] In addition to the transmitter 111 and the receiver 112, the chip 11 may further include a processor 113, which is connected to the transmitter 111 and the receiver 112, respectively. In addition to the transmitter 121 and the receiver 122, the chip 12 may further include a processor 123, which is connected to the transmitter 121 and the receiver 122, respectively. The processors 113 and 123 may be a built-in central processing unit (CPU), a built-in general-purpose processor, a built-in digital signal processor (DSP), an application-specific integrated circuit (ASIC), a built-in field programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0049] The following combination Figure 1 Introducing the method for determining parameter values ​​provided in the embodiment of this application. Figure 2 , which is a flow chart of a method for determining parameter values. The method involves a first chip and a second chip. In the embodiment of the present application, the first chip may be chip 11 and the second chip may be chip 12. Figure 2 In the embodiment, the steps performed by the first chip may be performed by, for example, the processor 113 of the chip 11 , and the steps performed by the second chip may be performed by, for example, the processor 123 of the chip 12 .

[0050] The method for determining the parameter value includes the following steps:

[0051] S101: The first chip obtains N reference values ​​of forward equalizer parameters of the second chip.

[0052] The principle of the forward equalizer is to amplify the main symbol (Main-cursor), forward symbol (Pre-cursor), and / or backward symbol (Post-cursor) in the signal. In the embodiment of the present application, the action of amplifying the main symbol is called the main-cursor setting, the action of amplifying the forward symbol is called the forward symbol setting, and the action of amplifying the backward symbol is called the backward symbol setting. Therefore, the forward equalizer parameters can include one or more of the main symbol setting parameters, the forward symbol setting parameters, and the backward symbol setting parameters.

[0053] In an embodiment of the present application, the forward equalizer parameters of the second chip are parameters used by the second chip to perform forward equalization on the transmitted signal, that is, the forward equalizer parameters corresponding to the forward equalizer at the transmitting end of the second chip, including one or more of the main symbol setting parameters, forward symbol setting parameters and backward symbol setting parameters of the second chip.

[0054] In this embodiment of the present application, the forward equalizer parameters of the second chip have N reference values, which can be considered as a search space for the forward equalizer parameters. The so-called reference value refers to all possible values ​​of the forward equalizer parameters. In this embodiment of the present application, the forward equalizer parameters can take N reference values, where N is an integer greater than 1.

[0055] When the second chip includes multiple forward equalizer parameters, each forward equalizer parameter has multiple corresponding reference values. For example, if the second chip includes two forward equalizer parameters, namely a first forward equalizer parameter and a second forward equalizer parameter, the first forward equalizer parameter can have N1 reference values, and the second forward equalizer parameter can have N2 reference values, where both N1 and N2 are integers greater than 1. The values ​​of N1 and N2 can be equal or unequal.

[0056] It should be noted that when the second chip includes multiple forward equalizer parameters, the multiple forward equalizer parameters can belong to the same or different types of the three forward equalizer parameters mentioned above. For example, the first forward equalizer parameter and the second forward equalizer parameter can both be backward symbol setting parameters, that is, the first forward equalizer parameter is the first backward symbol setting parameter, and the second forward equalizer parameter is the second backward symbol setting parameter. Alternatively, the first forward equalizer parameter is the main symbol setting parameter, and the second forward equalizer parameter is the forward symbol setting parameter.

[0057] In an embodiment of the present application, the way in which the first chip obtains N reference values ​​of the forward equalizer parameters of the second chip can be through pre-configuration and storage on the first chip, or obtained from the memory through the interface circuit, or automatically obtained by interacting with the second chip. For example, the first chip can continuously send a first adjustment instruction to the second chip until an adjustment response from the second chip is received. The first adjustment instruction is used for the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step size based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value. Then, the first chip can obtain N reference values ​​of the forward equalizer parameter based on the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size and the preset value.

[0058] For example, assuming the preset value is 0 and the preset step size is 1, and the maximum value of the forward equalizer parameter is 5, it means that before the second chip receives the first adjustment instruction for the first time, the value of the forward equalizer parameter of the second chip is 0. After receiving the first adjustment instruction for the first time, the value of the forward equalizer parameter of the second chip is set to 1. Then the second chip determines whether the maximum value that the forward equalizer parameter can be set to has been reached. If not, no adjustment response is sent to the first chip. After the first chip sends the first adjustment instruction for the first time, if it does not receive an adjustment response from the second chip within the preset time period, it is considered that the forward equalizer parameter of the second chip has not reached the maximum value, so the first adjustment instruction is sent to the second chip for the second time. The second chip receives the first adjustment instruction sent by the first chip for the second time, and sets the value of the forward equalizer parameter of the second chip to 2 according to the first adjustment instruction sent for the second time, and again determines whether the maximum value that the forward equalizer parameter can be set to has been reached. And so on, until the second chip determines that the maximum value of the forward equalizer parameter has been reached after receiving the first adjustment instruction five times, the second chip sends an adjustment response to the first chip to inform the first chip that the value of the forward equalizer parameter has been set to the maximum value. Then, the first chip can determine that the maximum value of the forward equalizer parameter of the second chip is 5, and thus determine that the reference values ​​of the forward equalizer parameter of the second chip include 1, 2, 3, 4 and 5.

[0059] In the above example, the preset step size is a positive number. In some examples, the preset step size can also be a negative number to determine the minimum value of the forward equalization coefficient. In addition to positive numbers, the reference value of the forward equalizer parameter can also include negative numbers, depending on the actual situation. In actual applications, the first adjustment instruction can be to increase (increment) and / or decrease (decrement) frames.

[0060] Optionally, before sending the first adjustment instruction to the second chip, the first chip may also send a second adjustment instruction to the second chip, where the second adjustment instruction is used to adjust the forward equalizer parameters of the second chip to a preset value, so that the second chip can start adjustment from the preset value. In some examples, the second adjustment instruction may be a preset frame. In addition, in the above example, the preset value is 0, but in some examples, the preset value may not be 0.

[0061] By sending a first adjustment instruction from the first chip to the second chip, and the second chip returning an adjustment response to the first chip, the first chip can know the maximum and minimum values ​​of the forward equalizer parameters of the second chip, and thus determine all reference values ​​of the forward equalizer parameters based on the maximum and minimum values, thereby achieving the purpose of automatically obtaining N reference values ​​of the forward equalizer parameters. If there are multiple forward equalizer parameters, then the first chip can perform the above steps for each forward equalizer parameter separately to automatically determine the corresponding multiple reference values. In some examples, the first chip can send a corresponding first adjustment instruction for each forward equalizer parameter separately to adjust the value of each forward equalizer parameter in turn. In other examples, the first chip can also send a first adjustment instruction to adjust the values ​​of all forward equalizer parameters at the same time.

[0062] After obtaining N reference values ​​of the forward equalizer parameters, the first chip can determine a target value from the N reference values ​​that provides a better equalization effect (i.e., a higher quality signal received by the first chip), so that the second chip can perform forward equalization on the transmitted signal based on the target value of the forward equalizer parameter. For details, see the following steps:

[0063] S102: The first chip determines a first optional value set from N reference values, where the first optional value set includes M optional values.

[0064] In an embodiment of the present application, when the number of reference values ​​is large, in order to improve efficiency, the first chip does not traverse each reference value, but selects M optional values ​​from N reference values ​​to obtain corresponding signal quality information, where M is an integer greater than or equal to 1 and less than N.

[0065] If there are multiple forward equalizer parameters, the first chip can select a first set of optional values ​​from the reference value combinations corresponding to the multiple forward equalizer parameters. For example, if the forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter, the first forward equalizer parameter has N1 reference values, and the second forward equalizer parameter has N2 reference values, then there are a total of N1*N2 reference value combinations. Therefore, the first chip can determine M optional values ​​from the N1*N2 reference value combinations, where M is an integer greater than or equal to 1 and less than N1*N2.

[0066] There are multiple ways for the first chip to determine the first set of selectable values. As one possible implementation, the first chip may randomly select M selectable values ​​from N reference values. For example, the first chip randomly selects M selectable values ​​from N1*N2 reference value combinations.

[0067] As another possible implementation, the first chip can arrange the N reference values ​​in order from small to large or from large to small, and evenly select M optional values ​​from the arranged N reference values ​​to obtain a first optional value set. For example, the reference values ​​of the forward equalizer parameters include 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and the first optional value set can be 1, 4, 7 and 10. For another example, the reference values ​​of the first forward equalizer parameters (such as pre setting) include 1, 2, 3, 4 and 5, and the reference values ​​of the second forward equalizer parameters (such as post setting) include 1, 2, 3, 4 and 5. Then the reference value combination composed of these two forward equalizer parameters is shown in Table 1, and the first optional value set can include (2,2), (2,4), (4,2) and (4,4).

[0068] Table 1

[0069]

[0070] Of course, the above two possible implementations do not constitute a limitation on S102 , and those skilled in the art may design them on their own according to actual conditions.

[0071] S103: The first chip obtains M pieces of signal quality information according to the M optional values.

[0072] As one possible implementation method, if the first chip obtains N reference values ​​of the forward equalizer parameters through pre-configuration, then after determining the first set of optional values, the first chip can send a third adjustment instruction corresponding to each optional value to the second chip, and the third adjustment instruction is used to adjust the forward equalizer parameter of the second chip to the optional value. The second chip adjusts the value of the forward equalizer parameter to the optional value according to the third adjustment instruction, and sends a signal after forward equalization according to the optional value to the first chip. The first chip receives the signal and detects the signal quality of the signal to obtain signal quality information indicating the signal quality. At this point, the first chip obtains the signal quality information corresponding to each optional value.

[0073] As another possible implementation, if the first chip automatically obtains N reference values ​​for the forward equalizer parameters through interaction with the second chip, then when the first chip sends a first adjustment instruction corresponding to each reference value to the second chip, the second chip can adjust the value of the forward equalizer parameter to the reference value according to the first adjustment instruction and send a signal after forward equalization based on the reference value to the first chip. The first chip receives the signal and detects the signal quality of the signal to obtain signal quality information indicating the signal quality. At this point, the first chip obtains signal quality information corresponding to each reference value, including signal quality information corresponding to M optional values.

[0074] Of course, the above two possible implementations do not constitute a limitation on S103, and those skilled in the art may design the method themselves according to actual conditions.

[0075] In an embodiment of the present application, each of the M pieces of signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values. The signal quality information may, for example, be one or more of information related to an eye diagram, a signal-to-noise ratio (SNR), and a bit error rate (BER). Information related to the eye diagram may include eye diagram width, eye diagram height, eye diagram area, and the like.

[0076] S104: The first chip determines a target value according to the M pieces of signal quality information.

[0077] After acquiring the signal quality information corresponding to the M optional values, the first chip may determine the target value of the forward equalizer parameter based on the M signal quality information.

[0078] As one possible implementation, in an embodiment of the present application, the first chip determines the target value as the optional value corresponding to the signal quality information indicating the best signal quality among the M pieces of signal quality information. For example, the first chip determines the target value of the forward equalizer parameter as the optional value corresponding to the signal with the highest signal-to-noise ratio or the lowest bit error rate.

[0079] As another possible implementation, the first chip may determine the target value from the average of optional values ​​corresponding to W pieces of signal quality information with higher signal quality among the M pieces of signal quality information, where W is an integer greater than 1 and less than M.

[0080] As another possible implementation, S104 may be implemented through the following S1041-S1043:

[0081] S1041: The first chip determines a second set of selectable values ​​from the N reference values, where the second set of selectable values ​​includes selectable values ​​in the first set of selectable values ​​whose signal quality information satisfies a first preset condition and S reference values ​​surrounding the selectable values ​​that satisfy the first preset condition. The N reference values ​​include the S reference values, where S is an integer greater than or equal to 1 and less than N-1.

[0082] In this embodiment of the present application, if the signal quality information of a signal satisfies a first preset condition, the signal quality of the signal may be considered to be high. The optional value for the signal quality information satisfying the first preset condition may be one or more. The S reference values ​​surrounding the optional value satisfying the first preset condition refer to the S optional values ​​adjacent to the optional value for which the signal quality information satisfies the first preset condition after sorting the Nth reference value in descending order or in ascending order.

[0083] For example, assuming that the first optional value set includes (2,2), (2,4), (4,2) and (4,4) in Table 1, where the optional value with the highest signal-to-noise ratio of the corresponding signal is (2,4), then the four optional values ​​closest to the optional value (2,4) are (1,4), (2,3), (3,4) and (2,5) respectively.

[0084] S1042: The first chip obtains S pieces of signal quality information according to the S reference values.

[0085] To determine the target value from the second set of selectable values, the first chip obtains signal quality information corresponding to each selectable value and reference value in the second set of selectable values. Since the signal quality information of the selectable value that meets the first preset condition has been obtained in S103, the signal quality information corresponding to the remaining S reference values ​​in the second set of selectable values ​​can be obtained.

[0086] Similar to obtaining the signal quality information corresponding to the first optional value set, there are at least two possible implementation methods for obtaining the signal quality information of S reference values:

[0087] As one possible implementation method, if the first chip obtains N reference values ​​of the forward equalizer parameters through pre-configuration, then after determining the S reference values, the first chip can send adjustment instructions corresponding to each of the S reference values ​​to the second chip, and the adjustment instructions are used to adjust the forward equalizer parameters of the second chip to the reference values. The second chip adjusts the value of the forward equalizer parameter to the corresponding reference value according to the third adjustment instruction, and sends a signal after forward equalization according to the reference value to the first chip. The first chip receives the signal and detects the signal quality of the signal to obtain signal quality information representing the signal quality. At this point, the first chip obtains the signal quality information corresponding to each reference value in the S reference values.

[0088] As another possible implementation, if the first chip automatically obtains N reference values ​​for the forward equalizer parameters through interaction with the second chip, then when the first chip sends a first adjustment instruction corresponding to each reference value to the second chip, the second chip can adjust the value of the forward equalizer parameter to the reference value according to the first adjustment instruction and send a signal after forward equalization based on the reference value to the first chip. The first chip receives the signal and detects the signal quality of the signal to obtain signal quality information indicating the signal quality. At this point, the first chip obtains signal quality information corresponding to each reference value, including signal quality information corresponding to S reference values.

[0089] S1043: The first chip determines a target value according to the signal quality information corresponding to the optional values ​​meeting the first preset condition included in the second optional value set and the S pieces of signal quality information.

[0090] In an embodiment of the present application, as one possible implementation, the first chip may determine, as a target value, the selectable value or reference value representing the highest signal quality in the signal quality information corresponding to the second selectable value set. For example, the first chip may determine, as a target value for a forward equalizer parameter, the selectable value or reference value with the highest signal-to-noise ratio in the second selectable value set.

[0091] As another possible implementation, the first chip may use as the target value the average of multiple optional values ​​and / or reference values ​​of the signal quality information corresponding to the second optional value set that meet a second preset condition. The second preset condition, for example, is that the signal-to-noise ratio is greater than or equal to a threshold. The second preset condition may be the same as or different from the first preset condition.

[0092] The several possible implementation methods for obtaining the target value described above do not constitute a limitation on the technical solution of the present application, and those skilled in the art may design them on their own according to actual conditions.

[0093] In summary, the first chip performs two rounds of screening to obtain the target value of the forward equalizer parameter. Since the signal quality information will show a certain regularity as the reference value increases or decreases, that is, the signal quality information has a maximum value (maximum value or minimum value), the reference value around the reference value corresponding to the maximum value will increase with the increase of the distance from the reference value, and the corresponding signal quality information will roughly show an increasing or decreasing trend. Therefore, through the first round of screening, that is, the signal quality meets the first preset condition, the area where the maximum value may appear can be roughly determined. Then, by obtaining the optional values ​​within the area for the second round of screening, the maximum value can be determined more accurately, so that the signal quality received by the second chip from the first chip is the best. In an embodiment of the present application, the target value can be one, that is, the maximum value. Of course, in some special scenarios, it is not ruled out that the target value can be multiple.

[0094] In addition to the possible implementations described above, those skilled in the art may also implement S104 in other possible implementations, which are not specifically limited in the embodiments of the present application.

[0095] S105: The first chip sends the target value to the second chip.

[0096] After the target value of the forward equalizer parameter is determined, the first chip can send a fourth adjustment instruction to the second chip. The second chip adjusts the forward equalizer parameter to the target value according to the fourth adjustment instruction, and performs forward equalization on the signal sent to the first chip according to the target value, so that the first chip can receive a signal with higher signal quality.

[0097] In the embodiment of the present application, the first chip obtains N reference values ​​for the forward equalizer parameters of the second chip, determines M optional values ​​from the N reference values, and obtains signal quality information of the signal transmitted when the forward equalizer parameters of the second chip are adjusted to the M optional values. Based on the M signal quality information, a target value indicating higher signal quality is determined. Compared to the traditional empirical determination of forward equalizer parameter values, the embodiment of the present application can be applied to various different transmission scenarios, has a wider range of applications, and can achieve better forward equalization effects and improve the quality of transmitted signals. Furthermore, because the first chip selects M optional values ​​from the N reference values ​​to obtain their signal quality information, rather than obtaining signal quality information for all N reference values, the efficiency of determining the target value of the forward equalization reference is higher.

[0098] The process of determining the target value of the forward equalizer parameter by the first chip and performing forward equalization by the second chip based on the target value of the forward equalizer parameter can be called link training. In practical applications, link training can be performed periodically, so the link training time can be specified. If the link training time is exceeded, the first chip sends a training fail frame to the second chip to re-perform link training. For example, the Non-Return to Zero (NRZ) code is specified to be less than or equal to 500ms, and the Four Pulse Amplitude Modulation (PAM4) code is specified to be less than or equal to 3.5s.

[0099] In some examples, after initiating link training, the first chip performs timing. To avoid link training timeouts, after receiving the adjustment response from the second chip and determining N reference values ​​for the second chip's forward equalizer parameters, the first chip can send a training failure frame to the second chip to restart timing. After restarting timing, the second chip can use the N reference values ​​to perform S102 and subsequent steps, avoiding link training interruption due to reaching the link training time before the second chip determines the target values ​​for the forward equalizer parameters.

[0100] See also Figure 3 The present application also provides a parameter value determination device 300, which can achieve Figure 2 The function of the first chip in the embodiment shown. The parameter value determination device 300 includes a first acquisition unit 301, a first determination unit 302, a second acquisition unit 303, a second determination unit 304 and a sending unit 305. Among them, the first acquisition unit 301 is used to implement Figure 2 In the embodiment shown in S101, the first determining unit 302 is used to implement Figure 2 In the embodiment shown in S102, the second acquisition unit 303 is used to implement Figure 2 In the embodiment shown in S103, the second determining unit 304 is used to implement Figure 2 In the embodiment shown in S104, the sending unit 305 is used to implement Figure 2 S105 in the illustrated embodiment.

[0101] Specifically, the first acquisition unit 301 is configured to acquire N reference values ​​of forward equalizer parameters of the second chip, where N is an integer greater than 1, and the forward equalizer parameters are parameters used by the forward equalizer of the second chip to adjust a transmitted signal;

[0102] A first determining unit 302 is configured to determine a first selectable value set from the N reference values, where the first selectable value set includes M selectable values, where M is an integer greater than or equal to 1 and less than N;

[0103] A second acquiring unit 303 is configured to acquire M pieces of signal quality information according to the M optional values, where each piece of signal quality information in the M pieces of signal quality information indicates a signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values;

[0104] A second determining unit 304 is configured to determine a target value based on the M pieces of signal quality information, where the target value is used by a forward equalizer of the second chip to adjust a transmitted signal;

[0105] The sending unit 305 is configured to send the target value to the second chip.

[0106] Please refer to the above for the specific execution process Figure 2 The detailed description of the corresponding steps in the illustrated embodiment will not be repeated here one by one.

[0107] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. For example, in the above embodiment, the acquisition unit and the processing unit can be the same unit or different units. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0108] Figure 4 The structure diagram of a device 400 provided in an embodiment of the present application is shown in FIG. The parameter value determination device 300 in the above text can be Figure 4 See the device shown. Figure 4 The device 400 includes at least one processor 401 , a communication bus 402 and at least one network interface 404 . Optionally, the device 400 may further include a memory 403 .

[0109] Processor 401 can be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits (ICs) for controlling the execution of the program of the present application. The processor can be used to process the configuration file to implement the parameter value determination method provided in the embodiment of the present application.

[0110] For example, when Figure 2 The first chip in Figure 4 When implemented using the device shown, the processor can be used to obtain N reference values ​​of the forward equalizer parameters of the second chip, determine a first optional value set from the N reference values, where the first optional value set includes M optional values, obtain M signal quality information based on the M optional values, determine a target value based on the M signal quality information, and send the target value to the second chip.

[0111] The communication bus 402 is used to transmit information between the processor 401 , the network interface 404 and the memory 403 .

[0112] The memory 403 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions. The memory 403 may also be a random access memory (RAM) or other type of dynamic storage device that can store information and instructions. It may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 403 may exist independently and be connected to the processor 401 via the communication bus 402. The memory 403 may also be integrated with the processor 401.

[0113] Optionally, the memory 403 is used to store program codes or instructions for executing the solution of the present application, and the execution is controlled by the processor 401. The processor 401 is used to execute the program codes or instructions stored in the memory 403. The program code may include one or more software modules. Optionally, the processor 401 may also store program codes or instructions for executing the solution of the present application. In this case, the processor 401 does not need to read the program codes or instructions from the memory 403.

[0114] The network interface 404 can be a device such as a transceiver for communicating with other devices or a communication network, and the communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). In an embodiment of the present application, the network interface 404 can be used to receive messages sent by other nodes in the segment routing network, and can also send messages to other nodes in the segment routing network. The network interface 404 can be an Ethernet interface, a Fast Ethernet (FE) interface, or a Gigabit Ethernet (GE) interface.

[0115] In a specific implementation, as an embodiment, the device 400 may include multiple processors, such as Figure 4 4 and 5. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0116] Figure 5 It is a structural diagram of a device 500 provided in an embodiment of the present application. Figure 2 The first chip in the Figure 5 See the device shown. Figure 5As shown in the device structure diagram, device 500 includes a main control board (MCB) and one or more interface boards. The MCB is communicatively connected to the interface boards. The MCB, also known as a main processing unit (MPU) or route processor card, includes a CPU and memory. It is responsible for controlling and managing various components in device 500, including routing calculations, device management, and maintenance. The interface board, also known as a line processing unit (LPU) or line card, is used to receive and send messages. In some embodiments, communication between the MCB and the interface boards, or between the interface boards, occurs via a bus. In some embodiments, the interface boards communicate via a switching fabric board (SFB). In this case, device 500 also includes a SFB, which is communicatively connected to the MCB and the interface boards. The SFB is used to forward data between the interface boards and is also referred to as a switch fabric unit (SFU). The interface board includes a CPU, memory, a forwarding engine, and an interface card (IC). The interface card may include one or more network interfaces. The network interface may be an Ethernet interface, a FE interface, or a GE interface. The CPU is communicatively connected to the memory, forwarding engine, and interface card. The memory is used to store a forwarding table. The forwarding engine is used to forward received messages based on the forwarding table stored in the memory. If the destination address of the received message is the IP address of device 500, the message is sent to the CPU of the main control board or interface board for processing. If the destination address of the received message is not the IP address of device 500, the forwarding engine searches the forwarding table based on the destination address. If the next hop and outgoing interface corresponding to the destination address are found in the forwarding table, the message is forwarded to the outgoing interface corresponding to the destination address. The forwarding engine can be a network processor (NP). The interface card, also known as a daughter card, can be installed on the interface board and is responsible for converting optical signals into data frames, performing a validity check on the data frames, and forwarding them to the forwarding engine or the interface board CPU for processing. In some embodiments, the CPU can also perform the functions of the forwarding engine, such as implementing soft forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding engine on the interface board. In some embodiments, the forwarding engine can be implemented using an ASIC or a field programmable gate array (FPGA). In some embodiments, the memory that stores the forwarding table can also be integrated into the forwarding engine as part of the forwarding engine.

[0117] See also Figure 6The embodiment of the present application further provides a first chip 600, comprising a control circuit 610 and an interface circuit 630. The control circuit 610 and the interface circuit 630 are connected via a communication line 620. The interface circuit 630 is used to connect the chip 300 to other communication devices via a communication link.

[0118] Specifically, the control circuit 610 and the interface circuit 630 are used to execute the above Figure 2 The function of the first chip in the illustrated embodiment. For example, the interface circuit 630 is used to obtain N reference values ​​of the forward equalizer parameters of the second chip, where N is an integer greater than 1, and the forward equalizer parameters are parameters used by the forward equalizer of the second chip to adjust the transmitted signal. The control circuit 610 is used to determine a first optional value set from the N reference values, where the first optional value set includes M optional values, where M is an integer greater than or equal to 1 and less than N; obtain M signal quality information based on the M optional values, each signal quality information in the M signal quality information indicates the signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value among the M optional values; determine a target value based on the M signal quality information, where the target value is used by the forward equalizer of the second chip to adjust the transmitted signal. The interface circuit 630 is also used to send the target value to the second chip.

[0119] Optionally, the control circuit in the first chip may be one or more, the control circuit may be a logic circuit, an integrated circuit, etc. Optionally, the interface circuit in the first chip may also be one or more.

[0120] Exemplarily, the first chip may be an FPGA, an ASIC, a system on chip (SoC), a CPU, an NP, a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0121] It should be understood that each step in the above method embodiment can be completed by hardware integrated logic circuits in a processor or by software instructions. The method steps disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or by a combination of hardware and software modules in a processor.

[0122] An embodiment of the present application also provides a computer-readable storage medium, including instructions, which, when executed on a computer, enables the computer to execute the parameter value determination method provided in the above method embodiment and executed by the first chip.

[0123] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the parameter value determination method provided in the above method embodiment and executed by the first chip.

[0124] The present application also provides a system comprising: Figure 2 A first chip and a second chip in the illustrated embodiment.

[0125] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0126] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical module division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0128] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be obtained based on actual needs to achieve the objectives of this embodiment.

[0129] In addition, each module unit in each embodiment of the present application can be integrated into a processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or software module units.

[0130] If the integrated unit is implemented in the form of a software module unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0131] Those skilled in the art will appreciate that in one or more of the above examples, the functions described herein can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0132] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are merely specific implementation methods of the present invention.

[0133] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for determining a parameter value, characterized in that: The method comprises: The first chip acquires N reference values ​​of a forward equalizer parameter of the second chip, where N is an integer greater than 1, and the forward equalizer parameter is a parameter used by the forward equalizer of the second chip to adjust a transmitted signal, and the forward equalizer parameter includes one or more of a main symbol setting parameter, a forward symbol setting parameter, and a backward symbol setting parameter; The first chip determines a first optional value set from the N reference values, where the first optional value set includes M optional values, where M is an integer greater than or equal to 1 and less than N; The first chip acquires M pieces of signal quality information according to the M optional values, each piece of signal quality information in the M pieces of signal quality information indicating a signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value in the M optional values; The first chip determines a target value according to the M signal quality information, and the target value is used by the forward equalizer of the second chip to adjust the transmitted signal; The first chip sends the target value to the second chip.

2. The method according to claim 1, characterized in that The first chip determines a first set of optional values ​​from the N reference values, including: The first chip arranges the N reference values ​​in an order from small to large or from large to small; The first chip uniformly selects the M optional values ​​from the arranged N reference values ​​to obtain the first optional value set.

3. The method according to claim 1 or 2, characterized in that: Determining the target value according to the M pieces of signal quality information includes: The first chip determines a second optional value set from the N reference values, where the second optional value set includes optional values ​​whose signal quality information satisfies a first preset condition in the first optional value set and S reference values ​​around the optional values ​​that satisfy the first preset condition, and the N reference values ​​include the S reference values; The first chip acquires S pieces of signal quality information according to the S reference values, each piece of signal quality information in the S pieces of signal quality information indicating a signal quality when the value of the forward equalizer parameter is adjusted to a corresponding reference value in the S reference values; The first chip determines a target value according to the signal quality information corresponding to the optional values ​​that meet the first preset condition and are included in the second optional value set and the S pieces of signal quality information.

4. The method according to claim 1 or 2, characterized in that: The first chip determines the target value according to the M signal quality information, including: The first chip determines an optional value corresponding to the signal quality information indicating the best signal quality among the M pieces of signal quality information as a target value.

5. The method according to any one of claims 1-2, characterized in that: The forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter; The first chip acquiring N reference values ​​of the forward equalizer parameters of the second chip includes: The first chip acquires N1 reference values ​​of a first forward equalizer parameter and N2 reference values ​​of a second forward equalizer parameter of the second chip, wherein both N1 and N2 are integers greater than 1; The first chip determines a first set of optional values ​​from the N reference values, including: The first chip determines a first optional value set from the N1 reference values ​​and the N2 reference values, the first optional value set includes M optional values, and M is an integer greater than or equal to 1 and less than N1*N2.

6. The method according to any one of claims 1-2, characterized in that: The first chip acquiring N reference values ​​of the forward equalizer parameters of the second chip includes: The first chip sends a first adjustment instruction to the second chip until receiving an adjustment response from the second chip, wherein the first adjustment instruction is used for the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step length based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value; The first chip obtains the N reference values ​​of the forward equalizer parameter according to the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size, and the preset value.

7. The method according to claim 6, characterized in that Before the first chip sends the first adjustment instruction to the second chip, the method further includes: The first chip sends a second adjustment instruction to the second chip, where the second adjustment instruction is used to adjust a forward equalizer parameter of the second chip to the preset value.

8. The method according to any one of claims 1-2, characterized in that: The first chip acquiring M pieces of signal quality information according to the M optional values ​​includes: The first chip sends third adjustment instructions respectively corresponding to the M optional values ​​to the second chip, where the third adjustment instructions are used to adjust a forward equalizer parameter of the second chip to the optional value, and receives a signal sent by the second chip when the forward equalizer parameter is adjusted to the M optional values; The first chip obtains signal quality information corresponding to the signal.

9. The method according to any one of claims 1-2, characterized in that: The first chip sending the target value to the second chip includes: The first chip sends a fourth adjustment instruction to the second chip, where the fourth adjustment instruction is used to adjust a forward equalizer parameter of the second chip to the target value.

10. The method according to any one of claims 1-2, characterized in that: The signal quality information includes at least one of the following: Eye width, eye height, eye area, signal-to-noise ratio and bit error rate.

11. A first chip, characterized in that: The first chip includes a control circuit and an interface circuit; The interface circuit is used to obtain N reference values ​​of the forward equalizer parameters of the second chip, where N is an integer greater than 1, and the forward equalizer parameters are parameters used by the forward equalizer of the second chip to adjust the transmitted signal, and the forward equalizer parameters include one or more of main symbol setting parameters, forward symbol setting parameters, and backward symbol setting parameters; The control circuit is configured to determine a first optional value set from the N reference values, the first optional value set including M optional values, where M is an integer greater than or equal to 1 and less than N; obtain M signal quality information according to the M optional values, each signal quality information in the M signal quality information indicating a signal quality when the value of the forward equalizer parameter is adjusted to a corresponding optional value in the M optional values; determine a target value according to the M signal quality information, the target value being used for the forward equalizer of the second chip to adjust the transmitted signal; The interface circuit is further used to send the target value to the second chip.

12. The first chip according to claim 11, characterized in that: The control circuit determines a first set of selectable values ​​from the N reference values, including: The control circuit arranges the N reference values ​​in order from small to large or from large to small, and uniformly selects the M optional values ​​from the arranged N reference values ​​to obtain the first optional value set.

13. The first chip according to claim 11 or 12, characterized in that: The control circuit determines the target value according to the M signal quality information, including: The control circuit determines a second optional value set from the N reference values, where the second optional value set includes optional values ​​whose signal quality information satisfies a first preset condition in the first optional value set and S reference values ​​around the optional values ​​that satisfy the first preset condition, and the N reference values ​​include the S reference values; The control circuit acquires S pieces of signal quality information according to the S reference values, each piece of signal quality information in the S pieces of signal quality information indicating a signal quality when the value of the forward equalizer parameter is adjusted to a corresponding reference value in the S reference values; The control circuit determines a target value according to the signal quality information corresponding to the optional values ​​that meet the first preset condition and are included in the second optional value set and the S pieces of signal quality information.

14. The first chip according to claim 11 or 12, characterized in that: The control circuit determines the target value according to the M signal quality information, including: The control circuit determines the optional value corresponding to the signal quality information indicating the best signal quality among the M signal quality information as the target value.

15. The first chip according to any one of claims 11 to 12, characterized in that: The forward equalizer parameters include a first forward equalizer parameter and a second forward equalizer parameter; The interface circuit acquires N reference values ​​of the forward equalizer parameters of the second chip, including: The interface circuit acquires N1 reference values ​​of the first forward equalizer parameter and N2 reference values ​​of the second forward equalizer parameter of the second chip, wherein both N1 and N2 are integers greater than 1; The control circuit determines a first set of selectable values ​​from the N reference values, including: The control circuit determines a first optional value set from the N1 reference values ​​and the N2 reference values, where the first optional value set includes M optional values, where M is an integer greater than or equal to 1 and less than N1*N2.

16. The first chip according to any one of claims 11 to 12, characterized in that: The interface circuit acquires N reference values ​​of the forward equalizer parameters of the second chip, including: The interface circuit sends a first adjustment instruction to the second chip until an adjustment response is received from the second chip, wherein the first adjustment instruction is used for the second chip to adjust the value of the forward equalizer parameter of the second chip according to a preset step length based on a preset value, and the adjustment response is used to indicate that the value of the forward equalizer parameter reaches a maximum value and / or a minimum value; The interface circuit obtains the N reference values ​​of the forward equalizer parameter according to the number of times the first adjustment instruction is sent before receiving the adjustment response, the preset step size and the preset value.

17. The first chip according to claim 16, characterized in that: The interface circuit is further used to send a second adjustment instruction to the second chip before sending the first adjustment instruction to the second chip, wherein the second adjustment instruction is used to adjust the forward equalizer parameter of the second chip to the preset value.

18. The first chip according to any one of claims 11 to 12, characterized in that: The control circuit acquiring M pieces of signal quality information according to the M optional values ​​includes: The control circuit sends third adjustment instructions respectively corresponding to the M optional values ​​to the second chip, wherein the third adjustment instructions are used to adjust the forward equalizer parameters of the second chip to the optional values, and receives a signal sent by the second chip when the forward equalizer parameters are adjusted to the M optional values; The control circuit obtains signal quality information corresponding to the signal.

19. The first chip according to any one of claims 11 to 12, characterized in that: The interface circuit sending the target value to the second chip includes: The interface circuit sends a fourth adjustment instruction to the second chip, where the fourth adjustment instruction is used to adjust a forward equalizer parameter of the second chip to the target value.

20. A computer-readable storage medium, characterized in that: The method comprises instructions, programs or codes, which, when executed on a computer, enable the computer to execute the method for determining a parameter value according to any one of claims 1 to 10.

21. A device for determining a parameter value, characterized in that: Applied to the first chip, the device includes a memory and a processor, the memory is used to store instructions or program codes, and the processor is used to call and run the instructions or program codes from the memory to execute the parameter value determination method as described in any one of claims 1-10.

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