SoC software and hardware collaborative verification system and method based on FPGA prototype

Abstract

The present invention provides a SoC software and hardware collaborative verification system and method based on an FPGA prototype, wherein the system includes multiple computers, connected to at least a first set of FPGA prototype verification platforms on the multiple computers through a physical interface, and connected to at least a second set of FPGA prototype verification platforms on the multiple computers through a physical interface. The present invention satisfies the high-performance SoC interface classification test operation by setting up two sets of FPGA prototype verification platforms, wherein the first set of FPGA prototype verification platforms is used for general interface transfer test verification, and the second set of FPGA prototype verification platforms is used for special interface transfer test verification. The present invention adopts a modular design concept and improves the collaborative verification method based on FPGA prototypes. The system and method provided by the present invention have strong reusability, avoid repeated development of multiple systems, greatly improve the verification progress before chip tape-out, and shorten the integration time of software and hardware.

Description

Technical Field

[0001] The present invention relates to the field of IC simulation verification, and in particular to a SoC software and hardware collaborative verification system and method based on FPGA prototype. Background Art

[0002] In SoC design, software-hardware co-verification is to run the software on a simulated hardware model before the chip is taped out to ensure that there are no hardware design defects. Software-hardware co-verification is a verification technology developed for SoC technology. Its main purpose is to verify the function and timing of the software-hardware interface of the SoC chip, solve the integration problem of SoC software and hardware, and develop and debug application software in advance before the chip is taped out, shortening the development cycle of the entire project.

[0003] At present, there are two main types of software and hardware co-verification methods: co-verification based on simulation platforms and co-verification based on FPGA prototypes.

[0004] Collaborative verification based on the simulation platform is to integrate the developed simulation components and the hardware design RTL code together to form a virtual environment that can simulate the actual working process of the chip. Various simulation components are used to simulate the peripheral devices of the actual working of the chip. Compared with the FPGA prototype verification platform, the simulation platform has low cost and is easy to quickly find and locate errors, but the overall efficiency is low.

[0005] The collaborative verification method based on FPGA prototype uses the actual hardware environment to simulate the working conditions of the chip in the actual environment during verification, which is more realistic than the simulation verification environment. First, the SoC logic design is synthesized, laid out, and routed, and then verified on the FPGA prototype verification platform. Using the programmable characteristics of FPGA, the logic design is repeatedly modified until a satisfactory result is achieved, avoiding the high cost and high risk caused by multiple tape-outs. The verification speed is fast enough, but it is not convenient for debugging operations.

[0006] Based on the collaborative verification method of FPGA prototype, the present invention proposes a high-performance SoC software and hardware collaborative verification method based on a mature architecture and easy to debug and transplant. Summary of the invention

[0007] The present invention provides a SoC software-hardware collaborative verification system and method based on FPGA prototype to address the deficiencies of the above-mentioned prior art. On the basis of the collaborative verification method of FPGA prototype, a high-performance SoC software-hardware collaborative verification method based on a mature architecture and easy to debug and transplant is proposed, which has strong practicality.

[0008] In order to achieve the purpose of the present invention, the following technologies are proposed:

[0009] In one aspect, the present invention provides a SoC software and hardware collaborative verification system based on FPGA prototype, comprising a plurality of computers, at least a first set of FPGA prototype verification platforms connected to the plurality of computers via a physical interface, and at least a second set of FPGA prototype verification platforms connected to the plurality of computers via a physical interface;

[0010] The first FPGA prototype verification platform is used for universal interface transfer test verification;

[0011] The second FPGA prototype verification platform is used for dedicated interface transfer test verification.

[0012] Furthermore, the first FPGA prototype verification platform includes a first debugger connected to multiple computers via USB, the first debugger is connected to the first FPGA prototype verification board via JTAG1, multiple computers are connected to a universal interface board via serial port and / USB, the universal interface board is connected to a first expansion daughter board, the first expansion daughter board is connected to the first FPGA prototype verification board, multiple computers are connected to a first SoC debugger via a network port, and the first SoC debugger is connected to the first FPGA prototype verification board via JTAG2.

[0013] Furthermore, the second FPGA prototype verification platform includes a second debugger connected to multiple computers via USB, the second debugger is connected to the second FPGA prototype verification board via JTAG3, multiple computers are connected to multiple dedicated interface boards via serial ports and / USB, the dedicated interface boards are connected to multiple second expansion sub-boards, the second expansion sub-boards are connected to the second FPGA prototype verification board, multiple computers are connected to the second FPGA prototype verification board via network ports, multiple computers are connected to the second SoC debugger via USB, and the second SoC debugger is connected to the second FPGA prototype verification board via JTAG4.

[0014] Furthermore, the first debugger downloads the SoC prototype to the first FPGA prototype verification board through JTAG1.

[0015] Furthermore, the first SoC debugger is used for downloading and debugging programs of the SoC soft core.

[0016] Furthermore, the second debugger downloads the SoC prototype to the second FPGA prototype verification board through JTAG3.

[0017] Furthermore, the second SoC debugger is used for downloading and debugging programs of the SoC soft core.

[0018] On the other hand, the present invention also provides a high-performance SoC software and hardware co-verification method based on FPGA prototype, which is implemented by a SoC software and hardware co-verification system based on FPGA prototype, comprising the steps of:

[0019] Step a, downloading the integrated RTL code to the main FPGA in the first FPGA prototype verification board or the second FPGA prototype verification board through JTAG1 or JTAG3 after ISE synthesis, so that the CPU is located in the FPGA in a soft core mode;

[0020] Step b, downloading the development code of the first SoC debugger or the second SoC debugger to the high-performance SoC core solidified by the main FPGA of the first FPGA prototype verification board or the second FPGA prototype verification board through JTAG2 or JTAG4 through the IDE to debug the test program;

[0021] Step c, verifying the universal interface transfer test and the dedicated interface transfer test by using the test software in the computer;

[0022] Among them, the general interface transfer test verification is used for CPU core performance test and peripheral function test verification, and the dedicated interface transfer test verification is used for user customized interface and high-speed bus interface test verification;

[0023] Step d, integrating the test codes of the general interface transfer test verification and the dedicated interface transfer test verification.

[0024] Furthermore, the universal interface transfer test verification includes the steps of:

[0025] Step 01, providing power to the universal interface board through a program-controlled voltage-stabilized power supply;

[0026] Step 02, the computer runs the test software therein, and causes the test software to send a test function command to the universal interface board;

[0027] Step 03, the universal interface board sends a test stimulus signal to the first expansion sub-board;

[0028] Step 04, the first expansion board transmits the signal to the high-performance SoC soft core through the first FPGA prototype verification board according to the test stimulus signal sent by the universal interface board;

[0029] Step 05, under the action of the excitation signal, the high-performance SoC soft core generates signal data and outputs the SoC processor output signal to the universal interface board through the first expansion daughter board;

[0030] Step 06, the universal interface board sends a test data packet to the computer according to the output signal of the SoC processor;

[0031] Step 07, the computer displays the status of the universal interface board, displays the CPU core performance test results, displays the test results of the high-performance SoC core, and receives the test results of the universal interface board memory and registers in real time through the test data packet, and displays the test results in a table.

[0032] Further, the dedicated interface transfer test verification includes the steps of:

[0033] Step 11, the test software in the computer sends a test function command to multiple dedicated interface boards;

[0034] Step 12, multiple dedicated interface boards send test stimulus signals to multiple second expansion sub-boards;

[0035] Step 13, multiple second expansion daughter boards provide the high-performance SoC soft core as signal input through the second FPGA prototype verification board according to the test stimulus signal, and simulate the 1553B interface, Spacewire interface, and Xilinx JTAG protocol conversion interface in the SoC soft core to receive input signals;

[0036] Step 14, the plurality of second expansion daughter boards send SoC processor output signals to the plurality of dedicated interface boards according to the test stimulus signals of the analog input of the high-performance SoC soft core;

[0037] Step 15, multiple dedicated interface boards send test data packets to the computer according to the SOC processor;

[0038] Step 16, the computer displays the 1553B interface test results according to the test data packet, displays the Spacewire configuration, mode selection and node transmission, and provides the FPGA test bit file downloaded by the Xilinx JTAG protocol conversion module.

[0039] The advantages of the above technical solution are:

[0040] 1. The present invention uses a SoC hardware and software collaborative verification system and method based on FPGA prototype. The system and method take the complexity of verification and the feasibility of test as the starting point, and plan the verification items in a unified manner, unifying the types of interface test boards. Avoid designing a wide variety of expansion boards, functional verification boards, test cables, and test software with different functions.

[0041] 2. The universal bus test board and supporting interface board are designed and debugged in advance. After the key modules of the chip front end are integrated, the universal interface function and timing verification can be carried out immediately, which greatly improves the verification progress before chip tape-out and shortens the development cycle.

[0042] 3. For the development of multiple IPs, the main difference in verification is reflected in the peripheral interface IP. By using the universal bus interface test, the platform has strong reusability and can be easily transplanted to the development of other processor SoC, ASIC, microsystem SiP and other products.

[0043] In summary, the present invention satisfies the high-performance SoC interface classification test operation by setting up two sets of FPGA prototype verification platforms, wherein the first set of FPGA prototype verification platforms is used for general interface transfer test verification, and the second set of FPGA prototype verification platforms is used for special interface transfer test verification. The present invention adopts a modular design concept and improves the collaborative verification method based on FPGA prototype. The system and method provided by the present invention have strong reusability, avoids repeated development of multiple systems, reduces the workload of preliminary preparation, greatly improves the verification progress before chip tape-out, shortens the integration time of software and hardware, and can facilitate designers to develop application software. It is generally applicable to the design and verification process of ASIC chips with multiple interfaces and has strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0045] Figure 1 The structure diagram of the SoC hardware and software co-verification system based on FPGA prototype is shown.

[0046] Figure 2 Shows the FPGA prototyping board block diagram.

[0047] Figure 3 A general interface transfer test verification flow chart is shown.

[0048] Figure 4 A dedicated interface transfer test verification flow chart is shown. DETAILED DESCRIPTION

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a SoC hardware and software collaborative verification system based on FPGA prototype, including multiple computers, at least a first set of FPGA prototype verification platforms connected to the multiple computers through physical interfaces, and at least a second set of FPGA prototype verification platforms connected to the multiple computers through physical interfaces. The first set of FPGA prototype verification platforms is used for general interface transfer test verification, and the second set of FPGA prototype verification platforms is used for special interface transfer test verification, wherein the physical interfaces mainly include serial ports, network ports, USB ports, etc.

[0051] The differences between the first FPGA prototype verification platform and the second FPGA prototype verification platform are as follows: First, the I / Os with different functions on the FPGA verification board are brought out through different expansion daughter boards; second, the first FPGA prototype verification platform is only connected to the general interface board to realize the general interface transfer test and verification; the second FPGA prototype verification platform can be connected to multiple special interface test boards to realize the transfer test and verification of user-customized special interfaces and high-speed interfaces; the test network supports cross-data access by multiple computers.

[0052] The first FPGA prototype verification platform includes a first debugger connected to multiple computers via USB, the first debugger is connected to a first FPGA prototype verification board via JTAG1, multiple computers are connected to a universal interface board via a serial port and / USB, the universal interface board is connected to a first expansion sub-board, the first expansion sub-board is connected to the first FPGA prototype verification board, multiple computers are connected to a first SoC debugger via a network port, and the first SoC debugger is connected to the first FPGA prototype verification board via JTAG2. The first debugger downloads the SoC prototype to the first FPGA prototype verification board via JTAG1, and the first SoC debugger is used for downloading and debugging the program of the SoC soft core.

[0053] The second FPGA prototype verification platform includes a second debugger connected to multiple computers via USB, the second debugger is connected to a second FPGA prototype verification board via JTAG3, multiple computers are connected to multiple dedicated interface boards via serial ports and / USB, the dedicated interface boards are connected to multiple second extension sub-boards, the second extension sub-boards are connected to the second FPGA prototype verification board, multiple computers are connected to the second FPGA prototype verification board via network ports, multiple computers are connected to a second SoC debugger via USB, and the second SoC debugger is connected to the second FPGA prototype verification board via JTAG4. The second debugger downloads the SoC prototype to the second FPGA prototype verification board via JTAG3, and the second SoC debugger is used for program download and debugging of the SoC soft core.

[0054] Among them, the FPGA prototype verification system in this embodiment connects two sets of FPGA prototype verification platforms, and multiple sets of FPGA prototype verification platforms can also be connected on this basis. However, considering that adding FPGA prototype verification platforms will lead to a surge in costs, generally no more than 4 sets of FPGA prototype verification platforms will be connected. Due to the complexity of SoC design, it is necessary to use a high-speed and large-capacity FPGA for prototype verification. And the FPGA resources occupied by the design should not exceed 80%, otherwise it will lead to a decrease in the performance of the design circuit. Therefore, in order to meet the needs, the FPGA prototype verification board uses S2C's Virtex-7 2000TFPGA fast SoC prototype verification hardware. Figure 2This is the block diagram of the FPGA prototype verification board. The FPGA has 20 million ASIC gates inside, which fully meets the verification requirements. The FPGA prototype verification board integrates USB, SD slot, PHY and other interfaces, and has a large number of I / O ports for connecting expansion boards to achieve functional expansion and Probe testing during debugging.

[0055] Among them, the implementation of the FPGA prototype system is to download the logic synthesis after the integration of the key modules of the high-performance SoC processor to the memory of the FPGA prototype verification board. After the FPGA prototype verification board is powered on, the microprocessor in it starts to obtain and execute instructions from the memory of the FPGA prototype verification board, and the signal input and output of the high-performance SoC processor are completed through other peripheral devices, which can achieve the same effect as the actual working process of the high-performance SoC processor.

[0056] Among them, after the high-performance SoC processor is converted from ASIC design to FPGA design, it is downloaded to the FPGA prototype verification board in the form of RTL code after synthesis, layout and routing, that is, the digital part is all implemented in the FPGA prototype verification board. The FPGA design process is mainly divided into several steps: design input, logic synthesis, functional simulation, design implementation, timing simulation, configuration download, and board-level debugging.

[0057] The execution process of SoC verification software is to synthesize the logic of the key modules of SoC into RTL code, and then run the verification software on two FPGA prototype verification platforms to perform hardware and software co-verification. The test cases used in hardware and software co-simulation only need simple modifications, such as address space allocation, which can be quickly transplanted to two FPGA prototype verification platforms for FPGA-level verification of corresponding modules, which improves the efficiency of chip FPGA verification to a certain extent.

[0058] In order to facilitate the implementation of general interface transfer test verification and user-customized special interface and high-speed interface transfer test verification through the above-mentioned first FPGA prototype verification platform and the second FPGA prototype verification platform, the high-performance SoC interface is divided into two categories.

[0059] General interface transfer test, mainly for CPU core and low-speed interface test, including: CPU core performance (Dhrystone, Coremark, L1-Cache, FPU, etc.) and peripheral function (GPIO, UART, I2C, CAN, LocalBus, etc.) test.

[0060] The transfer test of dedicated interface and high-speed interface is mainly for user customized interface and high-speed interface test. The user customized interface is 1553B interface, Spacewire, Xilinx JTAG protocol conversion module and other test units. The dedicated bus interface test can design one or more dedicated interface boards. In this way, a feature-rich dedicated data interface is provided, which provides various means for system debugging and covers the SoC chip functions as much as possible.

[0061] Example 2

[0062] On the other hand, the present invention also provides a SoC software and hardware co-verification method based on FPGA prototype, which is implemented by a SoC software and hardware co-verification system based on FPGA prototype, comprising the steps of:

[0063] Step a, after being synthesized by ISE, the RTL code of the integrated key modules of the SOC processor is downloaded to the main FPGA in the first FPGA prototype verification board or the second FPGA prototype verification board by JTAG1 or JTAG3, so that the CPU is located in the FPGA in a soft core manner;

[0064] Step b, downloading the development code of the first SoC debugger or the second SoC debugger to the high-performance SoC core solidified by the main FPGA of the first FPGA prototype verification board or the second FPGA prototype verification board through JTAG2 or JTAG4 through the IDE to debug the test program;

[0065] Step c, verifying the universal interface transfer test and the dedicated interface transfer test by using the test software in the computer;

[0066] Among them, the general interface transfer test verification is used for CPU core performance test and peripheral function test verification, and the dedicated interface transfer test verification is used for user customized interface and high-speed bus interface test verification;

[0067] Step d, integrating the test codes of the general interface transfer test verification and the dedicated interface transfer test verification.

[0068] Among them, the first set of FPGA prototype verification boards and the second set of FPGA prototype verification boards can download high-performance SoC soft-core RTL codes with the same functions, and distinguish the multiplexing relationship of the lead pins according to the connection relationship of the corresponding expansion daughter board. The high-performance SoC soft-core RTL code peripheral interface IP can also be divided and then downloaded to different FPGA prototype verification boards to facilitate large-scale integrated circuit design.

[0069] like Figure 3 As shown, the universal interface transfer test verification includes the following steps:

[0070] Step 01, providing power to the universal interface board through a program-controlled voltage-stabilized power supply;

[0071] Step 02, the computer runs the test software therein, and causes the test software to send a test function command to the universal interface board;

[0072] Step 03, the universal interface board sends a test stimulus signal to the first expansion sub-board;

[0073] Step 04, the first expansion board transmits the signal to the high-performance SoC soft core through the first FPGA prototype verification board according to the test stimulus signal sent by the universal interface board;

[0074] Step 05, under the action of the excitation signal, the high-performance SoC soft core generates signal data and outputs the SoC processor output signal to the universal interface board through the first expansion daughter board;

[0075] Step 06, the universal interface board sends a test data packet to the computer according to the output signal of the SoC processor;

[0076] Step 07, the computer displays the status of the universal interface board, the CPU core performance test results, the high-performance SoC core test results, and receives the test results of the memory and registers of the universal interface board in real time through the feedback data packet, and displays the test results in a table. The universal interface board status test includes whether the initialization is normal, the general interface status, etc. Provide an online injection test program interface to allow online modification of the first FPGA prototype verification board software. Display the CPU core performance (Dhrystone, Coremark, L1-Cache, FPU, etc.) test results. Display the high-performance processor SoC core (GPIO, UART, CAN, I2C, LocalBus, etc.) test results. Issue test instructions through the computer's test interface, receive the memory and register test results of the universal interface board in real time for processing and judgment, and display them in a table.

[0077] like Figure 4As shown in the figure, the dedicated interface transfer test verification is different from the general interface transfer test verification. The dedicated interface transfer test verification is completed by one or more second expansion daughter boards and one or more dedicated interface boards. It mainly completes the user customized interface and high-speed bus interface test. The dedicated bus interface of the high-performance SoC processor includes: 1553B interface, Spacewire interface and Xilinx JTAG protocol conversion interface. Among them, the 1553B bus is a command response bus, one master and multiple slave working mode, half-duplex communication, and the communication rate is 1Mbps. Its notable features are high reliability and strong real-time military serial bus, which can complete information integration, resource sharing, task coordination and fault-tolerant reconstruction. It is widely used in aerospace electronic integrated systems. SpaceWire is a bus that is widely concerned in the aerospace field and shows broad application prospects. It is characterized by high speed, high reliability, low power consumption, error detection and recovery capabilities. The JTAG protocol conversion module is designed to shift the JTAG vector to the target Xilinx FPGA associated with each other, supporting JTAG download and debugging of XILINX FPGA.

[0078] Dedicated interface transfer test verification includes the following steps:

[0079] Step 11, the test software in the computer sends a test function command to multiple dedicated interface boards;

[0080] Step 12, multiple dedicated interface boards send test stimulus signals to multiple second expansion sub-boards;

[0081] Step 13, multiple second expansion daughter boards provide the high-performance SoC soft core as signal input through the second FPGA prototype verification board according to the test stimulus signal, and simulate the 1553B interface, Spacewire interface, and Xilinx JTAG protocol conversion interface in the SoC soft core to receive input signals;

[0082] Step 14, the plurality of second expansion daughter boards send SoC processor output signals to the plurality of dedicated interface boards according to the test stimulus signals of the analog input of the high-performance SoC soft core;

[0083] Step 15, multiple dedicated interface boards send test data packets to the computer according to the SOC processor;

[0084] Step 16, the computer displays the 1553B interface test results according to the test data packet, displays the Spacewire configuration, mode selection and node transmission, and provides the FPGA test bit file downloaded by the Xilinx JTAG protocol conversion module.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. SoC software and hardware co-verification method based on FPGA prototype, implemented through SoC software and hardware co-verification system based on FPGA prototype, The FPGA prototype-based SoC hardware and software collaborative verification system includes multiple computers, connected to at least a first set of FPGA prototype verification platforms on the multiple computers through a physical interface, and connected to at least a second set of FPGA prototype verification platforms on the multiple computers through a physical interface; The first FPGA prototype verification platform is used for universal interface transfer test verification; The second FPGA prototype verification platform is used for dedicated interface transfer test verification; The first FPGA prototype verification platform includes a first debugger connected to multiple computers via USB, the first debugger is connected to a first FPGA prototype verification board via JTAG1, multiple computers are connected to a universal interface board via a serial port and / USB, the universal interface board is connected to a first expansion daughter board, the first expansion daughter board is connected to the first FPGA prototype verification board, multiple computers are connected to a first SoC debugger via a network port, and the first SoC debugger is connected to the first FPGA prototype verification board via JTAG2; The second FPGA prototype verification platform includes a second debugger connected to multiple computers via USB, the second debugger is connected to a second FPGA prototype verification board via JTAG3, multiple computers are connected to multiple dedicated interface boards via serial ports and / USB, the dedicated interface boards are connected to multiple second extension daughter boards, the second extension daughter boards are connected to the second FPGA prototype verification board, multiple computers are connected to the second FPGA prototype verification board via network ports, multiple computers are connected to a second SoC debugger via USB, and the second SoC debugger is connected to the second FPGA prototype verification board via JTAG4; It is characterized in that Includes steps: Step a, downloading the integrated RTL code to the main FPGA in the first FPGA prototype verification board or the second FPGA prototype verification board through JTAG1 or JTAG3 after ISE synthesis, so that the CPU is located in the FPGA in a soft core mode; Step b, downloading the development code of the first SoC debugger or the second SoC debugger to the high-performance SoC core solidified by the main FPGA of the first FPGA prototype verification board or the second FPGA prototype verification board through JTAG2 or JTAG4 through the IDE to debug the test program; Step c, verifying the universal interface transfer test and the dedicated interface transfer test by using the test software in the computer; Among them, the general interface transfer test verification is used for CPU core performance test and peripheral function test verification, and the dedicated interface transfer test verification is used for user customized interface and high-speed bus interface test verification; Step d: integrating the test codes of the general interface transfer test verification and the dedicated interface transfer test verification.

2. The SoC hardware and software collaborative verification method based on FPGA prototype according to claim 1 is characterized in that: The first debugger downloads the SoC prototype to the first FPGA prototype verification board through JTAG1.

3. The SoC software and hardware collaborative verification method based on FPGA prototype according to claim 1 is characterized in that: The first SoC debugger is used for program download and debugging of SoC soft core.

4. The SoC hardware and software collaborative verification method based on FPGA prototype according to claim 1, characterized in that: The second debugger downloads the SoC prototype to the second FPGA prototype verification board through JTAG3.

5. The SoC software and hardware collaborative verification method based on FPGA prototype according to claim 1 is characterized in that: The second SoC debugger is used for program download and debugging of the SoC soft core.

6. The SoC hardware and software collaborative verification method based on FPGA prototype according to claim 1, characterized in that: The general interface transfer test verification includes the following steps: Step 01, providing power to the universal interface board through a program-controlled voltage-stabilized power supply; Step 02, the computer runs the test software therein, and causes the test software to send a test function command to the universal interface board; Step 03, the universal interface board sends a test stimulus signal to the first expansion sub-board; Step 04, the first expansion board transmits the signal to the high-performance SoC soft core through the first FPGA prototype verification board according to the test stimulus signal sent by the universal interface board; Step 05, under the action of the excitation signal, the high-performance SoC soft core generates signal data and outputs the SoC processor output signal to the universal interface board through the first expansion daughter board; Step 06, the universal interface board sends a test data packet to the computer according to the output signal of the SoC processor; Step 07, the computer displays the status of the universal interface board, displays the CPU core performance test results, displays the test results of the high-performance SoC core, and receives the test results of the universal interface board memory and registers in real time through the test data packet, and displays the test results in a table.

7. The SoC software and hardware collaborative verification method based on FPGA prototype according to claim 1, characterized in that: Dedicated interface transfer test verification includes the following steps: Step 11, the test software in the computer sends a test function command to multiple dedicated interface boards; Step 12, multiple dedicated interface boards send test stimulus signals to multiple second expansion sub-boards; Step 13, multiple second expansion daughter boards provide the high-performance SoC soft core as signal input through the second FPGA prototype verification board according to the test stimulus signal, and simulate the 1553B interface, Spacewire interface, and Xilinx JTAG protocol conversion interface in the SoC soft core to receive input signals; Step 14, the plurality of second expansion daughter boards send SoC processor output signals to the plurality of dedicated interface boards according to the test stimulus signals of the analog input of the high-performance SoC soft core; Step 15, multiple dedicated interface boards send test data packets to the computer according to the SOC processor; Step 16, the computer displays the 1553B interface test results according to the test data packet, displays the Spacewire configuration, mode selection and node transmission, and provides the FPGA test bit file downloaded by the Xilinx JTAG protocol conversion module.

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