Display substrate and display device

Abstract

The present invention discloses a display substrate and a display panel. The display substrate includes: a substrate having a display area, a punching area, and a critical area disposed between the display area and the punching area. In the direction from the display area to the punching area, the critical area includes a first isolation column area, a barrier wall, and a second isolation column area arranged in sequence. The first isolation column area has at least one first isolation column, and the side wall of the first isolation column facing the display area is covered with an insulating layer. Thus, the occurrence of black spot defects in the display area can be reduced through the setting of the insulating layer, and the display effect can be improved.

Description

Technical Field

[0001] The present invention relates to the field of displays, and more particularly, to a display substrate and a display device. Background Art

[0002] With the increasing demand for high screen-to-body ratio of electronic devices, current smart terminal products are developing towards full-screen display technology. Making holes in the display area as the light-transmitting areas for functional components such as cameras and fingerprint recognition is the mainstream trend of current full-screen display technology. In the product reliability test of existing hole-punched screen electronic devices, black spots are prone to occur in the display area around the punched area, which cannot meet the usage requirements of users.

[0003] Therefore, the current display substrates and display devices still need to be improved. Summary of the Invention

[0004] The present invention aims to at least to some extent alleviate or solve at least one of the above-mentioned problems.

[0005] In one aspect of the invention, a display substrate is provided, including: a substrate having a display area, a punched area, and a critical area disposed between the display area and the punched area. In a direction from the display area to the punched area, the critical area includes a first isolation column area, a barrier wall, and a second isolation column area arranged in sequence. The first isolation column area has at least one first isolation column, and a side wall of the first isolation column facing the display area is covered with an insulating layer. Thus, the occurrence of black spot defects in the display area can be reduced through the setting of the insulating layer, and the display effect can be improved.

[0006] According to an embodiment of the present invention, the first isolation column area includes at least two first isolation columns, and adjacent side walls of the two first isolation columns are covered with the insulating layer, and the height of the insulating layer is not less than the height of the first isolation column. Thus, the insulating effect of the insulating layer can be further improved.

[0007] According to an embodiment of the present invention, the first isolation column area has at least two first isolation columns, and adjacent side walls of the two first isolation columns are not covered with the insulating layer. Thus, the stress concentration phenomenon of the display substrate can be alleviated.

[0008] According to an embodiment of the present invention, the first isolation column area has at least one first isolation column with a side wall not covered with the insulating layer. Thus, the insulating effect of the insulating layer can be further improved.

[0009] According to an embodiment of the present invention, the second isolation pillar region includes at least two of the second isolation pillars, and the side walls of the two adjacent second isolation pillars are covered by the insulating layer, and the height of the insulating layer is not less than the height of the second isolation pillar. Thereby, the insulation effect of the insulating layer can be further improved.

[0010] According to an embodiment of the present invention, there are at least two of the second isolation pillars in the second isolation pillar region, and the side walls of the two adjacent second isolation pillars are not covered by the insulating layer. Thereby, the stress concentration phenomenon of the display substrate can be alleviated.

[0011] According to an embodiment of the present invention, the second isolation pillar region has at least one of the second isolation pillars, and it has a side wall that is not covered by the insulating layer. Thereby, the insulation effect of the insulating layer can be further improved.

[0012] According to an embodiment of the present invention, a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, and a pixel definition layer are sequentially stacked in the display area on the substrate. The first isolation pillar and the second isolation pillar are formed by the second source-drain metal layer, and the insulating layer is formed by the second planarization layer or the pixel definition layer. Thereby, the preparation process of the display substrate can be simplified.

[0013] According to an embodiment of the present invention, a barrier buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer are sequentially stacked in the critical area on the substrate. The first isolation pillar region includes a plurality of the first isolation pillars, and there is a groove between the plurality of the first isolation pillars, and the groove extends at least into the first gate insulating layer. Thereby, the insulation effect of the insulating layer can be further improved.

[0014] In another aspect of the present invention, the present invention provides a display device, and the display device includes the foregoing display substrate. Thereby, the display device has all the features and advantages of the foregoing display substrate, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:

[0016] Figure 1 shows a schematic structural diagram of a display substrate according to an embodiment of the present invention;

[0017] Figure 2 shows a top view of a display substrate according to an embodiment of the present invention;

[0018] Figure 3Shows a partial structural schematic diagram of a display substrate according to an embodiment of the present invention;

[0019] Figure 4 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0020] Figure 5 Shows a partial structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0021] Figure 6 Shows a partial structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0022] Figure 7 Shows a structural schematic diagram of a display substrate according to a comparative example of the present invention;

[0023] Figure 8 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0024] Figure 9 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0025] Figure 10 Shows Figure 12 An enlarged schematic diagram of the structure at the dashed box in;

[0026] Figure 11 Shows Figure 13 An enlarged schematic diagram of the structure at the dashed box in;

[0027] Figure 12 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0028] Figure 13 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0029] Figure 14 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0030] Figure 15 Shows a structural schematic diagram of a display substrate according to another embodiment of the present invention;

[0031] Figure 16 Shows a schematic diagram of the GD SH black spots on a display panel according to a comparative example of the present invention.

[0032] Explanation of reference numerals:

[0033] 1: Display area; 2: Punching area; 3: Critical area; 100: Substrate; 210: Barrier buffer layer; 220: First gate insulating layer; 221: First gate metal layer; 230: Second gate insulating layer; 231: Second gate metal layer; 240: Interlayer dielectric layer; 250: Gate insulating layer; 310: First titanium material layer; 320: Aluminum material layer; 330: Second titanium material layer; 340: Barrier wall; 400: Insulating layer; 500: Cathode layer. Detailed implementation manners

[0034] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0035] In one aspect of the invention, the present invention provides a display substrate. Referring to Figure 1 , Figure 2 , and Figure 12 , it includes: a substrate 100 having a display area 1, a punching area 2, and a critical area 3 disposed between the display area 1 and the punching area 2. In the direction from the display area 1 to the punching area 2, the critical area 3 includes a first isolation column area, a barrier wall 340, and a second isolation column area arranged in sequence. The first isolation column area has at least one first isolation column, and the side wall of the first isolation column facing the display area 2 is covered by an insulating layer 400. Thus, based on the conventional display substrate manufacturing process, without adding an extra mask and without changing the isolation column structure, by covering the side wall of the original metal isolation column facing the display area with an insulating layer, the electrical signal in the display area is effectively blocked in the critical area, reducing the occurrence of the black spot defect in the display area.

[0036] For the convenience of understanding, the principle of the display substrate in the present application having the aforementioned beneficial effects will be described below:

[0037] In the present application, referring to Figure 16 , the inventors found that, taking an OLED display panel product with a punching area provided in the display area as an example, during the reliability test, when the display panel is tested under the conditions of 60 °C / 90% humidity or 85 °C / 85% humidity, after being powered on and running for a period of time, GDSH (Growing Dark Spot) black spot defects will occur, while under the same test conditions for the same storage test (i.e., power-off test) for the same time, the display panel does not have GDSH defects.

[0038] The inventor found through compositional analysis of each film layer in the display area that in the CVD1 layer on the cathode side in the cathode and encapsulation film layers (including the CVD1 layer, IJP, and CVD2 layer stacked in sequence) in the display area, there are compositional elements of the non-cathode layer and the CVD1 layer, such as potassium ions, sodium ions, and iodine ions. After a large number of experimental explorations and theoretical analyses, it was found that there are elements such as potassium, sodium, and iodine in the polarizer, and the polarizer structure in the conventional display area has a cross-section in the punching area. The potassium ions, sodium ions, and iodine ions in the cathode and CVD layer should leak out from the cross-section of the polarizer in the punching area. Further, taking the cathode of the display panel as a common cathode as an example, referring to Figure 7 it can be seen that the cathode layer 500 as the common cathode is generally formed by a whole-layer evaporation process. Thus, by setting a metal isolation column structure with an inverted trapezoid in the critical area, the light-emitting layer and the cathode layer 500 can be broken at the isolation column, and then the electrical signal in the display area can be disconnected in the critical area. Combining the fact that after the display substrate with the above structure is powered on and operated for a period of time, the problem of GDSH black spots will occur. The inventor reasonably analyzed that since the isolation column structure is usually formed of metal and a part of the cathode layer 500 overlaps on the isolation column, although the cathode layer 500 has a discontinuous break due to the step difference at the isolation column, because the isolation column is formed of a metal material, and the isolation column generally includes a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer stacked in sequence, and the aluminum layer has the best conductivity, and the cathode layer 500 just overlaps on the aluminum layer, the cathode electrical signal transmitted from the display area to the punching area is not disconnected in the critical area and can still transmit the electrical signal. And because the elements such as potassium, sodium, and iodine in the polarizer leak from the cross-section of the polarizer, in order to maintain charge balance, when there are K + 、Na + plasma ions, correspondingly, the areas where K + 、Na + plasma ions exist will accumulate OH - to ensure charge neutralization. Therefore, the leaked elements such as potassium, sodium, and iodine react electrochemically with the cathode layer and the CVD1 layer in the encapsulation film layer located in the critical area. The reaction equations include:

[0039] SiO2 + 2OH - =SiO3 2 - + H2O (CVD1 includes SiO2); e - + H2O = OH - + H2↑ (the cathode has a large number of electrons).

[0040] Since the cathode and CVD1 jointly undergo electrochemistry with elements such as potassium, sodium, and iodine, it accelerates the corrosion and aging of the cathode and CVD1, and further leads to the failure of the encapsulation layer, causing the problem of GDSH black spots in the display panel.

[0041] In the present application, with reference to Figure 8 , the inventor additionally disposes an insulating layer (such as a second planarization layer or a pixel definition layer) in the conventional preparation process of the display area on the sidewalls of the isolation pillars in the critical area. After the entire layer deposition of the cathode layer 500, due to the existence of the isolation pillar structure, the cathode layer 500 will still have an overlap on one side of the isolation pillar, while on the other sidewall, due to the coverage of the insulating layer 400, the cathode layer 500 cannot overlap on the aluminum layer 320 in the isolation pillar. As a result, the electrical signal transmitted from the cathode layer 500 in the display area to the cathode layer 500 in the punching area is disconnected at the isolation pillar in the critical area, thereby avoiding the leakage of K + , Na + plasma from reacting electrochemically with the cathode and the CVD1 film layer, thereby reducing the accelerated aging of the cathode and the CVD1 film layer and the occurrence of GD SH defects in the display panel.

[0042] According to some embodiments of the present invention, the composition of the isolation pillar is not particularly limited. For example, when a double-TFT structure is stacked on the display substrate, and a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, and a pixel definition layer are sequentially stacked in the display area on the substrate, the first isolation pillar and the second isolation pillar can be formed from the second source-drain metal layer. Specifically, with reference to Figure 4 , both the first isolation pillar and the second isolation pillar can include a first titanium material layer 310, an aluminum material layer 320, and a second titanium material layer 330 that are sequentially stacked. Among them, the projection of the surface of the aluminum material layer 320 on the side close to the second titanium material layer 330 on the substrate 100 is located inside the projection of the surface of the aluminum material layer 320 on the side close to the first titanium material layer 310 on the substrate 100, that is, the aluminum material layer 320 has a trapezoidal structure. Thus, when depositing the cathode layer 500, the cathode layer will be disconnected due to the step difference at the aluminum material layer 320 on the sidewall of the isolation pillar. And since both the first isolation pillar and the second isolation pillar are formed by means of the second source-drain layer forming process in the display area, the preparation of the first isolation pillar and the second isolation pillar can be achieved without adding an additional light-shielding mask and process steps.

[0043] According to some embodiments of the present invention, with reference to Figure 4, the composition of the insulating layer is not particularly limited. For example, when a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, and a pixel definition layer are sequentially stacked in the display area on the substrate, the insulating layer 400 can be formed by the second planarization layer or the pixel definition layer. Since both the first isolation pillar and the second isolation pillar are formed by means of the second source-drain layer forming process in the display area, the insulating layer 400 can be formed by means of the forming process of the second planarization layer or the pixel definition layer in the display area. That is, after the second planarization layer or the pixel definition layer is formed as a whole layer, when using a mask for patterning exposure and removal, only the mask opening setting is cancelled in the corresponding area of the side wall of the isolation pillar, so that the second planarization layer or the pixel definition layer on the side wall of the isolation pillar is retained, thus realizing the function of the insulating layer. Thus, without additionally increasing the number of light-shielding masks, the production cost is reduced, and the problem of GDSH defects can be effectively solved.

[0044] According to some embodiments of the present invention, by providing the barrier wall 340, various film layer structures on the display panel can be supported and protected. For example, it can prevent the metal material layer from being eroded by external pollutants such as water vapor, and can also block the flow range of the solution during evaporation or encapsulation, and can also prevent the film layer cracks in the punching area from spreading to the display area, etc.

[0045] For the sake of easy understanding, with reference to Figure 1 and Figure 3 , the following will be explained with the left side of the barrier wall 340 as the first isolation pillar area and the right side of the barrier wall 340 as the second isolation pillar area.

[0046] It should be particularly noted that the number of isolation pillars in the first isolation pillar area and the second isolation pillar area is not particularly limited. For example, the first isolation pillar area may have only one first isolation pillar. In this case, the second isolation pillar area may have only one second isolation pillar or may have multiple second isolation pillars; the first isolation pillar area may have multiple first isolation pillars. In this case, the second isolation pillar area may have only one second isolation pillar or may have multiple second isolation pillars. The number of first isolation pillars in the first isolation pillar area may be greater than, less than, or equal to the number of second isolation pillars in the second isolation pillar area. For another example, the spacing between adjacent first isolation pillars or adjacent second isolation pillars is not particularly limited either. The adjacent first isolation pillars may have the same spacing or may have different spacings. The adjacent second isolation pillars may have the same spacing or may have different spacings, and those skilled in the art can make a choice according to the actual situation.

[0047] According to some embodiments of the present invention, the number and position of the side walls of the first isolation pillars covered by the insulating layer in the first isolation pillar area are not particularly limited. For example, with reference to Figure 4 and Figure 9, when the first isolation pillar region includes at least two first isolation pillars, the adjacent side walls of the two first isolation pillars can both be covered by the insulating layer 400. At this time, the two adjacent first isolation pillars share the insulating layer 400. Thus, when the cathode layer 500 is deposited in the critical region, the cathode layer 500 breaks at the side wall of the first isolation pillar where the insulating layer is not provided and overlaps on the aluminum material layer 320. Since the insulating layer 400 fills the gap formed by the two adjacent side walls of the two first isolation pillars, the cathode layer 500 that was originally deposited in the gap and overlapped on the aluminum material layer 320 is deposited on the insulating layer 400 at this time. Therefore, the electrical signal transmitted from the cathode layer 500 in the display region to the cathode layer 500 in the punching region is disconnected due to the presence of the insulating layer 400 at the first isolation pillar in the critical region, thereby reducing the accelerated aging of the cathode and the CVD1 film layer and the occurrence of GDHS defects in the display panel.

[0048] According to some embodiments of the present invention, the height of the insulating layer on the side wall of the first isolation pillar is not particularly limited. For example, the height of the insulating layer may not be less than the height of the side wall of the isolation pillar. Due to process precision limitations, it is difficult for the height of the insulating layer on the side wall of the isolation pillar to be exactly the same as the height of the isolation pillar. In order to ensure that the insulating layer completely covers the side wall of the isolation pillar, when depositing the insulating layer, an insulating layer with a relatively high height can be formed, thereby ensuring that the side wall of the isolation pillar is completely covered by the insulating layer.

[0049] According to some embodiments of the present invention, the position and number of the side walls of the isolation pillar covered by the insulating layer are not particularly limited. Refer to Figure 13 , Figure 14 and Figure 15 , when the first isolation pillar region includes multiple first isolation pillars, multiple adjacent side walls of the first isolation pillars in the first isolation pillar region can be covered by the insulating layer 400. In order to avoid the stress in the critical region being too concentrated due to the dense arrangement of the insulating layer, which may cause the film layer in the critical region to crack due to excessive stress during laser lift-off in the back-end process of the display substrate. There should be at least two first isolation pillars in the critical region, and the adjacent side walls of the two first isolation pillars are not covered by the insulating layer. Specifically, taking Figure 13 as an example, when there are two pairs of adjacent side walls of the first isolation pillars in the first isolation pillar region that are both covered by the insulating layer 400, each isolation pillar in these two pairs of first isolation pillars should have only one side wall covered by the insulating layer. Thus, the insulating layer 400 can be filled in the gaps between the adjacent side walls of the first isolation pillars at intervals, thereby reducing the stress concentration in the critical region.

[0050] According to some embodiments of the present invention, refer to Figure 8 and Figure 9, when the height of the insulating layer is too high to completely cover the side wall of the isolation pillar, the cathode layer 500 will completely cover the surface of the insulating layer 400. At this time, since the isolation pillar is located inside the insulating layer 400 and the insulating layer 400 does not have a structure that can cause the cathode layer 500 to form a step difference and break, even if the insulating layer 400 is provided, the electrical signal transmission of the cathode layer 500 cannot be disconnected in the critical area. Therefore, the first isolation pillar area should have at least one first isolation pillar with a side wall not covered by the insulating layer 400, so that the cathode layer 500 is disconnected in the critical area, and then combined with the setting of the insulating layer 400, the electrical signal from the display area to the punching area is disconnected in the critical area. According to some other embodiments of the present invention, when the height of the insulating layer 400 is higher than the height of the first isolation pillar, the insulating layer 400 will cover the surface of the second titanium material layer 330 of the first isolation pillar. Specifically, the coverage area of the insulating layer 400 on the surface of the second titanium material layer 330 should not be greater than the surface area of the second titanium material layer 330, so that at least one first isolation pillar has a side wall not covered by the insulating layer 400. Preferably, the distance between the insulating layer 400 and the edge of the surface of the second titanium material layer 330 may not be less than 1 micron.

[0051] According to some embodiments of the present invention, referring to Figure 12 , since the electrical signal is transmitted from the cathode layer in the display area to the cathode layer in the punching area, preferably, an insulating layer 400 is provided on the side wall of the first isolation pillar in the first isolation area. For example, an insulating layer 400 is provided between the adjacent side walls of the two first isolation pillars closest to the display area in the first isolation pillar, and then the disconnection of the electrical signal transmission of the cathode layer is achieved at a position farther from the cathode layer in the punching area. Further, in order to reduce the uncertainty brought by only providing the insulating layer on the side wall of the first isolation pillar in the first isolation pillar area, such as the thickness of the insulating layer deposited on the side wall of the first isolation pillar in the first isolation pillar area is not enough to cover the side wall of the first isolation pillar or the opening of the mask plate is set, etc., an insulating layer can also be formed on the side wall of the second isolation pillar in the second isolation pillar area facing the display area. The structure and formation method of the formed insulating layer are the same as those of the insulating layer in the first isolation pillar area, and then through the setting of multiple insulating layers, the disconnection of the electrical signal transmission of the cathode layer in the critical area is further realized.

[0052] According to some embodiments of the present invention, the number and position of the side walls of the second isolation pillar covered by the insulating layer in the second isolation pillar area are not particularly limited. For example, referring to Figure 4 and Figure 9, when the second isolation pillar region includes at least two second isolation pillars, the adjacent side walls of the two second isolation pillars can be covered by the insulating layer 400. At this time, the two adjacent second isolation pillars share the insulating layer 400. Thus, when the cathode layer 500 is deposited in the critical region, the cathode layer 500 is disconnected at the side wall of the second isolation pillar where the insulating layer is not provided and overlaps on the aluminum material layer 320. Since the insulating layer 400 is filled in the gap formed by the two adjacent side walls of the two second isolation pillars, the cathode layer 500 originally deposited in the gap and overlapping on the aluminum material layer 320 is deposited on the insulating layer 400 at this time. Therefore, the electrical signal transmitted from the cathode layer 500 in the display region to the cathode layer 500 in the punching region is disconnected due to the presence of the insulating layer 400 at the second isolation pillar in the critical region, thereby reducing the accelerated aging of the cathode and the CVD1 film layer and the occurrence of GDSH defects in the display panel.

[0053] According to some embodiments of the present invention, the height of the insulating layer on the side wall of the second isolation pillar is not particularly limited. For example, the height of the insulating layer may not be less than the height of the side wall of the isolation pillar. Due to process precision limitations, it is difficult for the height of the insulating layer on the side wall of the isolation pillar to be exactly the same as the height of the isolation pillar. In order to ensure that the insulating layer completely covers the side wall of the isolation pillar, when depositing the insulating layer, an insulating layer with a relatively high height can be formed, thereby ensuring that the side wall of the isolation pillar is completely covered by the insulating layer.

[0054] According to some embodiments of the present invention, the position and number of the side walls of the isolation pillar covered by the insulating layer are not particularly limited. Refer to Figure 13 , Figure 14 and Figure 15 , when the second isolation pillar region includes multiple second isolation pillars, multiple adjacent side walls of the second isolation pillars in the second isolation pillar region can be covered by the insulating layer 400. In order to avoid the stress in the critical region being too concentrated due to the dense arrangement of the insulating layer, and then causing the film layer in the critical region to crack due to excessive stress when laser lift-off is performed in the back-end process of the display substrate. There should be at least two second isolation pillars in the critical region, and the adjacent side walls of the two second isolation pillars are not covered by the insulating layer. Specifically, taking Figure 13 as an example, when there are two pairs of adjacent side walls of the second isolation pillars in the second isolation pillar region that are covered by the insulating layer 400, each isolation pillar in these two pairs of second isolation pillars should have only one side wall covered by the insulating layer. Thus, the insulating layer 400 can be filled in the adjacent side walls of the second isolation pillars at intervals, thereby reducing the stress concentration in the critical region.

[0055] According to some embodiments of the present invention, refer to Figure 8 and Figure 9, when the height of the insulating layer is too high so as to completely cover the side wall of the isolation pillar, the cathode layer 500 will completely cover the surface of the insulating layer 400. At this time, since the isolation pillar is located inside the insulating layer 400, and the insulating layer 400 does not have a structure that can cause the cathode layer 500 to form a step difference and break. At this time, even if the insulating layer 400 is provided, it is impossible to make the electrical signal transmission of the cathode layer 500 break at the critical area. Therefore, the second isolation pillar area should have at least one second isolation pillar, which has a side wall not covered by the insulating layer 400, so that the cathode layer 500 breaks at the critical area, and then combined with the setting of the insulating layer 400, the electrical signal from the display area to the punching area is disconnected at the critical area. According to some other embodiments of the present invention, when the height of the insulating layer 400 is higher than the height of the second isolation pillar, the insulating layer 400 will cover the surface of the second titanium material layer 330 of the second isolation pillar. Specifically, the coverage area of the insulating layer 400 on the surface of the second titanium material layer 330 should not be greater than the surface area of the second titanium material layer 330, so that at least one second isolation pillar has a side wall not covered by the insulating layer 400. Preferably, the distance between the insulating layer 400 and the edge of the surface of the second titanium material layer 330 may not be less than 1 micron.

[0056] According to some embodiments of the present invention, referring to Figure 5 and Figure 10 , when a barrier buffer layer 210, a first gate insulating layer 220, a second gate insulating layer 230, and an interlayer dielectric layer 240 are sequentially stacked in the critical area on the substrate 100, the first isolation pillar area may include a plurality of first isolation pillars, and there may be a groove between the plurality of first isolation pillars, and the groove extends at least into the first gate insulating layer 220. When there is a groove between the plurality of first isolation pillars, the distance between the top end of the first isolation pillar and the bottom end of the groove is farther than the distance between the top end of the first isolation pillar and the upper surface of the interlayer dielectric layer 240 when there is no groove between the plurality of first isolation pillars. Then, the height difference when the cathode layer 500 is deposited and formed is greater, and the cathode layer 500 is more likely to break on the side wall of the first isolation pillar due to the step difference, and then better utilize the setting of the insulating layer to achieve the effect of disconnecting the electrical signal transmission of the cathode layer at the critical area. Specifically, according to some embodiments of the present invention, the thickness of the first gate insulating layer is about 1200 angstroms, the thickness of the first gate insulating layer is about 1300 angstroms, the thickness of the interlayer dielectric layer is about 5000 angstroms, and the depth range of the groove can be 7000 - 8000 angstroms.

[0057] According to some embodiments of the present invention, referring to Figure 6 and Figure 11, when a barrier buffer layer 210, a first gate insulating layer 220, a second gate insulating layer 230, and an interlayer dielectric layer 240 are sequentially stacked in a critical region on the substrate 100, the second isolation column region may include a plurality of second isolation columns. At this time, the substrate 100 of the second isolation column region further includes: a first gate metal layer 221, and the first gate metal layer 221 is located between the barrier buffer layer 210 and the first gate insulating layer 220; a second gate metal layer 231, and the second gate metal layer 231 is located between the first gate insulating layer 220 and the second gate insulating layer 230. The orthographic projection of the second gate metal layer 231 on the substrate 100 is located inside the orthographic projection of the first gate metal layer 221 on the substrate 100, and the orthographic projection of the second isolation column on the substrate 100 is located inside the orthographic projection of the second gate metal layer 231 on the substrate 100. When the substrate 100 of the second isolation column region further includes the first gate metal layer 221 and the second gate metal layer 231, the distance between the top end of the second isolation column and the upper surface of the interlayer dielectric layer 240 is farther than that when the substrate of the second isolation column region only includes the barrier buffer layer 210, the first gate insulating layer 220, the second gate insulating layer 230, and the interlayer dielectric layer 240. Then, when the cathode layer 500 is deposited and formed, the height difference is greater, and the cathode layer 500 is more likely to be disconnected on the side wall of the second isolation column due to the step difference, thereby better utilizing the setting of the insulating layer to achieve the effect of disconnecting the electrical signal transmission of the cathode layer in the critical region. According to some embodiments of the present invention, the thickness of the first gate metal layer is about 3000 Å, and the thickness of the second gate metal layer is about 3000 Å.

[0058] In another aspect of the present invention, the present invention provides a display device, and the display device includes the aforementioned display substrate. Thus, the display device has all the features and advantages of the aforementioned display substrate, which will not be elaborated herein.

[0059] The solution of the present application will be described below through specific embodiments. It should be noted that the following embodiments are only used to illustrate the present application and should not be regarded as limiting the scope of the present application. For those not specified in the embodiments regarding specific technologies or conditions, they shall be carried out according to the technologies or conditions described in the literature in the art or according to the product specifications. For reagents or instruments not specified by the manufacturer, they are all conventional products that can be obtained through commercial procurement.

[0060] In the following Examples 1-4, it is taken as an example that the first isolation column region includes four first isolation columns and the second isolation column region includes seven second isolation columns. From the display region towards the punching region, the four first isolation columns in the first isolation column region are sequentially numbered as No. 1, No. 2, No. 3, and No. 4, and the seven second isolation columns in the second isolation column region are sequentially numbered as No. 5, No. 6, No. 7, No. 8, No. 9, No. 10, and No. 11. The width of the second titanium material layer 330 is 4.8 microns. The second planarization layer is used as the insulating layer 400, and the distance between the insulating layer 400 on the surface of the second titanium material layer 300 and the boundary of the second titanium material layer 300 is 1.9 microns.

[0061] Example 1

[0062] Reference Figure 12 , an insulating layer 400 is provided on the adjacent side walls of the No. 1 first isolation column and the No. 2 first isolation column.

[0063] Example 2:

[0064] Reference Figure 13 , insulating layers 400 are provided on the adjacent side walls of the No. 1 first isolation column and the No. 2 first isolation column, on the adjacent side walls of the No. 3 first isolation column and the No. 4 first isolation column, on the adjacent side walls of the No. 6 second isolation column and the No. 7 second isolation column, and on the adjacent side walls of the No. 8 second isolation column and the No. 9 second isolation column.

[0065] Example 3:

[0066] Reference Figure 14 , insulating layers 400 are provided on the adjacent side walls of the No. 1 first isolation column and the No. 2 first isolation column, on the adjacent side walls of the No. 3 first isolation column and the No. 4 first isolation column, and on the adjacent side walls of the No. 6 second isolation column and the No. 7 second isolation column.

[0067] Example 4:

[0068] Reference Figure 15 , insulating layers 400 are provided on the adjacent side walls of the No. 1 first isolation column and the No. 2 first isolation column and on the adjacent side walls of the No. 5 second isolation column and the No. 6 second isolation column.

[0069] The test results show that in the display substrates in Examples 1-4 and the display panels having the display substrates in Examples 1-4, under the test conditions of 60 °C / humidity 90% or 85 °C / humidity 85%, no GDSH (Growing Dark Spot) black spot defects occurred after being powered on and running for a period of time. The results show that the electrical signal transmitted from the cathode layer 500 in the display region to the cathode layer 500 in the punching region is disconnected at the isolation columns in the critical region, thereby avoiding the leakage of K + , Na +The plasma undergoes an electrochemical reaction with the cathode and the CVD1 film layer, thereby reducing the accelerated aging of the cathode and the CVD1 film layer and the occurrence of GDHS defects in the display panel.

[0070] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0071] In the description of the present invention, the "first feature" and "second feature" may include one or more of such features.

[0072] In the description of the present invention, the meaning of "a plurality" is two or more.

[0073] In the description of the present invention, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween.

[0074] In the description of the present invention, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature.

[0075] In the description of this specification, the description referring to terms such as "one embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. Additionally, it should be noted that in this specification, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0076] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A display substrate, characterized in that, Comprising: A substrate having a display area, a punching area, and a critical area disposed between the display area and the punching area. In a direction from the display area to the punching area, the critical area includes a first isolation pillar area, a barrier wall, and a second isolation pillar area arranged in sequence. The first isolation pillar area has at least one first isolation pillar, and a side wall of the first isolation pillar facing the display area is covered by an insulating layer, and the first isolation pillar has a side wall not covered by the insulating layer.

2. The display substrate according to claim 1, wherein The first isolation pillar area includes at least two of the first isolation pillars, and the adjacent side walls of the two first isolation pillars are covered by the insulating layer, and the height of the insulating layer is not less than the height of the first isolation pillar.

3. The display substrate according to claim 2, wherein There are at least two of the first isolation pillars in the first isolation pillar area, and the adjacent side walls of the two first isolation pillars are not covered by the insulating layer.

4. The display substrate according to any one of claims 2, characterized in that, The first isolation pillar area has at least one of the first isolation pillars having a side wall not covered by the insulating layer.

5. The display substrate according to claim 1, wherein The second isolation pillar area includes at least two of the second isolation pillars, and the adjacent side walls of the two second isolation pillars are covered by the insulating layer, and the height of the insulating layer is not less than the height of the second isolation pillar.

6. The display substrate according to claim 5, wherein There are at least two of the second isolation pillars in the second isolation pillar area, and the adjacent side walls of the two second isolation pillars are not covered by the insulating layer.

7. The display substrate according to claim 5, characterized in that, The second isolation pillar area has at least one of the second isolation pillars having a side wall not covered by the insulating layer.

8. The display substrate according to claim 5, wherein: On the display area of the substrate, a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, and a pixel definition layer are sequentially stacked. The first isolation pillar and the second isolation pillar are formed by the second source-drain metal layer, and the insulating layer is formed by the second planarization layer or the pixel definition layer.

9. The display substrate according to claim 1, wherein On the critical area of the substrate, a barrier buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer are sequentially stacked. The first isolation pillar area includes a plurality of the first isolation pillars, and there are grooves between the plurality of first isolation pillars, and the grooves extend at least into the first gate insulating layer.

10. A display device, characterized in that, The display device includes the display substrate according to any one of claims 1-9.

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