A multi-event processing circuit based on silicon photomultiplier tube

Abstract

The invention discloses a multi-event processing circuit based on silicon photomultiplier tube, comprising: an event filtering circuit, connected to a SiPM array, used to filter out part of the photon event data stream output by the SiPM array; a correlation detection circuit, connected to the SiPM array, used to detect whether the number of events reaches a threshold value within a time window, and if so, trigger an enable generation circuit; an enable generation circuit, connected to the event filtering circuit and the correlation detection circuit through a two-input AND gate Y1, used to convert the remaining photon event data stream after the event filtering circuit is filtered into an enable signal for TDC quantization; a multi-event TDC, connected to the enable generation circuit, used to quantize the time interval between photon events when the enable generation circuit is triggered. The multi-event scheme of the invention only requires a specific logic circuit to alternately enable the multi-event TDC to perform time quantization, and has a more compact on-chip structure and higher adaptability and compatibility in similar technologies such as time-space correlation.

Description

Technical Field

[0001] The present invention belongs to the technical field of multi-echo event processing, and the present invention relates to a multi-echo event processing technology based on a laser radar chip, and specifically to a multi-event processing circuit based on a silicon photomultiplier tube. Background Art

[0002] Optoelectronic intelligent sensing and imaging technologies have achieved rapid development in advanced industries, intelligent driving, and consumer electronics. The TOF (Time of flight) sensor chip installed by Apple on the iPad Pro has accelerated the application expansion of LiDAR in the consumer field. As the key to the conversion of photoelectric sensing, single photon avalanche diodes (SPADs) are widely used in the field of photoelectric detection technology due to their internal high gain, high sensitivity, and insensitivity to electromagnetic noise. SPADs in Geiger mode can detect single photons. When the absorption region of the SPAD detects the photon echo, the carriers in the space charge region inside the device undergo strong collision ionization, and the large number of carriers generated quickly trigger avalanches to generate strong currents. The output end detects avalanche pulse signals, thereby completing the detection of single photons. Although the Geiger mode can provide a higher signal-to-noise ratio, SPADs require quenching and dynamic bias circuits, which are complex to control and have dark count problems. More importantly, SPAD and quenching circuits have dead time, which means they cannot respond to the next photon echo immediately after being triggered. Figure 1 When the background light is strong, the image is distorted by the pile-up effect, which makes it impossible to accurately extract the target TOF, affecting the performance of the receiving chip.

[0003] SiPM is an array structure composed of multiple Si-SPAD micro-units. The brief structure is as follows: Figure 2 As shown. Due to the array structure of SiPM, when a certain number of photons are incident on the SiPM surface, not all photons can be responded to, so a shorter dead time can be obtained compared to the traditional SPAD structure. The ratio of the number of incident photons to the number of responded photons is defined as the photon detection efficiency of SiPM, and its value is related to the filling factor, quantum efficiency, and avalanche probability of the detector. Its gain is the same as that of a single SPAD, which is about 10 5 ~10 7 .

[0004] Spatial and Temporal Resolution / Coincidence technology is used for correlation detection. Compared with randomly triggered background light noise, signal photons will show a relatively concentrated distribution in space, which is manifested as adjacent pixels being triggered. This corresponds to the arrival of multiple photons at very close times on the time axis. This correspondence between the time domain and the space domain is called spatial and temporal correlation. According to this scheme, the threshold for photon detection can be set within a certain period of time to distinguish between background light and signal photons, reduce the impact of pile-up distortion, and thus improve the performance of lidar chips in outdoor applications.

[0005] The multi-event test solution can quantify the time intervals of multiple photons, which can be achieved with a time-to-digital converter (TDC). The detection of multiple events makes the photoelectric detector model the scene more intelligent (such as targets behind glass, targets scattered on the surface, etc.). The TOF technology reflects the distance information of the target by measuring the interval between the moment the transmitter emits the laser signal and the moment the echo signal is reflected from the target back to the detector chip. The array implementation can model the target in the scene, that is, the depth and contour. The quantified time information is sometimes also called the TOF value.

[0006] However, how to realize multi-event correlation processing technology based on SiPM has become an urgent problem to be solved for the optimization and development of photoelectric detection technology. Summary of the invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a multi-event processing circuit based on silicon photomultiplier tube. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0008] A multi-event processing circuit based on a silicon photomultiplier tube, the multi-event processing circuit comprising:

[0009] An event filtering circuit, connected to the SiPM array, for filtering out part of the photon event data stream output by the SiPM array;

[0010] A correlation detection circuit, connected to the SiPM array via a switch S1, for detecting whether the number of events reaches a threshold within the time window, and if so, triggering an enable generation circuit, and if not, not triggering the enable generation circuit;

[0011] An enable generating circuit, connected to the event filtering circuit and the correlation detecting circuit via a two-input AND gate Y1, for converting the photon event data stream remaining after filtering by the event filtering circuit into an enable signal for TDC quantization;

[0012] A multi-event TDC is connected to the enable generation circuit and is used to quantify the time intervals between photon events when the enable generation circuit is triggered.

[0013] In one embodiment of the present invention, the event filtering circuit includes a D flip-flop D1 and a delay module, wherein:

[0014] The clock end of the D flip-flop D1 is connected to the output end of the SiPM array, the output end of the D flip-flop D1 is connected to the input end of the delay unit and the first input end of the two-input AND gate Y1, the output end of the delay unit is connected to the reset end of the D flip-flop D1, and the output end of the two-input AND gate Y1 is connected to the enable generation circuit.

[0015] In one embodiment of the present invention, the delay module includes a first inverter.

[0016] In one embodiment of the present invention, the first inverter is a Current-Starved first inverter.

[0017] In one embodiment of the present invention, the correlation detection circuit includes a counter and a multiplexer, wherein:

[0018] The input end of the counter is connected to the output end of the SiPM array, the output end of the counter is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the second input end of the two-input AND gate Y1.

[0019] In one embodiment of the present invention, the enable generation circuit includes a single event enable module and a multi-event enable module, wherein:

[0020] The input end of the single event enable module is connected to the output end of the two-input AND gate Y1 through a switch S2, the input end of the multi-event enable module is connected to the output end of the two-input AND gate Y1 through a switch S3, and the output ends of the single event enable module and the multi-event enable module are connected to the multi-event TDC.

[0021] In one embodiment of the present invention, the single event enable module includes a D flip-flop D2, a D flip-flop D3, a first inverter and a two-input AND gate Y2, wherein:

[0022] The clock end of the D flip-flop D2 is connected to the output end of the two-input AND gate Y1 through the switch S2, the Q end of the D flip-flop D2 is connected to the D end of the D flip-flop D3 and the first input end of the two-input AND gate Y2, the Q end of the D flip-flop D3 is connected to the input end of the first inverter, the output end of the first inverter is connected to the second input end of the two-input AND gate Y2, and the output end of the two-input AND gate Y2 is connected to the multi-event TDC.

[0023] In one embodiment of the present invention, the multi-event enable module includes a D flip-flop D4, a D flip-flop D5, a two-input AND gate Y3, a two-input AND gate Y4, a two-input AND gate Y5, a two-input AND gate Y6, a three-input OR gate H1 and a three-input OR gate H2, wherein:

[0024] The clock end of the D flip-flop D4 and the clock end of the D flip-flop D5 are connected to the output end of the two-input AND gate Y1 through the switch S3, the clock end of the D flip-flop D4 and the clock end of the D flip-flop D5 are also connected to the first input end of the two-input AND gate Y3 and the first input end of the two-input AND gate Y4, the Q end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y3, the QI end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y4, the Q end of the D flip-flop D5 is connected to the first input end of the two-input AND gate Y5 and the first input end of the two-input AND gate Y6, and the two-input AND gate Y3 is connected to the second input end of the two-input AND gate Y3. The output end of gate Y3 is connected to the first input end of the three-input OR gate H1, the output end of the two-input AND gate Y4 is connected to the first input end of the three-input OR gate H2, the second input end of the three-input OR gate H1 is connected to the output end of the three-input OR gate H2, the second input end of the three-input OR gate H2 is connected to the output end of the three-input OR gate H1, the output end of the three-input OR gate H1 is connected to the second input end of the two-input AND gate Y5, the output end of the three-input OR gate H2 is connected to the second input end of the two-input AND gate Y6, and the output end of the two-input AND gate Y5 and the output end of the two-input AND gate Y6 are connected to the multi-event TDC.

[0025] In one embodiment of the present invention, the multi-event TDC includes 4 first sub-path delay modules, 4 second sub-path delay modules, 8 main path delay modules and a multi-channel counter, wherein:

[0026] The node connected to the input end of the first main delay module 31 and the output end of the eighth main delay module 38 is commonly connected to the multi-channel counter, the output end of the first main delay module 31 is connected to the input end of the second main delay module 32, the output end of the first second sub-delay module 21 and the input end of the fourth second sub-delay module 24, the output end of the second main delay module 32 is connected to the input end of the third main delay module 33, the output end of the first first sub-delay module 11 and the input end of the fourth first sub-delay module 24. The input end of the delay module 14, the output end of the third main delay module 33, the input end of the fourth main delay module 34, the output end of the second first sub-path delay module 12 and the node connected to the fourth first sub-path delay module 14 are connected to the multi-channel counter, the output end of the fourth main delay module 34, the input end of the fifth main delay module 35 and the node connected to the output end of the second second sub-path delay module 22 are connected to the multi-channel counter, and the output end of the fifth main delay module 35 is connected to the sixth The input end of the main delay module 36, the output end of the third first sub-path delay module 13 and the input end of the second first sub-path delay module 13, the output end of the sixth main delay module 36 is connected to the input end of the seventh main delay module 37, the output end of the third second sub-path delay module 23 and the input end of the second second sub-path delay module 22, the output end of the seventh main delay module 37, the input end of the eighth main delay module 37, the output end of the fourth second sub-path delay module 24 and the input end of the second second sub-path delay module 25 are connected to each other. The node connected to the output end of block 22 is commonly connected to the multi-channel counter, the node connected to the output end of the eighth main-path delay module 38 and the output end of the fourth first sub-path delay module 14 is commonly connected to the multi-channel counter, the node connected to the input end of the first first sub-path delay module 11 and the input end of the first second sub-path delay module 21 is commonly connected to the multi-channel counter, and the node connected to the input end of the third first sub-path delay module 13 and the input end of the third second sub-path delay module 23 is commonly connected to the multi-channel counter;

[0027] The input end of each of the first sub-path delay modules is connected to the output end of the two-input AND gate Y5, the input end of each of the second sub-path delay modules is connected to the output end of the two-input AND gate Y6, and the input end of each of the main path delay modules is connected to the output end of the two-input AND gate Y2.

[0028] In one embodiment of the present invention, the first sub-path delay module, the second sub-path delay module and the main path delay module all include a second inverter, a diode M1, a diode M2, a diode M3 and a diode M4, wherein:

[0029] The input end of the second inverter receives an enable signal, the output end of the second inverter is connected to the gate of the diode M1, the source of the diode M1 is connected to the power supply end, the drain of the diode M1 is connected to the source of the diode M2, the gate of the diode M2 ​​is connected to the gate of the diode M3, the drain of the diode M2 ​​is connected to the drain of the diode M3, the source of the diode M3 is connected to the drain of the diode M4, the gate of the diode M4 receives the enable signal, and the source of the diode M4 is grounded.

[0030] Beneficial effects of the present invention:

[0031] 1. The event filtering circuit of the present invention reduces the amount of data processed by subsequent circuits, reduces the requirements for on-chip storage resources and output circuits, and saves power consumption.

[0032] 2. The spatiotemporal correlation technology of the present invention can better distinguish between background light noise and echo events, and enable subsequent circuits only when an echo event is determined. The adjustable detection threshold can reduce the distortion caused by the pile-up effect, improve the outdoor application performance of the chip and save power consumption;

[0033] 3. The event enabling circuit and multi-event TDC of the present invention can quantify the time intervals between multiple events, improve the accuracy of scene modeling, solve the problem of echo data loss in traditional quantization schemes, and reduce the number of experiments to improve the chip frame rate.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of a SPAD losing photon information due to dead time provided by an embodiment of the present invention;

[0036] Figure 2 is a simplified structural schematic diagram of a SiPM based on passive quenching provided by an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of a multi-event processing circuit structure based on a silicon photomultiplier tube provided by an embodiment of the present invention;

[0038] Figure 4 is a schematic diagram of a spatiotemporal correlation detection provided by an embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of a working mechanism of an enabling module provided by an embodiment of the present invention;

[0040] Figure 6 It is a schematic diagram of the circuit structure of a single event enabling module provided by an embodiment of the present invention;

[0041] Figure 7 It is a schematic diagram of the circuit structure of a multi-event enabling module provided by an embodiment of the present invention;

[0042] Figure 8 is a schematic diagram of the structure of a multi-event TDC provided by an embodiment of the present invention;

[0043] Fig. 9 It is a structural schematic diagram of a delay module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0045] Embodiment 1

[0046] See also Figure 3 , Figure 3 1 is a schematic diagram of a multi-event processing circuit structure based on a silicon photomultiplier tube provided by an embodiment of the present invention. This embodiment provides a multi-event processing circuit based on a silicon photomultiplier tube, and the multi-event processing circuit includes:

[0047] An event filtering circuit, connected to the SiPM array, for filtering out part of the photon event data stream output by the SiPM array;

[0048] A correlation detection circuit, connected to the SiPM array via a switch S1, is used to detect whether the number of events reaches a threshold within a time window, and if so, trigger the enable generation circuit, and if not, do not trigger the enable generation circuit;

[0049] The enable generation circuit is connected to the event filtering circuit and the correlation detection circuit through a two-input AND gate Y1, and is used to convert the photon event data stream remaining after filtering by the event filtering circuit into an enable signal for TDC quantization;

[0050] A multi-event TDC is coupled to the enable generation circuit and is used to quantify the time intervals between photon events when the enable generation circuit is triggered.

[0051] In a specific embodiment, the event filtering circuit is as follows Figure 3As shown, the event filtering circuit includes a D flip-flop D1 (DFF, Data Flip-flop) and a delay module, the clock end of the D flip-flop D1 is connected to the output end of the SiPM array, the output end (Q end) of the D flip-flop D1 is connected to the input end of the delay unit and the first input end of the two-input AND gate Y1, the output end of the delay unit is connected to the reset end (RST) of the D flip-flop D1, and the output end of the two-input AND gate Y1 is connected to the enable generation circuit.

[0052] Specifically, the event filtering circuit is mainly composed of a D flip-flop D1 with a high potential input and a voltage-controlled delay module. The clock terminal of the D flip-flop D1 is connected to the output of the SiPM array, that is, after multiple SPADs are triggered, they are quenched and reset through the pixel circuit, and then the photon event data stream (a continuous pulse) is obtained through the logic tree (such as OR / XOR-Tree). Due to the high level connected to the input terminal of the D flip-flop D1, when the first echo event arrives, the output of the D flip-flop D1 becomes a high level. After that, it will continue for a period of time and then decrease. The duration is determined by the reset moment of the DFF output by the voltage-controlled delay module. The voltage-controlled delay module is mainly implemented by the Current-Starved type first inverter, which adjusts Figure 3 The voltage value of Vn in the middle can change the size of the current flowing through the first inverter and thus change the delay. The period during which the output of the D flip-flop D1 is high forms a time window (Gate). The number of rising edges of consecutive Gates indicates the number of events after passing through the event filtering circuit, and the width of the time window also indicates the size of the time window for spatiotemporal correlation detection. The larger the time window, the more events are filtered out, the less data is required to be stored, and the pressure on the readout circuit is smaller. However, on the contrary, the larger the time window, the more signals entering the threshold detection in the time domain will also increase, which will reduce the actual effect of correlation detection. The event filtering circuit can filter out subsequent photon events within the preset delay time based on the detection of the first event. The output of the D flip-flop D1 after delayed reset can be quantified for single or multiple events according to application requirements to obtain target TOF data. This reduces the amount of data processed by the subsequent circuits, and also reduces the requirements for on-chip storage resources and output circuits, thereby saving power consumption.

[0053] In a specific embodiment, the correlation detection circuit is as follows Figure 3 As shown, the correlation detection circuit includes a counter and a multiplexer, the input end of the counter is connected to the output end of the SiPM array, the output end of the counter is connected to the input end of the multiplexer, the output end of the multiplexer is connected to the second input end of the two-input AND gate Y1, and the output end of the two-input AND gate Y1 is connected to the enable generation circuit.

[0054] Specifically, the correlation detection circuit is implemented by a threshold-controllable counter, a multiplexer, and the above-mentioned event filtering circuit. The reset signal of the counter is provided by the above-mentioned event filtering circuit, which can realize the threshold setting of 2, 4, 8, etc. photon events. Figure 4 As shown, the output of the counter is connected to the multiplexer, and the corresponding channel output enable signal Valid is selected according to the threshold setting. The above event filtering circuit can realize a controllable time window, and the window is triggered by the first SiPM input event. Multiplexing this time window can realize a time-space related threshold detection scheme. One input of the SiPM is connected to the event filtering circuit for triggering the time window, and the other is connected to the counter clock for threshold detection. The selected threshold can be switched through the multiplexer. After reaching the preset threshold, the multiplexer will generate a high-potential output connected to the subsequent enable generation circuit. If the threshold is not reached, it is background light noise, which will not trigger the subsequent circuit and save power consumption.

[0055] In a specific embodiment, the enable generation circuit is as follows Figure 3 As shown, the enable generation circuit includes a single event enable module and a multi-event enable module. The input end of the single event enable module is connected to the output end of the two-input AND gate Y1 through a switch S2, and the input end of the multi-event enable module is connected to the output end of the two-input AND gate Y1 through a switch S3. The output ends of the single event enable module and the multi-event enable module are connected to the multi-event TDC.

[0056] Specifically, the enable generation circuit is composed of a single event enable module and a multi-event enable module, which are divided into two paths to provide an enable interval for the external TDC. Figure 5 As shown, the reverse Start-Stop logic is adopted in this embodiment, that is, the echo event is used as the trigger signal and the laser synchronization signal is used as the global Stop signal. Compared with the traditional forward logic, this can reduce unnecessary work of the TDC and save a lot of power consumption when implemented in an array.

[0057] In this embodiment, the circuit of the single event enable module is as follows: Figure 6 As shown, the single event enable module includes a D flip-flop D2, a D flip-flop D3, a first inverter and a two-input AND gate Y2, the clock end of the D flip-flop D2 is connected to the output end of the two-input AND gate Y1 through a switch S2, the Q end of the D flip-flop D2 is connected to the D end of the D flip-flop D3 and the first input end of the two-input AND gate Y2, the Q end of the D flip-flop D3 is connected to the input end of the first inverter, the output end of the first inverter is connected to the second input end of the two-input AND gate Y2, and the output end of the two-input AND gate Y2 is connected to the multi-event TDC.

[0058] Specifically, Figure 5As shown in the figure, the data outputs the starting high level of the first event after passing through the first rising edge trigger. The global Stop signal generates a high level triggered at this moment. After negation and AND logic, the enable signal EN between the first event and the Stop signal is realized. The connected TDC realizes Figure 5 That is, the single event enable module provides the enable interval between the first signal of the multiplexer output (Data) and the global STOP signal, that is, the TDC no longer quantifies the TOF of subsequent events reaching the chip.

[0059] In this embodiment, a solution of alternately enabling to realize multi-event interval quantization is also proposed, that is, a multi-event enabling module is designed, which can quantify the time interval between each event including the Stop signal. Figure 7 As shown, the multi-event enable module includes a D flip-flop D4, a D flip-flop D5, a two-input AND gate Y3, a two-input AND gate Y4, a two-input AND gate Y5, a two-input AND gate Y6, a three-input OR gate H1 and a three-input OR gate H2, a clock end of the D flip-flop D4 and a clock end of the D flip-flop D5 are connected to the output end of the two-input AND gate Y1 through a switch S3, a clock end of the D flip-flop D4 and a clock end of the D flip-flop D5 are also connected to the first input end of the two-input AND gate Y3 and the first input end of the two-input AND gate Y4, a Q end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y3, a QI end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y4, and a The Q terminal is connected to the first input terminal of the two-input AND gate Y5 and the first input terminal of the two-input AND gate Y6, the output terminal of the two-input AND gate Y3 is connected to the first input terminal of the three-input OR gate H1, the output terminal of the two-input AND gate Y4 is connected to the first input terminal of the three-input OR gate H2, the second input terminal of the three-input OR gate H1 is connected to the output terminal of the three-input OR gate H2, the second input terminal of the three-input OR gate H2 is connected to the output terminal of the three-input OR gate H1, the output terminal of the three-input OR gate H1 is connected to the second input terminal of the two-input AND gate Y5, the output terminal of the three-input OR gate H2 is connected to the second input terminal of the two-input AND gate Y6, and the output terminals of the two-input AND gate Y5 and the two-input AND gate Y6 are connected to the multi-event TDC.

[0060] Specifically, the logic of the upper half of the multi-event enable module is used to generate the interval pulse between each event, and the lower half generates the enable interval from the first event to Stop. The two are combined with logic to generate the alternating enable sub-intervals within the enable interval, namely EN1 and EN2. Figure 5 As shown, a gray enable sub-interval can be generated between each adjacent event, when one is enabled, the other is in standby or readout state, and the two enable signals EN1 and EN2 are reset at the rising edge of the global Stop signal to prepare for the quantization of the next cycle.

[0061] In a specific embodiment, a multi-event TDC such as Figure 8 As shown, the multi-event TDC includes 4 first sub-path delay modules, 4 second sub-path delay modules, 8 main path delay modules and a multi-channel counter, wherein:

[0062] The node connected to the input end of the first main delay module 31 and the output end of the eighth main delay module 38 is commonly connected to the multi-channel counter, the output end of the first main delay module 31 is connected to the input end of the second main delay module 32, the output end of the first second sub-path delay module 21 and the input end of the fourth second sub-path delay module 24, the output end of the second main delay module 32 is connected to the input end of the third main delay module 33, the output end of the first first sub-path delay module 11 and the input end of the fourth first sub-path delay module 24. The input end of the module 14, the output end of the third main delay module 33, the input end of the fourth main delay module 34, the output end of the second first sub-path delay module 12 and the node connected to the fourth first sub-path delay module 14 are connected to the multi-channel counter, the output end of the fourth main delay module 34, the input end of the fifth main delay module 35 and the node connected to the output end of the second second sub-path delay module 22 are connected to the multi-channel counter, and the output end of the fifth main delay module 35 is connected to the sixth main delay module 14. The input end of the delay module 36, the output end of the third first sub-path delay module 13 and the input end of the second first sub-path delay module 13, the output end of the sixth main path delay module 36 is connected to the input end of the seventh main path delay module 37, the output end of the third second sub-path delay module 23 and the input end of the second second sub-path delay module 22, the output end of the seventh main path delay module 37, the input end of the eighth main path delay module 37, the output end of the fourth second sub-path delay module 24 and the input end of the second second sub-path delay module The node connected to the output end of 22 is commonly connected to the multi-channel counter, the node connected to the output end of the 8th main-path delay module 38 and the output end of the 4th first sub-path delay module 14 is commonly connected to the multi-channel counter, the node connected to the input end of the 1st first sub-path delay module 11 and the input end of the 1st second sub-path delay module 21 is commonly connected to the multi-channel counter, and the node connected to the input end of the 3rd first sub-path delay module 13 and the input end of the 3rd second sub-path delay module 23 is commonly connected to the multi-channel counter;

[0063] The input end of each first sub-path delay module is connected to the output end of the two-input AND gate Y5, the input end of each second sub-path delay module is connected to the output end of the two-input AND gate Y6, and the input end of each main path delay module is connected to the output end of the two-input AND gate Y2.

[0064] In this embodiment, the structures of the first sub-path delay module, the second sub-path delay module and the main path delay module are the same, and only the sizes of the MOSFETs are different, so that the delay times of the first sub-path delay module, the second sub-path delay module and the main path delay module are different. Specifically, Fig. 9 As shown, the first sub-path delay module, the second sub-path delay module and the main path delay module all include a second inverter, a diode M1, a diode M2, a diode M3 and a diode M4, the input end of the second inverter receives an enable signal, the output end of the second inverter is connected to the gate of the diode M1, the source of the diode M1 is connected to the power supply end, the drain of the diode M1 is connected to the source of the diode M2, the gate of the diode M2 ​​is connected to the gate of the diode M3, the drain of the diode M2 ​​is connected to the drain of the diode M3, the source of the diode M3 is connected to the drain of the diode M4, the gate of the diode M4 receives the enable signal, and the source of the diode M4 is grounded.

[0065] The structure of the multi-event TDC of this embodiment consists of one main loop ring oscillator and two sub-loop ring oscillators that are enabled separately. Through the module switch of the above-mentioned ring oscillator, EN1 and EN2 can enable the first sub-path delay module and the second sub-path delay module respectively. At this time, the switch S4 is disconnected, so that it oscillates alternately and resets when the global Stop signal arrives, thereby outputting two oscillation frequencies of f1 and f2. At the same time, only the main loop (i.e., the main path delay module) can be enabled to perform TOF measurement of a single event. In this mode, all three delay units work. At this time, the switch S4 is closed, and the first sub-path delay module and the second sub-path delay module are connected to the main loop respectively. The three enabling modules are all linked to the EN signal to form a "phase advance architecture" to achieve a faster oscillation frequency, thereby obtaining a higher distance resolution and outputting the corresponding f1. In different modes, the ring oscillator outputs different f for counter quantization.

[0066] The working process of the multi-event correlation processing circuit of the present invention is as follows:

[0067] like Figure 3As shown, the above-mentioned multi-event correlation processing circuit architecture does not include the SiPM array. Since the output of the SiPM array has been processed by the logic tree, the input to the event filtering circuit is a series of pulse data streams. According to the on-chip storage resources or the restrictions on the readout circuit clock, part of the data output by the SiPM can be filtered out to meet the design requirements. The number of filtered events depends on the length of the delay interval generated by the delay module. This interval can be adjusted by the voltage Vn, and no delay can be achieved without event filtering. When the first rising edge of the data stream arrives, the output of the D trigger D1 becomes a high level, and then jumps continuously according to the length of the delay and the number of data. At this time, the switch S1 can be disconnected without correlation detection, and the filtered data is generated by the enable generation circuit to generate an enable signal for TDC quantization. Switches S1 and S2 can be switched according to the application. In this way, the event output by the SiPM is filtered out and then quantized by the TDC to obtain the target TOF. And the delay signal generated by the event filtering circuit can be reused as a window signal for spatiotemporal correlation detection.

[0068] The detection mechanism of the above-mentioned spatiotemporal correlation detection circuit is as follows Figure 4 As shown, whether the number of events detected in a time window (Gate) reaches the threshold. The close proximity of echo events in the time domain corresponds to the reflection signal from the same target, which is manifested in the triggering of adjacent pixels on the pixel array. Because the background light noise event is discrete and non-distributed in the time domain compared to the echo signal, and is manifested as non-adjacent random pixel triggering in the spatial domain, the background light noise can be filtered out by the threshold detection circuit to achieve effective correlation detection in a Gate signal. When the switch S1 is closed, the data stream of the SiPM also passes through the correlation detection circuit, and the counter counts these events in the Gate signal generated by the above event filtering circuit. From the low position to the high position, a high level is output after 2, 4, 8 rising edges, so the threshold setting can be achieved by the multiplexer, and the corresponding output can be selected. At the same time, the reset of the counter cannot be achieved by the global signal, but can be achieved by the output of the above event filtering circuit to generate a valid Valid signal. Thereby reducing the pile-up distortion caused by excessive background light to improve the outdoor application performance of the chip.

[0069] The input of the enable generation circuit is the logic output of the above event filtering circuit and the above correlation detection circuit, that is, the effective echo signal Data without the background light noise. Figure 5 As shown, the Data signal passes through two enable generation modules according to application requirements to generate different enable intervals for TDC to quantify the target TOF value. Figure 6As shown in the figure, after the data passes through the first rising edge trigger, it outputs the starting high level of the first event. The global Stop signal generates a high level triggered at this moment. After negation and AND logic, the enable signal EN between the first event and the Stop signal is realized, as shown in the figure. Figure 5 The subsequent multi-event TDC implementation Figure 5 Compared with the single event enable module, the above multi-event enable signal can quantify the time interval between each event containing the Stop signal, such as Figure 7 As shown. The logic of the upper part of the multi-event enable module is used to generate the interval pulse between each event, and the lower part generates the enable interval from the first event to Stop. The two are combined with logic to generate the alternating enable sub-intervals EN1 and EN2 within the enable interval. Figure 5 As shown, a gray enable sub-interval can be generated between each adjacent event. When one is enabled, the other is on standby or in a readout state. The two enable signals EN1 and EN2 are reset at the rising edge of the global Stop signal to prepare for the quantization of the next cycle. The single event enable module realizes the time interval between the first event p1 and the global Stop signal. The interval quantified by TDC is the distance between p1 and the test chip. When using a multi-event enable module, the interval between each event from p1 to p4 to Stop will be quantified by TDC. Through the module switches S1 and S2, EN1 and EN2 can respectively enable the first sub-path delay module and the second sub-path delay module, and then output two oscillation frequencies f1 and f2 for counter quantization.

[0070] The architecture of the above multi-event TDC is as follows Figure 8 As shown, the traditional single event and multi-event TOF quantification can be achieved. The circuit of the multi-event TDC consists of a main loop ring oscillator and two sub-loop ring oscillators. The delay units of the first sub-path delay module and the second sub-path delay module are consistent, that is, the oscillation frequencies are the same. Through the module switch of the above-mentioned ring oscillator, EN1 and EN2 can respectively enable the first sub-path delay module and the second sub-path delay module in the multi-event mode, so that they oscillate alternately and reset when the global Stop signal arrives, and then output two oscillation frequencies f1 and f2. When a single event TOF measurement is required, the three delay units in this mode are all working, and the first sub-path delay module and the second sub-path delay module are respectively connected to the main loop. The output of the corresponding delay unit skips the next delay unit and is connected to the separated delay unit, forming a "phase advance architecture" to achieve a faster oscillation frequency, thereby obtaining a higher distance resolution and outputting the corresponding f1. The multi-channel counter is used to count the output frequency (f1~f3), and the output of the counter corresponds to the EN (i.e. Figure 5The corresponding shaded part in the figure) is the number of cycles of the ring oscillator. Each cycle is determined by the number of delay unit stages and unit delay. The time of a single delay unit corresponds to the time / distance resolution of the TDC.

[0071] The event filtering scheme uses a controllable delay unit to filter out individual photon events in the photon event sequence. Under conditions such as limited on-chip storage resources or TDC readout time constraints, the problem of SiPM data volume and circuit resource limitations can be reasonably alleviated. Secondly, by multiplexing the event filtering scheme, it is easier to implement threshold-controllable spatiotemporal correlation detection technology, further improving the detection performance of the lidar chip.

[0072] The multi-event correlation processing circuit of the present invention can achieve high integration and arraying while alleviating the contradiction between SiPM data volume and circuit resource limitations, effectively and flexibly suppress the interference of background light noise, reduce the impact of pile-up distortion on detector performance, and achieve multi-mode application compatibility.

[0073] The multi-mode multi-event processing technology based on SiPM front-end and spatiotemporal correlation detection proposed in this invention can realize a large array, high flexibility and high integration of optoelectronic integrated detection chip, which is one of the key parts of the lidar system. At the same time, it has indispensable and extensive applications in the consumer market, autonomous driving technology, biomedicine and aerospace fields. And with the rapid development of artificial intelligence and military equipment technology, further research on optoelectronic detection and processing technology is of great significance to ensuring national security and improving the core competitiveness of intelligent electronic systems.

[0074] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or special data points described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or special data points described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0076] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A multi-event processing circuit based on silicon photomultiplier tube, characterized in that: The multi-event processing circuit comprises: An event filtering circuit, connected to the SiPM array, for filtering out part of the photon event data stream output by the SiPM array; A correlation detection circuit, connected to the SiPM array via a switch S1, for detecting whether the number of events reaches a threshold within a time window, and if so, triggering an enable generation circuit, and if not, not triggering the enable generation circuit; An enable generation circuit is connected to the event filtering circuit and the correlation detection circuit through a two-input AND gate Y1, and is used to convert the photon event data stream remaining after the event filtering circuit is filtered into an enable signal for TDC quantization; wherein the enable generation circuit includes a single event enable module and a multi-event enable module, wherein the input end of the single event enable module is connected to the output end of the two-input AND gate Y1 through a switch S2, the input end of the multi-event enable module is connected to the output end of the two-input AND gate Y1 through a switch S3, and the output ends of the single event enable module and the multi-event enable module are connected to a multi-event TDC; The multi-event TDC is used to quantify the time intervals between photon events when the enable generation circuit is triggered.

2. The multi-event processing circuit based on silicon photomultiplier tube according to claim 1, characterized in that: The event filtering circuit includes a D trigger D1 and a delay module, wherein: The clock end of the D flip-flop D1 is connected to the output end of the SiPM array, the output end of the D flip-flop D1 is connected to the input end of the delay module and the first input end of the two-input AND gate Y1, the output end of the delay module is connected to the reset end of the D flip-flop D1, and the output end of the two-input AND gate Y1 is connected to the enable generation circuit.

3. The multi-event processing circuit based on silicon photomultiplier tube according to claim 2, characterized in that: The delay module includes a first inverter.

4. The multi-event processing circuit based on silicon photomultiplier tube according to claim 3, characterized in that: The first inverter is a Current-Starved first inverter.

5. The multi-event processing circuit based on silicon photomultiplier tube according to claim 2, characterized in that: The correlation detection circuit includes a counter and a multiplexer, wherein: The input end of the counter is connected to the output end of the SiPM array, the output end of the counter is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the second input end of the two-input AND gate Y1.

6. The multi-event processing circuit based on silicon photomultiplier tube according to claim 1, characterized in that: The single event enable module includes a D flip-flop D2, a D flip-flop D3, a first inverter and a two-input AND gate Y2, wherein: The clock end of the D flip-flop D2 is connected to the output end of the two-input AND gate Y1 through the switch S2, the Q end of the D flip-flop D2 is connected to the D end of the D flip-flop D3 and the first input end of the two-input AND gate Y2, the Q end of the D flip-flop D3 is connected to the input end of the first inverter, the output end of the first inverter is connected to the second input end of the two-input AND gate Y2, and the output end of the two-input AND gate Y2 is connected to the multi-event TDC.

7. The multi-event processing circuit based on silicon photomultiplier tube according to claim 6, characterized in that: The multi-event enable module includes a D flip-flop D4, a D flip-flop D5, a two-input AND gate Y3, a two-input AND gate Y4, a two-input AND gate Y5, a two-input AND gate Y6, a three-input OR gate H1 and a three-input OR gate H2, wherein: The clock end of the D flip-flop D4 and the clock end of the D flip-flop D5 are connected to the output end of the two-input AND gate Y1 through the switch S3, the clock end of the D flip-flop D4 and the clock end of the D flip-flop D5 are also connected to the first input end of the two-input AND gate Y3 and the first input end of the two-input AND gate Y4, the Q end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y3, the QI end of the D flip-flop D4 is connected to the second input end of the two-input AND gate Y4, the Q end of the D flip-flop D5 is connected to the first input end of the two-input AND gate Y5 and the first input end of the two-input AND gate Y6, and the two-input AND gate Y3 is connected to the second input end of the two-input AND gate Y3. The output end of gate Y3 is connected to the first input end of the three-input OR gate H1, the output end of the two-input AND gate Y4 is connected to the first input end of the three-input OR gate H2, the second input end of the three-input OR gate H1 is connected to the output end of the three-input OR gate H2, the second input end of the three-input OR gate H2 is connected to the output end of the three-input OR gate H1, the output end of the three-input OR gate H1 is connected to the second input end of the two-input AND gate Y5, the output end of the three-input OR gate H2 is connected to the second input end of the two-input AND gate Y6, and the output end of the two-input AND gate Y5 and the output end of the two-input AND gate Y6 are connected to the multi-event TDC.

8. The multi-event processing circuit based on silicon photomultiplier tube according to claim 7, characterized in that: The multi-event TDC includes 4 first sub-path delay modules, 4 second sub-path delay modules, 8 main path delay modules and a multi-channel counter, wherein: The node connected to the input end of the first main delay module 31 and the output end of the eighth main delay module 38 is commonly connected to the multi-channel counter, the output end of the first main delay module 31 is connected to the input end of the second main delay module 32, the output end of the first second sub-delay module 21 and the input end of the fourth second sub-delay module 24, the output end of the second main delay module 32 is connected to the input end of the third main delay module 33, the output end of the first first sub-delay module 11 and the input end of the fourth first sub-delay module 24. The input end of the delay module 14, the output end of the third main delay module 33, the input end of the fourth main delay module 34, the output end of the second first sub-path delay module 12 and the node connected to the fourth first sub-path delay module 14 are connected to the multi-channel counter, the output end of the fourth main delay module 34, the input end of the fifth main delay module 35 and the node connected to the output end of the second second sub-path delay module 22 are connected to the multi-channel counter, and the output end of the fifth main delay module 35 is connected to the sixth The input end of the main delay module 36, the output end of the third first sub-path delay module 13 and the input end of the second first sub-path delay module 13, the output end of the sixth main delay module 36 is connected to the input end of the seventh main delay module 37, the output end of the third second sub-path delay module 23 and the input end of the second second sub-path delay module 22, the output end of the seventh main delay module 37, the input end of the eighth main delay module 37, the output end of the fourth second sub-path delay module 24 and the input end of the second second sub-path delay module 25 are connected to each other. The node connected to the output end of block 22 is commonly connected to the multi-channel counter, the node connected to the output end of the eighth main-path delay module 38 and the output end of the fourth first sub-path delay module 14 is commonly connected to the multi-channel counter, the node connected to the input end of the first first sub-path delay module 11 and the input end of the first second sub-path delay module 21 is commonly connected to the multi-channel counter, and the node connected to the input end of the third first sub-path delay module 13 and the input end of the third second sub-path delay module 23 is commonly connected to the multi-channel counter; The input end of each of the first sub-path delay modules is connected to the output end of the two-input AND gate Y5, the input end of each of the second sub-path delay modules is connected to the output end of the two-input AND gate Y6, and the input end of each of the main path delay modules is connected to the output end of the two-input AND gate Y2.

9. The multi-event processing circuit based on silicon photomultiplier tube according to claim 8, characterized in that: The first sub-path delay module, the second sub-path delay module and the main path delay module each include a second inverter, a diode M1, a diode M2, a diode M3 and a diode M4, wherein: The input end of the second inverter receives an enable signal, the output end of the second inverter is connected to the gate of the diode M1, the source of the diode M1 is connected to the power supply end, the drain of the diode M1 is connected to the source of the diode M2, the gate of the diode M2 ​​is connected to the gate of the diode M3, the drain of the diode M2 ​​is connected to the drain of the diode M3, the source of the diode M3 is connected to the drain of the diode M4, the gate of the diode M4 receives the enable signal, and the source of the diode M4 is grounded.

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