Processors and related products

Abstract

The present application discloses a processor and related products, which include: a multi-threaded scalar execution unit, a multi-threaded vector execution unit, and an extended register; the multi-threaded scalar execution unit includes at least two single-threaded scalar execution units; the multi-threaded scalar execution unit is coupled to the extended register, and the multi-threaded vector execution unit is coupled to the extended register; the multi-threaded scalar execution unit is used to write first control information to the extended register; the multi-threaded vector execution unit is used to read the first control information from the extended register and perform data processing based on the first control information. In the embodiment of the present application, the extended register in the processor realizes data exchange between the multi-threaded vector execution unit and the multi-threaded scalar execution unit, can simultaneously realize thread parallelism and data operation parallelism, and can achieve a higher energy efficiency ratio.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a processor and related products. Background Art

[0002] Artificial intelligence (AI) is a new technical discipline that studies and develops theories, methods, technologies, and application systems for simulating, extending, and expanding human intelligence. Also known as intelligent machinery or machine intelligence, AI refers to the intelligence exhibited by machines created by humans. Generally, AI refers to the technology that replicates human intelligence through ordinary computer programs.

[0003] With the development of artificial intelligence technology, the demand for high computing power is becoming stronger and stronger. More and more specialized processors for artificial intelligence application scenarios have emerged. Therefore, it is necessary to research processors with higher computing power. Summary of the Invention

[0004] The embodiments of the present application disclose a processor and related products.

[0005] In a first aspect, an embodiment of the present application provides a processor comprising: a multi-threaded scalar execution unit, a multi-threaded vector execution unit, and an extended register; the multi-threaded scalar execution unit comprises at least two single-threaded scalar execution units, and the multi-threaded vector execution unit comprises at least two single-threaded vector execution units; the multi-threaded scalar execution unit is coupled to the extended register, and the multi-threaded vector execution unit is coupled to the extended register; the multi-threaded scalar execution unit is used to write first control information into the extended register; the multi-threaded vector execution unit is used to read the first control information from the extended register and perform a data processing task based on the first control information.

[0006] In an embodiment of the present application, the extended registers in the processor realize data interaction between the multi-threaded vector execution unit and the multi-threaded scalar execution unit, can simultaneously realize thread parallelism and data operation parallelism, and can obtain a higher energy efficiency ratio.

[0007] In one possible implementation, the at least two single-threaded scalar execution units are used to execute different threads in parallel based on the same instruction, and the at least two single-threaded vector execution units are used to execute the same operation on different data sets in parallel based on the same instruction.

[0008] In one possible implementation, the multi-threaded scalar execution unit is further used to perform an operation on the first data to obtain a first operation result, and generate the first control information based on the first operation result; the multi-threaded vector execution unit is used to perform an operation on the first operation result based on the first control information to obtain a second operation result.

[0009] The multi-threaded scalar execution unit is more suitable for performing operations on the first data, that is, the efficiency of the multi-threaded scalar execution unit in performing operations on the first data is higher than the efficiency of the multi-threaded vector execution unit in performing operations on the first data; the multi-threaded vector execution unit is more suitable for performing operations on the first operation result, that is, the efficiency of the multi-threaded vector execution unit in performing operations on the first operation result is higher than the efficiency of the multi-threaded scalar execution unit in performing operations on the first operation result.

[0010] In this implementation, the multi-threaded scalar execution unit and the multi-threaded vector execution unit cooperate to complete the same data processing task, which can fully utilize the advantages of the multi-threaded scalar execution unit and the multi-threaded vector execution unit to improve the efficiency of executing data processing tasks.

[0011] In one possible implementation, the first control information includes data indication information of multiple data elements contained in the vector data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit is used to determine at least one target data element to be processed included in the multiple data elements based on the data indication information, and perform operations on the at least one target data element.

[0012] In one possible implementation, the first control information includes enable indication information of M threads corresponding to the first instruction; the multi-threaded vector execution unit is used to determine at least one target thread among the M threads based on the enable indication information, and use at least one single-threaded vector execution unit corresponding to the at least one target thread to execute the data processing task.

[0013] In this implementation, the multi-threaded vector execution unit can accurately determine the target thread to be adopted for executing the data processing task according to the enable indication information included in the first control information, with low resource overhead.

[0014] In one possible implementation, the first control information also includes address information of data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit also includes a data handling unit and at least one register file, wherein the register file includes at least one vector register; the data handling unit is used to obtain the data to be processed from the external memory based on the address information included in the first control information, and store the obtained data to be processed in the at least one register file.

[0015] In one possible implementation, the first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; and the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

[0016] The computing power of a tensor compute unit is higher than that of a scalar compute unit. In other words, the computing power of a single-threaded vector execution unit is higher than that of a single-threaded scalar execution unit.

[0017] In this implementation, the fusion of the multi-threaded vector execution unit and the multi-threaded scalar execution unit is achieved by expanding the registers, which can combine the advantages of the multi-threaded vector execution unit and the advantages of the multi-threaded scalar execution unit to better execute computing tasks.

[0018] In a possible implementation, the extension register is set inside the processor independently of the multi-threaded scalar execution unit and the multi-threaded vector execution unit.

[0019] The extension register is independent of the multi-threaded scalar execution unit and the multi-threaded vector execution unit and is disposed within the processor. The extension register only needs to be coupled to the multi-threaded scalar execution unit and the multi-threaded vector execution unit, respectively, resulting in minimal impact on the multi-threaded scalar execution unit and the multi-threaded vector execution unit, and is easy to design and implement at a low cost.

[0020] In one possible implementation, the first control information indicates K data elements in the first data to be calculated in parallel, where K is an integer greater than 1; the data processing based on the first control information includes: K single-threaded vector execution units in the multi-threaded vector execution unit using the K data elements in parallel to perform a first operation; the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than K, and any single-threaded vector execution unit among the K single-threaded vector execution units uses one data element of the K data elements to perform the first operation.

[0021] In this implementation, the multi-threaded vector execution unit performs parallel calculations on multiple data elements through some of the single-threaded vector execution units included therein based on the first control information, which can improve calculation efficiency.

[0022] In one possible implementation, the first control information indicates masked data elements in the second data; the data processing based on the first control information includes: F single-threaded vector execution units in the multi-threaded vector execution unit perform a second operation in parallel using F data elements; F is an integer greater than 1, the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than F, the F data elements are unmasked data elements in the second data, and any single-threaded vector execution unit among the F single-threaded vector execution units performs the second operation using one data element of the F data elements.

[0023] In this implementation, the multi-threaded vector execution unit performs parallel calculations on multiple data elements through some of the single-threaded vector execution units included therein based on the first control information, which can improve calculation efficiency.

[0024] In one possible implementation, the first control information indicates N masked threads and / or L unmasked threads among the M threads corresponding to the first instruction, where N is an integer greater than 0 and less than M, and L is an integer greater than 1 and less than M; the data processing based on the first control information includes: multiple single-threaded vector execution units in the multi-threaded vector execution unit executing computing tasks of unmasked threads among the M threads in parallel; or, L single-threaded vector execution units in the multi-threaded vector execution unit executing computing tasks of the L unmasked threads in parallel.

[0025] In one possible implementation, the multi-threaded vector execution unit further includes a data handling unit; the data processing based on the first control information includes: the data handling unit obtains H data elements from an external memory based on address information included in the first control information, where H is an integer greater than 1; H single-threaded vector execution units in the multi-threaded vector execution unit use the H data elements in parallel to perform a third operation; the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than H, and any single-threaded vector execution unit among the H single-threaded vector execution units uses one data element of the H data elements to perform the third operation.

[0026] In this implementation, the multi-threaded vector execution unit performs parallel calculations on multiple data elements through some of the single-threaded vector execution units included therein based on the first control information, which can improve calculation efficiency.

[0027] In one possible implementation, the tensor calculation unit includes a matrix calculation unit and / or a vector calculation unit and a data sorting unit; the matrix calculation unit is used to perform matrix multiplication operations, the vector calculation unit is used to perform vector operations, and the data sorting unit is used to exchange and rearrange the data stored in the register file in the processor to obtain multiple data elements to be processed in parallel by the matrix calculation unit and / or the vector calculation unit.

[0028] In this implementation, the tensor computing unit can implement computing tasks that require high computing power through the matrix computing unit and / or the vector computing unit and the data sorting unit.

[0029] In a second aspect, an embodiment of the present application provides a multi-threaded processing method, which is applied to a processor, wherein the processor includes a multi-threaded scalar execution unit, a multi-threaded vector execution unit, and an extended register, wherein the multi-threaded vector execution unit includes at least two single-threaded vector execution units, and the multi-threaded vector execution unit includes at least two single-threaded vector execution units; the method includes: the multi-threaded scalar execution unit writes first control information into the extended register; the multi-threaded vector execution unit reads the first control information from the extended register, and performs a data processing task based on the first control information.

[0030] In one possible implementation, the at least two single-threaded scalar execution units are used to execute different threads in parallel based on the same instruction, and the at least two single-threaded vector execution units are used to execute the same operation on different data sets in parallel based on the same instruction.

[0031] In one possible implementation, before the multi-threaded scalar execution unit writes the first control information into the extended register, the method further includes: the multi-threaded scalar execution unit performs an operation on the first data to obtain a first operation result, and generates the first control information based on the first operation result; the multi-threaded vector execution unit performs a data processing task based on the first control information, including: the multi-threaded vector execution unit performs an operation on the first operation result based on the first control information to obtain a second operation result.

[0032] In one possible implementation, the first control information includes data indication information of multiple data elements included in the vector data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit performs a data processing task based on the first control information, including: the multi-threaded vector execution unit determines at least one target data element to be processed included in the multiple data elements based on the data indication information, and performs operations on the at least one target data element.

[0033] In one possible implementation, the first control information includes enable indication information of M threads corresponding to the first instruction; the multi-threaded vector execution unit executing the data processing task based on the first control information includes: the multi-threaded vector execution unit determining at least one target thread among the M threads based on the enable indication information, and using at least one single-threaded vector execution unit corresponding to the at least one target thread to execute the data processing task.

[0034] In one possible implementation, the first control information also includes address information of data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit also includes a data handling unit and at least one register file, wherein the register file includes at least one vector register; the method further includes: the data handling unit obtains the data to be processed from the external memory based on the address information included in the first control information, and stores the obtained data to be processed in the at least one register file.

[0035] In one possible implementation, the first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; and the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

[0036] In a possible implementation, the extension register is set inside the processor independently of the multi-threaded scalar execution unit and the multi-threaded vector execution unit.

[0037] In one possible implementation, the first control information indicates K data elements in the first data to be calculated in parallel, where K is an integer greater than 1; the data processing based on the first control information includes: K single-threaded vector execution units in the multi-threaded vector execution unit using the K data elements in parallel to perform a first operation; the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than K, and any single-threaded vector execution unit among the K single-threaded vector execution units uses one data element of the K data elements to perform the first operation.

[0038] In one possible implementation, the first control information indicates masked data elements in the second data; the data processing based on the first control information includes: F single-threaded vector execution units in the multi-threaded vector execution unit perform a second operation in parallel using F data elements; F is an integer greater than 1, the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than F, the F data elements are unmasked data elements in the second data, and any single-threaded vector execution unit among the F single-threaded vector execution units performs the second operation using one data element of the F data elements.

[0039] In one possible implementation, the first control information indicates N masked threads and / or L unmasked threads among the M threads corresponding to the first instruction, where N is an integer greater than 0 and less than M, and L is an integer greater than 1 and less than M; the data processing based on the first control information includes: multiple single-threaded vector execution units in the multi-threaded vector execution unit executing computing tasks of unmasked threads among the M threads in parallel; or, L single-threaded vector execution units in the multi-threaded vector execution unit executing computing tasks of the L unmasked threads in parallel.

[0040] In one possible implementation, the multi-threaded vector execution unit further includes a data handling unit; the data processing based on the first control information includes: the data handling unit obtains H data elements from an external memory based on address information included in the first control information, where H is an integer greater than 1; H single-threaded vector execution units in the multi-threaded vector execution unit use the H data elements in parallel to perform a third operation; the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than H, and any single-threaded vector execution unit among the H single-threaded vector execution units uses one data element of the H data elements to perform the third operation.

[0041] In one possible implementation, the tensor calculation unit includes a matrix calculation unit and / or a vector calculation unit and a data sorting unit; the matrix calculation unit is used to perform matrix multiplication operations, the vector calculation unit is used to perform vector operations, and the data sorting unit is used to exchange and rearrange the data stored in the register file in the processor to obtain multiple data elements to be processed in parallel by the matrix calculation unit and / or the vector calculation unit.

[0042] Regarding the technical effects brought about by the second aspect or various optional implementation methods, reference may be made to the introduction to the technical effects of the first aspect or corresponding implementation methods.

[0043] In a third aspect, an embodiment of the present application provides an electronic device comprising: a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory, so that the processor executes the method as described in the second aspect above and any possible implementation method.

[0044] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the processor of the first aspect or any possible implementation of the first aspect. Optionally, the processor is configured to execute the method of the second aspect or any possible implementation of the second aspect.

[0045] In a possible implementation, the electronic device is a chip.

[0046] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program includes program instructions, which, when executed by a processor, enable the processor to execute the method of the above-mentioned second aspect and any optional implementation method.

[0047] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes program instructions, and when the program instructions are executed by a processor, the processor executes the method of the above-mentioned second aspect and any optional implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0049] Figure 1 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of an example of a multi-threaded vector execution unit provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of the structure of an example of a single-threaded vector execution unit provided in an embodiment of the present application;

[0052] Figure 4 A schematic structural diagram of another example of a single-threaded vector execution unit provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of the structure of an example of a single-threaded scalar execution unit provided in an embodiment of the present application;

[0054] Figure 6A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0056] Figure 8 A flowchart of a multi-threaded processing method provided in an embodiment of the present application;

[0057] Figure 9 This is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0058] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described below with reference to the accompanying drawings.

[0060] The terms "first" and "second" in the specification, claims, and drawings of this application are used only to distinguish different objects and are not used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device.

[0061] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It will be understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0062] In this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three and more than three, and "and / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0063] The structure of the processor provided in the embodiment of the present application is first introduced below. Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of the present application. Figure 1 As shown, the processor includes:

[0064] A multi-threaded scalar execution unit 101, a multi-threaded vector execution unit 102, and an extended register 103; the multi-threaded scalar execution unit 101 includes at least two single-threaded scalar execution units, and the multi-threaded vector execution unit 102 includes at least two single-threaded vector execution units;

[0065] The multi-threaded scalar execution unit 101 is coupled to the extension register 103 , and the multi-threaded vector execution unit 101 is coupled to the extension register 103 ;

[0066] The multi-threaded scalar execution unit 101 is configured to write the first control information into the extension register;

[0067] The multi-threaded vector execution unit 102 is configured to read the first control information from the extension register and execute a data processing task based on the first control information.

[0068] In some embodiments, the at least two single-threaded scalar execution units are used to execute different threads based on the same instruction in parallel, and the at least two single-threaded vector execution units are used to perform the same operation on different data sets based on the same instruction in parallel. In some embodiments, the multi-threaded scalar execution unit 101 includes multiple single-threaded scalar execution units, and the multi-threaded scalar execution unit 101 adopts a SIMT architecture. In some embodiments, each time the multi-threaded scalar execution unit 101 executes an instruction, multiple single-threaded scalar execution units simultaneously complete the process of fetching, calculating, and writing back the results, thereby realizing thread parallel computing. That is, the multi-threaded scalar execution unit 101 uses single instruction multiple threads (SIMT) technology to execute different threads based on the same instruction in parallel. In some embodiments, the architecture of the multi-threaded scalar execution unit 101 may be similar to that of a graphics processing unit (GPU).

[0069] SIMT technology can effectively improve computing efficiency. Compared with traditional single-threaded processors, on the one hand, the programming abstraction of parallel tasks is simpler. On the other hand, it hides computing delays by multiple threads, reducing the design complexity of instruction scheduling.

[0070] In some embodiments, the multi-threaded vector execution unit 102 includes multiple single-threaded vector execution units, and the multi-threaded vector execution unit 102 adopts a SIMD architecture. In some embodiments, each time the multi-threaded vector execution unit 102 executes an instruction, multiple single-threaded vector execution units simultaneously complete the process of fetching data, calculating, and writing back the results, thereby enabling thread-parallel computing. In other words, the multi-threaded vector execution unit 102 uses single instruction multiple data (SIMD) technology to perform the same operation on different data sets based on the same instruction in parallel. In some embodiments, the architecture of the multi-threaded vector execution unit 102 can be similar to that of a central processing unit (CPU).

[0071] SIMD is a technology that uses a single controller to control multiple processors, simultaneously performing the same operation on each piece of a set of data (also known as a "data vector"), thereby achieving spatial parallelism. In other words, SIMD is a technology that achieves data-level parallelism, typified by vector processors and array processors. The key to SIMD technology is the simultaneous execution of multiple operations within a single instruction to increase processor throughput. To this end, a SIMD-structured central processing unit (CPU) has multiple processing units, all controlled by the same instruction set. The central controller sends instructions to each processing unit. The entire system requires only one central controller and only one program to be stored, and all calculations are synchronized. The following example uses the addition instruction to illustrate the performance advantages of SIMD over single instruction single data stream (SISD): After a SISD CPU decodes an addition instruction, the execution unit must first access main memory to obtain the first operand, then access main memory again to obtain the second operand before performing the sum operation. In contrast, in a SIMD CPU, after the instruction is decoded, several execution units access main memory simultaneously, obtaining all operands at once for calculation. Therefore, using SIMD technology can improve the processing efficiency of tasks such as data-intensive computing.

[0072] In some embodiments, extension registers 103 enable data exchange between the multi-threaded vector execution unit 102 and the multi-threaded scalar execution unit 101. When executing computations, each thread in the multi-threaded vector execution unit 102 requires different computation control information, which must be provided by the multi-threaded scalar computation unit 101. In other words, the multi-threaded vector execution unit 102 requires control information obtained by the multi-threaded scalar computation unit 101 from executing certain scalar execution instructions. The multi-threaded scalar execution unit 101 writes this control information into the extension registers 103, and the multi-threaded vector execution unit 102 reads the control information from the extension registers 103.

[0073] In a possible implementation, the multi-threaded scalar execution unit 101 is further configured to perform an operation on the first data to obtain a first operation result, and generate the first control information based on the first operation result;

[0074] The multi-threaded vector execution unit 102 is configured to perform a calculation on the first calculation result based on the first control information to obtain a second calculation result.

[0075] The multi-threaded scalar execution unit 101 is more suitable for performing operations on the first data, that is, the efficiency of the multi-threaded scalar execution unit 101 in performing operations on the first data is higher than the efficiency of the multi-threaded vector execution unit 102 in performing operations on the first data; the multi-threaded vector execution unit 102 is more suitable for performing operations on the first operation result, that is, the efficiency of the multi-threaded vector execution unit 102 in performing operations on the first operation result is higher than the efficiency of the multi-threaded scalar execution unit 101 in performing operations on the first operation result.

[0076] In this implementation, the multi-threaded scalar execution unit and the multi-threaded vector execution unit cooperate to complete the same data processing task, which can fully utilize the advantages of the multi-threaded scalar execution unit and the multi-threaded vector execution unit to improve the efficiency of executing data processing tasks.

[0077] In order to adapt to the increasing demand for computing power, the common practice is to increase the number of threads of the SIMT processor. Since a single thread is scheduled independently, this leads to an increase in the complexity of hardware design while the increase in computing power is relatively limited. SIMD technology increases computing performance by executing a single instruction while having multiple sets of data participate in the calculation. The multiple data corresponding to SIMD are fixed and continuous, sacrificing some flexibility but with higher access and execution efficiency. The related technology uses only SIMT technology or SIMD technology to improve computing efficiency and parallelism, but lacks a processor design architecture and solution that effectively integrates the two technologies. The present application provides a processor architecture (corresponding to the processor in this application) that effectively integrates SIMT technology and SIMD technology, which can effectively improve computing power.

[0078] In a possible implementation, the first control information includes data indication information of a plurality of data elements included in the vector data to be processed by the multi-threaded vector execution unit 102;

[0079] The multi-threaded vector execution unit 102 is configured to determine, based on the data indication information, at least one target data element to be processed included in the plurality of data elements, and perform operations on the at least one target data element. For example, the multi-threaded vector execution unit 102 may perform computations on 16 data elements in parallel. The data indication information indicates 8 (corresponding to K) data elements included in the vector data to be processed by the multi-threaded vector execution unit 102, and 8 single-threaded vector execution units in the multi-threaded vector execution unit 102 each perform operations using one of the 8 data elements; wherein the 8 single-threaded vector execution units perform operations in parallel.

[0080] In a possible implementation, the first control information includes enable indication information of M threads corresponding to the first instruction; and M is an integer greater than 1.

[0081] The multi-threaded vector execution unit 102 is configured to determine at least one target thread among the M threads based on the enable indication information, and to execute the data processing task using at least one single-threaded vector execution unit corresponding to the at least one target thread. Optionally, the enable indication information is configured to indicate a portion of the M threads corresponding to the first instruction, namely, the at least one target thread. In some embodiments, M is less than the number of single-threaded vector execution units included in the multi-threaded vector execution unit 102 and greater than 1.

[0082] In this implementation, the multi-threaded vector execution unit can accurately determine the target thread to be adopted for executing the data processing task according to the enable indication information included in the first control information, with low resource overhead.

[0083] In one possible implementation, the first control information also includes address information of the data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit also includes a data transfer unit and at least one register stack, wherein the register stack includes at least one vector register; the data transfer unit is used to obtain the data to be processed from the external memory based on the address information included in the first control information, and store the obtained data to be processed in the at least one register stack.

[0084] In one possible implementation, the first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; and the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

[0085] The computing power of a tensor compute unit is higher than that of a scalar compute unit. In other words, the computing power of a single-threaded vector execution unit is higher than that of a single-threaded scalar execution unit.

[0086] In this implementation, the fusion of the multi-threaded vector execution unit and the multi-threaded scalar execution unit is achieved by expanding the registers, which can combine the advantages of the multi-threaded vector execution unit and the advantages of the multi-threaded scalar execution unit to better execute computing tasks.

[0087] In a possible implementation, the extension register 103 is provided inside the processor independently of the multi-threaded scalar execution unit 101 and the multi-threaded vector execution unit 102 .

[0088] The extension register is independent of the multi-threaded scalar execution unit and the multi-threaded vector execution unit and is disposed within the processor. The extension register only needs to be coupled to the multi-threaded scalar execution unit and the multi-threaded vector execution unit, respectively, resulting in minimal impact on the multi-threaded scalar execution unit and the multi-threaded vector execution unit, and is easy to design and implement at a low cost.

[0089] In a possible implementation, the extension register 103 is set inside the multi-threaded scalar execution unit 101 or inside the multi-threaded vector execution unit 102 .

[0090] In one possible implementation, the first control information indicates masked data elements in the second data; the multi-threaded vector execution unit 102 processes data based on the first control information as follows: F single-threaded vector execution units in the multi-threaded vector execution unit 102 concurrently perform a second operation using F data elements; F is an integer greater than 1, the number of single-threaded vector execution units in the multi-threaded vector execution unit 102 is greater than F, the F data elements are unmasked data elements in the second data, and any single-threaded vector execution unit in the F single-threaded vector execution units performs the second operation using one of the F data elements. The second data can be any data and is not limited in this application. A possible example is as follows: a programmer writes a program, which is compiled to generate one or more instructions that can be executed by the processor in the embodiment of this application. The one or more instructions are initially stored in external storage space, such as double data rate synchronous dynamic random access memory (DDR). When the program in the processor starts running, the processor retrieves the instructions from the external storage space to perform the computing task. When programming, the calculation and judgment of control information will be involved. For example, the multi-threaded vector execution unit has both multi-threaded parallelism and SIMD (corresponding to arithmetic operations) parallelism. These degrees of parallelism are fixed values ​​after the design is finalized. However, in actual programming, there are often situations where the degree of parallelism is not fully utilized. For example, the multi-threaded vector execution unit 102 can perform calculation tasks for 16 data elements at a time, but currently only 8 valid data elements can be calculated in parallel. In this case, the programmer needs to calculate and generate corresponding control bits (corresponding to control information) in the program to mask the positions that do not need to be calculated. The generation of these control bits requires the multi-threaded scalar calculation unit to calculate and obtain them, and then write them into the extension register to pass the control information to the multi-threaded vector execution unit. The first control information can be understood as being used to mask the data elements that do not need to be calculated in the second data.

[0091] In one possible implementation, the first control information indicates N threads that are masked and / or L threads that are not masked among the M threads corresponding to the first instruction, where N is an integer greater than 0 and less than M, and L is an integer greater than 1 and less than M. The data processing based on the first control information includes:

[0092] Multiple single-threaded vector execution units in the multi-threaded vector execution unit execute computing tasks of unmasked threads in the M threads in parallel; or L single-threaded vector execution units in the multi-threaded vector execution unit execute computing tasks of the L unmasked threads in parallel.

[0093] In one possible implementation, the multi-threaded vector execution unit 102 further includes a data transfer unit. The multi-threaded vector execution unit 102 performs data processing based on the first control information as follows: the data transfer unit retrieves H data elements from the external memory based on the address information included in the first control information, where H is an integer greater than 1; H single-threaded vector execution units in the multi-threaded vector execution unit 102 concurrently perform a third operation using the H data elements; and if the number of single-threaded vector execution units in the multi-threaded vector execution unit 102 is greater than H, any of the H single-threaded vector execution units performs the third operation using one of the H data elements. In some embodiments, the multi-threaded vector execution unit 102 further includes a register file. Optionally, each unit of the register file is a vector register, for example, containing 16 data elements for parallel computation. In some embodiments, the register file is divided into multiple banks to support simultaneous access by multiple single-threaded vector execution units. The data transfer unit can transfer data between the register file and the external memory (corresponding to the external memory). In some embodiments, the first control information includes a portion of address information required by the data handling unit to access external memory, such as an address offset.

[0094] In some embodiments, the first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computation unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computation unit; and the computing power of the tensor computation unit is higher than the computing power of the scalar computation unit. The first single-threaded vector execution unit is any single-threaded vector execution unit among the at least two single-threaded vector execution units, and the first single-threaded scalar execution unit is any single-threaded scalar execution unit among the at least two single-threaded scalar execution units. Optionally, the tensor computation unit includes a matrix computation unit and / or a vector computation unit and a data sorting unit; the matrix computation unit is configured to perform matrix multiplication operations, the vector computation unit is configured to perform vector operations, and the data sorting unit is configured to exchange and rearrange data stored in the register file of the processor to obtain multiple data elements to be processed in parallel by the matrix computation unit and / or the vector computation unit. Optionally, the scalar computation unit is divided into an integer computation unit and a floating-point computation unit, wherein the integer computation unit is configured to perform integer computations and the floating-point computation unit is configured to perform floating-point computations. That is, any single-threaded scalar execution unit may include multiple groups of scalar computing units, where the integer computing unit is a group of scalar computing units and the floating-point computing unit is a group of scalar computing units.

[0095] In an embodiment of the present application, the extended registers in the processor realize data interaction between the multi-threaded vector execution unit and the multi-threaded scalar execution unit, can simultaneously realize thread parallelism and data operation parallelism, and can obtain a higher energy efficiency ratio.

[0096] The following describes an example structure of a multi-threaded vector execution unit with reference to the accompanying drawings.

[0097] Figure 2 This is a schematic diagram of an example of a multi-threaded vector execution unit provided in an embodiment of the present application. Figure 2 As shown, the multi-threaded vector execution unit 102 includes P (e.g., 16) single-threaded vector execution units and a register file 1021. The above P is an integer greater than 1. In some embodiments, the structures and functions of the single-threaded vector execution units included in the multi-threaded vector execution unit 102 are the same. The single-threaded vector execution units included in the multi-threaded vector execution unit 102 share the register file 1021, and each single-threaded vector execution unit can execute the same operation in parallel. In some embodiments, the register file is divided into multiple banks to support simultaneous access by multiple single-threaded vector execution units. For example, the register file includes multiple vector registers, each single-threaded vector execution unit occupies one vector register, for example, the register file contains 16 data elements for parallel calculation.

[0098] Since the structures and functions of the single-threaded vector execution units included in the multi-threaded vector execution unit 102 are the same, the structure of the single-threaded vector execution unit is described below by taking any single-threaded vector execution unit as an example.

[0099] Figure 3 This is a schematic diagram of an example of a single-threaded vector execution unit provided in an embodiment of the present application. Figure 3 As shown, 30 represents any single-threaded vector execution unit included in the multi-threaded vector execution unit 102. The single-threaded vector execution unit 30 includes a tensor calculation unit 301 and a data handling unit 302. The tensor calculation unit 301 is responsible for high-performance calculations, such as matrix multiplication operations. The data handling unit 302 can realize data transfer between the register file 1021 and the external memory (corresponding to the external memory). In other words, the data handling unit 302 can read data from the external memory and write the read data to the register file. Figure 3 In the embodiment, the register file 1021 is not exclusively used by the single-threaded vector execution unit 30, but rather the single-threaded vector execution unit 30 shares the register file 1021 with other single-threaded vector execution units. In some embodiments, each time the multi-threaded vector execution unit 102 executes an instruction, multiple single-threaded vector execution units perform operations of fetching, calculating, and writing back results in parallel, thereby achieving thread-parallel calculations. For example, the multi-threaded vector execution unit 102 includes 16 single-threaded vector execution units, each of which includes a data handling unit. Each single-threaded vector execution unit occupies a vector register in the register file. The data handling unit of each single-threaded vector execution unit reads a data element from external memory and writes it into the vector register occupied by the single-threaded vector execution unit. Each single-threaded vector execution unit reads a data element from the vector register it occupies and performs calculations. In this example, the 16 single-threaded vector execution units perform operations of fetching (i.e., reading data elements from the vector register), calculating, and writing back results in parallel. Result writing back means that the single-threaded vector execution unit writes its calculation result into the vector register it occupies. For another example, the multi-threaded vector execution unit 102 reads first control information from the extended register, and based on the first control information, executes eight computing tasks in parallel through eight of the 16 single-threaded vector execution units included therein; wherein each of the eight single-threaded vector execution units reads data elements from the vector register it occupies, performs calculations using the read data elements, and writes the calculation results to the vector register it occupies.

[0100] In some embodiments, the tensor calculation unit 301 includes a matrix calculation unit and / or a vector calculation unit and a data sorting unit; the above-mentioned matrix calculation unit is used to perform matrix multiplication operations, the above-mentioned vector calculation unit is used to perform vector operations, and the above-mentioned data sorting unit is used to exchange and rearrange the data stored in the register stack in the above-mentioned processor to obtain multiple data elements to be processed in parallel by the above-mentioned matrix calculation unit and / or the above-mentioned vector calculation unit. Figure 4 A schematic structural diagram of another example of a single-threaded vector execution unit provided in an embodiment of the present application. Figure 4 The single-threaded vector execution unit in Figure 3 A refinement of the single-threaded vector execution unit in . Figure 4 As shown, the single-threaded vector execution unit 30 includes a tensor calculation unit 301 and a data handling unit 302 . The tensor calculation unit 301 includes a matrix calculation unit 3011 , a vector calculation unit 3012 , and a data sorting unit 3013 . Figure 4 In the multi-threaded vector execution unit, each single-threaded vector execution unit shares a register file 1021. In some embodiments, each single-threaded vector execution unit performs computational tasks for a single thread and includes a register file, a matrix calculation unit, a vector calculation unit, a data sorting unit, and a data handling unit. For example, each unit in the register file is a vector register containing 16 data elements for parallel computation. The register file is divided into multiple banks to support simultaneous access by multiple single-threaded vector execution units. The matrix calculation unit 3011 performs matrix multiplication, for example, by obtaining the raw data of two input matrices from the register file, performing the matrix multiplication, and then writing the result to the register file. The vector calculation unit 3012 performs basic vector operations such as addition, subtraction, multiplication, division, exponentiation, and square root, supporting the input and output of integer and floating-point data. The data sorting unit 3013 can exchange and reorder data within multiple threads, as well as exchange and reorder different data elements within a thread's vector registers. The data handling unit 302 handles data transfer between the register file and external memory.

[0101] Since the structures and functions of the single-threaded scalar execution units included in the multi-threaded scalar execution unit 101 are the same, the structure of the single-threaded scalar execution unit is introduced below by taking any single-threaded scalar execution unit as an example.

[0102] The structure of an example of a multi-threaded scalar execution unit is described below with reference to the accompanying drawings.

[0103] Figure 4 This is a schematic diagram of an example of a multi-threaded scalar execution unit provided in an embodiment of the present application. Figure 4As shown, the multi-threaded scalar execution unit 101 includes Q (for example, 16) single-threaded scalar execution units and a register stack 1011. The above Q is an integer greater than 1. In some embodiments, the structures and functions of the single-threaded scalar execution units included in the multi-threaded scalar execution unit 101 are the same, and the single-threaded scalar execution units included in the multi-threaded scalar execution unit 101 share the register stack 1011, and each single-threaded scalar execution unit can execute multiple threads corresponding to the same instruction in parallel. In an embodiment of the present application, the multi-threaded scalar execution unit 101 includes multiple single-threaded scalar execution units, and each single-threaded scalar execution unit can undertake the computing task of one thread. In some embodiments, each time the multi-threaded scalar execution unit 101 executes an instruction, multiple single-threaded scalar execution units simultaneously complete the process of fetching, calculating, and writing back the results, thereby realizing thread parallel computing. In some embodiments, the register stack is divided into multiple banks to support simultaneous access by multiple single-threaded vector execution units.

[0104] Since the structures and functions of the single-threaded scalar execution units included in the multi-threaded scalar execution unit 101 are the same, the structure of the single-threaded scalar execution unit is introduced below by taking any single-threaded scalar execution unit as an example.

[0105] Figure 5 This is a schematic diagram of an example of a single-threaded scalar execution unit provided in an embodiment of the present application. Figure 5 As shown, 50 represents any single-threaded scalar execution unit included in the multi-threaded scalar execution unit 101, 501 represents a scalar calculation unit, and 502 represents a data handling unit. The scalar calculation unit 501 can be a plurality of groups, such as an integer calculation unit, a floating-point calculation unit, etc. In other words, the scalar calculation unit 501 can be divided into an integer calculation unit and a floating-point calculation unit. The scalar calculation unit is used to perform operations with lower computing power requirements using integer data and / or floating-point data, such as addition and subtraction. Matrix multiplication can be understood as an operation with higher computing power requirements. The data handling unit 502 implements data transfer between the external memory and the register file 1011. Figure 5 In the embodiment, the register file 1011 is not exclusive to the single-threaded scalar execution unit 50, but is a register file shared by the single-threaded scalar execution unit 50 and other single-threaded scalar execution units, that is, a register file shared by each single-threaded scalar execution unit in the multi-threaded scalar execution unit.

[0106] Figure 6 A schematic diagram of the structure of another processor provided in an embodiment of the present application. Figure 6 The processor in Figure 1 A possible implementation of the processor in . Figure 6As shown, the processor includes: a multi-threaded scalar execution unit 101, a multi-threaded vector execution unit 102, an extension register 103, an instruction cache unit 104 and an instruction scheduling unit 105. Figure 6 In the embodiment, the multi-threaded vector execution unit 102 includes P (eg, 16) single-threaded vector execution units and a register file 1021. Each single-threaded vector execution unit includes a tensor calculation unit and a data handling unit (see Figure 3 ); The multi-threaded scalar execution unit 101 includes Q (eg, 16) single-threaded scalar execution units and a register file 1011, each of which includes a scalar calculation unit and a data handling unit (see Figure 5 ).

[0107] The instruction cache unit 104 is used to implement the retrieval, caching, and issuance of multi-threaded instructions. One instruction can correspond to multiple threads. For example, one instruction corresponds to 16 threads executing together. Multi-threaded instructions refer to instructions corresponding to multiple threads. When a processor executes a multi-threaded instruction, it executes the multiple threads corresponding to the instruction. The retrieval of multi-threaded instructions can be the instruction cache unit 104 reading the multi-threaded instructions from external memory (such as DDR). The issuance of multi-threaded instructions can be the instruction cache unit 104 sending the cached instructions to the instruction scheduling unit 105.

[0108] The instruction dispatch unit 105 is responsible for processing instructions such as branches, jumps, and loops in the program. It receives the execution status of the multi-threaded vector execution unit and / or the multi-threaded scalar execution unit, maintains register occupancy, performs dependency checks between instructions to ensure that the instruction execution order conforms to the programming expectations, arbitrates and selects multiple groups of instructions, and issues them to different execution units (corresponding to single-threaded scalar execution units and / or single-threaded vector execution units). It should be understood that the instruction dispatch unit 105 is responsible for scheduling instructions, that is, arbitrating and selecting multiple groups of instructions and issuing them to different execution units.

[0109] In some embodiments, instructions to be executed by the processor are initially placed in an external memory space, such as a DDR. The instruction cache unit 104 retrieves and caches the instructions from the external memory space. The instruction cache unit 104 then sends the cached instructions to the instruction dispatch unit 105. The instruction dispatch unit 105 arbitrates and selects the instructions sent by the instruction cache unit 104 and sends the instructions to the corresponding execution unit. The multi-threaded scalar execution unit 101 and the multi-threaded vector execution unit 102 cooperate to execute the instructions sent by the instruction dispatch unit 105. In some embodiments, the multi-threaded scalar execution unit 101 or the multi-threaded vector execution unit 102 can independently execute the instructions sent by the instruction dispatch unit 105.

[0110] In the embodiment of the present application, on the one hand, the multi-threaded vector execution unit and the multi-threaded scalar execution unit share the instruction cache unit and the instruction scheduling unit, which can achieve effective reuse on the control path; on the other hand, the scheduling supports the parallel execution of single instruction multiple threads, simplifies the thread control logic, and ensures that higher computing power is obtained without excessively increasing the complexity of the hardware design, that is, obtaining a higher energy efficiency ratio.

[0111] Figure 7 A schematic diagram of the structure of another processor provided in an embodiment of the present application. Figure 7 The processor in Figure 6 The refinement and improvement of the processor in Figure 7 As shown, the processor includes: a multi-threaded scalar execution unit 101, a multi-threaded vector execution unit 102, an extension register 103, an instruction cache unit 104 and an instruction scheduling unit 105. Figure 7 In the figure, the multi-threaded vector execution unit 102 includes P (for example, 16) single-threaded vector execution units and a register stack 1021, 701 represents a matrix calculation unit, 702 represents a vector calculation unit, 703 represents a data sorting unit, and 704 represents a data handling unit; the multi-threaded scalar execution unit 101 includes Q (for example, 16) single-threaded scalar execution units and a register stack 1011, 705 represents an integer calculation unit, 706 represents a floating-point calculation unit, and 707 represents a data handling unit. Figure 7 In the example, each single-threaded vector execution unit includes a matrix calculation unit, a vector calculation unit, a data sorting unit, and a data handling unit, and each single-threaded scalar execution unit includes an integer calculation unit, a floating-point calculation unit, and a data handling unit. Figure 7 In the figure, the matrix calculation unit, vector calculation unit, and data sorting unit included in each single-threaded vector execution unit can be understood as the tensor calculation unit included in the single-threaded vector execution unit; the integer calculation unit and floating-point calculation unit included in each single-threaded scalar execution unit can be understood as the scalar calculation unit included in the single-threaded scalar execution unit.

[0112] It should be understood that the division of the various units of the above processor is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. For example, the above units can be separately established processing elements, or they can be integrated into the same chip for implementation. In addition, they can also be stored in the storage element of the controller in the form of program code, and called and executed by a certain processing element of the processor. The functions of the above units can also be integrated together or implemented independently. The processing element here can be an integrated circuit chip with signal processing capabilities. In the implementation process, the above units can be completed by the integrated logic circuit of the hardware in the processor element or the instructions in the form of software.

[0113] The processor provided by the embodiment of the present application is introduced above. The multi-threaded processing method provided by the embodiment of the present application is introduced below.

[0114] Figure 8 A flowchart of a multi-thread processing method provided in an embodiment of the present application is provided. The method is applied to a processor, wherein the processor includes a multi-thread scalar execution unit, a multi-thread vector execution unit, and an extension register, wherein the multi-thread vector execution unit includes at least two single-thread vector execution units; the method includes:

[0115] 801. The multi-threaded scalar execution unit writes first control information into an extension register.

[0116] 802. The multi-threaded vector execution unit reads the first control information from the extension register and executes a data processing task based on the first control information.

[0117] The processor applicable to the multi-thread processing method provided in the embodiment of the present application can be any processor in the aforementioned embodiment, such as Figure 6 or Figure 7 The processor in.

[0118] In one possible implementation, the at least two single-threaded scalar execution units are used to execute different threads in parallel based on the same instruction, and the at least two single-threaded vector execution units are used to execute the same operation on different data sets in parallel based on the same instruction.

[0119] In one possible implementation, before executing step 801, the multi-threaded scalar execution unit may perform an operation on the first data to obtain a first operation result, and generate the first control information based on the first operation result. A possible implementation of step 802 is as follows: the multi-threaded vector execution unit performs an operation on the first operation result based on the first control information to obtain a second operation result.

[0120] In one possible implementation, the first control information includes data indication information of multiple data elements included in the vector data to be processed by the multi-threaded vector execution unit. A possible implementation of step 802 is as follows: the multi-threaded vector execution unit reads the first control information from the extended register, and based on the data indication information, determines at least one target data element to be processed included in the multiple data elements, and performs operations on the at least one target data element (corresponding to executing a data processing task).

[0121] In one possible implementation, the first control information includes enable indication information of the M threads corresponding to the first instruction. A possible implementation of step 802 is as follows: the multi-threaded vector execution unit reads the first control information from the extended register, determines at least one target thread among the M threads based on the enable indication information, and uses at least one single-threaded vector execution unit corresponding to the at least one target thread to execute the data processing task.

[0122] In one possible implementation, the first control information further includes address information of data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit further includes a data transfer unit and at least one register file, wherein the register file includes at least one vector register; and the method further includes:

[0123] The data transport unit acquires the data to be processed from the external memory based on the address information included in the first control information, and stores the acquired data to be processed in the at least one register file.

[0124] In a possible implementation, the extension register is provided inside the processor independently of the multi-threaded scalar execution unit and the multi-threaded vector execution unit.

[0125] In one possible implementation, the first control information indicates a masked data element in the second data; and the data processing based on the first control information includes:

[0126] F single-threaded vector execution units in the multi-threaded vector execution unit execute a second operation in parallel using F data elements; F is an integer greater than 1, the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than F, the F data elements are unmasked data elements in the second data, and any single-threaded vector execution unit in the F single-threaded vector execution units executes the second operation using one data element of the F data elements.

[0127] In one possible implementation, the first control information indicates N threads that are masked and / or L threads that are not masked among the M threads corresponding to the first instruction, where N is an integer greater than 0 and less than M, and L is an integer greater than 1 and less than M. The data processing based on the first control information includes:

[0128] Multiple single-threaded vector execution units in the multi-threaded vector execution unit execute computing tasks of unmasked threads in the M threads in parallel; or L single-threaded vector execution units in the multi-threaded vector execution unit execute computing tasks of the L unmasked threads in parallel.

[0129] In one possible implementation, the multi-threaded vector execution unit further includes a data handling unit; and the data processing based on the first control information includes:

[0130] The data handling unit obtains H data elements from the external memory based on the address information included in the first control information, where H is an integer greater than 1;

[0131] H single-threaded vector execution units in the multi-threaded vector execution unit perform a third operation in parallel using the H data elements; the number of single-threaded vector execution units in the multi-threaded vector execution unit is greater than H, and any single-threaded vector execution unit in the H single-threaded vector execution units performs the third operation using one data element of the H data elements.

[0132] In one possible implementation, the first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; and the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

[0133] In one possible implementation, the tensor calculation unit includes a matrix calculation unit and / or a vector calculation unit and a data sorting unit; the matrix calculation unit is used to perform matrix multiplication operations, the vector calculation unit is used to perform vector operations, and the data sorting unit is used to exchange and rearrange the data stored in the register stack in the processor to obtain multiple data elements to be processed in parallel by the matrix calculation unit and / or the vector calculation unit.

[0134] It can be understood that the multi-threaded processing method provided in the embodiment of the present application can be applied to any computing task that executes multi-threaded instructions, such as image processing tasks, text recognition tasks, etc. By adopting a processor that integrates SIMT and SIMD, the efficiency of executing multi-threaded instructions can be improved.

[0135] The processor provided in this application can be applied to a variety of electronic devices, such as servers and terminal devices. The following describes an example of a server configured with the processor provided in this application and an example of a terminal device configured with the processor provided in this application.

[0136] Figure 9: This is a structural diagram of a server provided in an embodiment of the present application. The server 900 may have relatively large differences due to different configurations or performances, and may include one or more processors 922 and memories 932 provided in the aforementioned embodiments, and one or more storage media 930 (such as one or more massive storage devices) for storing application programs 942 or data 944. Among them, the memory 932 and the storage medium 930 may be short-term storage or persistent storage. The program stored in the storage medium 930 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the server. Furthermore, the processor 922 may be configured to communicate with the storage medium 930 to execute a series of instruction operations in the storage medium 930 on the server 900. The server 900 may be a multi-threaded instruction execution method provided in the present application.

[0137] The server 900 may also include one or more power supplies 926, one or more wired or wireless network interfaces 950, one or more input and output interfaces 958, and / or one or more operating systems 941, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0138] It should be understood that Figure 9 This is only an example of a server configured with the processor provided in this application.

[0139] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 10 As shown, the electronic device 100 includes a processor 1001, a memory 1002, and a communication interface 1003. The processor 1001, the memory 1002, and the communication interface 1003 are interconnected via a bus. The processor 1001 may be the processor provided in the embodiment of the present application.

[0140] The memory 1002 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CDROM), and is used for related instructions and data. The communication interface 1003 is used to receive and send data.

[0141] In an embodiment of the present application, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the multi-threaded instruction execution method provided in the above embodiment is implemented.

[0142] An embodiment of the present application provides a computer program product containing instructions, which, when executed on a computer, enables the computer to execute the multi-threaded instruction execution method provided by the aforementioned embodiment.

[0143] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A processor, characterized in that: include: Multi-threaded scalar execution unit, multi-threaded vector execution unit, and extended registers; The multi-threaded scalar execution unit includes at least two single-threaded scalar execution units, and the multi-threaded vector execution unit includes at least two single-threaded vector execution units; The multi-threaded scalar execution unit is coupled to the extended register, and the multi-threaded vector execution unit is coupled to the extended register; The multi-threaded scalar execution unit is configured to write the first control information into the extended register; The multi-threaded vector execution unit is configured to read the first control information from the extended register and execute a data processing task based on the first control information; The at least two single-threaded scalar execution units are used to execute different threads in parallel based on the same instruction, and the at least two single-threaded vector execution units are used to execute the same operation on different data sets in parallel based on the same instruction.

2. The processor according to claim 1, wherein: The multi-threaded scalar execution unit is further configured to perform an operation on the first data to obtain a first operation result, and generate the first control information based on the first operation result; The multi-threaded vector execution unit is configured to perform an operation on the first operation result based on the first control information to obtain a second operation result.

3. The processor according to claim 1, wherein: The first control information includes data indication information of a plurality of data elements contained in the vector data to be processed by the multi-threaded vector execution unit; The multi-threaded vector execution unit is configured to determine, based on the data indication information, at least one target data element to be processed included in the plurality of data elements, and perform an operation on the at least one target data element.

4. The processor according to claim 1, wherein: The first control information includes enable indication information of M threads corresponding to the first instruction; The multi-threaded vector execution unit is configured to determine at least one target thread among the M threads based on the enable indication information, and execute the data processing task using at least one single-threaded vector execution unit corresponding to the at least one target thread.

5. The processor according to any one of claims 1 to 4, characterized in that The first control information further includes address information of data to be processed by the multi-threaded vector execution unit; The multi-threaded vector execution unit further includes a data handling unit and at least one register file, wherein the register file includes at least one vector register; The data transport unit is configured to obtain the data to be processed from the external memory based on the address information included in the first control information, and store the obtained data to be processed in the at least one register file.

6. The processor according to any one of claims 1 to 4, characterized in that: The first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

7. The processor according to any one of claims 1 to 4, characterized in that The extension register is set inside the processor independently of the multi-thread scalar execution unit and the multi-thread vector execution unit.

8. A multi-thread processing method, applied to a processor, characterized in that: The processor includes a multi-threaded scalar execution unit, a multi-threaded vector execution unit, and an extended register, wherein the multi-threaded vector execution unit includes at least two single-threaded vector execution units; the method includes: The multi-threaded scalar execution unit writes the first control information into the extension register; The multi-threaded vector execution unit reads the first control information from the extended register and performs a data processing task based on the first control information; The at least two single-threaded scalar execution units are used to execute different threads in parallel based on the same instruction, and the at least two single-threaded vector execution units are used to execute the same operation on different data sets in parallel based on the same instruction.

9. The method according to claim 8, characterized in that Before the multi-threaded scalar execution unit writes the first control information into the extension register, the method further includes: The multi-threaded scalar execution unit performs an operation on the first data to obtain a first operation result, and generates the first control information based on the first operation result; The multi-threaded vector execution unit executing the data processing task based on the first control information includes: The multi-threaded vector execution unit performs an operation on the first operation result based on the first control information to obtain a second operation result.

10. The method according to claim 8, characterized in that The first control information includes data indication information of a plurality of data elements contained in the vector data to be processed by the multi-threaded vector execution unit; The multi-threaded vector execution unit executing the data processing task based on the first control information includes: The multi-threaded vector execution unit determines at least one target data element to be processed included in the plurality of data elements based on the data indication information, and performs an operation on the at least one target data element.

11. The method according to claim 8, characterized in that The first control information includes enable indication information of M threads corresponding to the first instruction; The multi-threaded vector execution unit executing the data processing task based on the first control information includes: The multi-threaded vector execution unit determines at least one target thread among the M threads based on the enable indication information, and uses at least one single-threaded vector execution unit corresponding to the at least one target thread to execute the data processing task.

12. The method according to any one of claims 8 to 11, characterized in that The first control information further includes address information of data to be processed by the multi-threaded vector execution unit; the multi-threaded vector execution unit further includes a data handling unit and at least one register file, wherein the register file includes at least one vector register; the method further includes: The data transport unit acquires data to be processed from an external memory based on address information included in the first control information, and stores the acquired data to be processed in the at least one register file.

13. The method according to any one of claims 8 to 11, characterized in that The first single-threaded vector execution unit among the at least two single-threaded vector execution units includes a tensor computing unit; the first single-threaded scalar execution unit among the at least two single-threaded scalar execution units includes a scalar computing unit; the computing power of the tensor computing unit is higher than the computing power of the scalar computing unit.

14. The method according to any one of claims 8 to 11, characterized in that The extension register is set inside the processor independently of the multi-thread scalar execution unit and the multi-thread vector execution unit.

15. An electronic device, characterized in that: The processor comprises the processor according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that The computer storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor is caused to perform the method according to any one of claims 8 to 14.

Images