Shift register, gate driving circuit and display device

Abstract

This disclosure provides a shift register, including: a precharge reset circuit connected to a precharge signal input terminal, a reset signal input terminal, and a pull-up node, configured to write a valid level signal to the pull-up node in response to a valid level signal provided by the precharge signal input terminal, and to write an invalid level signal to the pull-up node in response to a valid level signal provided by the reset signal input terminal; a drive output circuit connected to a clock signal input terminal, the pull-up node, and a drive signal output terminal, configured to write a clock signal provided by the clock signal input terminal to the drive signal output terminal in response to a valid level signal at the pull-up node; and an output noise reduction circuit connected to a noise reduction signal input terminal, a noise reduction control signal input terminal, and the drive signal output terminal, configured to write an invalid level signal provided by the noise reduction signal input terminal to the drive signal output terminal in response to a valid level signal provided by the noise reduction control signal input terminal, so as to perform noise reduction on the drive signal output terminal.

Description

Technical Field

[0001] This invention relates to the field of display, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] Gate Driver On Array (GOA) is a high-tech design structure that has been widely used in display products. The biggest advantage of GOA circuits is that they eliminate the need for a gate driver IC, reducing costs and minimizing product bezels.

[0003] In practical applications, it has been found that during the period from the moment the display device is powered on until the display device displays the first frame of the image, the display device will exhibit a problem of "flickering horizontal bright lines". Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a shift register, a gate driving circuit and a display device.

[0005] In a first aspect, embodiments of this disclosure provide a shift register, including:

[0006] A precharge reset circuit, connected to a precharge signal input terminal, a reset signal input terminal, and a pull-up node, is configured to write a valid level signal to the pull-up node in response to a valid level signal provided by the precharge signal input terminal, and to write an invalid level signal to the pull-up node in response to a valid level signal provided by the reset signal input terminal.

[0007] A drive output circuit is connected to the clock signal input terminal, the pull-up node, and the drive signal output terminal, and is configured to write the clock signal provided by the clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node.

[0008] An output noise reduction circuit is connected to a noise reduction signal input terminal, a noise reduction control signal input terminal, and a drive signal output terminal. It is configured to write an ineffective level signal provided by the noise reduction signal input terminal to the drive signal output terminal in response to the control of an effective level signal provided by the noise reduction control signal input terminal, so as to reduce noise at the drive signal output terminal.

[0009] In some embodiments, the noise reduction signal input terminal is a ground terminal or a power supply terminal that provides an inactive level signal.

[0010] In some embodiments, the output noise reduction circuit includes: an output noise reduction transistor;

[0011] The control electrode of the output noise reduction transistor is connected to the noise reduction control signal input terminal, the first electrode of the output noise reduction transistor is connected to the noise reduction signal input terminal, and the second electrode of the output noise reduction transistor is connected to the drive signal output terminal.

[0012] In some embodiments, the shift register further includes:

[0013] A cascaded output circuit, connected to the clock signal input terminal, the pull-up node, and the cascaded signal output terminal, is configured to write the clock signal provided by the clock signal input terminal to the cascaded signal output terminal in response to the control of the effective level signal at the pull-up node.

[0014] In some embodiments, the shift register further includes:

[0015] A first pull-down control circuit, connected to the pull-up node and the first pull-down node, is configured to write an invalid level signal to the first pull-down node in response to a valid level signal at the pull-up node, and to write a valid level signal to the first pull-down node in response to a invalid level signal at the pull-up node.

[0016] The second pull-down control circuit is connected to the pull-up node and the second pull-down node, and is configured to write an invalid level signal to the second pull-down node in response to the control of an invalid level signal at the pull-up node, and to write an valid level signal to the second pull-down node in response to the control of an invalid level signal at the pull-up node.

[0017] A pull-up control circuit, connected to the pull-up node, the first pull-down node, and the second pull-down node, is configured to write an invalid level signal to the pull-up node in response to a valid level signal at the first pull-down node, and to write an invalid level signal to the pull-up node in response to a valid level signal at the second pull-down node.

[0018] A global reset circuit, connected to a global reset control signal input terminal and a pull-up node, is configured to write an invalid level signal to the pull-up node in response to a valid level signal provided by the global reset control signal input terminal.

[0019] The drive output circuit is also connected to the first pull-down node and the second pull-down node. The drive output circuit is also configured to write an invalid level signal to the drive signal output terminal in response to the control of the valid level signal at the first pull-down node, and to write an invalid level signal to the drive signal output terminal in response to the control of the valid level signal at the second pull-down node.

[0020] The cascaded output circuit is also connected to the first pull-down node and the second pull-down node. The cascaded output circuit is further configured to write an invalid level signal to the cascaded signal output terminal in response to the control of the valid level signal at the first pull-down node, and to write an invalid level signal to the cascaded signal output terminal in response to the control of the valid level signal at the second pull-down node.

[0021] In some embodiments, the precharge reset circuit includes a first transistor and a second transistor, the first pull-down control circuit includes a third transistor and a fourth transistor, the second pull-down control circuit includes a fifth transistor and a sixth transistor, the pull-up control circuit includes a seventh transistor and an eighth transistor, the drive output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor, the cascaded output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor, and the global reset circuit includes a fifteenth transistor.

[0022] The control electrode of the first transistor is connected to the precharge signal input terminal, the first electrode of the first transistor is connected to the precharge signal input terminal, and the second electrode of the first transistor is connected to the pull-up node.

[0023] The control electrode of the second transistor is connected to the reset signal input terminal, the first electrode of the second transistor is connected to the pull-up node, and the first electrode of the second transistor is connected to the first power supply terminal.

[0024] The control electrode of the third transistor is connected to the second power supply terminal, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode of the first transistor is connected to the first pull-down node.

[0025] The control electrode of the fourth transistor is connected to the pull-up node, the first electrode of the fourth transistor is connected to the first pull-down node, and the second electrode of the fourth transistor is connected to the first power supply terminal.

[0026] The control electrode of the fifth transistor is connected to the third power supply terminal, the first electrode of the fifth transistor is connected to the third power supply terminal, and the second electrode of the fifth transistor is connected to the second pull-down node.

[0027] The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second pull-down node, and the second electrode of the sixth transistor is connected to the first power supply terminal.

[0028] The control electrode of the seventh transistor is connected to the first pull-down node, the first electrode of the seventh transistor is connected to the pull-up node, and the second electrode of the seventh transistor is connected to the first power supply terminal.

[0029] The control electrode of the eighth transistor is connected to the second pull-down node, the first electrode of the eighth transistor is connected to the pull-up node, and the second electrode of the eighth transistor is connected to the first power supply terminal.

[0030] The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the clock signal input terminal, and the second electrode of the ninth transistor is connected to the drive signal output terminal.

[0031] The control electrode of the tenth transistor is connected to the first pull-down node, the first electrode of the tenth transistor is connected to the drive signal output terminal, and the second electrode of the tenth transistor is connected to the fourth power supply terminal.

[0032] The control electrode of the eleventh transistor is connected to the second pull-down node, the first electrode of the eleventh transistor is connected to the drive signal output terminal, and the second electrode of the eleventh transistor is connected to the fourth power supply terminal.

[0033] The control electrode of the twelfth transistor is connected to the pull-up node, the first electrode of the twelfth transistor is connected to the clock signal input terminal, and the second electrode of the twelfth transistor is connected to the cascaded signal output terminal.

[0034] The control electrode of the thirteenth transistor is connected to the first pull-down node, the first electrode of the thirteenth transistor is connected to the cascaded signal output terminal, and the second electrode of the thirteenth transistor is connected to the second power supply terminal.

[0035] The control electrode of the fourteenth transistor is connected to the second pull-down node, the first electrode of the fourteenth transistor is connected to the cascaded signal output terminal, and the second electrode of the fourteenth transistor is connected to the second power supply terminal.

[0036] The control electrode of the fifteenth transistor is connected to the global reset control signal input terminal, the first electrode of the fifteenth transistor is connected to the pull-up node, and the second electrode of the fifteenth transistor is connected to the first power supply terminal.

[0037] The first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the drive signal output terminal.

[0038] In a second aspect, this disclosure also provides a gate driving circuit, comprising: a cascaded multi-stage shift register, wherein the shift register employs the shift register described in the first aspect.

[0039] Thirdly, this disclosure also provides a display device, comprising:

[0040] The gate drive circuit adopts the gate drive circuit described in the second aspect.

[0041] A noise reduction control module is connected to the noise reduction control signal input terminal of each of the shift registers in the gate drive circuit. The noise reduction control module is configured to provide an effective level signal to the noise reduction control signal input terminal of any shift register during at least a portion of the time period between the power-on time of the display device and the start time when the drive signal output terminal of the shift register is first output in an effective level state.

[0042] In some embodiments, the noise reduction control module is specifically configured to: continuously provide valid level signals to the noise reduction control signal input terminals of each stage of the shift register from the power-on time of the display device to the start time when the drive signal output terminal of the shift register located in the first stage of the gate drive circuit first outputs a clock signal in a valid level state; and continuously provide invalid level signals to the noise reduction control signal input terminals of each stage of the shift register from the start time when the drive signal output terminal of the shift register located in the first stage first outputs a clock signal in a valid level state.

[0043] In some embodiments, the gate drive circuit includes N stages of the shift register;

[0044] The noise reduction control module is specifically configured as follows: for the i-th stage shift register, from the power-on time of the display device to the start time when the drive signal output terminal of the i-th stage shift register first outputs a clock signal in an effective level state, continuously providing an effective level signal to the noise reduction control signal input terminal of the i-th stage shift register; and from the start time when the drive signal output terminal of the i-th stage shift register first outputs a clock signal in an effective level state, continuously providing an ineffective level signal to the noise reduction control signal input terminal of the i-th stage shift register.

[0045] Where i is an integer and 1≤i≤N. Attached Figure Description

[0046] Figure 1 A schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0047] Figure 2 This is a comparative schematic diagram showing the signals loaded at the drive signal output terminal of the shift register involved in this disclosure and the shift register involved in related technologies during the power-on phase;

[0048] Figure 3 A schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0049] Figure 4 A schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0050] Figure 5 for Figure 4 The diagram shows a timing diagram of one type of shift register.

[0051] Figure 6 A schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of this disclosure;

[0052] Figure 7 A schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0053] Figure 8 This is a schematic diagram showing the connection between the gate drive circuit and the noise reduction control module in an embodiment of this disclosure;

[0054] Figure 9 This is a timing diagram of the gate drive circuit in an embodiment of the present disclosure;

[0055] Figure 10 This is a schematic diagram illustrating another connection between the gate drive circuit and the noise reduction control module in an embodiment of this disclosure;

[0056] Figure 11 This is another timing diagram of the gate drive circuit in an embodiment of this disclosure. Detailed Implementation

[0057] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register, gate driving circuit and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0058] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect (e.g., other electronic components may exist between two coupled elements).

[0059] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example.

[0060] In this disclosure, "effective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0061] In the following description, an N-type transistor will be used as an example. In this case, the active level signal refers to a high-level signal, and the inactive level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0062] The display devices involved in the related technology exhibit a "flickering horizontal bright line" phenomenon during the period from power-on to the presentation of the first frame. Research has revealed that this phenomenon is caused by an abnormal voltage surge (accidental charging) at the output of the drive signal of a portion of the shift register within the gate drive circuit during power-on. This causes the drive signal output of some shift registers to mistakenly provide a valid drive signal to the corresponding row gate line, resulting in some row pixel units in the display device being mistakenly activated, thus displaying horizontal bright lines.

[0063] In view of the aforementioned technical problems in the related technologies, this disclosure provides corresponding solutions. Figure 1 This is a schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the shift register includes: a precharge reset circuit 1, a drive output circuit 4, and an output noise reduction circuit 7.

[0064] The precharge reset circuit 1 is connected to the precharge signal input terminal INPUT, the reset signal input terminal RESET, and the pull-up node PU. The precharge reset circuit 1 is configured to write a valid level signal to the pull-up node PU in response to the control of the valid level signal provided by the precharge signal input terminal INPUT, and to write an invalid level signal to the pull-up node PU in response to the control of the valid level signal provided by the reset signal input terminal RESET.

[0065] The drive output circuit 4 is connected to the clock signal input terminal CLK, the pull-up node PU, and the drive signal output terminal OUT. The drive output circuit 4 is configured to write the clock signal provided by the clock signal input terminal CLK to the drive signal output terminal OUT in response to the control of the effective level signal at the pull-up node PU.

[0066] The output noise reduction circuit 7 is connected to the noise reduction signal input terminal GND, the noise reduction control signal input terminal NR, and the drive signal output terminal OUT. The output noise reduction circuit 7 is configured to write the ineffective level signal provided by the noise reduction signal input terminal GND to the drive signal output terminal OUT in response to the control of the effective level signal provided by the noise reduction control signal input terminal NR, so as to reduce the noise of the drive signal output terminal OUT.

[0067] The shift register provided in this embodiment is equipped with an output noise reduction circuit 7. By writing an effective level signal to the noise reduction control signal input terminal NR of the shift register during the period from the power-on time of the display device to the display device displaying the first frame, the output noise reduction circuit 7 is made to work and reduce the noise of the drive signal output terminal OUT, thereby making the voltage at the drive signal output terminal OUT in an ineffective level state, thereby effectively preventing the pixel unit line corresponding to the drive signal output terminal OUT in the display device from being mistakenly turned on.

[0068] Figure 2 This is a comparative diagram showing the signal loaded at the drive signal output terminal OUT of the shift register involved in this disclosure and the shift register involved in related technologies during the power-on phase, as shown in the diagram. Figure 2As shown, the printed circuit board (PCB) is powered on immediately after the display device is powered on. In related technologies, because the drive signal output terminal OUT of the shift register is in a floating state, the voltage at the drive signal output terminal OUT of the shift register is abnormally pulled up and is in an effective level state due to factors such as the power-on of the PCB and electromagnetic interference from other electrical components. However, in the shift register provided in this disclosure, due to the presence of the output noise reduction circuit 7, an effective level signal can be written to the noise reduction control signal input terminal NR during the above-mentioned power-on process, so that the output noise reduction circuit 7 can work and reduce noise at the drive signal output terminal OUT, thereby ensuring that the voltage at the drive signal output terminal OUT is always in an ineffective level state.

[0069] In some embodiments, the noise reduction signal input terminal is a ground terminal (no corresponding figure is shown). With this design, there is no need to configure a dedicated noise reduction power supply terminal for the output noise reduction circuit 7, which can effectively reduce costs.

[0070] In some embodiments, or as a power supply terminal providing an inactive level signal VGL, noise reduction is performed using the inactive level signal provided by the power supply terminal, resulting in better noise reduction performance.

[0071] In some embodiments, the output noise reduction circuit 7 includes an output noise reduction transistor Mr. The control terminal of the output noise reduction transistor Mr is connected to the noise reduction control signal input terminal NR, the first terminal of the output noise reduction transistor Mr is connected to the noise reduction signal input terminal GND, and the second terminal of the output noise reduction transistor Mr is connected to the drive signal output terminal OUT. Taking an N-type transistor as an example, by providing a high-level signal to the noise reduction control signal input terminal NR, the noise reduction signal input terminal GND and the drive signal output terminal OUT can be turned on. The inactive level signal provided by the noise reduction signal input terminal GND is written to the drive signal output terminal OUT, and the voltage at the drive signal output terminal OUT is in an inactive level state. When the output noise reduction circuit 7 is not required to perform noise reduction processing on the drive signal output terminal OUT, a low-level signal can be provided to the noise reduction control signal input terminal NR.

[0072] Figure 3 This is a schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure, such as... Figure 3 As shown, in some embodiments, the shift register further includes a cascaded output circuit; wherein the cascaded output circuit 6 is connected to the clock signal input terminal CLK, the pull-up node PU, and the cascaded signal output terminal CR, and the cascaded output circuit 6 is configured to write the clock signal provided by the clock signal input terminal CLK to the cascaded signal output terminal CR in response to the control of the effective level signal at the pull-up node PU.

[0073] In a GOA circuit, the shift register not only outputs drive signals but also cascade signals. In related technologies, often only one drive signal output circuit is configured, and the drive signal output terminal OUT of this circuit is used to output both the drive signal and the cascade signal. That is, the drive signal output terminal OUT of this shift register is connected not only to the corresponding row gate line in the display device but also to the shift register of the adjacent stage in the gate drive circuit. In this case, due to the large load connected to the drive signal output terminal OUT, signal distortion is likely to occur. To effectively solve this technical problem, in this embodiment, an independent cascade output circuit is provided within the shift register, and an independent cascade signal output terminal CR is configured. In this case, the drive signal output terminal OUT can be used to output the drive signal, and the cascade signal output terminal CR can be used to output the cascade signal, thus effectively reducing the load connected to the drive signal output terminal OUT and ensuring stable signal output.

[0074] It should be noted that when the shift register includes a cascaded output circuit, a corresponding output noise reduction circuit 7 can also be configured for the cascaded signal output terminal CR (no corresponding diagram is given in this case).

[0075] Figure 4 This is a schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure. Figure 5 for Figure 4 The following is a timing diagram of a shift register, such as... Figure 4 and Figure 5 As shown, in some embodiments, the shift register further includes: a first pull-down control circuit 2, a second pull-down control circuit 3, a pull-up control circuit 5, and a global reset circuit 8.

[0076] The first pull-down control circuit 2 is connected to the pull-up node PU and the first pull-down node PD1. The first pull-down control circuit 2 is configured to write an invalid level signal to the first pull-down node PD1 in response to the control of the valid level signal at the pull-up node PU, and to write an valid level signal to the first pull-down node PD1 in response to the control of the invalid level signal at the pull-up node PU.

[0077] The second pull-down control circuit 3 is connected to the pull-up node PU and the second pull-down node PD2. The second pull-down control circuit 3 is configured to write an invalid level signal to the second pull-down node PD2 in response to the control of the valid level signal at the pull-up node PU, and to write an valid level signal to the second pull-down node PD2 in response to the control of the invalid level signal at the pull-up node PU.

[0078] The pull-up control circuit 5 is connected to the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2. The pull-up control circuit 5 is configured to write an invalid level signal to the pull-up node PU in response to the control of the valid level signal at the first pull-down node PD1, and to write an invalid level signal to the pull-up node PU in response to the control of the valid level signal at the second pull-down node PD2.

[0079] The global reset circuit 8 is connected to the global reset control signal input terminal T-RE and the pull-up node PU. The global reset circuit 8 is configured to write an invalid level signal to the pull-up node PU in response to the control of the valid level signal provided by the global reset control signal input terminal.

[0080] The drive output circuit 4 is also connected to the first pull-down node PD1 and the second pull-down node PD2. The drive output circuit 4 is also configured to write an invalid level signal to the drive signal output terminal OUT in response to the control of the valid level signal at the first pull-down node PD1, and to write an invalid level signal to the drive signal output terminal OUT in response to the control of the valid level signal at the second pull-down node PD2.

[0081] The cascaded output circuit 6 is also connected to the first pull-down node PD1 and the second pull-down node PD2. The cascaded output circuit 6 is also configured to write an invalid level signal to the cascaded signal output terminal CR in response to the control of the valid level signal at the first pull-down node PD1, and to write an invalid level signal to the cascaded signal output terminal CR in response to the control of the valid level signal at the second pull-down node PD2.

[0082] In some embodiments, the precharge reset circuit 1 includes a first transistor M1 and a second transistor M2, the first pull-down control circuit 2 includes a third transistor M3 and a fourth transistor M4, the second pull-down control circuit 3 includes a fifth transistor M5 and a sixth transistor M6, the pull-up control circuit 5 includes a seventh transistor M7 and an eighth transistor M8, the drive output circuit 4 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a first capacitor C1, the cascaded output circuit 6 includes a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14, and the global reset circuit 8 includes a fifteenth transistor M15.

[0083] The control electrode of the first transistor M1 is connected to the precharge signal input terminal INPUT, the first electrode of the first transistor M1 is connected to the precharge signal input terminal INPUT, and the second electrode of the first transistor M1 is connected to the pull-up node PU.

[0084] The control electrode of the second transistor M2 is connected to the reset signal input terminal RESET, the first electrode of the second transistor M2 is connected to the pull-up node PU, and the first electrode of the second transistor M2 is connected to the first power supply terminal.

[0085] The control electrode of the third transistor M3 is connected to the second power supply terminal, the first electrode of the third transistor M3 is connected to the second power supply terminal, and the second electrode of the first transistor M1 is connected to the first pull-down node PD1.

[0086] The control electrode of the fourth transistor M4 is connected to the pull-up node PU, the first electrode of the fourth transistor M4 is connected to the first pull-down node PD1, and the second electrode of the fourth transistor M4 is connected to the first power supply terminal.

[0087] The control electrode of the fifth transistor M5 is connected to the third power supply terminal, the first electrode of the fifth transistor M5 is connected to the third power supply terminal, and the second electrode of the fifth transistor M5 is connected to the second pull-down node PD2.

[0088] The control terminal of the sixth transistor M6 is connected to the pull-up node PU, the first terminal of the sixth transistor M6 is connected to the second pull-down node PD2, and the second terminal of the sixth transistor M6 is connected to the first power supply terminal.

[0089] The control electrode of the seventh transistor M7 is connected to the first pull-down node PD1, the first electrode of the seventh transistor M7 is connected to the pull-up node PU, and the second electrode of the seventh transistor M7 is connected to the first power supply terminal.

[0090] The control electrode of the eighth transistor M8 is connected to the second pull-down node PD2, the first electrode of the eighth transistor M8 is connected to the pull-up node PU, and the second electrode of the eighth transistor M8 is connected to the first power supply terminal.

[0091] The control electrode of the ninth transistor M9 is connected to the pull-up node PU, the first electrode of the ninth transistor M9 is connected to the clock signal input terminal CLK, and the second electrode of the ninth transistor M9 is connected to the drive signal output terminal OUT.

[0092] The control electrode of the tenth transistor M10 is connected to the first pull-down node PD1, the first electrode of the tenth transistor M10 is connected to the drive signal output terminal OUT, and the second electrode of the tenth transistor M10 is connected to the fourth power supply terminal.

[0093] The control electrode of the eleventh transistor M11 is connected to the second pull-down node PD2, the first electrode of the eleventh transistor M11 is connected to the drive signal output terminal OUT, and the second electrode of the eleventh transistor M11 is connected to the fourth power supply terminal.

[0094] The control electrode of the twelfth transistor M12 is connected to the pull-up node PU, the first electrode of the twelfth transistor M12 is connected to the clock signal input terminal CLK, and the second electrode of the twelfth transistor M12 is connected to the cascaded signal output terminal CR.

[0095] The control electrode of the thirteenth transistor M13 is connected to the first pull-down node PD1, the first electrode of the thirteenth transistor M13 is connected to the cascaded signal output terminal CR, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

[0096] The control electrode of the fourteenth transistor M14 is connected to the second pull-down node PD2, the first electrode of the fourteenth transistor M14 is connected to the cascaded signal output terminal CR, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

[0097] The control electrode of the fifteenth transistor M15 is connected to the global reset control signal input terminal T-RE, the first electrode of the fifteenth transistor M15 is connected to the pull-up node PU, and the second electrode of the fifteenth transistor M15 is connected to the first power supply terminal.

[0098] The first terminal of the first capacitor C1 is connected to the pull-up node PU, and the second terminal of the first capacitor C1 is connected to the drive signal output terminal OUT.

[0099] In this embodiment, the operation of the shift register can be divided into a power-on phase and a normal display phase. During the power-on phase, the precharge signal input terminal INPUT, the reset signal terminal, and the clock signal input terminal CLK are all not providing signals (they are in a floating state). The noise reduction control signal input terminal NR provides a high-level signal, the output noise reduction transistor Mr is turned on, and the drive signal output terminal OUT is grounded to perform noise reduction on the drive signal output terminal OUT.

[0100] Figure 5 Examples are given in the middle. Figure 4 The diagram illustrates a timing sequence during normal display when all transistors in the shift register are N-type transistors. During normal display, the noise reduction control signal input NR is always low, and the output noise reduction transistor Mr is always off. A first power supply provides a first operating voltage V1, a second power supply provides a second operating voltage V2, a third power supply provides a third operating voltage V3, and a fourth power supply provides a fourth operating voltage V4. The first and fourth operating voltages V1 and V4 are inactive. The second and third operating voltages V2 and V3 are variable voltages, with one being low and the other high at any given time. During normal display, the second and third operating voltages V2 and V3 can change periodically (the specific period can be set according to actual needs). The shift register operates periodically, with each period consisting of six sub-stages from t1 to t6. The specific operating states of each transistor and important node (pull-up node PU, first pull-down node PD1, second pull-down node PD2) in each sub-stage of the shift register can be found by referring to... Figure 5 The details are not described in detail here.

[0101] During use, a global reset can be performed as needed. When a global reset is performed, a high-level signal is provided at the global reset control signal input terminal, the fifteenth transistor M15 is turned on, and the first operating voltage V1 is written to the pull-up node PU through the fifteenth transistor M15.

[0102] It should be noted that the shift register includes a first pull-down control circuit 2, a second pull-down control circuit 3, a pull-up control circuit 5, and a global reset circuit 8, as well as... Figure 4 The specific circuit structures of each functional circuit shown are for illustrative purposes only and do not limit the technical solutions of this disclosure.

[0103] Based on the same inventive concept, this disclosure also provides a gate driving circuit. Figure 6 This is a schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of the present disclosure, such as... Figure 6 As shown, the gate drive circuit includes cascaded multi-stage shift registers SR_1, SR_2, SR_3, and SR_4, wherein the shift registers SR_1, SR_2, SR_3, and SR_4 are shift registers provided in any of the previous embodiments. For a detailed description of these shift registers, please refer to the content in the previous embodiments; further details will not be repeated here.

[0104] In some embodiments, two clock signal lines CK1 and CK2 are configured for the gate drive circuit, wherein the clock signal input terminal CLK of the shift register located in the odd-numbered stage is connected to one clock signal line CK1, and the clock signal input terminal CLK of the shift register located in the even-numbered stage is connected to the other clock signal line CK2.

[0105] Taking the case where the gate drive circuit is configured with a cascaded signal output terminal CR as an example, the precharge signal input terminal INPUT of the shift register SR_1 in the first stage is connected to the frame start signal terminal STV. The precharge signal input terminal INPUT of any shift register SR_2, SR_3, SR_4 in the other stage is connected to the cascaded signal output terminal CR of the shift register in the previous stage. The reset signal input terminal RESET of the shift register in the last stage (not shown) is connected to the frame end reset signal. The reset signal input terminal RESET of any shift register SR_1, SR_2, SR_3, SR_4 in the other stage is connected to the cascaded signal output terminal CR of the shift register in the next stage.

[0106] Based on the same inventive concept, this disclosure also provides a display device. Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure, such as... Figure 7As shown, the display device includes a gate driving circuit 21; wherein, the gate driving circuit 21 adopts the gate driving circuit provided in the previous embodiment. For a detailed description of the gate driving circuit, please refer to the content in the previous embodiment, which will not be repeated here.

[0107] The display device also includes a display panel 22, which includes gate lines, data lines, and a plurality of pixel units (not shown). The drive signal output terminals of each shift register in the gate drive circuit 21 are connected to the corresponding row gate lines to provide drive signals to the corresponding row gate lines. In some embodiments, the gate drive circuit is directly fabricated on the array substrate within the display panel 22 in a GOA manner.

[0108] In some embodiments, the display device further includes a noise reduction control module 23; the noise reduction control module 23 is connected to the noise reduction control signal input terminal of each shift register in the gate drive circuit 21, and the noise reduction control module 23 is configured to provide an effective level signal to the noise reduction control signal input terminal of any shift register during at least a portion of the time period between the power-on time of the display device and the start time when the drive signal output terminal OUT of the shift register is first output in an effective level state.

[0109] In this embodiment, the noise reduction control module 23 can be used to provide an effective level signal or an ineffective level signal to the noise reduction control signal input terminal of each shift register, so as to control the output noise reduction circuit in each shift register to work or stop working. Specifically, for any shift register, during at least a portion of the time period between the power-on time of the display device and the start time when the drive signal output terminal of the shift register first outputs an effective level signal, an effective level signal is provided to the noise reduction control signal input terminal of the shift register. This allows noise reduction processing to be performed on each shift register after power-on and before each shift register outputs an effective level signal, which can effectively prevent the voltage at the drive signal output terminal of each shift register from being abnormally pulled during the power-on phase, and helps to maintain the voltage at the drive signal output terminal of each shift register in an ineffective level state during the power-on phase.

[0110] Figure 8 This is a schematic diagram illustrating one connection between the gate drive circuit and the noise reduction control module in an embodiment of this disclosure. Figure 9 This is a timing diagram of a gate drive circuit in an embodiment of the present disclosure, such as... Figure 8 and Figure 9 As shown, in a specific power-on noise reduction scenario, the noise reduction control module 23 is configured with a noise reduction control signal output terminal. The noise reduction control signal input terminals of each shift register SR_1, SR_2, SR_3, and SR_4 in the gate drive circuit 21 are connected to the same noise reduction control signal output terminal on the noise reduction control module 23.

[0111] See Figure 9 As shown, the noise reduction control module 23 is specifically configured to: continuously provide valid level signals to the noise reduction control signal input terminals of each stage of the shift register from the moment the display device is powered on (i.e., the moment the PCB board is powered on) to the moment when the drive signal output terminal of the first stage shift register in the gate drive circuit first outputs a clock signal in a valid level state; and continuously provide invalid level signals to the noise reduction control signal input terminals of each stage of the shift register from the moment when the drive signal output terminal of the first stage shift register first outputs a clock signal in a valid level state.

[0112] In other words, from the moment the display device is powered on until the moment the clock signal at the first valid level output terminal SR_1--OUT of the shift register in the first stage of the gate drive circuit is first output, the output noise reduction circuits in each stage of the shift register are all in working state. From the moment the clock signal at the first valid level output terminal SR_1--OUT of the shift register in the first stage is first output, the output noise reduction circuits in each stage of the shift register are all in non-working state.

[0113] Figure 10 This is a schematic diagram illustrating another connection between the gate drive circuit and the noise reduction control module in an embodiment of this disclosure. Figure 11 This is another timing diagram of the gate drive circuit in an embodiment of this disclosure, as shown below. Figure 10 and Figure 11 As shown, in another specific power-on noise reduction scenario, the noise reduction control module is configured with multiple noise reduction control signal output terminals that correspond one-to-one with the noise reduction control signal input terminals of each shift register in the gate drive circuit. The noise reduction control signal input terminal of each shift register is connected to the corresponding noise reduction control signal output terminal.

[0114] The noise reduction control module is specifically configured as follows: For the i-th stage shift register, from the moment the display device is powered on until the moment the clock signal at the drive signal output terminal SR_i--OUT of the i-th stage shift register is first output in an effective level state, an effective level signal is continuously provided to the noise reduction control signal input terminal of the i-th stage shift register; and from the moment the clock signal at the drive signal output terminal SR_i--OUT of the i-th stage shift register is first output in an effective level state, an ineffective level signal is continuously provided to the noise reduction control signal input terminal of the i-th stage shift register; where i is an integer and 1≤i≤N.

[0115] and Figure 8 and Figure 9 The output noise reduction circuits in all the shift registers shown in the diagram operate and stop operating simultaneously, but the situations are different. Figure 10 and Figure 11 In the illustrated scenario, the operating state of the output noise reduction circuits within each shift register can be controlled independently. Specifically, for any shift register, from the moment the display device is powered on until the start of the first valid clock signal output from the drive signal output terminal of the shift register, the output noise reduction circuit within the shift register is in an operating state. From the start of the first valid clock signal output from the drive signal output terminal of the shift register, the output noise reduction circuit within the shift register is in a non-operating state.

[0116] It should be noted that, Figure 9 and Figure 11 In this context, SR_i--NR represents the noise reduction control signal input terminal NR configured in the i-th stage shift register SR_i, and SR_i--OUT represents the drive signal output terminal OUT configured in the i-th stage shift register SR_i; i is a positive integer. Figures 8 to 11 Only a 4-stage shift register is shown schematically in the diagram.

[0117] In some embodiments, a PCB board is provided in the display device, and the noise reduction control module 23 is disposed on the PCB board. As a specific solution, a timing controller (TCON) is provided on the PCB board. The timing controller can be used to provide signals such as frame start signal and clock signal to the gate driving circuit to control the gate driving circuit to operate. The noise reduction control module 23 can be integrated into the timing controller.

[0118] The display device provided in this disclosure can be any product or component with display function, such as a liquid crystal display screen, wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0119] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, characterized in that, include: A precharge reset circuit, connected to a precharge signal input terminal, a reset signal input terminal, and a pull-up node, is configured to write a valid level signal to the pull-up node in response to a valid level signal provided by the precharge signal input terminal, and to write an invalid level signal to the pull-up node in response to a valid level signal provided by the reset signal input terminal. A drive output circuit is connected to the clock signal input terminal, the pull-up node, and the drive signal output terminal, and is configured to write the clock signal provided by the clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node. An output noise reduction circuit, connected to a noise reduction signal input terminal, a noise reduction control signal input terminal, and a drive signal output terminal, is configured to write an invalid level signal provided by the noise reduction signal input terminal to the drive signal output terminal in response to a valid level signal provided by the noise reduction control signal input terminal, so as to reduce noise at the drive signal output terminal; during at least a portion of the time period between the power-on time and the start time when the drive signal output terminal of the shift register first outputs a valid level state, the noise reduction control signal input terminal of the shift register outputs a valid level signal.

2. The shift register according to claim 1, characterized in that, The noise reduction signal input terminal is either a ground terminal or a power supply terminal that provides an inactive level signal.

3. The shift register according to claim 1, characterized in that, The output noise reduction circuit includes: an output noise reduction transistor; The control electrode of the output noise reduction transistor is connected to the noise reduction control signal input terminal, the first electrode of the output noise reduction transistor is connected to the noise reduction signal input terminal, and the second electrode of the output noise reduction transistor is connected to the drive signal output terminal.

4. The shift register according to claim 1, characterized in that, Also includes: A cascaded output circuit, connected to the clock signal input terminal, the pull-up node, and the cascaded signal output terminal, is configured to write the clock signal provided by the clock signal input terminal to the cascaded signal output terminal in response to the control of the effective level signal at the pull-up node.

5. The shift register according to claim 4, characterized in that, Also includes: A first pull-down control circuit, connected to the pull-up node and the first pull-down node, is configured to write an invalid level signal to the first pull-down node in response to a valid level signal at the pull-up node, and to write a valid level signal to the first pull-down node in response to a invalid level signal at the pull-up node. The second pull-down control circuit is connected to the pull-up node and the second pull-down node, and is configured to write an invalid level signal to the second pull-down node in response to the control of an invalid level signal at the pull-up node, and to write an valid level signal to the second pull-down node in response to the control of an invalid level signal at the pull-up node. A pull-up control circuit, connected to the pull-up node, the first pull-down node, and the second pull-down node, is configured to write an invalid level signal to the pull-up node in response to a valid level signal at the first pull-down node, and to write an invalid level signal to the pull-up node in response to a valid level signal at the second pull-down node. A global reset circuit, connected to a global reset control signal input terminal and a pull-up node, is configured to write an invalid level signal to the pull-up node in response to a valid level signal provided by the global reset control signal input terminal. The drive output circuit is also connected to the first pull-down node and the second pull-down node. The drive output circuit is also configured to write an invalid level signal to the drive signal output terminal in response to the control of the valid level signal at the first pull-down node, and to write an invalid level signal to the drive signal output terminal in response to the control of the valid level signal at the second pull-down node. The cascaded output circuit is also connected to the first pull-down node and the second pull-down node. The cascaded output circuit is further configured to write an invalid level signal to the cascaded signal output terminal in response to the control of the valid level signal at the first pull-down node, and to write an invalid level signal to the cascaded signal output terminal in response to the control of the valid level signal at the second pull-down node.

6. The shift register according to claim 5, characterized in that, The precharge reset circuit includes a first transistor and a second transistor; the first pull-down control circuit includes a third transistor and a fourth transistor; the second pull-down control circuit includes a fifth transistor and a sixth transistor; the pull-up control circuit includes a seventh transistor and an eighth transistor; the drive output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor; the cascaded output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor; and the global reset circuit includes a fifteenth transistor. The control electrode of the first transistor is connected to the precharge signal input terminal, the first electrode of the first transistor is connected to the precharge signal input terminal, and the second electrode of the first transistor is connected to the pull-up node. The control electrode of the second transistor is connected to the reset signal input terminal, the first electrode of the second transistor is connected to the pull-up node, and the first electrode of the second transistor is connected to the first power supply terminal. The control electrode of the third transistor is connected to the second power supply terminal, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode of the first transistor is connected to the first pull-down node. The control electrode of the fourth transistor is connected to the pull-up node, the first electrode of the fourth transistor is connected to the first pull-down node, and the second electrode of the fourth transistor is connected to the first power supply terminal. The control electrode of the fifth transistor is connected to the third power supply terminal, the first electrode of the fifth transistor is connected to the third power supply terminal, and the second electrode of the fifth transistor is connected to the second pull-down node. The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second pull-down node, and the second electrode of the sixth transistor is connected to the first power supply terminal. The control electrode of the seventh transistor is connected to the first pull-down node, the first electrode of the seventh transistor is connected to the pull-up node, and the second electrode of the seventh transistor is connected to the first power supply terminal. The control electrode of the eighth transistor is connected to the second pull-down node, the first electrode of the eighth transistor is connected to the pull-up node, and the second electrode of the eighth transistor is connected to the first power supply terminal. The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the clock signal input terminal, and the second electrode of the ninth transistor is connected to the drive signal output terminal. The control electrode of the tenth transistor is connected to the first pull-down node, the first electrode of the tenth transistor is connected to the drive signal output terminal, and the second electrode of the tenth transistor is connected to the fourth power supply terminal. The control electrode of the eleventh transistor is connected to the second pull-down node, the first electrode of the eleventh transistor is connected to the drive signal output terminal, and the second electrode of the eleventh transistor is connected to the fourth power supply terminal. The control electrode of the twelfth transistor is connected to the pull-up node, the first electrode of the twelfth transistor is connected to the clock signal input terminal, and the second electrode of the twelfth transistor is connected to the cascaded signal output terminal. The control electrode of the thirteenth transistor is connected to the first pull-down node, the first electrode of the thirteenth transistor is connected to the cascaded signal output terminal, and the second electrode of the thirteenth transistor is connected to the second power supply terminal. The control electrode of the fourteenth transistor is connected to the second pull-down node, the first electrode of the fourteenth transistor is connected to the cascaded signal output terminal, and the second electrode of the fourteenth transistor is connected to the second power supply terminal. The control electrode of the fifteenth transistor is connected to the global reset control signal input terminal, the first electrode of the fifteenth transistor is connected to the pull-up node, and the second electrode of the fifteenth transistor is connected to the first power supply terminal. The first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the drive signal output terminal.

7. A gate driving circuit, characterized in that, include: A cascaded multi-stage shift register, wherein the shift register is any one of the shift registers described in claims 1 to 6.

8. A display device, characterized in that, include: The gate driving circuit adopts the gate driving circuit described in claim 7; A noise reduction control module is connected to the noise reduction control signal input terminal of each of the shift registers in the gate drive circuit. The noise reduction control module is configured to provide an effective level signal to the noise reduction control signal input terminal of any shift register during at least a portion of the time period between the power-on time of the display device and the start time when the drive signal output terminal of the shift register is first output in an effective level state.

9. The display device according to claim 8, characterized in that, The noise reduction control module is specifically configured to: continuously provide valid level signals to the noise reduction control signal input terminals of each stage of the shift register from the moment the display device is powered on until the start of the first valid level clock signal output from the drive signal output terminal of the shift register located in the first stage of the gate drive circuit; and continuously provide invalid level signals to the noise reduction control signal input terminals of each stage of the shift register from the start of the first valid level clock signal output from the drive signal output terminal of the shift register located in the first stage.

10. The display device according to claim 8, characterized in that, The gate drive circuit includes N stages of the shift register; The noise reduction control module is specifically configured to: for the i-th stage shift register, from the power-on time of the display device to the start time when the drive signal output terminal of the i-th stage shift register first outputs a clock signal in an effective level state, continuously provide an effective level signal to the noise reduction control signal input terminal of the i-th stage shift register; And, starting from the moment when the clock signal in an effective level state is first output from the drive signal output terminal of the i-th stage shift register, an ineffective level signal is continuously provided to the noise reduction control signal input terminal of the i-th stage shift register; Where i is an integer and 1≤i≤N.

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