Integration with redistribution layer bumps

Abstract

The present disclosure relates generally to integration with redistribution layer bumps. A method of forming a semiconductor device includes forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled with the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over the first conductive feature and electrically coupled with the first conductive feature, wherein the first bump via is between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, wherein the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

Description

Technical Field

[0001] This disclosure generally relates to bump integration with redistribution layers. Background Technology

[0002] High-density integrated circuits (e.g., Very Large Scale Integration (VLSI) circuits) are typically formed with interconnect structures (also known as interconnects) serving as a three-dimensional wiring structure. The purpose of the interconnect structure is to properly connect densely packaged devices together to form functional circuits. As the level of integration increases, the parasitic capacitance effect between the interconnect metal lines (which causes RC delay and crosstalk) increases accordingly. To reduce parasitic capacitance and improve the conduction speed of interconnects, low-k dielectric materials are typically used to form the inter-layer dielectric (ILD) layer and the inter-metal dielectric (IMD) layer.

[0003] Metal lines and vias are formed in the IMD layer. The formation process may include forming an etch stop layer over a first conductive feature and a low-k dielectric layer over the etch stop layer. The low-k dielectric layer and the etch stop layer are patterned to form trenches and via openings. The trenches and via openings are then filled with a conductive material, followed by a planarization process to remove excess conductive material, thereby forming the metal lines and vias. Conductive bumps (e.g., micro-bumps (μ-bumps) and controlled-collapse chip-connection bumps (C4 bumps)) are formed on the interconnect structure for connection to other devices. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming an interconnect structure on a substrate; forming a first passivation layer on the interconnect structure; forming a first conductive feature on the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer on the first conductive feature and the first passivation layer; forming a dielectric layer on the second passivation layer; and forming a first bump via and a first conductive bump on the first conductive feature and electrically coupled to the first conductive feature, wherein the first bump via is between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, wherein the first conductive bump is on the dielectric layer and electrically coupled to the first bump via.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a first passivation layer over an interconnect structure, wherein the interconnect structure is located over and electrically coupled to an electronic component formed in a substrate; forming a conductive feature over the first passivation layer, wherein the conductive feature is electrically coupled to the interconnect structure; forming a second passivation layer over the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along an outer surface of the conductive feature; forming a dielectric layer over the second passivation layer, wherein an upper surface of the dielectric layer remote from the substrate extends further from the substrate than an upper surface of the conductive feature remote from the substrate; forming a bump via extending from the upper surface of the dielectric layer to the upper surface of the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and forming conductive bumps on the bump via.

[0006] Another embodiment of this disclosure provides a semiconductor device comprising: a substrate including a device region; an interconnect structure on the substrate and electrically coupled to the device region; a first passivation layer on the interconnect structure; a conductive feature on the first passivation layer and electrically coupled to the interconnect structure; a second passivation layer on the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along an outer surface of the conductive feature; a dielectric layer on the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive feature; a bump via in the dielectric layer, wherein the bump via extends from an upper surface of the dielectric layer away from the substrate to the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and a conductive bump on the bump via. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1A , Figure 1B , Figures 2-7 and Figures 8A-8C Cross-sectional views of semiconductor devices at various manufacturing stages according to embodiments are shown.

[0009] Figures 9-11 A cross-sectional view of a semiconductor device at various manufacturing stages according to another embodiment is shown.

[0010] Figures 12-15 , Figure 16A and Figure 16B Cross-sectional views of a semiconductor device at various manufacturing stages according to yet another embodiment are shown.

[0011] Figure 17 A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Detailed Implementation

[0012] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact.

[0013] Furthermore, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Throughout the description herein, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar elements formed using one or more of the same or similar materials by the same or similar forming methods. Furthermore, unless otherwise stated, figures with the same numerals and different letters (e.g., Figure 8A and Figure 8B The images show different views (e.g., along different cross sections) of the same semiconductor device at the same stage of manufacturing.

[0014] According to an embodiment, conductive bumps (e.g., C4 bumps or μ bumps) are formed in aligned-up openings or pulled-in openings in a dielectric layer above a conductive feature (e.g., conductive pads or conductive lines). A conformal passivation layer is formed on the conductive feature, and a dielectric layer is formed on the conformal passivation layer. Aligned-up openings or pulled-in openings are formed to extend through the dielectric layer and the passivation layer, thereby exposing the underlying conductive feature, and then conductive bumps are formed in the aligned-up openings or pulled-in openings on the conductive feature. Aligned-up openings or pulled-in openings increase the adhesion between the passivation layer and the dielectric layer and reduce the stress at the interface between the passivation layer and the dielectric layer. As a result, delamination at the interface between the passivation layer and the dielectric layer is avoided or reduced. By forming a dielectric layer as a planarization layer on top of the passivation layer, problems such as bump seed layer step coverage and discontinuities can be avoided or reduced, thereby improving device reliability and production yield.

[0015] Figure 1A , Figure 1B , Figures 2-7 and Figures 8A-8C Cross-sectional views of a semiconductor device 100 at various manufacturing stages according to embodiments are shown. The semiconductor device 100 may be a device wafer including active devices (e.g., transistors) and / or passive devices (e.g., capacitors, inductors, resistors, etc.). In some embodiments, the semiconductor device 100 is an interposer wafer, which may or may not include active devices and / or passive devices. According to yet another embodiment of this disclosure, the semiconductor device 100 is a packaging substrate strip, which may be a packaging substrate with a core or a coreless packaging substrate. In the following discussion, the device wafer is used as an example of the semiconductor device 100. As will be readily understood by those skilled in the art, the teachings of this disclosure can also be applied to interposer wafers, packaging substrates, or other semiconductor structures.

[0016] like Figure 1A As shown, the semiconductor device 100 includes a semiconductor substrate 101 (also referred to as substrate 101) and electronic components 103 (e.g., transistors, resistors, inductors, etc.) formed on or in the semiconductor substrate 101. The semiconductor substrate 101 may include a semiconductor material (e.g., silicon) (doped or undoped), or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 101 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0017] exist Figure 1A In the example, electronic component 103 is formed in the device region of semiconductor substrate 101. Examples of electronic component 103 include transistors (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), resistors, capacitors, diodes, etc. Electronic component 103 can be formed using any suitable method, details of which are not discussed here.

[0018] In some embodiments, after forming the electronic component 103, an interlayer dielectric (ILD) layer is formed on the semiconductor substrate 101 and on the electronic component 103. The ILD layer may fill the space between the gate stacks of the transistors (not shown) of the electronic component 103. According to some embodiments, the ILD layer includes silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD layer can be formed using spin coating, flow chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0019] Contact plugs are formed in the ILD layer, which electrically couple electronic component 103 to conductive features (e.g., metal wires, vias) of subsequently formed interconnect structure 106. Note that in this disclosure, unless otherwise stated, conductive features refer to electrically conductive features, and conductive materials refer to electrically conductive materials. According to some embodiments, the contact plugs are formed of conductive materials such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Forming the contact plugs may include: forming contact openings in the ILD layer, forming one or more conductive materials in the contact openings, and performing a planarization process such as chemical mechanical polishing (CMP) to make the top surface of the contact plug flush with the top surface of the ILD layer.

[0020] Still referencing Figure 1A An interconnect structure 106 is formed on top of the ILD layer and the electronic component 103. The interconnect structure 106 includes a plurality of dielectric layers 109 and conductive features (e.g., metal lines, vias) formed in the dielectric layers 109. In some embodiments, the interconnect structure 106 interconnects the electronic component 103 to form functional circuitry of the semiconductor device 100.

[0021] In some embodiments, each dielectric layer 109 (which may also be referred to as an intermetallic dielectric (IMD) layer) is formed of a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc.). According to some embodiments, the dielectric layer 109 is formed of a low-k dielectric material with a dielectric constant (k value) below 3.0 (e.g., about 2.5, about 2.0, or even lower). The dielectric layer 109 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. As an example, the formation of each dielectric layer 109 may include depositing a pore-forming dielectric material on top of the ILD layer, followed by a curing process to remove the pore-forming agent, thereby forming a porous dielectric layer 109. Other suitable methods may also be used to form the dielectric layer 109.

[0022] like Figure 1A As shown, conductive features, such as conductive lines 105 and vias 107, are formed in the dielectric layer 109. In an example embodiment, the conductive features may include a diffusion barrier layer and a conductive material (e.g., copper or a copper-containing material) on top of the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc., and may be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc. After forming the diffusion barrier layer, a conductive material is formed on top of the diffusion barrier layer. The formation of the conductive features may include a single damascene process, a dual damascene process, etc.

[0023] Next, a passivation layer 111 is formed over the interconnect structure 106, and a plurality of metal-insulator-metal (MIM) capacitors 113 are formed in the passivation layer 111. The passivation layer 111 may include a plurality of sublayers (see, for example, Figure 1B The passivation layer 111 (111A-111E) can be formed from one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations thereof, etc. The passivation layer 111 can be formed by processes such as chemical vapor deposition (CVD), FVCD, etc., but any suitable process can be used.

[0024] A MIM capacitor 113 is formed in the passivation layer 111. Figure 1B It shows Figure 1A An enlarged view of region 102 in the image to show details of the MIM capacitor 113. (See image for details.) Figure 1BAs shown, each MIM capacitor 113 includes two metal layers 113M (e.g., copper layers) and a dielectric layer 113I (e.g., a high-k dielectric layer) located between the metal layers 113M. Each layer of the MIM capacitor 113 (e.g., 113M, 113I, and 113M) is formed in a respective passivation layer (e.g., 111B, 111C, or 111D). As an example, the upper metal layer 113M and the lower metal layer 113M of the MIM capacitor 113 can be connected to an overlay via 119V and a lower via 108, respectively, wherein the overlay via 119V and the lower via 108 are formed in passivation layers 111E and 111A, respectively. As another example, the upper metal layer 113M and the lower metal layer 113M of the MIM capacitor 113 can be connected to a first overlay via 119V1 and a second overlay via 119V2, respectively. Figure 1B In the example, the second overlay via 119V2 extends through the passivation layer 111D and the dielectric layer 113I to connect with the lower metal layer 113M. Note that the second overlay via 119V2 extends through an opening in the upper metal layer 113M of the MIM capacitor, and is therefore separated from the upper metal layer 113M of the MIM capacitor (e.g., not in contact) through a portion of the passivation layer 111D.

[0025] Return to reference Figure 1A The lower metal layer of the MIM capacitor 113 can be electrically coupled to the conductive features of the interconnect structure 106, for example, through vias extending from the lower metal layer of the MIM capacitor 113 to the conductive features of the interconnect structure 106. Furthermore, multiple MIM capacitors 113 can be connected in parallel with electrical coupling to provide a large capacitance value. For example, the upper metal layers of the MIM capacitors 113 can be electrically coupled together, and the lower metal layers of the MIM capacitors 113 can be electrically coupled together. In some embodiments, the MIM capacitor 113 is omitted.

[0026] Next reference Figure 2 An opening 112 is formed in the passivation layer 111. Some openings 112 extend through the passivation layer 111 to expose the conductive features of the interconnect structure 106. In some embodiments, some openings 112 partially extend through the passivation layer 111 to expose the upper metal layer of the MIM capacitor 113. The openings 112 may be formed in one or more etching processes (e.g., anisotropic etching processes).

[0027] After forming the opening 112, a barrier layer 115 is conformally formed over the upper surface of the passivation layer 111 and along the sidewalls and bottom of the opening 112. The barrier layer 115 may have a multilayer structure and may include a diffusion barrier layer (e.g., a TiN layer) and a seed layer (e.g., a copper seed layer) formed on the diffusion barrier layer. The barrier layer 115 may be formed using one or more suitable formation methods, such as CVD, PVD, ALD, combinations thereof, etc.

[0028] Next, in Figure 3 In this process, a photoresist layer 137 is formed over the barrier layer 115. The photoresist layer 137 is patterned (e.g., using photolithography) to form a pattern on the conductive pads 119 (see [link to image]). Figure 4 An opening 138 is formed at the location where it will be formed. The opening 138 exposes a seed layer, such as a barrier layer 115. After the opening 138 is formed, a descumming process 110 is performed to remove residues left by the patterning process of the photoresist layer 137. As an example, the descumming process 110 may be a plasma process performed using a process gas containing oxygen.

[0029] Next, in Figure 4 In the process, conductive pads 119 (e.g., 119A and 119B) are formed in openings 138 above the barrier layer 115. The conductive pads 119 may comprise a conductive material, such as copper or a copper alloy (e.g., copper-silver alloy, copper-cobalt alloy, etc.), and can be formed using suitable forming methods (e.g., electroplating, electroless plating, etc.). After the conductive pads 119 are formed, the photoresist layer 137 is removed by a suitable removal process (e.g., ashing). Next, an etching process is performed to remove the portions of the barrier layer 115 on which the conductive pads 119 are not formed. Figure 4 As shown, some portions of the conductive material fill the openings 112 in the passivation layer 111 (see Figure 112). Figure 3 This forms a via 119V that electrically couples the conductive pad 119 to the conductive features of the MIM capacitor 113 and / or the underlying interconnect structure 106. Note that in the discussion herein, the barrier layer 115 in the opening 112 is considered part of the via 119V, and the barrier layer 115 above the upper surface of the passivation layer 111 is considered part of the conductive pad 119. Although in Figure 4 Not shown, but during the same processing steps of forming conductive pads 119, conductive lines (e.g., copper wires) may also be formed on the upper surface of passivation layer 111 (see, for example, Figure 12(118 in the original text). The conductive pad 119 and the conductive line can be collectively referred to as the redistribution layer (RDL), and the via 119V can be referred to as the RDL via. As an example, the cross-sectional shape of the conductive pad 119 can be dome-shaped (e.g., with a curved upper surface), concave, polygonal, or rectangular (or square). As an example, the area of ​​the RDL via 119V can be approximately 0.9 x 0.9 μm. 2 Approximately 3.5 x 3.5 μm 2 between.

[0030] Note that in Figure 4 In this configuration, some conductive pads 119 (e.g., 119A) are larger than other conductive pads 119 (e.g., 119B) (e.g., having a larger width measured between opposing sidewalls). In some embodiments, controlled collapse chip connection bumps (C4 bumps) are formed on the larger conductive pads 119A, and microbumps (μbumps) are formed on the smaller conductive pads 119B. As will be readily understood by those skilled in the art, the number of conductive pads 119 can be any suitable number, and they can be arranged in any order. Furthermore, although Figure 4 An RDL via 119V is shown below each conductive pad 119, but the number of RDL vias 119V below each conductive pad 119 can be any suitable number, such as one, two, three or more. Furthermore, the RDL vias 119V below each conductive pad 119 can be centered relative to the conductive pad 119, or they can be off-center relative to the conductive pad 119.

[0031] Next, in Figure 5 In this embodiment, a passivation layer 121 is conformally formed over the conductive pads 119 and the passivation layer 111. In some embodiments, the passivation layer 121 has a multilayer structure and includes an oxide layer (e.g., silicon oxide) and a nitride layer (e.g., silicon nitride) over the oxide layer. In other embodiments, the passivation layer 121 has a monolayer structure, such as having a single nitride layer. The passivation layer 121 can be formed using, for example, CVD, PVD, ALD, combinations thereof.

[0032] Next, in Figure 6In this process, a photoresist layer 135 is formed, for example, by spin coating onto a passivation layer 121. The photoresist layer 135 is then patterned using, for example, photolithography to form openings 136 at locations where conductive bumps will be formed. Next, an etching process is performed to remove the portions of the passivation layer 121 exposed by the openings 136. In some embodiments, the etching process is a dry etching process (e.g., plasma etching) using a process gas comprising a mixture of CF4, CHF3, N2, and Ar. Other process gases may also be used; for example, O2 may be used instead of CF4. After the etching process, the conductive pads 119 are exposed. The photoresist layer 135 is then removed by a suitable removal process (e.g., ashing). Note that, for simplicity, Figure 6 Only used in forming conductive bumps 125 (see Figure 8A An opening 136 is shown on the larger conductive pad 119A, and no openings are formed on the other conductive pads (e.g., 119B). Of course, this is merely a non-limiting example. Those skilled in the art will readily understand that the same or similar processing steps can be performed to form conductive bumps on other conductive pads (e.g., 119B).

[0033] Next, in Figure 7 In this configuration, a dielectric layer 131 is formed over passivation layer 121, conductive pads 119, and passivation layer 111. An opening 132 is formed in the dielectric layer 131 to expose the underlying conductive pads 119. The dielectric layer 131 may be formed of, for example, a polymer, polyimide (PI), benzocyclobutene (BCB), oxide (e.g., silicon oxide), or nitride (e.g., silicon nitride). As a non-limiting example, the dielectric layer 131... Figure 7 The dielectric layer 131 is shown as a single layer. The dielectric layer 131 may have a multilayer structure, including multiple sublayers formed of different dielectric materials.

[0034] In some embodiments, the dielectric layer 131 is a photosensitive material, such as a photosensitive polymer material, and the opening 132 is formed using photolithography. For example, the photosensitive material can be exposed to a patterned energy source (e.g., light) through, for example, a reticle. The impact of energy induces a chemical reaction in those portions of the photosensitive material impacted by the patterned energy source, thereby altering the physical properties of the exposed portions of the photosensitive material so that the physical properties of the exposed portions of the photosensitive material differ from those of the unexposed portions of the photosensitive material. The photosensitive material can then be developed with a developer to remove the exposed or unexposed portions of the photosensitive material, depending on, for example, whether a negative or positive photosensitive material is used. The remaining portion of the photosensitive material can be cured to form the patterned dielectric layer 131. As a non-limiting example, in Figure 7In the diagram, the apex corner of the dielectric layer 131 at the opening 132 is shown as sharp (e.g., including two intersecting lines). The apex corner of the dielectric layer 131 at the opening 132 can be, for example, rounded.

[0035] exist Figure 7 In the middle, the first distance between the opposite sidewalls 131S of the dielectric layer 131 exposed by the opening 132 is less than Figure 6 The second distance between the opposing sidewalls 121S of the passivation layer 121 exposed by the opening 136. In other words, the opening 132 in the dielectric layer 131 is narrower than the opening 136 in the passivation layer 121, such that the upper surface 121U and the sidewalls 121S of the passivation layer 121 are completely covered by the dielectric layer 131. Since the dielectric layer 131 is pulled in from the sidewalls 121S of the passivation layer 121, Figure 7 The opening 132 in the middle is referred to as a pull-in opening. As a non-limiting example, in... Figure 7 The sidewalls 131S of the dielectric layer 131 are shown as having a linear profile (e.g., a sloping line, or a flat sidewall sloping relative to the main upper surface of the substrate 101). The sidewalls 131S can be straight lines (e.g., perpendicular to the main upper surface of the substrate 101) or curved. The width of the opening 132 (e.g., the distance measured between opposing sidewalls 131S) can be constant, or it can vary continuously along the depth direction of the opening 132 (e.g., gradually, without step changes).

[0036] Compared to a pull-out opening, a pull-in opening 132 improves device reliability and manufacturing yield. In a pull-out opening, the sidewall 131S of the dielectric layer 131 is pulled out from the opening 132. Figure 7 The position indicated by the dashed line 130. In other words, if opening 132 is formed as a pull-out opening, then the width of opening 132 will be greater than... Figure 6 The width of the opening 136. When a pull-out opening is formed, the mechanical stress at the interface between the dielectric layer 131 and the passivation layer 121 near the dashed line 130 (e.g., between the portion of the dielectric layer 131 above the conductive pad 119 and the portion of the passivation layer 121 above the conductive pad 119) is much higher than in other areas of the device. This increased stress can cause delamination of the material layers in the high-stress region, leading to device failure and reduced production yield. Furthermore, the width of the seed layer 126 formed for forming the conductive bump 125 (see...) Figure 8AIn subsequent processing, pull-out openings can be more challenging for forming a conformal, continuous seed layer 126 (which lining the sidewalls and bottom of the pull-out opening) because the pull-out opening has more stepped shapes to be covered by the conformal seed layer 126. This is known as the bump seed layer step coverage problem. The bump seed layer step coverage problem can lead to discontinuities (e.g., holes) in the seed layer 126, which in turn can lead to defects in the conductive bumps 125 formed thereon. This disclosure avoids or reduces the aforementioned problems by forming pull-in openings for forming the conductive bumps 125, thereby improving device reliability and production yield. Note that in addition to pull-in openings, alignment openings (see, for example) can also be used. Figure 10 The aligned opening 136 (as discussed herein) provides the same or similar advantages as the pull-in opening. In some embodiments, the openings (e.g., 132, 136) for forming the conductive bump 125 are pull-in and / or aligned openings, and no pull-out opening is formed for forming the conductive bump 125.

[0037] Next, in Figure 8A In this embodiment, conductive bumps 125 are formed on conductive pads 119, and solder regions 129 are formed on the conductive bumps 125. The width of the conductive bumps 125 can be between about 5 μm and about 90 μm. The conductive bumps 125 can be μ bumps or C4 bumps. For example, a μ bump with a width (e.g., the width measured between opposite sidewalls) between about 5 μm and about 30 μm can be formed on conductive pad 119B, and a C4 bump with a width between about 32 μm and about 90 μm can be formed on conductive pad 119A. In the example embodiment, each of the μ bumps and C4 bumps is formed in a pull-in opening 132 formed on the respective conductive pad 119 (see [link to example embodiment]). Figure 7 )middle.

[0038] The conductive bump 125 can be formed by: forming a seed layer 126 over the dielectric layer 131 and along the sidewalls and bottom of the opening 132; forming a patterned photoresist layer over the seed layer 126, wherein the opening of the patterned photoresist layer is formed at the location where the conductive bump 125 is to be formed; forming (e.g., electroplating) a conductive material (e.g., copper) over the seed layer 126 in the opening; removing the patterned photoresist layer; and removing the portion of the seed layer 126 on which the conductive bump 125 is not formed. Note that some portions of the conductive material fill the opening 132 to form a bump via 125V, which electrically couples the conductive bump 125 to the underlying conductive pad 119. Note that in the discussion herein, the opening 132 (see...) Figure 7The seed layer 126 in the dielectric layer 131 is considered part of the bump via 125V, and the seed layer 126 above the upper surface of the dielectric layer 131 is considered part of the conductive bump 125. As an example, Figure 8A The interface between the conductive material (e.g., copper) of the conductive bump 125 and the seed layer 126 is shown. In some embodiments, the conductive material of the conductive bump 125 and the seed layer 126 are formed of the same material, so there may be no interface between them.

[0039] exist Figure 8A In this configuration, the number of bump vias 125V below (e.g., directly below) each conductive bump 125 is one. Of course, this is merely a non-limiting example. The number of bump vias 125V below each conductive bump 125 can be any suitable number, such as one, two, three, or more. Furthermore, one or more bump vias 125V below each conductive bump 125 can be centered relative to the conductive bump 125, or can be off-center relative to the conductive bump 125.

[0040] exist Figure 8A In the via 125V, the sidewalls of the bump via 125V contact (e.g., physically contact) the sidewalls of the dielectric layer 131 and extend along the sidewalls of the dielectric layer 131. The width of the bump via 125V may be constant (e.g., having sidewalls perpendicular to the main upper surface of the substrate 101), or may vary continuously as the bump via 125V extends toward the substrate 101 (e.g., gradually without step changes, or without discontinuous changes). Figure 8A In the example, the sidewalls of the bump via 125V have a linear profile (e.g., a sloping straight line), and the width of the bump via 125V decreases continuously as the bump via 125V extends toward the substrate 101. The sidewalls of the bump via 125V may have a curved profile (e.g., a curve), such as when the sidewall 131S of the dielectric layer 131 is exposed by the opening 132 (see...). Figure 7 When the via has a curved profile, note that there is a gap between the sidewall of the bump via 125V and the corresponding sidewall of the passivation layer 121, and the dielectric layer 131 fills the gap and contacts the upper surface of the conductive pad 119A. In other words, the bump via 125V is spaced apart (e.g., separated) from the passivation layer 121 by the portion of the dielectric layer 131 laterally disposed between the bump via 125V and the passivation layer 121.

[0041] exist Figure 8AIn the example, the thickness A of the portion of the dielectric layer 131 disposed above the passivation layer 121 on the conductive pad 119 is between about 1 μm and about 20 μm. The spacing S between adjacent smaller conductive pads 119B (e.g., on which μ bumps are formed) is greater than about 1.5 μm, and the spacing S between adjacent larger conductive pads 119A (e.g., on which C4 bumps are formed) is greater than about 4 μm. Figure 8A The sidewall portion of the passivation layer 121 is also shown (e.g., along the sidewall of the conductive pad 119, or along...). Figure 16A The thickness T of the portion of the conductive line 118 (the sidewall portion) and the thickness G of the upper portion of the passivation layer 121 (e.g., along the upper surface of the conductive pad 119 or along the upper surface of the conductive line 118) are specified, wherein the thickness G is between about 0.5 μm and about 5 μm, and wherein the ratio between T and G (e.g., T / G) (which is referred to as the stepped coverage of the passivation layer 121) is between about 20% and about 95%. In some embodiments, the spacing P between adjacent conductive bumps 125 is between about 10 μm and about 140 μm.

[0042] Figure 8B It shows Figure 8A An enlarged view of the portion of the semiconductor device 100 including the conductive bump 125. The dimensions of the conductive bump 125 and its surrounding structure are discussed below.

[0043] like Figure 8B As shown, the width W of the conductive bump 125 (e.g., a C4 bump or a μ bump) is between about 5 μm and about 90 μm. The width B at the top of the opening 132 in the dielectric layer 131 is between about 5 μm and about 22 μm for the μ bump, and between about 5 μm and about 78 μm for the C4 bump. Note that... Figure 8B The width W in the middle is along Figure 8B Measured in the horizontal direction, opening 132 has a length along the same direction as... Figure 8B The direction perpendicular to the cross-section (e.g., out of the paper and along) Figure 16B Another width W2 (measured along the longitudinal axis of conductive line 118 in the dielectric layer 131) is between approximately 5 μm and approximately 36 μm for μ bumps and between approximately 20 μm and approximately 40 μm for C4 bumps. The width E at the bottom of opening 132 in dielectric layer 131 is between approximately 5 μm and approximately 22 μm for μ bumps and between approximately 5 μm and approximately 78 μm for C4 bumps. The height D of bump via 125V is greater than the thickness A of dielectric layer 131 (see...). Figure 8A ), and greater than the thickness G of the passivation layer 121 (see Figure 8A ).

[0044] Still referencing Figure 8B, if the conductive pad 119 is a larger conductive pad 119A (e.g., on which C4 bumps are formed), the width L of the conductive pad 119 is between about 5 μm and about 45 μm, or if the conductive pad is a smaller conductive pad 119B (e.g., on which μ-bumps are formed), the width L of the conductive pad 119 is between about 1.5 μm and about 10 μm. The ratio between the width L of the conductive pad 119 and the pitch S (see Figure 8A ) is equal to or greater than one. The height J of the conductive pad 119 (or the conductive line 118 in Figure 16A ) is between about 2 μm and about 6 μm. Figure 8B Also shown is the angle F' between the sidewall of the dielectric layer 131 and the upper surface of the conductive pad 119, and the angle F between the sidewall of the passivation layer 121 and the upper surface of the conductive pad 119, where F can be between 10 degrees and 90 degrees (e.g., 10° < F < 90°), and F' can be between 10 degrees and 90 degrees (e.g., 10° < F' < 90°). If the opening (e.g., 136 in Figure 10 ) in which the conductive bump 125 is formed is an aligned opening, the corresponding F and F' are equal. Otherwise, F may be different from F'.

[0045] Figure 8C Shown is Figure 8B a plan view of the semiconductor device 100, and Figure 8B corresponds to a cross-sectional view taken along the cross-section A-A of Figure 8C . Note that, for simplicity, Figure 8C not all features are shown. As a non-limiting example, Figure 8C the conductive pad 119 in Figure 8C is shown as having an octagonal shape. Other shapes (e.g., circular, elliptical, rectangular, other polygons, etc.) are also possible and are fully intended to be included within the scope of the present disclosure. In the example of Figure 8C , the conductive bump 125 is shown as having a geometric shape similar to that of the conductive pad 119. In other embodiments, the conductive bump 125 and the conductive pad 119 have different shapes (e.g., non-geometrically similar shapes). Figure 8C Also shown is the conductive line 120 connected to the conductive pad 119. The conductive line 120 extends along the upper surface of the dielectric layer 131 and forms part of the redistribution layer together with the conductive pad 119.

[0046] Figures 9-11 Shown is a cross-sectional view of the semiconductor device 100B at various manufacturing stages according to another embodiment. The semiconductor device 100B is similar to Figure 8A the semiconductor device 100, but has an aligned opening 136 for exposing the conductive pad 119A and for forming the conductive bump 125 (see Figure 10 ). Figure 9 The processing followed Figure 1A , Figure 1B and Figures 2-5 After that processing. In other words, Figure 1A , Figure 1B , Figures 2-5 and Figures 9-11 The processing steps for forming semiconductor device 100B are shown.

[0047] exist Figure 9 In this process, after the passivation layer 121 is formed, a dielectric layer 131 is formed on top of the passivation layer 121, and an opening 132 is formed in the dielectric layer 131 to expose the passivation layer 121. The formation of the dielectric layer 131 and the opening 132 can be performed using the method described above. Figure 7 The same or similar processes are discussed, so details will not be repeated. Note that until this stage of processing, no openings are formed in the passivation layer 121 above the conductive pad 119. Therefore, the upper surface of the conductive pad 119 is covered by the passivation layer 121.

[0048] Next, in Figure 10 In this process, a patterned photoresist layer 133 is formed on the dielectric layer 131. The openings 136 of the patterned photoresist layer 133 overlap the corresponding openings 132 of the dielectric layer 131 (see [reference]). Figure 9 In some embodiments, the width of the opening 136, measured at the upper surface of the dielectric layer 131, is the same as the width of the opening 132, measured at the upper surface of the dielectric layer 131. In other embodiments, the width of the opening 136, measured at the upper surface of the dielectric layer 131, is greater than the width of the opening 132, measured at the upper surface of the dielectric layer 131. Next, the patterned photoresist layer 133 is used as an etching mask for a subsequent etching process, which can be performed in conjunction with... Figure 6 The etching process for the exposed conductive pad 119A is the same or similar. For example... Figure 10 As shown, after the etching process, the opening 136 extends downward through the passivation layer 121 and exposes the conductive pad 119A.

[0049] Still referencing Figure 10The openings 136 are formed as aligned openings. For each aligned opening 136, the sidewalls 131S of the dielectric layer 131 exposed by the opening 136 and the corresponding sidewalls 121S of the passivation layer 121 exposed by the opening 136 are aligned along the same line (e.g., a straight line perpendicular to the main upper surface of the substrate 101, or an inclined line relative to the main upper surface of the substrate 101, or a curve). In other words, the distance between the opposite sidewalls of the openings 136 varies continuously along the depth direction of the openings 136 (e.g., gradually without step changes). After forming the aligned openings 136, the photoresist layer 133 is removed, for example, by an ashing process.

[0050] Next, in Figure 11 In the middle, in with Figure 8A After the same or similar processing, conductive bumps 125 are formed on the conductive pads 119; details will not be repeated. Figure 11 In the example, the upper sidewall of the bump via 125V (e.g., the upper portion of the sidewall) contacts and extends along the sidewall 131S of the dielectric layer 131, and the lower sidewall of the bump via 125V (e.g., the lower portion of the sidewall) contacts and extends along the sidewall 121S of the passivation layer 121. In some embodiments, the width of the bump via 125V (e.g., the width measured between the opposing sidewalls of the bump via 125V) is constant (e.g., having straight sidewalls) or varies continuously as the bump via 125V extends toward the substrate 101 (e.g., gradually without step changes).

[0051] Figures 12-15 , Figure 16A and Figure 16B Cross-sectional views of a semiconductor device 100C at various manufacturing stages according to yet another embodiment are shown. The semiconductor device 100C is similar to... Figure 11 The semiconductor device 100B has conductive bumps 125 formed on conductive lines 118 instead of conductive pads 119. Figure 12 The processing followed Figure 1A , Figure 1B and Figure 2 After that processing. In other words, Figure 1A , Figure 1B , Figure 2 , Figures 12-15 , Figure 16A and Figure 16BThe processing steps for forming semiconductor device 100C are shown. Note that although semiconductor devices 100, 100B, and 100C are described as different embodiments, any combination of semiconductor devices 100, 100B, and 100C (e.g., 100 and 100C, or 100B and 100C) can be formed on the same substrate 101, for example, in different regions of the same substrate 101.

[0052] exist Figure 12 In China, use and Figure 3 A similar process is shown to form multiple conductive lines 118 on the passivation layer 111. In some embodiments, to form the conductive lines 118, a patterned photoresist layer 137 (see, for example) is used. Figure 3 A patterned photoresist layer 137 is formed on the barrier layer 115, wherein the pattern (e.g., openings) of the patterned photoresist layer 137 corresponds to the location of the subsequently formed conductive lines 118. Next, a descaling process 110 is performed. Next, a conductive material (e.g., copper) is formed in the pattern of the patterned photoresist layer 137 on the barrier layer 115. Next, the patterned photoresist layer 137 is removed, and an etching process is performed to remove portions of the barrier layer 115 on which no conductive material is formed.

[0053] Next, in Figure 13 In this process, a passivation layer 121 is conformally formed over the conductive line 118 and the passivation layer 111. The formation of the passivation layer 121 is similar to that described above. Figure 5 The treatments discussed are the same or similar, so the details will not be repeated.

[0054] Next, in Figure 14 In this configuration, a dielectric layer 131 is formed over the passivation layer 121, and an opening 132 is formed in the dielectric layer 131 to expose the passivation layer 121 disposed above the upper surface of the conductive line 118. The formation of the dielectric layer 131 and the opening 132 is as described above. Figure 7 The processes discussed are the same or similar, so the details will not be repeated. Note that until this stage of processing, no openings are formed in the passivation layer 121 to expose the conductive lines 118.

[0055] Next, in Figure 15 In this process, a photoresist layer 133 is formed on top of the dielectric layer 131, and covers the opening 132 (see...). Figure 14 An opening 136 is formed in the photoresist layer 133. Next, an etching process (e.g., an anisotropic etching process) is performed using the patterned photoresist layer 133 as an etching mask, causing the opening 136 to extend downwards, extending through the passivation layer 121 to expose the conductive line 118. The etching process can be the same as described above. Figure 6The etching processes discussed are the same or similar, so details will not be repeated. Note that, due to the anisotropic etching process used, for example, to form opening 136, opening 136 is an aligned opening.

[0056] Next, in Figure 16A In the middle, in with Figure 8A After the same or similar processing, conductive bumps 125 are formed on the conductive line 118; details will not be repeated. Figure 16A In the example, two bump vias 125V are formed below the conductive bump 125, and the conductive bump 125 is electrically coupled to two underlying conductive lines 118. In other words, each bump via 125V extends into the dielectric layer 131, through the passivation layer 121, and contacts (e.g., physically contacts) the underlying conductive lines 118, thereby electrically coupling the conductive bump 125 to the underlying conductive lines 118. Figure 16A The number of bump vias 125V below each conductive bump 125 and the number of conductive lines 118 electrically coupled to the overlying conductive bump 125 shown are merely non-limiting examples, and any suitable number of bump vias 125V and conductive lines 118 may be formed below each conductive bump 125.

[0057] like Figure 16A As shown, the upper sidewall (e.g., the upper portion of the sidewall) of the bump via 125V contacts and extends along the sidewall 131S of the dielectric layer 131, and the lower sidewall (e.g., the lower portion of the sidewall) of the bump via 125V contacts and extends along the sidewall 121S of the passivation layer 121. In some embodiments, the width of the bump via 125V (e.g., the width measured between the opposing sidewalls of the bump via 125V) is constant (e.g., having straight sidewalls) or varies continuously as the bump via 125V extends toward the substrate 101 (e.g., gradually without step changes).

[0058] Figure 16B It shows Figure 16A A plan view of a portion of the semiconductor device 100C, and Figure 16A Corresponding to along Figure 16B The cross-sectional view of section BB. Note that, for simplicity, Figure 16B Not all features are shown. As a non-limiting example, Figure 16B The conductive bump 128 is shown as having an octagonal shape. Other shapes (e.g., circular, elliptical, rectangular, other polygonal, etc.) are also possible and are fully intended to be included within the scope of this disclosure.

[0059] Variations or modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, although different embodiments 100, 100B, and 100C are described as different semiconductor devices, different structures / shapes of the conductive bumps 125 disclosed in embodiments 100, 100B, and 100C can be formed in different regions of the same semiconductor device. In other words, a semiconductor device can have different structures / shapes formed in different regions of the same semiconductor device. Figure 8A , Figure 11 and Figure 16A Different conductive bump structures disclosed in the paper.

[0060] Embodiments of this disclosure achieve several advantageous features. For example, by forming a pull-in opening (see example...) Figure 7 132) or aligned opening (see example) Figure 10 The formation of dielectric layer 136 improves the adhesion between dielectric layer 131 and passivation layer 121 and reduces mechanical stress in the device near the interface between dielectric layer 131 and passivation layer 121 (e.g., at the lower corner of dielectric layer 131 facing the opening). The improved adhesion and reduced stress help reduce or avoid delamination at the interface between dielectric layer 131 and passivation layer 121, thereby improving device performance, device reliability, and manufacturing yield. As another example, the formation of dielectric layer 131 eliminates some of the difficulties associated with forming conductive bump 125 and improves device reliability and manufacturing yield. Recall that to form conductive bump 125, a seed layer 126 is first formed, and then a conductive material is formed (e.g., plated) on the seed layer 126. Without dielectric layer 131, seed layer 126 would have to be conformally formed on conductive pad 119 and / or conductive line 118. In advanced semiconductor manufacturing, small gaps between conductive pads 119 or conductive lines 118 may have a high aspect ratio, and it may be difficult to form a seed layer 126 in these gaps, which could lead to the incorrect formation of conductive bumps 125. Furthermore, after forming the conductive bumps 125, it is necessary to remove the portions of the seed layer 126 on which the conductive bumps 125 are not formed. If these portions of the seed layer 126 are located in small gaps, it may be difficult to remove the seed layer 126, which could lead to electrical short circuits between the conductive bumps 125. Conversely, in the case of forming a dielectric layer 131, the seed layer 126 is formed over the dielectric layer 131 and in openings 132 or 136, which have a smaller aspect ratio, and therefore the seed layer 126 can be easily formed in the openings and easily removed from the openings, thus avoiding the problems discussed above.

[0061] Figure 17A flowchart of a method 1000 for manufacturing a semiconductor structure according to some embodiments is shown. It should be understood that... Figure 17 The illustrated embodiment method is merely one example of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, or repetitions may be made. Figure 17 The various steps are shown.

[0062] refer to Figure 17 At frame 1010, an interconnect structure is formed on the substrate. At frame 1020, a first passivation layer is formed on the interconnect structure. At frame 1030, a first conductive feature is formed on the first passivation layer and electrically coupled to the interconnect structure. At frame 1040, a second passivation layer is conformally formed on the first conductive feature and the first passivation layer. At frame 1050, a dielectric layer is formed on the second passivation layer. At frame 1060, a first bump via and a first conductive bump are formed on and electrically coupled to the first conductive feature, wherein the first bump via is between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, and wherein the first conductive bump is on the dielectric layer and electrically coupled to the first bump via.

[0063] According to one embodiment of this disclosure, a method of forming a semiconductor device includes: forming an interconnect structure on a substrate; forming a first passivation layer on the interconnect structure; forming a first conductive feature on the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer on the first conductive feature and the first passivation layer; forming a dielectric layer on the second passivation layer; and forming a first bump via and a first conductive bump on the first conductive feature and electrically coupled to the first conductive feature, wherein the first bump via is between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, and wherein the first conductive bump is on the dielectric layer and electrically coupled to the first bump via.

[0064] According to one embodiment of this disclosure, a method of forming a semiconductor device includes: forming a first passivation layer over an interconnect structure, wherein the interconnect structure is located over and electrically coupled to an electronic component formed in a substrate; forming a conductive feature over the first passivation layer, wherein the conductive feature is electrically coupled to the interconnect structure; forming a second passivation layer over the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along an outer surface of the conductive feature; forming a dielectric layer over the second passivation layer, wherein an upper surface of the dielectric layer remote from the substrate extends further from the substrate than an upper surface of the conductive feature remote from the substrate; forming a bump via extending from the upper surface of the dielectric layer to the upper surface of the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and forming conductive bumps on the bump via.

[0065] According to one embodiment of this disclosure, a semiconductor device includes: a substrate including a device region; an interconnect structure on the substrate and electrically coupled to the device region; a first passivation layer on the interconnect structure; a conductive feature on the first passivation layer and electrically coupled to the interconnect structure; a second passivation layer on the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along the outer surface of the conductive feature; a dielectric layer on the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive feature; a bump via in the dielectric layer, wherein the bump via extends from an upper surface of the dielectric layer away from the substrate to the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and conductive bumps on the bump via.

[0066] Example 1 is a method of forming a semiconductor device, the method comprising: forming an interconnect structure on a substrate; forming a first passivation layer on the interconnect structure; forming a first conductive feature on the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer on the first conductive feature and the first passivation layer; forming a dielectric layer on the second passivation layer; and forming a first bump via and a first conductive bump on the first conductive feature and electrically coupled to the first conductive feature, wherein the first bump via is between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, wherein the first conductive bump is on the dielectric layer and electrically coupled to the first bump via.

[0067] Example 2 is the method of Example 1, wherein the dielectric layer surrounds the first conductive feature, and the upper surface of the dielectric layer, away from the substrate, extends further from the substrate than the first conductive feature.

[0068] Example 3 is the method described in Example 1, wherein forming the first bump via and the first conductive bump includes: forming a first opening in the second passivation layer to expose the upper surface of the first conductive feature after forming the second passivation layer and before forming the dielectric layer; forming a second opening in the dielectric layer to expose the upper surface of the first conductive feature after forming the dielectric layer, wherein, after forming the second opening, the sidewall of the second passivation layer facing the second opening is covered by the dielectric layer; and forming a conductive material that fills the second opening and extends above the upper surface of the dielectric layer away from the substrate.

[0069] Example 4 is the method described in Example 3, wherein a first portion of the conductive material in the second opening forms the first bump via, and a second portion of the conductive material above the upper surface of the dielectric layer forms the first conductive bump.

[0070] Example 5 is the method of Example 3, wherein the second width of the second opening, measured between the opposite sidewalls of the second opening, is less than the first width of the first opening, measured between the opposite sidewalls of the first opening.

[0071] Example 6 is the method described in Example 5, wherein the second width of the second opening varies continuously along the depth direction of the second opening.

[0072] Example 7 is the method of Example 1, wherein forming the first bump via and the first conductive bump comprises: after forming the dielectric layer, forming a first opening in the dielectric layer, the first opening extending into the dielectric layer to expose an upper surface of the second passivation layer away from the substrate, wherein the second passivation layer exposed at the bottom of the first opening extends along and covers the upper surface of the first conductive feature; after forming the first opening, forming a patterned mask layer over the dielectric layer, wherein a second opening in the patterned mask layer covers the first opening; and using the patterned mask layer as an etching mask to perform an anisotropic etching process, wherein the anisotropic etching process causes the second opening to extend through the second passivation layer to expose the upper surface of the first conductive feature.

[0073] Example 8 is the method of Example 7, wherein, after the anisotropic etching process, the sidewall of the dielectric layer facing the second opening is aligned along the same line with the corresponding sidewall of the second passivation layer facing the second opening.

[0074] Example 9 is the method of Example 7, further comprising: after the anisotropic etching process, forming a conductive material on the upper surface of the first conductive feature, wherein a first portion of the conductive material in the dielectric layer forms the first bump via, and a second portion of the conductive material on the upper surface of the dielectric layer forms the first conductive bump.

[0075] Example 10 is the method described in Example 7, wherein the first conductive feature is a first conductive line.

[0076] Example 11 is the method of Example 10, wherein the method further includes: forming a second conductive line on the first passivation layer and adjacent to the first conductive line, wherein the second passivation layer is conformally formed on the second conductive line; and forming a second bump via between the first conductive bump and the second conductive line, wherein the second bump via extends into the dielectric layer, through the second passivation layer, and contacts the second conductive line, wherein the first conductive bump is electrically coupled to the first bump via and the second bump via.

[0077] Example 12 is the method of Example 1, further comprising: forming a metal-insulator-metal (MIM) capacitor in the first passivation layer, wherein the first conductive feature is formed to be electrically coupled to the MIM capacitor.

[0078] Example 13 is a method of forming a semiconductor device, the method comprising: forming a first passivation layer over an interconnect structure, wherein the interconnect structure is located over and electrically coupled to an electronic component formed in a substrate; forming a conductive feature over the first passivation layer, wherein the conductive feature is electrically coupled to the interconnect structure; forming a second passivation layer over the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along an outer surface of the conductive feature; forming a dielectric layer over the second passivation layer, wherein an upper surface of the dielectric layer remote from the substrate extends further from the substrate than an upper surface of the conductive feature remote from the substrate; forming a bump via extending from the upper surface of the dielectric layer to the upper surface of the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and forming conductive bumps on the bump via.

[0079] Example 14 is the method of Example 13, wherein the upper sidewall of the bump via contacts and extends along the first sidewall of the dielectric layer facing the bump via, and the lower sidewall of the bump via contacts and extends along the second sidewall of the second passivation layer facing the bump via.

[0080] Example 15 is the method described in Example 14, wherein the first sidewall of the dielectric layer is aligned with the second sidewall of the second passivation layer along the same line.

[0081] Example 16 is the method of Example 13, wherein the bump via and the second passivation layer are spaced apart by a portion of the dielectric layer that is laterally disposed between the bump via and the second passivation layer.

[0082] Example 17 is the method of Example 13, further comprising: forming a metal-insulator-metal (MIM) capacitor in the first passivation layer, wherein the conductive feature is formed to be electrically coupled to the MIM capacitor.

[0083] Example 18 is a semiconductor device comprising: a substrate including a device region; an interconnect structure on the substrate and electrically coupled to the device region; a first passivation layer on the interconnect structure; a conductive feature on the first passivation layer and electrically coupled to the interconnect structure; a second passivation layer on the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along an outer surface of the conductive feature; a dielectric layer on the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive feature; a bump via in the dielectric layer, wherein the bump via extends from an upper surface of the dielectric layer away from the substrate to the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature; and a conductive bump on the bump via.

[0084] Example 19 is the semiconductor device described in Example 18, wherein the upper sidewall of the bump via contacts and extends along the first sidewall of the dielectric layer facing the bump via, and the lower sidewall of the bump via contacts and extends along the second sidewall of the second passivation layer facing the bump via, wherein the first sidewall and the second sidewall are aligned along the same line.

[0085] Example 20 is the semiconductor device described in Example 18, wherein a portion of the dielectric layer is laterally disposed between the second passivation layer and the bump via, such that the bump via is separated from the second passivation layer.

[0086] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: Interconnect structures are formed on the substrate; A first passivation layer is formed on the interconnect structure; A first conductive feature is formed on top of the first passivation layer and electrically coupled to the interconnect structure; A second passivation layer is conformally formed on the first conductive feature and the first passivation layer, wherein the second passivation layer includes a sidewall portion along the sidewall of the first conductive feature and an upper portion along the upper surface of the first conductive feature, and the thickness of the sidewall portion is less than the thickness of the upper portion. A dielectric layer is formed on top of the second passivation layer; and A first bump via and a first conductive bump are formed on and electrically coupled to the first conductive feature, wherein the first bump via is located between the first conductive bump and the first conductive feature, wherein the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, and wherein the first conductive bump is on the dielectric layer and electrically coupled to the first bump via. Wherein, after the first bump via is formed, the angle between the sidewall of the dielectric layer facing the first bump via and the upper surface of the first conductive feature is different from the angle between the sidewall of the second passivation layer facing the first bump via and the upper surface of the first conductive feature.

2. The method according to claim 1, wherein, The dielectric layer surrounds the first conductive feature, and the upper surface of the dielectric layer, away from the substrate, extends further from the substrate than the first conductive feature.

3. The method according to claim 1, wherein, The formation of the first bump via and the first conductive bump includes: After the second passivation layer is formed and before the dielectric layer is formed, a first opening is formed in the second passivation layer to expose the upper surface of the first conductive feature; After forming the dielectric layer, a second opening is formed in the dielectric layer to expose the upper surface of the first conductive feature, wherein, after forming the second opening, the sidewalls of the second passivation layer facing the second opening are covered by the dielectric layer; and A conductive material is formed that fills the second opening and extends above the upper surface of the dielectric layer away from the substrate.

4. The method according to claim 3, wherein, The first portion of the conductive material in the second opening forms the first bump via, and the second portion of the conductive material above the upper surface of the dielectric layer forms the first conductive bump.

5. The method according to claim 3, wherein, The second width of the second opening, measured between the opposite sidewalls of the second opening, is less than the first width of the first opening, measured between the opposite sidewalls of the first opening.

6. The method according to claim 5, wherein, The second width of the second opening varies continuously along the depth direction of the second opening.

7. The method according to claim 1, wherein, The formation of the first bump via and the first conductive bump includes: After the dielectric layer is formed, a first opening is formed in the dielectric layer, the first opening extending into the dielectric layer to expose the upper surface of the second passivation layer away from the substrate, wherein the second passivation layer exposed at the bottom of the first opening extends along the upper surface of the first conductive feature and covers the upper surface of the first conductive feature. After forming the first opening, a patterned mask layer is formed on the dielectric layer, wherein a second opening in the patterned mask layer covers the first opening; and An anisotropic etching process is performed using the patterned mask layer as an etching mask, wherein the anisotropic etching process causes the second opening to extend through the second passivation layer to expose the upper surface of the first conductive feature.

8. The method according to claim 7, wherein, After the anisotropic etching process, the sidewall of the dielectric layer facing the second opening is aligned with the corresponding sidewall of the second passivation layer facing the second opening along the same line.

9. The method according to claim 7, further comprising: After the anisotropic etching process, a conductive material is formed on the upper surface of the first conductive feature, wherein a first portion of the conductive material in the dielectric layer forms the first bump via, and a second portion of the conductive material on the upper surface of the dielectric layer forms the first conductive bump.

10. The method according to claim 7, wherein, The first conductive feature is the first conductive line.

11. The method according to claim 10, wherein, The method further includes: A second conductive line is formed on the first passivation layer and adjacent to the first conductive line, wherein the second passivation layer is conformally formed on the second conductive line; and A second bump via is formed between the first conductive bump and the second conductive line, wherein the second bump via extends into the dielectric layer, passes through the second passivation layer, and contacts the second conductive line, wherein the first conductive bump is electrically coupled to the first bump via and the second bump via.

12. The method according to claim 1, further comprising: A metal-insulator-metal (MIM) capacitor is formed in the first passivation layer, wherein the first conductive feature is formed to be electrically coupled to the MIM capacitor.

13. A method of forming a semiconductor device, the method comprising: A first passivation layer is formed on an interconnect structure, wherein the interconnect structure is located on and electrically coupled to an electronic component formed in a substrate; A conductive feature is formed on the first passivation layer, wherein the conductive feature is electrically coupled to the interconnect structure; A second passivation layer is formed on the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along the outer surface of the conductive feature, the second passivation layer includes a sidewall portion along the sidewall of the conductive feature and an upper portion along the upper surface of the conductive feature, and the thickness of the sidewall portion is less than the thickness of the upper portion. A dielectric layer is formed on the second passivation layer, wherein the upper surface of the dielectric layer away from the substrate extends further from the substrate than the upper surface of the conductive feature away from the substrate. A bump via is formed extending from the upper surface of the dielectric layer to the upper surface of the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature, and wherein, after the bump via is formed, the angle between the sidewall of the dielectric layer toward the bump via and the upper surface of the conductive feature is different from the angle between the sidewall of the second passivation layer toward the bump via and the upper surface of the conductive feature; and Conductive bumps are formed on the bump vias.

14. The method according to claim 13, wherein, The upper sidewall of the bump via contacts the first sidewall of the dielectric layer facing the bump via and extends along the first sidewall, and the lower sidewall of the bump via contacts the second sidewall of the second passivation layer facing the bump via and extends along the second sidewall.

15. The method according to claim 14, wherein, The first sidewall of the dielectric layer is aligned with the second sidewall of the second passivation layer along the same line.

16. The method according to claim 13, wherein, The bump via and the second passivation layer are separated by a portion of the dielectric layer that is laterally disposed between the bump via and the second passivation layer.

17. The method of claim 13, further comprising: A metal-insulator-metal (MIM) capacitor is formed in the first passivation layer, wherein the conductive features are formed to be electrically coupled to the MIM capacitor.

18. A semiconductor device, comprising: Substrate, including the device region; An interconnect structure is situated on the substrate and electrically coupled to the device region; A first passivation layer is applied over the interconnect structure; A conductive feature is present above the first passivation layer and electrically coupled to the interconnect structure; A second passivation layer is disposed above the conductive feature and the first passivation layer, wherein the second passivation layer is conformal and extends along the outer surface of the conductive feature, the second passivation layer includes a sidewall portion along the sidewall of the conductive feature and an upper portion along the upper surface of the conductive feature, and the thickness of the sidewall portion is less than the thickness of the upper portion. A dielectric layer, above the second passivation layer, wherein the dielectric layer extends further from the substrate than the conductive feature; A bump via, in the dielectric layer, wherein the bump via extends from the upper surface of the dielectric layer away from the substrate to the conductive feature, wherein the width of the bump via continuously varies as the bump via extends toward the conductive feature, and the angle between the sidewall of the dielectric layer toward the bump via and the upper surface of the conductive feature is different from the angle between the sidewall of the second passivation layer toward the bump via and the upper surface of the conductive feature; and A conductive bump is located on the bump through-hole.

19. The semiconductor device according to claim 18, wherein, The upper sidewall of the bump via contacts the first sidewall of the dielectric layer facing the bump via and extends along the first sidewall, and the lower sidewall of the bump via contacts the second sidewall of the second passivation layer facing the bump via and extends along the second sidewall, wherein the first sidewall and the second sidewall are aligned along the same line.

20. The semiconductor device according to claim 18, wherein, A portion of the dielectric layer is laterally disposed between the second passivation layer and the bump via, such that the bump via is separated from the second passivation layer.

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