Display substrate and preparation method thereof, and display panel

Abstract

The present invention discloses a display substrate and a preparation method thereof, and a display panel, which are used to solve the technical problem of poor via overlap of a double-layer LTPS thin-film transistor existing in the prior art. The display substrate comprises: a first thin-film transistor and a second thin-film transistor located on a base substrate; wherein the active layer of the first thin-film transistor is located in a film layer between the base substrate and the active layer of the second thin-film transistor, and there is at least one first insulating layer between the active layer of the first thin-film transistor and the active layer of the second thin-film transistor, and the at least one first insulating layer has a first via hole penetrating in the thickness direction, and the first electrode of the second thin-film transistor is electrically connected to the active layer of the first thin-film transistor through the first via hole, and the material of the first electrode of the second thin-film transistor is amorphous silicon rich in phosphorus.

Description

Technical Field

[0001] The present invention relates to the field of thin film transistors, and in particular to a display substrate and a preparation method thereof, and a display panel. Background Art

[0002] In the process of manufacturing a high-resolution organic light emitting diode (OLED) display panel, it is necessary to use a double-layer low-temperature polysilicon (LTPS) technology to improve the resolution of the display panel.

[0003] At present, the double-layer LTPS technology is to connect two LTPS thin film transistors (TFTs) stacked on different layers through vias. Without considering the crystallization process, the first layer of amorphous silicon (1 st The amorphous silicon (2nd a-Si) layer is formed by depositing a second layer of amorphous silicon (2nd a-Si) after the via is opened. Direct crystallization without experience will result in ineffective crystallization of the amorphous silicon on the via sidewalls corresponding to the opening. When using excimer laser annealing (ELA) to crystallize the 2nd a-Si, the slope of the via sidewalls and the short ELA line scan distance result in low overlap. Consequently, the a-Si on the via sidewalls cannot absorb sufficient laser energy to crystallize, resulting in poor overlap at the via location and abnormal resistance of the upper LTPS thin-film transistor.

[0004] In view of this, how to improve the poor via overlap of double-layer LTPS thin-film transistors has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a display substrate and a preparation method thereof, and a display panel, which are used to solve the technical problem of poor via-hole overlap of a double-layer LTPS thin-film transistor existing in the prior art.

[0006] In a first aspect, to solve the above technical problems, an embodiment of the present invention provides a display substrate, comprising: a first thin film transistor and a second thin film transistor located on a base substrate; wherein,

[0007] The active layer of the first thin film transistor is located in a film layer between the base substrate and the active layer of the second thin film transistor, and there is at least one first insulating layer between the active layer of the first thin film transistor and the active layer of the second thin film transistor. The at least one first insulating layer has a first via hole running through the thickness direction. The first electrode of the second thin film transistor is electrically connected to the active layer of the first thin film transistor through the first via hole. The material of the first electrode of the second thin film transistor is amorphous silicon rich in phosphorus.

[0008] A possible implementation further includes an etch stop portion provided in the same layer as the first electrode of the second thin film transistor, the etch stop portion being located between the second electrode of the second thin film transistor and the active layer; wherein the material of the etch stop portion is the phosphorus-rich amorphous silicon.

[0009] In a possible implementation manner, the first electrode of the second thin film transistor and the etch stopper are respectively disposed in direct contact with the active layer of the second thin film transistor;

[0010] There is a second insulating layer between the layer where the second electrode of the second thin film transistor is located and the layer where the etch stop part is located. The second insulating layer has a second via hole running through the thickness direction. The second electrode of the second thin film transistor is electrically connected to the etch stop part through the second via hole.

[0011] In a possible implementation manner, the orthographic projection of the etch stop portion on the base substrate covers the orthographic projection of the second via hole on the base substrate.

[0012] In a possible implementation manner, the material of the active layer of the second thin film transistor is silicon-based nanowires.

[0013] In a possible implementation manner, both the first thin film transistor and the second thin film transistor are top-gate thin film transistors, or both the first thin film transistor and the second thin film transistor are bottom-gate thin film transistors;

[0014] The orthographic projections of the active layer of the first thin film transistor and the active layer of the second thin film transistor on the base substrate are arranged to overlap with each other.

[0015] In a second aspect, an embodiment of the present invention provides a method for preparing a composite device structure, comprising:

[0016] forming an active layer of a first thin film transistor on a base substrate;

[0017] forming at least one first insulating layer on the active layer of the first thin film transistor;

[0018] forming an active layer of a second thin film transistor on the at least one first insulating layer;

[0019] forming a first via hole penetrating the at least one first insulating layer;

[0020] Amorphous silicon material rich in phosphorus is used to form a first electrode of the second thin film transistor on the active layer of the second thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the active layer of the first thin film transistor through the first via hole.

[0021] In a possible implementation manner, forming an active layer of a second thin film transistor on the at least one first insulating layer includes:

[0022] forming a groove on the first insulating layer at the top layer;

[0023] depositing an indium tin oxide material in the trench;

[0024] Performing hydrogen plasma treatment on the indium tin oxide material to form a plurality of indium balls arranged along the extension direction of the groove, and using the plurality of indium balls as catalyst particles to induce the amorphous silicon to grow into silicon nanowires;

[0025] depositing an amorphous silicon layer in the trench having the catalyst particles;

[0026] The non-silicon layer is annealed to form silicon-based nanowires as the active layer of the second thin film transistor.

[0027] In a possible implementation manner, the preparation method further comprises:

[0028] forming an etching stopper while forming a first electrode of the second thin film transistor on the active layer of the second thin film transistor;

[0029] forming a second insulating layer covering the first electrode of the second thin film transistor and the etch stopper;

[0030] forming a second via hole penetrating the second insulating layer;

[0031] A second electrode of the second thin film transistor is formed on the second insulating layer, and the second electrode of the second thin film transistor is electrically connected to the etch stopper through the second via hole.

[0032] In a third aspect, an embodiment of the present invention further provides a display panel, comprising the display substrate as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of a double-layer LTPS thin film transistor in the related art;

[0034] Figure 2 Schematic diagram of a-Si deposition at the via hole location;

[0035] Figure 3 Shown is the SEM image of the via sidewall;

[0036] Figure 4 for Figure 3 A local magnified view of the normal crystallized part of the sidewall of the middle via;

[0037] Figure 5 A schematic structural diagram of a composite display substrate is provided for an embodiment of the present invention;

[0038] Figure 6 A schematic structural diagram of another display substrate provided by an embodiment of the present invention;

[0039] Figure 7 A schematic structural diagram of another display substrate provided by an embodiment of the present invention;

[0040] Figure 8 A schematic structural diagram of another display substrate provided by an embodiment of the present invention;

[0041] Figure 9 A schematic structural diagram of another display substrate provided by an embodiment of the present invention;

[0042] Figure 10 A schematic diagram of another display substrate provided by an embodiment of the present invention;

[0043] Figure 11 A flow chart of manufacturing a display substrate provided by an embodiment of the present invention;

[0044] Figure 12 A flow chart of preparing a second thin film transistor in a display substrate provided by an embodiment of the present invention;

[0045] Figure 13 A flow chart of forming an active layer of a second thin film transistor provided in an embodiment of the present invention.

[0046] Base substrate 1, first thin film transistor 2, second thin film transistor 3, first insulating layer 4, first via 41, second insulating layer 5, second via 51, active layer 21 of first thin film transistor 2, active layer 31 of second thin film transistor 3, first electrode 32 of second thin film transistor 3, etching stopper 33, second electrode 34 of second thin film transistor 3. DETAILED DESCRIPTION

[0047] The embodiments of the present invention provide a display substrate and a method for manufacturing the same, and a display panel, to solve the technical problem of poor via-hole connection of a double-layer LTPS thin film transistor in the prior art.

[0048] In order to better understand the above technical solution, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0049] See Figure 1 Schematic diagram of the structure of a double-layer LTPS thin-film transistor in related technology.

[0050] Figure 1 The double-layer LTPS TFT includes a first layer TFT and a second layer TFT, and the film layer between the second layer TFT and the first layer TFT has a via hole perpendicular to the thickness direction of the film layer ( Figure 1 The dotted line in the middle shows the position of the via hole), after depositing the a-Si of the second layer TFT (as shown in FIG. Figure 2 The figure shows a schematic diagram of a-Si deposition at the location of the via hole), and the a-Si of the second layer TFT is subjected to ELA treatment to obtain p-Si to form the second active layer of the second layer TFT. The second active layer passes through the above-mentioned through hole and is connected to the drain of the first layer TFT.

[0051] from Figure 2 It can be seen that the sidewall of the via hole has a certain slope. When the second layer of a-Si is subjected to ELA treatment, the overlap rate between the two is low due to the short ELA line scanning distance. The a-Si on top cannot absorb enough laser energy to crystallize. The sidewall of the via hole is scanned with a scanning electron microscope (SEM) to obtain the corresponding SEM image, as shown below. Figure 3 The following is an SEM image of the via sidewall. Figure 3 It can be seen that some of the upper and lower edges of the via cannot be crystallized, while some of the side walls can be crystallized normally, such as Figure 4 Shown Figure 3 A partial enlarged view of the normally crystalline portion of the sidewall of the middle via shows that the sidewall of the via is partially crystallized to form p-Si, which causes poor overlap at the via position, resulting in abnormal resistance of the second-layer TFT.

[0052] In order to solve the above problems, the present invention provides the following solutions:

[0053] Please refer to Figure 5 , is a schematic structural diagram of a display substrate provided in an embodiment of the present invention, the display substrate comprising:

[0054] A first thin film transistor 2 and a second thin film transistor 3 are located on a base substrate 1; wherein,

[0055] The active layer 21 of the first thin film transistor 2 is located in a film layer between the base substrate 1 and the active layer 31 of the second thin film transistor 3, and there is at least one first insulating layer 4 between the active layer 21 of the first thin film transistor 2 and the active layer 31 of the second thin film transistor 3. The at least one first insulating layer 4 has a first via 41 extending through the thickness direction. The first electrode 32 of the second thin film transistor 3 is electrically connected to the active layer 21 of the first thin film transistor 2 through the first via 41. The material of the first electrode 32 of the second thin film transistor 3 is amorphous silicon rich in phosphorus.

[0056] When the first thin-film transistor 2 and the second thin-film transistor 3 are both top-gate thin-film transistors, three first insulating layers 4 are located between the active layer 21 of the first thin-film transistor 2 and the active layer 31 of the second thin-film transistor 3. These layers are the gate insulating layer (GI), the interlayer dielectric layer (ILD), and the buffer layer, stacked sequentially on the side of the active layer 21 away from the substrate 1. When the first thin-film transistor 2 is a top-gate thin-film transistor and the second thin-film transistor 3 is a bottom-gate thin-film transistor, two first insulating layers 4 are located between the active layer 21 of the first thin-film transistor 2 and the active layer 31 of the second thin-film transistor 3. These layers are the gate insulating layer and the interlayer dielectric layer, stacked sequentially on the side of the active layer 21 away from the substrate 1.

[0057] The gate insulating layer is usually made of silicon oxide, the interlayer dielectric layer is usually made of silicon nitride, and the buffer layer is usually made of silicon nitride and silicon oxide.

[0058] The above-mentioned zero element-rich amorphous silicon can be heavily doped with N + a-Si may also be other types of heavily doped amorphous silicon, without specific limitation.

[0059] In the embodiment provided by the present invention, by using zero-element amorphous silicon as the material for the first electrode 32 of the second thin film transistor 3, the contact barrier with the active layer 21 of the first thin film transistor 2 and the active layer 31 of the second thin film transistor 3 can be reduced, the tunneling effect at the interface can be enhanced, and the on-state current of the second thin film transistor 3 and the first thin film transistor 2 can be increased, thereby reducing the resistance of the second thin film transistor 3 and improving the problem of poor connection of the stacked thin film transistor. In addition, because the first insulating layer 4 between the active layer 31 of the second thin film transistor 3 and the active layer 21 of the first thin film transistor 2 is provided with a first via 41, the first electrode 32 of the second thin film transistor 3 is directly connected to the active layer 21 of the first thin film transistor 2 through the first via 41. This eliminates the need to provide a via for connecting the metal electrode (such as the drain) of the thin film transistor located in the lower layer of the stacked thin film transistor to its active layer, and also provide a via for connecting the active layer of the thin film transistor in the upper layer to the drain of the thin film transistor in the lower layer, as in the related art. Therefore, the display substrate in the embodiment of the present invention can also effectively reduce the number of vias, thereby saving process.

[0060] See Figure 6 A schematic structural diagram of another display substrate provided in an embodiment of the present invention. The display substrate further includes:

[0061] An etch stopper 33 is provided in the same layer as the first electrode 32 of the second thin-film transistor 3. The etch stopper 33 is located between the second electrode 34 of the second thin-film transistor 3 and the active layer 31 of the second thin-film transistor 3. The etch stopper 33 is made of phosphorus-rich amorphous silicon. The etch stopper 33 is made of the same material as the first electrode 32 of the second thin-film transistor 3.

[0062] See Figure 7 This is a schematic structural diagram of another display substrate provided by an embodiment of the present invention, in which the first electrode 32 and the etching stopper 33 of the second thin film transistor 3 are respectively disposed in direct contact with the active layer 31 of the second thin film transistor 3;

[0063] There is a second insulating layer 5 between the layer where the second electrode 34 of the second thin film transistor 3 is located and the layer where the etching stopper 33 is located. The second insulating layer 5 has a second via hole 51 running through the thickness direction. The second electrode 34 of the second thin film transistor 3 is electrically connected to the etching stopper 33 through the second via hole 51.

[0064] When the second thin-film transistor 3 is a top-gate thin-film transistor, two second insulating layers 5 are located between the layer where the second electrode 34 of the second thin-film transistor 3 is located and the layer where the etch stop portion 33 is located. These layers are a gate insulating layer located on the side of the etch stop portion away from the substrate, and an interlayer dielectric layer located on the side of the gate insulating layer away from the substrate. When the second thin-film transistor 3 is a bottom-gate thin-film transistor, one second insulating layer 5 is located between the layer where the second electrode 34 of the second thin-film transistor 3 is located and the layer where the etch stop portion 33 is located. This interlayer dielectric layer is located on the side of the etch stop portion away from the substrate.

[0065] The orthographic projection of the etch stopper 33 on the base substrate 1 covers the orthographic projection of the second via hole 51 on the base substrate 1. In this way, when forming the second via hole 51, the active layer 31 of the second thin film transistor 3 can be prevented from being etched.

[0066] In the embodiment provided by the present invention, an etching stopper 33 in the same layer as the first electrode 32 of the second thin film transistor 3 is provided between the second electrode 34 of the second thin film transistor 3 and the active layer 31, and phosphorus-rich amorphous silicon is used as the material of the etching stopper 33. The first electrode 32 of the second thin film transistor 3 and the etching stopper 33 can be formed simultaneously during production. Furthermore, when etching the metal of the second electrode 34 of the second thin film transistor 3 or the second via 51, damage to the active layer 31 of the second thin film transistor 3 due to severe over-etching can be prevented, thereby protecting the mobility of the active layer 31 of the second thin film transistor 3 from loss due to over-etching.

[0067] The orthographic projection of the bottom surface of the second via hole 51 on the base substrate 1 is located within the orthographic projection of the etch stop portion 33 on the base substrate 1. By arranging the orthographic projection of the bottom surface of the second via hole 51 on the base substrate 1 within the orthographic projection of the etch stop portion 33 on the base substrate 1, it is ensured that the active layer 31 of the second thin film transistor 3 is not damaged when the second via hole 51 is formed.

[0068] See Figure 8 , is a schematic structural diagram of another display substrate provided by an embodiment of the present invention, wherein the material of the active layer 31 of the second thin film transistor 3 is silicon-based nanowires.

[0069] By using silicon-based nanowires as the material of the active layer 31 of the second thin film crystal 3, the mobility of the active layer 31 of the second thin film transistor 3 can be improved, the resistance of the second thin film crystal 3 transistor can be reduced, and the problem of poor overlap of the stacked thin film transistor can be further improved.

[0070] In a possible implementation manner, the first thin film transistor 2 and the second thin film transistor 3 are both top-gate thin film transistors, or the first thin film transistor 2 and the second thin film transistor 3 are both bottom-gate thin film transistors;

[0071] The orthographic projections of the active layer 21 of the first thin film transistor 2 and the active layer 31 of the second thin film transistor 3 on the base substrate 1 are arranged to overlap with each other.

[0072] For example, see Figure 9 A schematic structural diagram of another display substrate provided by an embodiment of the present invention, Figure 8 The first thin-film transistor 2 and the second thin-film transistor 3 are both top-gate thin-film transistors. A first buffer layer is provided on the side of the substrate 1 near the first thin-film transistor 2. The first insulating layer 4 includes a first gate insulating layer, a first interlayer dielectric layer, and a second buffer layer. The first gate insulating layer is located on the side of the active layer 21 of the first thin-film transistor 2 facing away from the substrate 1. The gate of the first thin-film transistor 2 is located on the side of the first gate insulating layer facing away from the substrate 1. The first interlayer dielectric layer is located on the side of the gate of the first thin-film transistor 2 facing away from the substrate 1. The second buffer layer is located on the side of the first interlayer dielectric layer facing away from the substrate 1. If the first vias 41 corresponding to the above-mentioned first insulating layers 4 are formed when the corresponding insulating layers are patterned, the first vias 41 penetrate the second buffer layer, the first interlayer dielectric layer, and the first gate insulating layer in a direction perpendicular to the thickness. Ideally, the centers of the first vias 41 of the three first insulating layers 4 coincide with each other, but when masking is performed in actual production, there may be a certain alignment deviation. Therefore, the centers of the first vias 41 of the three first insulating layers 4 may not coincide with each other, but within the allowable error range.

[0073] The second insulating layer 5 includes a second gate insulating layer and a second interlayer dielectric layer. The second gate insulating layer is located on the side of the first electrode 32 of the second thin-film transistor 3 facing away from the substrate 1. The gate of the second thin-film transistor 3 is located on the side of the second gate insulating layer facing away from the substrate 1. The second interlayer dielectric layer is located on the side of the gate of the second thin-film transistor 3 facing away from the substrate 1. The second via 51 passes through the second gate insulating layer and the second interlayer dielectric layer in a direction perpendicular to the thickness. Similarly, the centers of the second vias 51 in the second gate insulating layer and the second interlayer dielectric layer may not coincide. The above-mentioned first via 41 and second via 51 can also be formed after the second buffer layer and the second interlayer dielectric layer are formed respectively. This allows the centers of the first vias 41 in each first insulating layer 4 and the centers of the first vias 41 in each second insulating layer 5 to coincide.

[0074] When the first thin film transistor 2 and the second thin film transistor 3 are both bottom-gate thin film transistors, their structures are similar to those of top-gate thin film transistors. The difference is that the gate is arranged on the side of the active layer of the corresponding thin film transistor close to the base substrate 1. For details, please refer to the structure of the bottom-gate thin film transistor in the relevant technology.

[0075] In the embodiment provided by the present invention, by setting the first thin film transistor 2 and the second thin film crystal 3 to the same type of thin film crystal, the positive projection area of ​​the display substrate on the base substrate 1 can be reduced, thereby improving the resolution of the array substrate composed of the above display substrate.

[0076] See Figure 10 This is a schematic diagram of another display substrate provided by an embodiment of the present invention, wherein the first thin film transistor 2 is a top-gate thin film transistor, and the second thin film transistor 3 is a bottom-gate thin film transistor;

[0077] The gate of the first thin film transistor 2 and the gate of the second thin film transistor 3 are provided in the same layer.

[0078] When the first thin film transistor 2 is a top-gate thin film transistor and the second thin film transistor 3 is a bottom-gate thin film transistor, a first buffer layer is provided on the side of the substrate 1 close to the first thin film transistor 2. At this time, the first insulating layer 4 includes a gate insulating layer and an interlayer dielectric layer, and the first via 41 passes through the gate insulating layer and the interlayer dielectric layer; the second insulating layer 5 is composed of a second buffer layer, and the second via 51 passes through the second buffer layer.

[0079] By configuring the first thin-film transistor 2 as a top-gate thin-film transistor and the second thin-film transistor 3 as a bottom-gate thin-film transistor, and by arranging the gates of the first thin-film transistor 2 and the second thin-film transistor 3 in the same layer, the gates of the first thin-film transistor 2 and the second thin-film transistor 3 can share a mask, and the first via 41 can be simultaneously opened in the gate insulating layer, while guiding trenches for the silicon-based nanowires are simultaneously prepared. This eliminates the need for vias and buffer masks, shortening the overall process flow. Furthermore, the thickness of the prepared display substrate can be reduced, facilitating a thinner and lighter product.

[0080] In the embodiment provided by the present invention, the material of the active layer 21 of the first thin film transistor 2 is low-temperature polysilicon. By setting the material of the active layer 21 of the first thin film transistor 2 to low-temperature polysilicon, the size of the first thin film crystal layer can be reduced, making the resulting display substrate smaller. It can also enable the gate of the first thin film transistor 2 and the gate of the second thin film transistor 3 to share a mask, saving process steps and thus improving production efficiency.

[0081] Based on the same inventive concept, an embodiment of the present invention provides a method for preparing a display substrate. The specific implementation of the display substrate prepared by the preparation method can be found in the description of the display substrate embodiment. The repeated parts will not be repeated. Figure 11 , the preparation method comprises:

[0082] Step 111: forming an active layer of a first thin film transistor on a base substrate;

[0083] Step 112: forming at least one first insulating layer on the active layer of the first thin film transistor;

[0084] Step 113: forming an active layer of a second thin film transistor on at least one first insulating layer;

[0085] Step 114: forming a first via hole penetrating at least one first insulating layer;

[0086] Step 115: using phosphorus-rich amorphous silicon material to form a first electrode of the second thin film transistor on the active layer of the second thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the active layer of the first thin film transistor through a first via hole.

[0087] For example, to prepare Figure 8 Taking the second thin film transistor in the as an example, it is necessary to form a first buffer layer of the first thin film crystal on the substrate, form an active layer of the first thin film transistor on the first buffer layer, and then form a first gate insulating layer on the active layer of the first thin film crystal, form a gate of the first thin film transistor on the first gate insulating layer, form a first interlayer dielectric layer on the gate of the first thin film transistor, form the second electrode of the first thin film transistor on the first interlayer dielectric layer, and form a second buffer layer on the second gate. At this time, the first thin film transistor is completed (the second buffer layer can also be regarded as the insulating layer in the second thin film transistor), and then the second thin film transistor can be prepared.

[0088] See Figure 12 The flowchart of preparing the second thin film transistor in the display substrate provided by the embodiment of the present invention is as follows:

[0089] S10: forming an active layer of a first thin film transistor.

[0090] An active layer of a first thin film transistor is formed on the second buffer layer.

[0091] S11: forming a first via hole.

[0092] Figure 10 In the embodiment, the three insulating layers from the first gate insulating layer to the second buffer layer, namely the first insulating layer between the active layer of the first thin film crystal and the active layer of the second thin film crystal, have first via holes penetrating these three first insulating layers.

[0093] S12: forming an amorphous silicon layer rich in phosphorus.

[0094] An amorphous silicon layer rich in phosphorus is deposited on the side of the active layer of the second thin film transistor facing away from the substrate to form the first electrode and the etching stopper of the first thin film transistor.

[0095] S13: forming a second gate insulating layer.

[0096] A second gate insulating layer is formed on the phosphorus-rich amorphous silicon layer.

[0097] S14: forming a gate, a second interlayer dielectric layer, and a second via hole in sequence.

[0098] A gate of a second thin film transistor and a second interlayer dielectric layer are sequentially formed on the second gate insulating layer. The second gate insulating layer and the second gate dielectric layer constitute a second insulating layer between the etching stop portion and the second pole of the second thin film crystal. A second via hole penetrating the second gate insulating layer and the second gate dielectric layer is formed on the second gate insulating layer and the second gate dielectric layer.

[0099] S15: forming a second pole.

[0100] A second electrode of the second thin film transistor is formed on the second gate insulating layer, and the material of the second electrode is metal.

[0101] In a possible implementation manner, forming the active layer of the second thin film transistor on the at least one first insulating layer may be achieved by:

[0102] A groove is formed on the first insulating layer of the top layer; catalyst particles are formed in the groove, and the catalyst particles are used to induce amorphous silicon to grow into silicon nanowires; an amorphous silicon layer is deposited in the groove with the catalyst particles; the non-silicon layer is annealed to form silicon-based nanowires as the active layer of the second thin film transistor.

[0103] The catalyst particles may be indium, tin, cadmium, indium oxide, etc., without specific limitation.

[0104] When the catalyst is indium, the catalyst particles may be formed in the grooves in the following manner:

[0105] Indium tin oxide (ITO) material is deposited in the trench; the ITO material is treated with hydrogen plasma to form a plurality of indium balls arranged along the extending direction of the trench, wherein the plurality of indium balls are catalyst particles.

[0106] In an embodiment provided by the present invention, the method for preparing a display substrate further includes:

[0107] An etch stop portion is formed while a first electrode of the second thin film transistor is formed on the active layer of the second thin film transistor; a second insulating layer is formed covering the first electrode of the second thin film transistor and the etch stop portion; a second via hole is formed penetrating the second insulating layer; and a second electrode of the second thin film transistor is formed on the second insulating layer, the second electrode of the second thin film transistor being electrically connected to the etch stop portion through the second via hole.

[0108] For example, Figure 12Taking the active layer of the first thin film transistor as an example, the catalyst particles are indium, see Figure 13 A flow chart of forming an active layer of a second thin film transistor provided in an embodiment of the present invention.

[0109] S21: forming a groove.

[0110] A trench is formed on the second buffer layer (ie, the top first insulating layer).

[0111] S22: forming an ITO layer.

[0112] An indium tin oxide layer is deposited on the groove and patterned, wherein the retained ITO area serves as the starting area for silicon-based nanowire growth.

[0113] S23: Indium balls are formed.

[0114] The ITO layer is treated with hydrogen plasma to form a plurality of indium balls arranged along the extension direction of the grooves. These indium balls are catalyst particles.

[0115] S24: depositing an amorphous silicon layer.

[0116] An amorphous silicon layer is deposited within the trenches having the indium balls.

[0117] S25: forming an active layer of a second thin film transistor.

[0118] The amorphous silicon layer is annealed to form an active layer of a second thin film transistor composed of silicon-based nanowires.

[0119] By using ITO to prepare catalyst particles of silicon-based nanowires, catalyst particles can be prepared without introducing new materials, thereby facilitating the management of production raw materials.

[0120] An etching stopper is provided between the second electrode of the second thin film transistor and the active layer to prevent the active layer of the second thin film transistor formed with silicon-based nanowires from being damaged due to over-etching when etching the metal layer of the second electrode of the second thin film transistor.

[0121] Based on the same inventive concept, an embodiment of the present invention provides a display panel including the above-mentioned device structure.

[0122] The array substrate can be used in a display panel, such as a liquid crystal display panel, an OLED display panel, a flat panel detector, etc., without any specific limitation.

[0123] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or program products. Therefore, embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a machine program product implemented on one or more computer / processor-usable readable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing program code.

[0124] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] These program instructions may also be stored in a readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer / processor-implemented process, thereby providing instructions for executing on the computer / processor or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0127] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, characterized in that: include: A first thin film transistor, a second thin film transistor, and an etching stopper provided in the same layer as the first electrode of the second thin film transistor are located on a substrate; wherein, The active layer of the first thin film transistor is located in a film layer between the base substrate and the active layer of the second thin film transistor, and there is at least one first insulating layer between the active layer of the first thin film transistor and the active layer of the second thin film transistor. The at least one first insulating layer has a first via hole running through the thickness direction. The first electrode of the second thin film transistor is electrically connected to the active layer of the first thin film transistor through the first via hole. The material of the first electrode of the second thin film transistor is amorphous silicon rich in phosphorus. The etching stopper is located between the second electrode and the active layer of the second thin film transistor, and the material of the etching stopper is the amorphous silicon rich in phosphorus.

2. The display substrate according to claim 1, wherein The first electrode of the second thin film transistor and the etching stopper are respectively arranged in direct contact with the active layer of the second thin film transistor; There is a second insulating layer between the layer where the second electrode of the second thin film transistor is located and the layer where the etch stop part is located. The second insulating layer has a second via hole running through the thickness direction. The second electrode of the second thin film transistor is electrically connected to the etch stop part through the second via hole.

3. The display substrate according to claim 2, wherein: The orthographic projection of the etch stop portion on the base substrate covers the orthographic projection of the second via hole on the base substrate.

4. The display substrate according to claim 2, wherein: The material of the active layer of the second thin film transistor is silicon-based nanowire.

5. The display substrate according to any one of claims 1 to 4, wherein: The first thin film transistor and the second thin film transistor are both top-gate thin film transistors, or the first thin film transistor and the second thin film transistor are both bottom-gate thin film transistors; The orthographic projections of the active layer of the first thin film transistor and the active layer of the second thin film transistor on the base substrate are arranged to overlap with each other.

6. A method for preparing a display substrate, characterized in that: include: forming an active layer of a first thin film transistor on a base substrate; forming at least one first insulating layer on the active layer of the first thin film transistor; forming an active layer of a second thin film transistor on the at least one first insulating layer; forming a first via hole penetrating the at least one first insulating layer; Amorphous silicon material rich in phosphorus is used to form the first electrode of the second thin film transistor on the active layer of the second thin film transistor, and at the same time, an etch stop portion is formed and arranged in the same layer as the first electrode of the second thin film transistor. The etch stop portion is located between the second electrode of the second thin film transistor and the active layer, and the first electrode of the second thin film transistor is electrically connected to the active layer of the first thin film transistor through the first via hole.

7. The preparation method according to claim 6, wherein Forming an active layer of a second thin film transistor on the at least one first insulating layer, comprising: forming a groove on the first insulating layer at the top layer; depositing an indium tin oxide material in the trench; Performing hydrogen plasma treatment on the indium tin oxide material to form a plurality of indium balls arranged along the extension direction of the groove, and using the plurality of indium balls as catalyst particles to induce the amorphous silicon to grow into silicon nanowires; depositing an amorphous silicon layer in the trench having the catalyst particles; The amorphous silicon layer is annealed to form silicon-based nanowires as the active layer of the second thin film transistor.

8. The preparation method according to claim 6 or 7, characterized in that Also includes: forming a second insulating layer covering the first electrode of the second thin film transistor and the etch stopper; forming a second via hole penetrating the second insulating layer; A second electrode of the second thin film transistor is formed on the second insulating layer, and the second electrode of the second thin film transistor is electrically connected to the etch stopper through the second via hole.

9. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 5.

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